2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

	* arm-dis.c: Use preferred form of vrint instruction variants
	for disassembly.

2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction
	variants for disassembly.
	* gas/arm/armv8-a+fp.s: Likewise.
	* gas/arm/armv8-a+simd.d: Likewise.
	* gas/arm/armv8-a+simd.s: Likewise.

7 files changed, 122 insertions, 109 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 37632e5c9..907543a63 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,13 @@
 2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
+	* gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction
+	variants for disassembly.
+	* gas/arm/armv8-a+fp.s: Likewise.
+	* gas/arm/armv8-a+simd.d: Likewise.
+	* gas/arm/armv8-a+simd.s: Likewise.
+
+2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
 	* gas/arm/ldgesb-bad.d: New file.
 	* gas/arm/ldgesb-bad.l: Likewise.
 	* gas/arm/ldgesb-bad.s: Likewise.
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index bb52e0a40..d50a73bd1 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -36,20 +36,20 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fefd0b60 	vcvtn.u32.f64	s1, d16
 0[0-9a-f]+ <[^>]+> febefb4f 	vcvtp.u32.f64	s30, d15
 0[0-9a-f]+ <[^>]+> fefffb6f 	vcvtm.u32.f64	s31, d31
-0[0-9a-f]+ <[^>]+> eeb60ac0 	vrintz.f32.f32	s0, s0
-0[0-9a-f]+ <[^>]+> eef70a60 	vrintx.f32.f32	s1, s1
-0[0-9a-f]+ <[^>]+> 0eb6fa4f 	vrintreq.f32.f32	s30, s30
-0[0-9a-f]+ <[^>]+> feb80a40 	vrinta.f32.f32	s0, s0
-0[0-9a-f]+ <[^>]+> fef90a60 	vrintn.f32.f32	s1, s1
-0[0-9a-f]+ <[^>]+> febafa4f 	vrintp.f32.f32	s30, s30
-0[0-9a-f]+ <[^>]+> fefbfa6f 	vrintm.f32.f32	s31, s31
-0[0-9a-f]+ <[^>]+> eeb60bc0 	vrintz.f64.f64	d0, d0
-0[0-9a-f]+ <[^>]+> eeb71b41 	vrintx.f64.f64	d1, d1
-0[0-9a-f]+ <[^>]+> 0ef6eb6e 	vrintreq.f64.f64	d30, d30
-0[0-9a-f]+ <[^>]+> feb80b40 	vrinta.f64.f64	d0, d0
-0[0-9a-f]+ <[^>]+> feb91b41 	vrintn.f64.f64	d1, d1
-0[0-9a-f]+ <[^>]+> fefaeb6e 	vrintp.f64.f64	d30, d30
-0[0-9a-f]+ <[^>]+> fefbfb6f 	vrintm.f64.f64	d31, d31
+0[0-9a-f]+ <[^>]+> eeb60ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef70a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> 0eb6fa4f 	vrintreq.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb80a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef90a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febafa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefbfa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb60bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb71b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> 0ef6eb6e 	vrintreq.f64	d30, d30
+0[0-9a-f]+ <[^>]+> feb80b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb91b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> fefaeb6e 	vrintp.f64	d30, d30
+0[0-9a-f]+ <[^>]+> fefbfb6f 	vrintm.f64	d31, d31
 0[0-9a-f]+ <[^>]+> eeb30bc0 	vcvtt.f16.f64	s0, d0
 0[0-9a-f]+ <[^>]+> eef30b60 	vcvtb.f16.f64	s1, d16
 0[0-9a-f]+ <[^>]+> eeb3fbcf 	vcvtt.f16.f64	s30, d15
@@ -90,20 +90,20 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fefd 0b60 	vcvtn.u32.f64	s1, d16
 0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
 0[0-9a-f]+ <[^>]+> feff fb6f 	vcvtm.u32.f64	s31, d31
-0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32.f32	s0, s0
-0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32.f32	s1, s1
-0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32.f32	s30, s30
-0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32.f32	s0, s0
-0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32.f32	s1, s1
-0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32.f32	s30, s30
-0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32.f32	s31, s31
-0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64.f64	d0, d0
-0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64.f64	d1, d1
-0[0-9a-f]+ <[^>]+> eef6 eb6e 	vrintr.f64.f64	d30, d30
-0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64.f64	d0, d0
-0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64.f64	d1, d1
-0[0-9a-f]+ <[^>]+> fefa eb6e 	vrintp.f64.f64	d30, d30
-0[0-9a-f]+ <[^>]+> fefb fb6f 	vrintm.f64.f64	d31, d31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> eef6 eb6e 	vrintr.f64	d30, d30
+0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> fefa eb6e 	vrintp.f64	d30, d30
+0[0-9a-f]+ <[^>]+> fefb fb6f 	vrintm.f64	d31, d31
 0[0-9a-f]+ <[^>]+> eeb3 0bc0 	vcvtt.f16.f64	s0, d0
 0[0-9a-f]+ <[^>]+> eef3 0b60 	vcvtb.f16.f64	s1, d16
 0[0-9a-f]+ <[^>]+> eeb3 fbcf 	vcvtt.f16.f64	s30, d15
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index f99302f26..f7a54736a 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -36,20 +36,20 @@
 	vcvtn.s32.f64	s1, d16
 	vcvtp.u32.f64	s30, d15
 	vcvtm.u32.f64	s31, d31
-	vrintz.f32.f32  s0, s0
-        vrintx.f32.f32  s1, s1
-        vrintreq.f32.f32 s30, s30
-	vrinta.f32.f32	s0, s0
-	vrintn.f32.f32	s1, s1
-	vrintp.f32.f32	s30, s30
-	vrintm.f32.f32	s31, s31
-	vrintz.f64.f64  d0, d0
-        vrintx.f64.f64  d1, d1
-        vrintreq.f64.f64 d30, d30
-	vrinta.f64.f64	d0, d0
-	vrintn.f64.f64	d1, d1
-	vrintp.f64.f64	d30, d30
-	vrintm.f64.f64	d31, d31
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintreq.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
+	vrintz.f64	d0, d0
+        vrintx.f64	d1, d1
+        vrintreq.f64	d30, d30
+	vrinta.f64	d0, d0
+	vrintn.f64	d1, d1
+	vrintp.f64	d30, d30
+	vrintm.f64	d31, d31
 	vcvtt.f16.f64	s0, d0
 	vcvtb.f16.f64	s1, d16
 	vcvtt.f16.f64	s30, d15
@@ -92,20 +92,20 @@
 	vcvtn.s32.f64	s1, d16
 	vcvtp.u32.f64	s30, d15
 	vcvtm.u32.f64	s31, d31
-	vrintz.f32.f32  s0, s0
-        vrintx.f32.f32  s1, s1
-        vrintr.f32.f32 s30, s30
-	vrinta.f32.f32	s0, s0
-	vrintn.f32.f32	s1, s1
-	vrintp.f32.f32	s30, s30
-	vrintm.f32.f32	s31, s31
-	vrintz.f64.f64  d0, d0
-        vrintx.f64.f64  d1, d1
-        vrintr.f64.f64 d30, d30
-	vrinta.f64.f64	d0, d0
-	vrintn.f64.f64	d1, d1
-	vrintp.f64.f64	d30, d30
-	vrintm.f64.f64	d31, d31
+	vrintz.f32	s0, s0
+        vrintx.f32	s1, s1
+        vrintr.f32	s30, s30
+	vrinta.f32	s0, s0
+	vrintn.f32	s1, s1
+	vrintp.f32	s30, s30
+	vrintm.f32	s31, s31
+	vrintz.f64	d0, d0
+        vrintx.f64	d1, d1
+        vrintr.f64	d30, d30
+	vrinta.f64	d0, d0
+	vrintn.f64	d1, d1
+	vrintp.f64	d30, d30
+	vrintm.f64	d31, d31
 	vcvtt.f16.f64	s0, d0
 	vcvtb.f16.f64	s1, d16
 	vcvtt.f16.f64	s30, d15
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
index c6a4a5eb5..49ef5b6a3 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.d
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -28,18 +28,18 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3fb0160 	vcvtn.s32.f32	q8, q8
 0[0-9a-f]+ <[^>]+> f3bbe2ce 	vcvtp.u32.f32	q7, q7
 0[0-9a-f]+ <[^>]+> f3fbe3ee 	vcvtm.u32.f32	q15, q15
-0[0-9a-f]+ <[^>]+> f3ba0500 	vrinta.f32.f32	d0, d0
-0[0-9a-f]+ <[^>]+> f3fa0420 	vrintn.f32.f32	d16, d16
-0[0-9a-f]+ <[^>]+> f3baf68f 	vrintm.f32.f32	d15, d15
-0[0-9a-f]+ <[^>]+> f3faf7af 	vrintp.f32.f32	d31, d31
-0[0-9a-f]+ <[^>]+> f3ba04af 	vrintx.f32.f32	d0, d31
-0[0-9a-f]+ <[^>]+> f3fa058f 	vrintz.f32.f32	d16, d15
-0[0-9a-f]+ <[^>]+> f3ba0540 	vrinta.f32.f32	q0, q0
-0[0-9a-f]+ <[^>]+> f3fa0460 	vrintn.f32.f32	q8, q8
-0[0-9a-f]+ <[^>]+> f3bae6ce 	vrintm.f32.f32	q7, q7
-0[0-9a-f]+ <[^>]+> f3fae7ee 	vrintp.f32.f32	q15, q15
-0[0-9a-f]+ <[^>]+> f3ba04ee 	vrintx.f32.f32	q0, q15
-0[0-9a-f]+ <[^>]+> f3fa05ce 	vrintz.f32.f32	q8, q7
+0[0-9a-f]+ <[^>]+> f3ba0500 	vrinta.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3fa0420 	vrintn.f32	d16, d16
+0[0-9a-f]+ <[^>]+> f3baf68f 	vrintm.f32	d15, d15
+0[0-9a-f]+ <[^>]+> f3faf7af 	vrintp.f32	d31, d31
+0[0-9a-f]+ <[^>]+> f3ba04af 	vrintx.f32	d0, d31
+0[0-9a-f]+ <[^>]+> f3fa058f 	vrintz.f32	d16, d15
+0[0-9a-f]+ <[^>]+> f3ba0540 	vrinta.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3fa0460 	vrintn.f32	q8, q8
+0[0-9a-f]+ <[^>]+> f3bae6ce 	vrintm.f32	q7, q7
+0[0-9a-f]+ <[^>]+> f3fae7ee 	vrintp.f32	q15, q15
+0[0-9a-f]+ <[^>]+> f3ba04ee 	vrintx.f32	q0, q15
+0[0-9a-f]+ <[^>]+> f3fa05ce 	vrintz.f32	q8, q7
 0[0-9a-f]+ <[^>]+> ff00 0f10 	vmaxnm.f32	d0, d0, d0
 0[0-9a-f]+ <[^>]+> ff40 0fb0 	vmaxnm.f32	d16, d16, d16
 0[0-9a-f]+ <[^>]+> ff0f ff1f 	vmaxnm.f32	d15, d15, d15
@@ -64,15 +64,15 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fffb 0160 	vcvtn.s32.f32	q8, q8
 0[0-9a-f]+ <[^>]+> ffbb e2ce 	vcvtp.u32.f32	q7, q7
 0[0-9a-f]+ <[^>]+> fffb e3ee 	vcvtm.u32.f32	q15, q15
-0[0-9a-f]+ <[^>]+> ffba 0500 	vrinta.f32.f32	d0, d0
-0[0-9a-f]+ <[^>]+> fffa 0420 	vrintn.f32.f32	d16, d16
-0[0-9a-f]+ <[^>]+> ffba f68f 	vrintm.f32.f32	d15, d15
-0[0-9a-f]+ <[^>]+> fffa f7af 	vrintp.f32.f32	d31, d31
-0[0-9a-f]+ <[^>]+> ffba 04af 	vrintx.f32.f32	d0, d31
-0[0-9a-f]+ <[^>]+> fffa 058f 	vrintz.f32.f32	d16, d15
-0[0-9a-f]+ <[^>]+> ffba 0540 	vrinta.f32.f32	q0, q0
-0[0-9a-f]+ <[^>]+> fffa 0460 	vrintn.f32.f32	q8, q8
-0[0-9a-f]+ <[^>]+> ffba e6ce 	vrintm.f32.f32	q7, q7
-0[0-9a-f]+ <[^>]+> fffa e7ee 	vrintp.f32.f32	q15, q15
-0[0-9a-f]+ <[^>]+> ffba 04ee 	vrintx.f32.f32	q0, q15
-0[0-9a-f]+ <[^>]+> fffa 05ce 	vrintz.f32.f32	q8, q7
+0[0-9a-f]+ <[^>]+> ffba 0500 	vrinta.f32	d0, d0
+0[0-9a-f]+ <[^>]+> fffa 0420 	vrintn.f32	d16, d16
+0[0-9a-f]+ <[^>]+> ffba f68f 	vrintm.f32	d15, d15
+0[0-9a-f]+ <[^>]+> fffa f7af 	vrintp.f32	d31, d31
+0[0-9a-f]+ <[^>]+> ffba 04af 	vrintx.f32	d0, d31
+0[0-9a-f]+ <[^>]+> fffa 058f 	vrintz.f32	d16, d15
+0[0-9a-f]+ <[^>]+> ffba 0540 	vrinta.f32	q0, q0
+0[0-9a-f]+ <[^>]+> fffa 0460 	vrintn.f32	q8, q8
+0[0-9a-f]+ <[^>]+> ffba e6ce 	vrintm.f32	q7, q7
+0[0-9a-f]+ <[^>]+> fffa e7ee 	vrintp.f32	q15, q15
+0[0-9a-f]+ <[^>]+> ffba 04ee 	vrintx.f32	q0, q15
+0[0-9a-f]+ <[^>]+> fffa 05ce 	vrintz.f32	q8, q7
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s
index 9a08a07cb..4d7bce7ba 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.s
+++ b/gas/testsuite/gas/arm/armv8-a+simd.s
@@ -27,18 +27,18 @@
 	vcvtn.s32.f32	q8, q8
 	vcvtp.u32.f32	q7, q7
 	vcvtm.u32.f32	q15, q15
-	vrinta.f32.f32	d0, d0
-	vrintn.f32.f32  d16, d16
-	vrintm.f32.f32	d15, d15
-	vrintp.f32.f32  d31, d31
-	vrintx.f32.f32	d0, d31
-	vrintz.f32.f32  d16, d15
-	vrinta.f32.f32	q0, q0
-	vrintn.f32.f32  q8, q8
-	vrintm.f32.f32	q7, q7
-	vrintp.f32.f32  q15, q15
-	vrintx.f32.f32	q0, q15
-	vrintz.f32.f32  q8, q7
+	vrinta.f32	d0, d0
+	vrintn.f32	d16, d16
+	vrintm.f32	d15, d15
+	vrintp.f32	d31, d31
+	vrintx.f32	d0, d31
+	vrintz.f32	d16, d15
+	vrinta.f32	q0, q0
+	vrintn.f32	q8, q8
+	vrintm.f32	q7, q7
+	vrintp.f32	q15, q15
+	vrintx.f32	q0, q15
+	vrintz.f32	q8, q7
 
 	.thumb
 	vmaxnm.f32	d0, d0, d0
@@ -65,15 +65,15 @@
 	vcvtn.s32.f32	q8, q8
 	vcvtp.u32.f32	q7, q7
 	vcvtm.u32.f32	q15, q15
-	vrinta.f32.f32	d0, d0
-	vrintn.f32.f32  d16, d16
-	vrintm.f32.f32	d15, d15
-	vrintp.f32.f32  d31, d31
-	vrintx.f32.f32	d0, d31
-	vrintz.f32.f32  d16, d15
-	vrinta.f32.f32	q0, q0
-	vrintn.f32.f32  q8, q8
-	vrintm.f32.f32	q7, q7
-	vrintp.f32.f32  q15, q15
-	vrintx.f32.f32	q0, q15
-	vrintz.f32.f32  q8, q7
+	vrinta.f32	d0, d0
+	vrintn.f32	d16, d16
+	vrintm.f32	d15, d15
+	vrintp.f32	d31, d31
+	vrintx.f32	d0, d31
+	vrintz.f32	d16, d15
+	vrinta.f32	q0, q0
+	vrintn.f32	q8, q8
+	vrintm.f32	q7, q7
+	vrintp.f32	q15, q15
+	vrintx.f32	q0, q15
+	vrintz.f32	q8, q7
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 17f7fee99..db6746af0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* arm-dis.c: Use preferred form of vrint instruction variants
+	for disassembly.
+
 2012-10-09  Nagajyothi Eggone  <nagajyothi.eggone@amd.com>
 
 	* i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 22bdd829d..d140761e0 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -498,10 +498,10 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
   {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
   {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
-  {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"},
-  {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"},
-  {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"},
-  {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"},
+  {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
+  {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
+  {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
+  {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 
   /* Generic coprocessor instructions.  */
   { 0, SENTINEL_GENERIC_START, 0, "" },
@@ -584,7 +584,7 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 
   /* Two registers, miscellaneous.  */
-  {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"},
+  {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
   {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},