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authoryufeng <yufeng>2012-10-15 14:57:30 +0000
committeryufeng <yufeng>2012-10-15 14:57:30 +0000
commit01554f25e34f06217a8c88ea81f66391e1c8917f (patch)
tree7996826515c618a14f988fe2d12e48900931ca94
parent0cf58d0ed8d221ee0971470f45e5343f2de1336a (diff)
downloadbinutils-01554f25e34f06217a8c88ea81f66391e1c8917f.tar.gz
Added the changelog for the previous commit.
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--opcodes/ChangeLog6
2 files changed, 11 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2fa6b8d5b..ab713eded 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * gas/aarch64/illegal-2.s: Add test case.
+ * gas/aarch64/illegal-2.l: Update.
+
2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* gas/hppa/basic/fmemLRbug.s: Remove double load and store instructions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index db6746af0..ad5a07034 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Change to check
+ the alignment of addr.offset.imm instead of that of shifter.amount for
+ operand type AARCH64_OPND_ADDR_UIMM12.
+
2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Use preferred form of vrint instruction variants