diff options
| author | Dave Hansen <dave.hansen@intel.com> | 2017-11-06 17:16:44 -0800 |
|---|---|---|
| committer | Dave Hansen <dave.hansen@intel.com> | 2017-11-06 17:16:44 -0800 |
| commit | 07b45278fa54d86214293de537516f63818f09de (patch) | |
| tree | a0121217b2d95de0aac7d640753277461aff9d43 | |
| parent | 7c463ed1afe0a26149443bb750ff7832f79cc2b4 (diff) | |
| download | x86-kaiser-07b45278fa54d86214293de537516f63818f09de.tar.gz | |
x86, mm: document X86_CR4_PGE toggling behavior
From: Dave Hansen <dave.hansen@linux.intel.com>
The comment says it all here. The problem here is that the
X86_CR4_PGE bit affects all PCIDs in a way that is totally
obscure.
This makes it easier for someone to find if grepping for PCID-
related stuff and documents the hardware behavior that we are
depending on.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Moritz Lipp <moritz.lipp@iaik.tugraz.at>
Cc: Daniel Gruss <daniel.gruss@iaik.tugraz.at>
Cc: Michael Schwarz <michael.schwarz@iaik.tugraz.at>
Cc: Richard Fellner <richard.fellner@student.tugraz.at>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Kees Cook <keescook@google.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: x86@kernel.org
| -rw-r--r-- | arch/x86/include/asm/tlbflush.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 9bf9652690b1c8..21d69ff4a9781c 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -257,10 +257,12 @@ static inline void __native_flush_tlb_global_irq_disabled(void) */ WARN_ON_ONCE(!(cr4 & X86_CR4_PGE)); /* - * Architecturally, any _change_ to X86_CR4_PGE will fully flush the - * TLB of all entries including all entries in all PCIDs and all - * global pages. Make sure that we _change_ the bit, regardless of + * Architecturally, any _change_ to X86_CR4_PGE will fully flush + * all entries. Make sure that we _change_ the bit, regardless of * whether we had X86_CR4_PGE set in the first place. + * + * Note that just toggling PGE *also* flushes all entries from all + * PCIDs, regardless of the state of X86_CR4_PCIDE. */ native_write_cr4(cr4 ^ X86_CR4_PGE); /* Put original CR4 value back: */ |