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| author | openeuler-ci-bot <george@openeuler.sh> | 2024-04-17 01:26:45 +0000 |
|---|---|---|
| committer | Gitee <noreply@gitee.com> | 2024-04-17 01:26:45 +0000 |
| commit | 824161c6f233cd0cbdd6d7c2b779fc7f06c05ad1 (patch) | |
| tree | 8fc2ef5d25cd23ade00bfdc55586cd0416557aac | |
| parent | 91470760c999c20780d2b3a945531c03208eb5be (diff) | |
| parent | b4972783807d8fb958553b5e30bc2567fb31f41e (diff) | |
| download | openEuler-kernel-824161c6f233cd0cbdd6d7c2b779fc7f06c05ad1.tar.gz | |
!6187 [sync] PR-5770: v2 scsi: hisi_sas: Fixed some issues in the SAS
Merge Pull Request from: @openeuler-sync-bot
Origin pull request:
https://gitee.com/openeuler/kernel/pulls/5770
PR sync from: Yihang Li <liyihang9@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/FC7IJTYWFKOM2YNCUWGC3KNMOO3QF2D5/
This patchset includes 2 minor changes
- For interrupt coalescing, the count of CQ entries is set to 10, and the
interrupt coalescing timeout period is set to 10us.
- Add cond_resched() to cq_thread_v3_hw() to execute the watchdog thread.
Changes since v1:
- Remove unnecessary comments.
- Update the commit message for patch 1.
Yihang Li (2):
scsi: hisi_sas: Default enable interrupt coalescing
scsi: hisi_sas: Add cond_resched() to cq_thread_v3_hw()
--
2.33.0
https://gitee.com/openeuler/kernel/issues/I9BBFQ
Link:https://gitee.com/openeuler/kernel/pulls/6187
Reviewed-by: Yihang Li <liyihang9@huawei.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>
| -rw-r--r-- | drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index e714ea328e55ef..a555827d944fbf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -631,9 +631,9 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80); hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); - hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); - hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); - hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); + hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0xa); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0xa); hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, hisi_sas_intr_conv); hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); @@ -2479,6 +2479,7 @@ static irqreturn_t cq_thread_v3_hw(int irq_no, void *p) /* update rd_point */ cq->rd_point = rd_point; hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); + cond_resched(); return IRQ_HANDLED; } @@ -2761,11 +2762,9 @@ static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) if (hisi_hba->intr_coal_ticks == 0 || hisi_hba->intr_coal_count == 0) { - hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); - hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); - hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0xa); + hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0xa); } else { - hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, hisi_hba->intr_coal_ticks); hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, |