diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/align.c 504-ppc64-update/arch/ppc64/kernel/align.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/align.c Tue Feb 25 23:03:44 2003 +++ 504-ppc64-update/arch/ppc64/kernel/align.c Sun Apr 20 22:21:42 2003 @@ -237,7 +237,7 @@ fix_alignment(struct pt_regs *regs) dsisr = regs->dsisr; /* Power4 doesn't set DSISR for an alignment interrupt */ - if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) { + if (!cpu_alignexc_sets_dsisr()) { unsigned int real_instr; if (__get_user(real_instr, (unsigned int *)regs->nip)) return 0; diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/chrp_setup.c 504-ppc64-update/arch/ppc64/kernel/chrp_setup.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/chrp_setup.c Tue Apr 8 14:38:14 2003 +++ 504-ppc64-update/arch/ppc64/kernel/chrp_setup.c Sun Apr 20 22:21:42 2003 @@ -261,8 +261,9 @@ chrp_progress(char *s, unsigned short he struct device_node *root; int width, *p; char *os; - static int display_character, set_indicator; + static int display_character; static int max_width; + static spinlock_t progress_lock = SPIN_LOCK_UNLOCKED; if (!rtas.base) return; @@ -276,16 +277,10 @@ chrp_progress(char *s, unsigned short he else max_width = 0x10; display_character = rtas_token("display-character"); - set_indicator = rtas_token("set-indicator"); - } - if (display_character == RTAS_UNKNOWN_SERVICE) { - /* use hex display */ - if (set_indicator == RTAS_UNKNOWN_SERVICE) - return; - rtas_call(set_indicator, 3, 1, NULL, 6, 0, hex); - return; } + spin_lock(&progress_lock); + rtas_call(display_character, 1, 1, NULL, '\r'); width = max_width; @@ -306,6 +301,8 @@ chrp_progress(char *s, unsigned short he /* Blank to end of line. */ while ( width-- > 0 ) rtas_call(display_character, 1, 1, NULL, ' ' ); + + spin_unlock(&progress_lock); } extern void setup_default_decr(void); diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/ioctl32.c 504-ppc64-update/arch/ppc64/kernel/ioctl32.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/ioctl32.c Wed Mar 5 07:36:58 2003 +++ 504-ppc64-update/arch/ppc64/kernel/ioctl32.c Sun Apr 20 22:21:42 2003 @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -4159,6 +4160,7 @@ COMPATIBLE_IOCTL(AUTOFS_IOC_FAIL), COMPATIBLE_IOCTL(AUTOFS_IOC_CATATONIC), COMPATIBLE_IOCTL(AUTOFS_IOC_PROTOVER), COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE), +COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE_MULTI), /* DEVFS */ COMPATIBLE_IOCTL(DEVFSDIOC_GET_PROTO_REV), COMPATIBLE_IOCTL(DEVFSDIOC_SET_EVENT_MASK), diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/irq.c 504-ppc64-update/arch/ppc64/kernel/irq.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/irq.c Mon Mar 17 21:43:40 2003 +++ 504-ppc64-update/arch/ppc64/kernel/irq.c Sun Apr 20 22:21:42 2003 @@ -695,7 +695,7 @@ static void register_irq_proc (unsigned struct proc_dir_entry *entry; char name [MAX_NAMELEN]; - if (!root_irq_dir || (irq_desc[irq].handler == NULL)) + if (!root_irq_dir || (irq_desc[irq].handler == NULL) || irq_dir[irq]) return; memset(name, 0, MAX_NAMELEN); diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/misc.S 504-ppc64-update/arch/ppc64/kernel/misc.S --- 503-ppc64-scruffiness/arch/ppc64/kernel/misc.S Sun Apr 20 22:21:39 2003 +++ 504-ppc64-update/arch/ppc64/kernel/misc.S Sun Apr 20 22:21:42 2003 @@ -737,7 +737,7 @@ _GLOBAL(sys_call_table32) .llong .sys_set_tid_address .llong .ppc32_fadvise64 .llong .sys_exit_group - .llong .ppc32_lookup_dcookie /* 245 */ + .llong .ppc32_lookup_dcookie /* 235 */ .llong .sys_epoll_create .llong .sys_epoll_ctl .llong .sys_epoll_wait diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/module.c 504-ppc64-update/arch/ppc64/kernel/module.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/module.c Thu Feb 13 11:08:04 2003 +++ 504-ppc64-update/arch/ppc64/kernel/module.c Sun Apr 20 22:21:42 2003 @@ -20,6 +20,7 @@ #include #include #include +#include /* FIXME: We don't do .init separately. To do this, we'd need to have a separate r2 value in the init and core section, and stub between @@ -382,7 +383,7 @@ int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, struct module *me) { - sort_ex_table(me->extable.entry, - me->extable.entry + me->extable.num_entries); + sort_ex_table(me->extable, + me->extable + me->num_exentries); return 0; } diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/open_pic.c 504-ppc64-update/arch/ppc64/kernel/open_pic.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/open_pic.c Tue Feb 25 23:03:44 2003 +++ 504-ppc64-update/arch/ppc64/kernel/open_pic.c Sun Apr 20 22:21:42 2003 @@ -111,7 +111,6 @@ unsigned int openpic_vec_spurious; * data has probably been corrupted and we're going to panic or deadlock later * anyway --Troy */ -extern unsigned long* _get_SP(void); #define check_arg_irq(irq) \ if (irq < open_pic_irq_offset || irq >= (NumSources+open_pic_irq_offset)){ \ printk(KERN_ERR "open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \ diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/pSeries_lpar.c 504-ppc64-update/arch/ppc64/kernel/pSeries_lpar.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/pSeries_lpar.c Tue Apr 8 14:38:14 2003 +++ 504-ppc64-update/arch/ppc64/kernel/pSeries_lpar.c Sun Apr 20 22:21:42 2003 @@ -110,29 +110,6 @@ long plpar_put_term_char(unsigned long t lbuf[0], lbuf[1], &dummy, &dummy, &dummy); } -long plpar_eoi(unsigned long xirr) -{ - return plpar_hcall_norets(H_EOI, xirr); -} - -long plpar_cppr(unsigned long cppr) -{ - return plpar_hcall_norets(H_CPPR, cppr); -} - -long plpar_ipi(unsigned long servernum, - unsigned long mfrr) -{ - return plpar_hcall_norets(H_IPI, servernum, mfrr); -} - -long plpar_xirr(unsigned long *xirr_ret) -{ - unsigned long dummy; - return plpar_hcall(H_XIRR, 0, 0, 0, 0, - xirr_ret, &dummy, &dummy); -} - static void tce_build_pSeriesLP(struct TceTable *tbl, long tcenum, unsigned long uaddr, int direction ) { @@ -179,66 +156,6 @@ static void tce_free_one_pSeriesLP(struc } } - -/* PowerPC Interrupts for lpar. */ -/* NOTE: this typedef is duplicated (for now) from xics.c! */ -typedef struct { - int (*xirr_info_get)(int cpu); - void (*xirr_info_set)(int cpu, int val); - void (*cppr_info)(int cpu, u8 val); - void (*qirr_info)(int cpu, u8 val); -} xics_ops; -static int pSeriesLP_xirr_info_get(int n_cpu) -{ - unsigned long lpar_rc; - unsigned long return_value; - - lpar_rc = plpar_xirr(&return_value); - if (lpar_rc != H_Success) { - panic(" bad return code xirr - rc = %lx \n", lpar_rc); - } - return ((int)(return_value)); -} - -static void pSeriesLP_xirr_info_set(int n_cpu, int value) -{ - unsigned long lpar_rc; - unsigned long val64 = value & 0xffffffff; - - lpar_rc = plpar_eoi(val64); - if (lpar_rc != H_Success) { - panic(" bad return code EOI - rc = %ld, value=%lx \n", lpar_rc, val64); - } -} - -static void pSeriesLP_cppr_info(int n_cpu, u8 value) -{ - unsigned long lpar_rc; - - lpar_rc = plpar_cppr(value); - if (lpar_rc != H_Success) { - panic(" bad return code cppr - rc = %lx \n", lpar_rc); - } -} - -static void pSeriesLP_qirr_info(int n_cpu , u8 value) -{ - unsigned long lpar_rc; - - lpar_rc = plpar_ipi(n_cpu, value); - if (lpar_rc != H_Success) { - panic(" bad return code qirr -ipi - rc = %lx \n", lpar_rc); - } -} - -xics_ops pSeriesLP_ops = { - pSeriesLP_xirr_info_get, - pSeriesLP_xirr_info_set, - pSeriesLP_cppr_info, - pSeriesLP_qirr_info -}; -/* end TAI-LPAR */ - int vtermno; /* virtual terminal# for udbg */ diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/process.c 504-ppc64-update/arch/ppc64/kernel/process.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/process.c Tue Apr 8 14:38:14 2003 +++ 504-ppc64-update/arch/ppc64/kernel/process.c Sun Apr 20 22:21:42 2003 @@ -533,8 +533,6 @@ static void show_tsk_stack(struct task_s } while (count++ < 32); } -extern unsigned long *_get_SP(void); - void dump_stack(void) { show_tsk_stack(current, (unsigned long)_get_SP()); diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/smp.c 504-ppc64-update/arch/ppc64/kernel/smp.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/smp.c Tue Apr 8 14:38:14 2003 +++ 504-ppc64-update/arch/ppc64/kernel/smp.c Sun Apr 20 22:21:42 2003 @@ -46,8 +46,9 @@ #include #include "open_pic.h" #include +#include -int smp_threads_ready = 0; +int smp_threads_ready; unsigned long cache_decay_ticks; /* initialised so it doesn't end up in bss */ @@ -62,18 +63,6 @@ extern unsigned char stab_array[]; extern int cpu_idle(void *unused); void smp_call_function_interrupt(void); void smp_message_pass(int target, int msg, unsigned long data, int wait); - -void xics_setup_cpu(void); -void xics_cause_IPI(int cpu); - -/* - * XICS only has a single IPI, so encode the messages per CPU - */ -struct xics_ipi_struct { - volatile unsigned long value; -} ____cacheline_aligned; - -struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; #define smp_message_pass(t,m,d,w) smp_ops->message_pass((t),(m),(d),(w)) diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/kernel/xics.c 504-ppc64-update/arch/ppc64/kernel/xics.c --- 503-ppc64-scruffiness/arch/ppc64/kernel/xics.c Tue Feb 25 23:03:44 2003 +++ 504-ppc64-update/arch/ppc64/kernel/xics.c Sun Apr 20 22:21:42 2003 @@ -1,5 +1,5 @@ /* - * arch/ppc/kernel/xics.c + * arch/ppc64/kernel/xics.c * * Copyright 2000 IBM Corporation. * @@ -22,10 +22,11 @@ #include #include #include -#include "i8259.h" #include #include -#include +#include + +#include "i8259.h" void xics_enable_irq(u_int irq); void xics_disable_irq(u_int irq); @@ -61,33 +62,39 @@ struct hw_interrupt_type xics_8259_pic = /* Want a priority other than 0. Various HW issues require this. */ #define DEFAULT_PRIORITY 5 +/* + * Mark IPIs as higher priority so we can take them inside interrupts that + * arent marked SA_INTERRUPT + */ +#define IPI_PRIORITY 4 + struct xics_ipl { union { - u32 word; - u8 bytes[4]; + u32 word; + u8 bytes[4]; } xirr_poll; union { u32 word; - u8 bytes[4]; + u8 bytes[4]; } xirr; - u32 dummy; + u32 dummy; union { - u32 word; - u8 bytes[4]; + u32 word; + u8 bytes[4]; } qirr; }; -struct xics_info { - volatile struct xics_ipl * per_cpu[NR_CPUS]; -}; +static struct xics_ipl *xics_per_cpu[NR_CPUS]; -struct xics_info xics_info; +static int xics_irq_8259_cascade = 0; +static int xics_irq_8259_cascade_real = 0; +static unsigned int default_server = 0xFF; +static unsigned int default_distrib_server = 0; -unsigned long long intr_base = 0; -int xics_irq_8259_cascade = 0; -int xics_irq_8259_cascade_real = 0; -unsigned int default_server = 0xFF; -unsigned int default_distrib_server = 0; +/* + * XICS only has a single IPI, so encode the messages per CPU + */ +struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; /* RTAS service tokens */ int ibm_get_xive; @@ -95,11 +102,6 @@ int ibm_set_xive; int ibm_int_on; int ibm_int_off; -struct xics_interrupt_node { - unsigned long long addr; - unsigned long long size; -} inodes[NR_CPUS*2]; - typedef struct { int (*xirr_info_get)(int cpu); void (*xirr_info_set)(int cpu, int val); @@ -108,24 +110,26 @@ typedef struct { } xics_ops; +/* SMP */ + static int pSeries_xirr_info_get(int n_cpu) { - return (xics_info.per_cpu[n_cpu]->xirr.word); + return xics_per_cpu[n_cpu]->xirr.word; } static void pSeries_xirr_info_set(int n_cpu, int value) { - xics_info.per_cpu[n_cpu]->xirr.word = value; + xics_per_cpu[n_cpu]->xirr.word = value; } static void pSeries_cppr_info(int n_cpu, u8 value) { - xics_info.per_cpu[n_cpu]->xirr.bytes[0] = value; + xics_per_cpu[n_cpu]->xirr.bytes[0] = value; } -static void pSeries_qirr_info(int n_cpu , u8 value) +static void pSeries_qirr_info(int n_cpu, u8 value) { - xics_info.per_cpu[n_cpu]->qirr.bytes[0] = value; + xics_per_cpu[n_cpu]->qirr.bytes[0] = value; } static xics_ops pSeries_ops = { @@ -136,113 +140,174 @@ static xics_ops pSeries_ops = { }; static xics_ops *ops = &pSeries_ops; -extern xics_ops pSeriesLP_ops; -void -xics_enable_irq( - u_int virq - ) +/* LPAR */ + +static inline long plpar_eoi(unsigned long xirr) { - u_int irq; - unsigned long status; - long call_status; + return plpar_hcall_norets(H_EOI, xirr); +} + +static inline long plpar_cppr(unsigned long cppr) +{ + return plpar_hcall_norets(H_CPPR, cppr); +} + +static inline long plpar_ipi(unsigned long servernum, unsigned long mfrr) +{ + return plpar_hcall_norets(H_IPI, servernum, mfrr); +} + +static inline long plpar_xirr(unsigned long *xirr_ret) +{ + unsigned long dummy; + return plpar_hcall(H_XIRR, 0, 0, 0, 0, xirr_ret, &dummy, &dummy); +} + +static int pSeriesLP_xirr_info_get(int n_cpu) +{ + unsigned long lpar_rc; + unsigned long return_value; + + lpar_rc = plpar_xirr(&return_value); + if (lpar_rc != H_Success) + panic(" bad return code xirr - rc = %lx \n", lpar_rc); + return (int)return_value; +} + +static void pSeriesLP_xirr_info_set(int n_cpu, int value) +{ + unsigned long lpar_rc; + unsigned long val64 = value & 0xffffffff; + + lpar_rc = plpar_eoi(val64); + if (lpar_rc != H_Success) + panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc, + val64); +} + +static void pSeriesLP_cppr_info(int n_cpu, u8 value) +{ + unsigned long lpar_rc; + + lpar_rc = plpar_cppr(value); + if (lpar_rc != H_Success) + panic("bad return code cppr - rc = %lx\n", lpar_rc); +} + +static void pSeriesLP_qirr_info(int n_cpu , u8 value) +{ + unsigned long lpar_rc; + + lpar_rc = plpar_ipi(n_cpu, value); + if (lpar_rc != H_Success) + panic("bad return code qirr - rc = %lx\n", lpar_rc); +} + +xics_ops pSeriesLP_ops = { + pSeriesLP_xirr_info_get, + pSeriesLP_xirr_info_set, + pSeriesLP_cppr_info, + pSeriesLP_qirr_info +}; + +void xics_enable_irq(u_int virq) +{ + u_int irq; + long call_status; + unsigned int server; virq -= XICS_IRQ_OFFSET; irq = virt_irq_to_real(virq); if (irq == XICS_IPI) return; + #ifdef CONFIG_IRQ_ALL_CPUS - call_status = rtas_call(ibm_set_xive, 3, 1, (unsigned long*)&status, - irq, smp_threads_ready ? default_distrib_server : default_server, DEFAULT_PRIORITY); + if (smp_threads_ready) + server = default_distrib_server; + else + server = default_server; #else - call_status = rtas_call(ibm_set_xive, 3, 1, (unsigned long*)&status, - irq, default_server, DEFAULT_PRIORITY); + server = default_server; #endif - if( call_status != 0 ) { - printk("xics_enable_irq: irq=%x: rtas_call failed; retn=%lx, status=%lx\n", - irq, call_status, status); + + call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, + DEFAULT_PRIORITY); + if (call_status != 0) { + printk("xics_enable_irq: irq=%x: ibm_set_xive returned %lx\n", + irq, call_status); return; } + /* Now unmask the interrupt (often a no-op) */ - call_status = rtas_call(ibm_int_on, 1, 1, (unsigned long*)&status, - irq); - if( call_status != 0 ) { - printk("xics_disable_irq on: irq=%x: rtas_call failed, retn=%lx\n", + call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); + if (call_status != 0) { + printk("xics_enable_irq: irq=%x: ibm_int_on returned %lx\n", irq, call_status); return; } } -void -xics_disable_irq( - u_int virq - ) -{ - u_int irq; - unsigned long status; - long call_status; +void xics_disable_irq(u_int virq) +{ + u_int irq; + long call_status; virq -= XICS_IRQ_OFFSET; irq = virt_irq_to_real(virq); - call_status = rtas_call(ibm_int_off, 1, 1, (unsigned long*)&status, - irq); - if( call_status != 0 ) { - printk("xics_disable_irq: irq=%x: rtas_call failed, retn=%lx\n", + if (irq == XICS_IPI) + return; + + call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); + if (call_status != 0) { + printk("xics_disable_irq: irq=%x: ibm_int_off returned %lx\n", irq, call_status); return; } } -void -xics_end_irq( - u_int irq - ) +void xics_end_irq(u_int irq) { int cpu = smp_processor_id(); - ops->cppr_info(cpu, 0); /* actually the value overwritten by ack */ - iosync(); - ops->xirr_info_set(cpu, ((0xff<<24) | (virt_irq_to_real(irq-XICS_IRQ_OFFSET)))); iosync(); + ops->xirr_info_set(cpu, ((0xff<<24) | + (virt_irq_to_real(irq-XICS_IRQ_OFFSET)))); } -void -xics_mask_and_ack_irq(u_int irq) +void xics_mask_and_ack_irq(u_int irq) { int cpu = smp_processor_id(); - if( irq < XICS_IRQ_OFFSET ) { + if (irq < XICS_IRQ_OFFSET) { i8259_pic.ack(irq); iosync(); - ops->xirr_info_set(cpu, ((0xff<<24) | xics_irq_8259_cascade_real)); - iosync(); - } - else { - ops->cppr_info(cpu, 0xff); + ops->xirr_info_set(cpu, ((0xff<<24) | + xics_irq_8259_cascade_real)); iosync(); } } -int -xics_get_irq(struct pt_regs *regs) +int xics_get_irq(struct pt_regs *regs) { - u_int cpu = smp_processor_id(); - u_int vec; + u_int cpu = smp_processor_id(); + u_int vec; int irq; vec = ops->xirr_info_get(cpu); /* (vec >> 24) == old priority */ vec &= 0x00ffffff; + /* for sanity, this had better be < NR_IRQS - 16 */ - if( vec == xics_irq_8259_cascade_real ) { + if (vec == xics_irq_8259_cascade_real) { irq = i8259_irq(cpu); - if(irq == -1) { + if (irq == -1) { /* Spurious cascaded interrupt. Still must ack xics */ xics_end_irq(XICS_IRQ_OFFSET + xics_irq_8259_cascade); irq = -1; } - } else if( vec == XICS_IRQ_SPURIOUS ) { + } else if (vec == XICS_IRQ_SPURIOUS) { irq = -1; } else { irq = real_irq_to_virt(vec) + XICS_IRQ_OFFSET; @@ -250,35 +315,36 @@ xics_get_irq(struct pt_regs *regs) return irq; } -struct xics_ipi_struct { - volatile unsigned long value; -} ____cacheline_aligned; +#ifdef CONFIG_SMP extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; -#ifdef CONFIG_SMP void xics_ipi_action(int irq, void *dev_id, struct pt_regs *regs) { int cpu = smp_processor_id(); ops->qirr_info(cpu, 0xff); while (xics_ipi_message[cpu].value) { - if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, &xics_ipi_message[cpu].value)) { + if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, + &xics_ipi_message[cpu].value)) { mb(); smp_message_recv(PPC_MSG_CALL_FUNCTION, regs); } - if (test_and_clear_bit(PPC_MSG_RESCHEDULE, &xics_ipi_message[cpu].value)) { + if (test_and_clear_bit(PPC_MSG_RESCHEDULE, + &xics_ipi_message[cpu].value)) { mb(); smp_message_recv(PPC_MSG_RESCHEDULE, regs); } #if 0 - if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK, &xics_ipi_message[cpu].value)) { + if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK, + &xics_ipi_message[cpu].value)) { mb(); smp_message_recv(PPC_MSG_MIGRATE_TASK, regs); } #endif #ifdef CONFIG_XMON - if (test_and_clear_bit(PPC_MSG_XMON_BREAK, &xics_ipi_message[cpu].value)) { + if (test_and_clear_bit(PPC_MSG_XMON_BREAK, + &xics_ipi_message[cpu].value)) { mb(); smp_message_recv(PPC_MSG_XMON_BREAK, regs); } @@ -288,7 +354,7 @@ void xics_ipi_action(int irq, void *dev_ void xics_cause_IPI(int cpu) { - ops->qirr_info(cpu,0) ; + ops->qirr_info(cpu, IPI_PRIORITY); } void xics_setup_cpu(void) @@ -298,15 +364,20 @@ void xics_setup_cpu(void) ops->cppr_info(cpu, 0xff); iosync(); } + #endif /* CONFIG_SMP */ -void -xics_init_IRQ( void ) +void xics_init_IRQ(void) { int i; unsigned long intr_size = 0; struct device_node *np; uint *ireg, ilen, indx=0; + unsigned long intr_base = 0; + struct xics_interrupt_node { + unsigned long long addr; + unsigned long long size; + } inodes[NR_CPUS*2]; ppc64_boot_msg(0x20, "XICS Init"); @@ -391,12 +462,13 @@ nextnode: for (i = 0; i < NR_CPUS; ++i) { if (!cpu_possible(i)) continue; - xics_info.per_cpu[i] = - __ioremap((ulong)inodes[i].addr, - (ulong)inodes[i].size, _PAGE_NO_CACHE); + xics_per_cpu[i] = __ioremap((ulong)inodes[i].addr, + (ulong)inodes[i].size, + _PAGE_NO_CACHE); } #else - xics_info.per_cpu[0] = __ioremap((ulong)intr_base, intr_size, _PAGE_NO_CACHE); + xics_per_cpu[0] = __ioremap((ulong)intr_base, intr_size, + _PAGE_NO_CACHE); #endif /* CONFIG_SMP */ #ifdef CONFIG_PPC_PSERIES /* actually iSeries does not use any of xics...but it has link dependencies @@ -417,8 +489,8 @@ nextnode: ops->cppr_info(boot_cpuid, 0xff); iosync(); if (xics_irq_8259_cascade != -1) { - if (request_irq(xics_irq_8259_cascade + XICS_IRQ_OFFSET, no_action, - 0, "8259 cascade", 0)) + if (request_irq(xics_irq_8259_cascade + XICS_IRQ_OFFSET, + no_action, 0, "8259 cascade", 0)) printk(KERN_ERR "xics_init_IRQ: couldn't get 8259 cascade\n"); i8259_init(); } diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/arch/ppc64/xmon/xmon.c 504-ppc64-update/arch/ppc64/xmon/xmon.c --- 503-ppc64-scruffiness/arch/ppc64/xmon/xmon.c Mon Mar 17 21:43:40 2003 +++ 504-ppc64-update/arch/ppc64/xmon/xmon.c Sun Apr 20 22:21:42 2003 @@ -469,12 +469,10 @@ insert_bpts() } } - if (!__is_processor(PV_POWER4) && !__is_processor(PV_POWER4p)) { - if (dabr.enabled) - set_dabr(dabr.address); - if (iabr.enabled) - set_iabr(iabr.address); - } + if (cpu_has_dabr() && dabr.enabled) + set_dabr(dabr.address); + if (cpu_has_iabr() && iabr.enabled) + set_iabr(iabr.address); } static void @@ -486,10 +484,11 @@ remove_bpts() if (naca->platform != PLATFORM_PSERIES) return; - if (!__is_processor(PV_POWER4) && !__is_processor(PV_POWER4p)) { + + if (cpu_has_dabr()) set_dabr(0); + if (cpu_has_iabr()) set_iabr(0); - } bp = bpts; for (i = 0; i < NBPTS; ++i, ++bp) { @@ -778,8 +777,8 @@ bpt_cmds(void) cmd = inchar(); switch (cmd) { case 'd': /* bd - hardware data breakpoint */ - if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) { - printf("Not implemented on POWER4\n"); + if (cpu_has_dabr()) { + printf("Not implemented on this cpu\n"); break; } mode = 7; @@ -798,7 +797,7 @@ bpt_cmds(void) dabr.address = (dabr.address & ~7) | mode; break; case 'i': /* bi - hardware instr breakpoint */ - if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) { + if (cpu_has_iabr()) { printf("Not implemented on POWER4\n"); break; } diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/include/asm-ppc64/processor.h 504-ppc64-update/include/asm-ppc64/processor.h --- 503-ppc64-scruffiness/include/asm-ppc64/processor.h Mon Mar 17 21:43:49 2003 +++ 504-ppc64-update/include/asm-ppc64/processor.h Sun Apr 20 22:21:42 2003 @@ -595,6 +595,8 @@ GLUE(GLUE(.LT,NAME),_procname_end): asm volatile("mfasr %0" : "=r" (rval)); rval;}) #ifndef __ASSEMBLY__ +extern unsigned long *_get_SP(void); + extern int have_of; struct task_struct; @@ -739,6 +741,15 @@ static inline void prefetchw(const void #define cpu_has_noexecute() (processor_type() == PV_POWER4 || \ processor_type() == PV_POWER4p) + +/* XXX we have to call HV to set when in LPAR */ +#define cpu_has_dabr() (1) + +#define cpu_has_iabr() (processor_type() != PV_POWER4 && \ + processor_type() != PV_POWER4p) + +#define cpu_alignexc_sets_dsisr() (processor_type() != PV_POWER4 && \ + processor_type() != PV_POWER4p) #endif /* ASSEMBLY */ diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/include/asm-ppc64/unistd.h 504-ppc64-update/include/asm-ppc64/unistd.h --- 503-ppc64-scruffiness/include/asm-ppc64/unistd.h Tue Feb 25 23:03:50 2003 +++ 504-ppc64-update/include/asm-ppc64/unistd.h Sun Apr 20 22:21:42 2003 @@ -260,7 +260,7 @@ #define __NR_clock_getres 247 #define __NR_clock_nanosleep 248 -#define __NR_syscalls 249 +#define __NR_syscalls 239 #ifdef __KERNEL__ #define NR_syscalls __NR_syscalls #endif diff -urpN -X /home/fletch/.diff.exclude 503-ppc64-scruffiness/include/asm-ppc64/xics.h 504-ppc64-update/include/asm-ppc64/xics.h --- 503-ppc64-scruffiness/include/asm-ppc64/xics.h Thu Jan 9 19:16:12 2003 +++ 504-ppc64-update/include/asm-ppc64/xics.h Sun Apr 20 22:21:42 2003 @@ -12,7 +12,17 @@ #ifndef _PPC64_KERNEL_XICS_H #define _PPC64_KERNEL_XICS_H +#include + void xics_init_IRQ(void); int xics_get_irq(struct pt_regs *); +void xics_setup_cpu(void); +void xics_cause_IPI(int cpu); + +struct xics_ipi_struct { + volatile unsigned long value; +} ____cacheline_aligned; + +extern struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; #endif /* _PPC64_KERNEL_XICS_H */