# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
#   2004/04/22 15:15:17-04:00 len.brown@intel.com 
#   [ACPI] allow IRQ2 to be used in ACPI/IOAPIC mode
#   http://bugzilla.kernel.org/show_bug.cgi?id=2564
# 
# arch/x86_64/kernel/io_apic.c
#   2004/04/22 15:12:30-04:00 len.brown@intel.com +6 -10
#   allow IRQ2 to be used in ACPI/IOAPIC mode
# 
# arch/i386/kernel/io_apic.c
#   2004/04/22 15:12:30-04:00 len.brown@intel.com +6 -10
#   allow IRQ2 to be used in ACPI/IOAPIC mode
# 
diff -Nru a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c
--- a/arch/i386/kernel/io_apic.c	Thu Apr 22 15:15:23 2004
+++ b/arch/i386/kernel/io_apic.c	Thu Apr 22 15:15:23 2004
@@ -2259,18 +2259,10 @@
 
 /*
  *
- * IRQ's that are handled by the old PIC in all cases:
+ * IRQ's that are handled by the PIC in the MPS IOAPIC case.
  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
  *   Linux doesn't really care, as it's not actually used
  *   for any interrupt handling anyway.
- * - There used to be IRQ13 here as well, but all
- *   MPS-compliant must not use it for FPU coupling and we
- *   want to use exception 16 anyway.  And there are
- *   systems who connect it to an I/O APIC for other uses.
- *   Thus we don't mark it special any longer.
- *
- * Additionally, something is definitely wrong with irq9
- * on PIIX4 boards.
  */
 #define PIC_IRQS	(1 << PIC_CASCADE_IR)
 
@@ -2278,7 +2270,11 @@
 {
 	enable_IO_APIC();
 
-	io_apic_irqs = ~PIC_IRQS;
+	if (acpi_ioapic)
+		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
+	else
+		io_apic_irqs = ~PIC_IRQS;
+
 	printk("ENABLING IO-APIC IRQs\n");
 
 	/*
diff -Nru a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
--- a/arch/x86_64/kernel/io_apic.c	Thu Apr 22 15:15:23 2004
+++ b/arch/x86_64/kernel/io_apic.c	Thu Apr 22 15:15:23 2004
@@ -1726,18 +1726,10 @@
 
 /*
  *
- * IRQ's that are handled by the old PIC in all cases:
+ * IRQ's that are handled by the PIC in the MPS IOAPIC case.
  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
  *   Linux doesn't really care, as it's not actually used
  *   for any interrupt handling anyway.
- * - There used to be IRQ13 here as well, but all
- *   MPS-compliant must not use it for FPU coupling and we
- *   want to use exception 16 anyway.  And there are
- *   systems who connect it to an I/O APIC for other uses.
- *   Thus we don't mark it special any longer.
- *
- * Additionally, something is definitely wrong with irq9
- * on PIIX4 boards.
  */
 #define PIC_IRQS	(1<<2)
 
@@ -1745,7 +1737,11 @@
 {
 	enable_IO_APIC();
 
-	io_apic_irqs = ~PIC_IRQS;
+	if (acpi_ioapic)
+		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
+	else
+		io_apic_irqs = ~PIC_IRQS;
+
 	printk("ENABLING IO-APIC IRQs\n");
 
 	/*