# This is a BitKeeper generated patch for the following project: # Project Name: Linux kernel tree # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: # ChangeSet 1.1135 -> 1.1136 # arch/x86_64/kernel/mpparse.c 1.3 -> 1.4 # arch/x86_64/kernel/io_apic.c 1.4 -> 1.5 # include/asm-x86_64/io_apic.h 1.2 -> 1.3 # # The following is the BitKeeper ChangeSet Log # -------------------------------------------- # 03/10/28 len.brown@intel.com 1.1136 # [ACPI] fix x86_64 ACPI build in 2.4.22 by backporting from 2.4.23 # -------------------------------------------- # diff -Nru a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c --- a/arch/x86_64/kernel/io_apic.c Tue Oct 28 23:19:56 2003 +++ b/arch/x86_64/kernel/io_apic.c Tue Oct 28 23:19:56 2003 @@ -165,6 +165,14 @@ struct IO_APIC_route_entry entry; unsigned long flags; + /* Check delivery_mode to be sure we're not clearing an SMI pin */ + spin_lock_irqsave(&ioapic_lock, flags); + *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin); + *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin); + spin_unlock_irqrestore(&ioapic_lock, flags); + if (entry.delivery_mode == dest_SMI) + return; + /* * Disable it in the IO-APIC irq-routing table: */ @@ -194,9 +202,11 @@ int pirq_entries [MAX_PIRQS]; int pirqs_enabled; int skip_ioapic_setup; +int ioapic_force; static int __init noioapic_setup(char *str) { + ioapic_force = 1; skip_ioapic_setup = 1; return 1; } @@ -205,12 +215,66 @@ static int __init ioapic_setup(char *str) { + ioapic_force = 1; skip_ioapic_setup = 0; return 1; } __setup("apic", ioapic_setup); +#ifndef CONFIG_SMP +#include +#include +#include + +/* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC + off. Check for an Nvidia or VIA PCI bridge and turn it off. + Use pci direct infrastructure because this runs before the PCI subsystem. + + Can be overwritten with "apic" */ +void __init check_ioapic(void) +{ + int num,slot,func; + if (ioapic_force) + return; + + /* Poor man's PCI discovery */ + for (num = 0; num < 32; num++) { + for (slot = 0; slot < 32; slot++) { + for (func = 0; func < 8; func++) { + u32 class; + u32 vendor; + class = read_pci_config(num,slot,func, + PCI_CLASS_REVISION); + if (class == 0xffffffff) + break; + + if ((class >> 16) != PCI_CLASS_BRIDGE_PCI) + continue; + + vendor = read_pci_config(num, slot, func, + PCI_VENDOR_ID); + vendor &= 0xffff; + switch (vendor) { + case PCI_VENDOR_ID_NVIDIA: + case PCI_VENDOR_ID_VIA: + printk(KERN_INFO + "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n", + num,slot,vendor); + skip_ioapic_setup = 1; + return; + } + + /* No multi-function device? */ + u8 type = read_pci_config_byte(num,slot,func, + PCI_HEADER_TYPE); + if (!(type & 0x80)) + break; + } + } + } +} +#endif static int __init ioapic_pirq_setup(char *str) { @@ -1762,7 +1826,7 @@ } -int io_apic_set_pci_routing (int ioapic, int pin, int irq) +int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level ,int active_high_low) { struct IO_APIC_route_entry entry; unsigned long flags; @@ -1785,18 +1849,21 @@ entry.dest_mode = INT_DELIVERY_MODE; entry.dest.logical.logical_dest = TARGET_CPUS; entry.mask = 1; /* Disabled (masked) */ - entry.trigger = 1; /* Level sensitive */ - entry.polarity = 1; /* Low active */ + entry.trigger = edge_level; + entry.polarity = active_high_low; add_pin_to_irq(irq, ioapic, pin); entry.vector = assign_irq_vector(irq); printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> " - "IRQ %d)\n", ioapic, - mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq); + "IRQ %d) Mode:%i Active:%i\n", ioapic, + mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low); - irq_desc[irq].handler = &ioapic_level_irq_type; + if (edge_level) + irq_desc[irq].handler = &ioapic_level_irq_type; + else + irq_desc[irq].handler = &ioapic_edge_irq_type; set_intr_gate(entry.vector, interrupt[irq]); diff -Nru a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c --- a/arch/x86_64/kernel/mpparse.c Tue Oct 28 23:19:56 2003 +++ b/arch/x86_64/kernel/mpparse.c Tue Oct 28 23:19:56 2003 @@ -139,9 +139,12 @@ str[6] = 0; Dprintk("Bus #%d is %s\n", m->mpc_busid, str); - if (m->mpc_busid >= MAX_MP_BUSSES) { +#if MAX_MP_BUSSES < 256 + if ((long)m->mpc_busid >= MAX_MP_BUSSES) { printk(KERN_ERR "MAX_MP_BUSSES ERROR mpc_busid %d, max %d\n", m->mpc_busid, MAX_MP_BUSSES); - } else if (strncmp(str, "ISA", 3) == 0) { + } else +#endif + if (strncmp(str, "ISA", 3) == 0) { mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; } else if (strncmp(str, "EISA", 4) == 0) { mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; @@ -713,7 +716,7 @@ return i; } - printk(KERN_ERR "ERROR: Unable to locate IOAPIC for IRQ %d/n", irq); + printk(KERN_ERR "ERROR: Unable to locate IOAPIC for IRQ %d\n", irq); return -1; } @@ -756,7 +759,7 @@ mp_ioapic_routing[idx].irq_end = irq_base + io_apic_get_redir_entries(idx); - printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, " + printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " "IRQ %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, mp_ioapic_routing[idx].irq_start, @@ -883,8 +886,6 @@ #ifndef CONFIG_ACPI_HT_ONLY -/* Ensure the ACPI SCI interrupt level is active low, edge-triggered */ - extern FADT_DESCRIPTOR acpi_fadt; void __init mp_config_ioapic_for_sci(int irq) @@ -893,6 +894,7 @@ int ioapic_pin; struct acpi_table_madt* madt; struct acpi_table_int_src_ovr *entry = NULL; + acpi_interrupt_flags flags; void *madt_end; acpi_status status; @@ -911,23 +913,42 @@ while ((void *) entry < madt_end) { if (entry->header.type == ACPI_MADT_INT_SRC_OVR && - acpi_fadt.sci_int == entry->global_irq) - return; + acpi_fadt.sci_int == entry->bus_irq) + goto found; entry = (struct acpi_table_int_src_ovr *) ((unsigned long) entry + entry->header.length); } } + /* + * Although the ACPI spec says that the SCI should be level/low + * don't reprogram it unless there is an explicit MADT OVR entry + * instructing us to do so -- otherwise we break Tyan boards which + * have the SCI wired edge/high but no MADT OVR. + */ + return; + +found: + /* + * See the note at the end of ACPI 2.0b section + * 5.2.10.8 for what this is about. + */ + flags = entry->flags; + acpi_fadt.sci_int = entry->global_irq; + irq = entry->global_irq; ioapic = mp_find_ioapic(irq); ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start; - io_apic_set_pci_routing(ioapic, ioapic_pin, irq); + io_apic_set_pci_routing(ioapic, ioapic_pin, irq, + (flags.trigger >> 1) , (flags.polarity >> 1)); } #endif /*CONFIG_ACPI_HT_ONLY*/ +int acpi_tolerant; + #ifdef CONFIG_ACPI_PCI void __init mp_parse_prt (void) @@ -939,6 +960,8 @@ int ioapic_pin = 0; int irq = 0; int idx, bit = 0; + int edge_level = 0; + int active_high_low = 0; /* * Parsing through the PCI Interrupt Routing Table (PRT) and program @@ -949,13 +972,23 @@ /* Need to get irq for dynamic entry */ if (entry->link.handle) { - irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index); + irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low); if (!irq) continue; - } else + } else { + edge_level = 1; + active_high_low = 1; irq = entry->link.index; + } irq = entry->link.index; + + /* Don't set up the ACPI SCI because it's already set up */ + if (acpi_fadt.sci_int == irq) { + entry->irq = irq; /*we still need to set entry's irq*/ + continue; + } + ioapic = mp_find_ioapic(irq); if (ioapic < 0) continue; @@ -983,7 +1016,7 @@ mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<irq = irq; diff -Nru a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h --- a/include/asm-x86_64/io_apic.h Tue Oct 28 23:19:56 2003 +++ b/include/asm-x86_64/io_apic.h Tue Oct 28 23:19:56 2003 @@ -148,6 +148,6 @@ extern int io_apic_get_unique_id (int ioapic, int apic_id); extern int io_apic_get_version (int ioapic); extern int io_apic_get_redir_entries (int ioapic); -extern int io_apic_set_pci_routing (int ioapic, int pin, int irq); +extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int); #endif