Ð þíwHx(ÿ0à(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53arm,armv8HcpuTXpsciflcpu@1arm,cortex-a53arm,armv8HcpuTXpsciflcpu@2arm,cortex-a53arm,armv8HcpuTXpsciflcpu@3arm,cortex-a53arm,armv8HcpuTXpsciflcpu@100arm,cortex-a53arm,armv8HcpuTXpsciflcpu@101arm,cortex-a53arm,armv8HcpuTXpsciflcpu@102arm,cortex-a53arm,armv8HcpuTXpsciflcpu@103arm,cortex-a53arm,armv8HcpuTXpscif l interrupt-controller@f6801000 arm,gic-400@Tö€ö€ ö€@ ö€` t… š ÿfltimerarm,armv8-timer 0š ÿÿ ÿ ÿsoc simple-bus+¥ao_ctrl@f7800000hisilicon,hi6220-aoctrlsysconT÷€ ¬f l sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsysconT÷ ¬f l media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconTôA¬pm_ctrl@f7032000hisilicon,hi6220-pmctrlsysconT÷ ¬uart@f8015000arm,pl011arm,primecellTøP š$¹ $ $Àuartclkapb_pclkuart@f7111000arm,pl011arm,primecellT÷ š%¹  Àuartclkapb_pclk Ìdisableduart@f7112000arm,pl011arm,primecellT÷  š&¹  Àuartclkapb_pclk Ìdisableduart@f7113000arm,pl011arm,primecellT÷0 š'¹  Àuartclkapb_pclkuart@f7114000arm,pl011arm,primecellT÷@ š(¹  Àuartclkapb_pclk ÌdisabledaliasesÓ/soc/uart@f8015000Û/soc/uart@f7111000ã/soc/uart@f7112000ë/soc/uart@f7113000chosenóserial3:115200n8memory@0HmemoryT@ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodlinux,phandle#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cellsclocksclock-namesstatusserial0serial1serial2serial3stdout-path