Return-Path: X-Original-To: colinomail@colino.net Delivered-To: colinomail@colino.net Received: by paperstreet.colino.net (Postfix, from userid 1015) id 48C16101D9; Wed, 6 Apr 2005 21:58:29 +0200 (CEST) Received: from ylpvm01.prodigy.net (ylpvm01-ext.prodigy.net [207.115.57.32]) by paperstreet.colino.net (Postfix) with ESMTP id 57B83101D9 for ; Wed, 6 Apr 2005 21:58:14 +0200 (CEST) Received: from ascent (adsl-69-107-61-180.dsl.pltn13.pacbell.net [69.107.61.180]) by ylpvm01.prodigy.net (8.12.10 outbound/8.12.10) with ESMTP id j36JwD4H022078; Wed, 6 Apr 2005 15:58:14 -0400 From: David Brownell To: linux-usb-devel@lists.sourceforge.net Subject: [patch 2.6.12-rc2] ehci misc updates, notably port power switching Date: Wed, 6 Apr 2005 12:58:13 -0700 User-Agent: KMail/1.7.1 Cc: Colin Leroy References: <20050405204449.5ab0cdea@jack.colino.net> <200504051353.36788.david-b@pacbell.net> In-Reply-To: <200504051353.36788.david-b@pacbell.net> MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_W9DVCdbpudi3RMT" Message-Id: <200504061258.14092.david-b@pacbell.net> X-Spam-Checker-Version: SpamAssassin 2.64 (2004-01-11) on paperstreet.colino.net X-Spam-Level: X-Spam-Status: No, hits=0.1 required=5.0 tests=AWL autolearn=no version=2.64 X-UIDL: ^UO!!"\l!!$=I!!*)8!! Status: RO --Boundary-00=_W9DVCdbpudi3RMT Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Here's the promised update for EHCI port power switching. - Dave --Boundary-00=_W9DVCdbpudi3RMT Content-Type: text/x-diff; charset="us-ascii"; name="ehci-0405.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="ehci-0405.patch" Miscellaneous updates for EHCI. - Mostly updates the power switching on EHCI controllers. One routine centralizes the "power on/off all ports" logic, and the capability to do that is reported more correctly. - Courtesy Colin Leroy, a patch to always power up ports after resumes which didn't keep a USB device suspended. The reset-everything logic powers down those ports (on some hardware) so something needs to turn them back on. - Minor tweaks/bugfixes for the debug port support. Signed-off-by: David Brownell --- a/drivers/usb/host/ehci-hcd.c 2005-04-05 15:04:13 -07:00 +++ b/drivers/usb/host/ehci-hcd.c 2005-04-05 15:04:13 -07:00 @@ -346,6 +347,22 @@ return 0; } +static void ehci_port_power (struct ehci_hcd *ehci, int is_on) +{ + unsigned port; + + if (!HCS_PPC (ehci->hcs_params)) + return; + + ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); + for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) + (void) ehci_hub_control(ehci_to_hcd(ehci), + is_on ? SetPortFeature : ClearPortFeature, + USB_PORT_FEAT_POWER, + port--, NULL, 0); + msleep(20); +} + /* called by khubd or root hub init threads */ @@ -362,8 +379,10 @@ dbg_hcs_params (ehci, "reset"); dbg_hcc_params (ehci, "reset"); + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = readl (&ehci->caps->hcs_params); + #ifdef CONFIG_PCI - /* EHCI 0.96 and later may have "extended capabilities" */ if (hcd->self.controller->bus == &pci_bus_type) { struct pci_dev *pdev = to_pci_dev(hcd->self.controller); @@ -383,9 +402,30 @@ break; } + /* optional debug port, normally in the first BAR */ + temp = pci_find_capability (pdev, 0x0a); + if (temp) { + pci_read_config_dword(pdev, temp, &temp); + temp >>= 16; + if ((temp & (3 << 13)) == (1 << 13)) { + temp &= 0x1fff; + ehci->debug = hcd->regs + temp; + temp = readl (&ehci->debug->control); + ehci_info (ehci, "debug port %d%s\n", + HCS_DEBUG_PORT(ehci->hcs_params), + (temp & DBGP_ENABLED) + ? " IN USE" + : ""); + if (!(temp & DBGP_ENABLED)) + ehci->debug = NULL; + } + } + temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params)); } else temp = 0; + + /* EHCI 0.96 and later may have "extended capabilities" */ while (temp && count--) { u32 cap; @@ -414,8 +454,7 @@ ehci_reset (ehci); #endif - /* cache this readonly data; minimize PCI reads */ - ehci->hcs_params = readl (&ehci->caps->hcs_params); + ehci_port_power (ehci, 0); /* at least the Genesys GL880S needs fixup here */ temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); @@ -657,16 +696,11 @@ static void ehci_stop (struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci (hcd); - u8 rh_ports, port; ehci_dbg (ehci, "stop\n"); /* Turn off port power on all root hub ports. */ - rh_ports = HCS_N_PORTS (ehci->hcs_params); - for (port = 1; port <= rh_ports; port++) - (void) ehci_hub_control(hcd, - ClearPortFeature, USB_PORT_FEAT_POWER, - port, NULL, 0); + ehci_port_power (ehci, 0); /* no more interrupts ... */ del_timer_sync (&ehci->watchdog); @@ -748,7 +782,6 @@ unsigned port; struct usb_device *root = hcd->self.root_hub; int retval = -EINVAL; - int powerup = 0; // maybe restore (PCI) FLADJ @@ -766,8 +799,6 @@ up (&hcd->self.root_hub->serialize); break; } - if ((status & PORT_POWER) == 0) - powerup = 1; if (!root->children [port]) continue; dbg_port (ehci, __FUNCTION__, port + 1, status); @@ -794,16 +825,9 @@ retval = ehci_start (hcd); /* here we "know" root ports should always stay powered; - * but some controllers may lost all power. + * but some controllers may lose all power. */ - if (powerup) { - ehci_dbg (ehci, "...powerup ports...\n"); - for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) - (void) ehci_hub_control(hcd, - SetPortFeature, USB_PORT_FEAT_POWER, - port--, NULL, 0); - msleep(20); - } + ehci_port_power (ehci, 1); } return retval; --- a/drivers/usb/host/ehci-hub.c 2005-04-05 15:04:13 -07:00 +++ b/drivers/usb/host/ehci-hub.c 2005-04-05 15:04:13 -07:00 @@ -281,6 +281,8 @@ temp = 0x0008; /* per-port overcurrent reporting */ if (HCS_PPC (ehci->hcs_params)) temp |= 0x0001; /* per-port power control */ + else + temp |= 0x0002; /* no power switching */ #if 0 // re-enable when we support USB_PORT_FEAT_INDICATOR below. if (HCS_INDICATOR (ehci->hcs_params)) --- a/drivers/usb/host/ehci.h 2005-04-05 15:04:13 -07:00 +++ b/drivers/usb/host/ehci.h 2005-04-05 15:04:13 -07:00 @@ -47,6 +47,12 @@ #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ struct ehci_hcd { /* one per controller */ + /* glue to PCI and HCD framework */ + struct ehci_caps __iomem *caps; + struct ehci_regs __iomem *regs; + struct ehci_dbg_port __iomem *debug; + + __u32 hcs_params; /* cached register copy */ spinlock_t lock; /* async schedule support */ @@ -84,11 +90,6 @@ unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ - /* glue to PCI and HCD framework */ - struct ehci_caps __iomem *caps; - struct ehci_regs __iomem *regs; - __u32 hcs_params; /* cached register copy */ - /* irq statistics */ #ifdef EHCI_STATS struct ehci_stats stats; @@ -165,7 +166,7 @@ /* these fields are specified as 8 and 16 bit registers, * but some hosts can't perform 8 or 16 bit PCI accesses. */ - u32 hc_capbase; + u32 hc_capbase; #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ u32 hcs_params; /* HCSPARAMS - offset 0x4 */ @@ -273,7 +274,7 @@ #define DBGP_ENABLED (1<<28) #define DBGP_DONE (1<<16) #define DBGP_INUSE (1<<10) -#define DBGP_ERRCODE(x) (((x)>>7)&0x0f) +#define DBGP_ERRCODE(x) (((x)>>7)&0x07) # define DBGP_ERR_BAD 1 # define DBGP_ERR_SIGNAL 2 #define DBGP_ERROR (1<<6) @@ -282,11 +283,11 @@ #define DBGP_LEN(x) (((x)>>0)&0x0f) u32 pids; #define DBGP_PID_GET(x) (((x)>>16)&0xff) -#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)); +#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) u32 data03; u32 data47; u32 address; -#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)); +#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) } __attribute__ ((packed)); /*-------------------------------------------------------------------------*/ --Boundary-00=_W9DVCdbpudi3RMT--