diff -urN -X /home/andrea/bin/dontdiff 2.4.0ac3-fxsr/arch/i386/config.in 2.4.0ac3-fxsr-sfence/arch/i386/config.in --- 2.4.0ac3-fxsr/arch/i386/config.in Mon Jan 8 21:43:16 2001 +++ 2.4.0ac3-fxsr-sfence/arch/i386/config.in Mon Jan 8 21:46:47 2001 @@ -45,8 +45,6 @@ # Define implied options from the CPU selection here # -unset CONFIG_X86_SFENCE - if [ "$CONFIG_M386" = "y" ]; then define_bool CONFIG_X86_CMPXCHG n define_int CONFIG_X86_L1_CACHE_SHIFT 4 @@ -93,7 +91,6 @@ define_bool CONFIG_X86_GOOD_APIC y define_bool CONFIG_X86_PGE y define_bool CONFIG_X86_USE_PPRO_CHECKSUM y - define_bool CONFIG_X86_SFENCE y fi if [ "$CONFIG_MPENTIUM4" = "y" ]; then define_int CONFIG_X86_L1_CACHE_SHIFT 7 @@ -101,7 +98,6 @@ define_bool CONFIG_X86_GOOD_APIC y define_bool CONFIG_X86_PGE y define_bool CONFIG_X86_USE_PPRO_CHECKSUM y - define_bool CONFIG_X86_SFENCE y fi if [ "$CONFIG_MK6" = "y" ]; then define_int CONFIG_X86_L1_CACHE_SHIFT 5 @@ -116,7 +112,6 @@ define_bool CONFIG_X86_USE_3DNOW y define_bool CONFIG_X86_PGE y define_bool CONFIG_X86_USE_PPRO_CHECKSUM y - define_bool CONFIG_X86_SFENCE y fi if [ "$CONFIG_MCRUSOE" = "y" ]; then define_int CONFIG_X86_L1_CACHE_SHIFT 5 diff -urN -X /home/andrea/bin/dontdiff 2.4.0ac3-fxsr/include/asm-i386/system.h 2.4.0ac3-fxsr-sfence/include/asm-i386/system.h --- 2.4.0ac3-fxsr/include/asm-i386/system.h Mon Jan 8 06:32:58 2001 +++ 2.4.0ac3-fxsr-sfence/include/asm-i386/system.h Mon Jan 8 21:42:06 2001 @@ -267,15 +267,8 @@ * I expect future Intel CPU's to have a weaker ordering, * but I'd also expect them to finally get their act together * and add some real memory barriers if so. - * - * The Pentium III does add a real memory barrier with the - * sfence instruction, so we use that where appropriate. */ -#ifndef CONFIG_X86_SFENCE #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory") -#else -#define mb() __asm__ __volatile__ ("sfence": : :"memory") -#endif #define rmb() mb() #define wmb() __asm__ __volatile__ ("": : :"memory")