diff -urN 2.2.19pre2/Documentation/Configure.help cacheline/Documentation/Configure.help
--- 2.2.19pre2/Documentation/Configure.help	Wed Dec 20 02:31:10 2000
+++ cacheline/Documentation/Configure.help	Wed Dec 20 03:13:09 2000
@@ -1768,6 +1768,8 @@
      K6-3D, as well as the Cyrix/VIA CyrixIII
    - "PPro" for the Cyrix/IBM/National Semiconductor 6x86MX, MII and
      Intel Pentium II/Pentium Pro.
+   - "K7" for the AMD Athlon K7 CPUs with 64 bytes large L1 cachelines.
+   - "P4" for the Intel Pentium4 CPUs with 128 bytes large L1 cachelines.
 
   If you don't know what to do, choose "386".
 
diff -urN 2.2.19pre2/arch/i386/Makefile cacheline/arch/i386/Makefile
--- 2.2.19pre2/arch/i386/Makefile	Wed Aug  2 19:24:47 2000
+++ cacheline/arch/i386/Makefile	Wed Dec 20 03:13:09 2000
@@ -43,6 +43,14 @@
 CFLAGS := $(CFLAGS) -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -DCPU=686
 endif
 
+ifdef CONFIG_M686_L1_64
+CFLAGS := $(CFLAGS) -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -DCPU=686
+endif
+
+ifdef CONFIG_M686_L1_128
+CFLAGS := $(CFLAGS) -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -DCPU=686
+endif
+
 HEAD := arch/i386/kernel/head.o arch/i386/kernel/init_task.o
 
 SUBDIRS := $(SUBDIRS) arch/i386/kernel arch/i386/mm arch/i386/lib
diff -urN 2.2.19pre2/arch/i386/config.in cacheline/arch/i386/config.in
--- 2.2.19pre2/arch/i386/config.in	Wed Dec 20 02:31:10 2000
+++ cacheline/arch/i386/config.in	Wed Dec 20 03:14:59 2000
@@ -16,7 +16,9 @@
 	 486/Cx486			CONFIG_M486	\
 	 586/K5/5x86/6x86		CONFIG_M586	\
 	 Pentium/K6/TSC/CyrixIII	CONFIG_M586TSC	\
-	 PPro/6x86MX			CONFIG_M686" PPro
+	 PPro/6x86MX			CONFIG_M686	\
+	 K7				CONFIG_M686_L1_64 \
+	 P4				CONFIG_M686_L1_128" PPro
 #
 # Define implied options from the CPU selection here
 #
@@ -26,10 +28,10 @@
   define_bool CONFIG_X86_BSWAP y
   define_bool CONFIG_X86_POPAD_OK y
 fi
-if [ "$CONFIG_M686" = "y" -o "$CONFIG_M586TSC" = "y" ]; then
+if [ "$CONFIG_M686" = "y" -o "$CONFIG_M586TSC" = "y" -o "$CONFIG_M686_L1_64" = "y" -o "$CONFIG_M686_L1_128" = "y" ]; then
   define_bool CONFIG_X86_TSC y
 fi
-if [ "$CONFIG_M686" = "y" ]; then
+if [ "$CONFIG_M686" = "y" -o "$CONFIG_M686_L1_64" = "y" -o "$CONFIG_M686_L1_128" = "y" ]; then
   define_bool CONFIG_X86_GOOD_APIC y
 fi
 
diff -urN 2.2.19pre2/arch/i386/kernel/irq.h cacheline/arch/i386/kernel/irq.h
--- 2.2.19pre2/arch/i386/kernel/irq.h	Tue Nov 14 03:39:08 2000
+++ cacheline/arch/i386/kernel/irq.h	Wed Dec 20 03:13:09 2000
@@ -40,7 +40,9 @@
 	struct hw_interrupt_type *handler;	/* handle/enable/disable functions */
 	struct irqaction *action;		/* IRQ action list */
 	unsigned int depth;			/* Disable depth for nested irq disables */
-	unsigned int unused[4];
+#ifdef CONFIG_SMP
+	unsigned int unused[L1_CACHE_BYTES-16];
+#endif
 } irq_desc_t;
 
 /*
diff -urN 2.2.19pre2/arch/i386/kernel/smp.c cacheline/arch/i386/kernel/smp.c
--- 2.2.19pre2/arch/i386/kernel/smp.c	Mon Dec 11 16:57:44 2000
+++ cacheline/arch/i386/kernel/smp.c	Wed Dec 20 03:13:09 2000
@@ -112,7 +112,7 @@
 static volatile unsigned long cpu_callout_map[NR_CPUS] = {0,};	/* We always use 0 the rest is ready for parallel delivery */
 volatile unsigned long smp_invalidate_needed;		/* Used for the invalidate map that's also checked in the spinlock */
 volatile unsigned long kstack_ptr;			/* Stack vector for booting CPUs			*/
-struct cpuinfo_x86 cpu_data[NR_CPUS];			/* Per CPU bogomips and other parameters 		*/
+struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned = { { 0, }, };			/* Per CPU bogomips and other parameters 		*/
 static unsigned int num_processors = 1;			/* Internal processor count				*/
 unsigned char boot_cpu_id = 0;				/* Processor that is doing the boot up 			*/
 static int smp_activated = 0;				/* Tripped once we need to start cross invalidating 	*/
diff -urN 2.2.19pre2/arch/i386/vmlinux.lds.S cacheline/arch/i386/vmlinux.lds.S
--- 2.2.19pre2/arch/i386/vmlinux.lds.S	Mon Dec 11 16:57:45 2000
+++ cacheline/arch/i386/vmlinux.lds.S	Wed Dec 20 03:13:09 2000
@@ -1,6 +1,7 @@
 /* ld script to make i386 Linux kernel
  * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>;
  */
+#include <asm/cache.h>
 OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
 OUTPUT_ARCH(i386)
 ENTRY(_start)
@@ -53,7 +54,7 @@
   __init_end = .;
 
 
-  . = ALIGN(32);
+  . = ALIGN(L1_CACHE_BYTES);
   .data.cacheline_aligned : { *(.data.cacheline_aligned) }
 
   . = ALIGN(4096);
diff -urN 2.2.19pre2/include/asm-i386/cache.h cacheline/include/asm-i386/cache.h
--- 2.2.19pre2/include/asm-i386/cache.h	Mon Jan 17 16:44:44 2000
+++ cacheline/include/asm-i386/cache.h	Wed Dec 20 03:13:09 2000
@@ -5,7 +5,11 @@
 #define __ARCH_I386_CACHE_H
 
 /* bytes per L1 cache line */
-#if    CPU==586 || CPU==686
+#ifdef CONFIG_M686_L1_64
+#define        L1_CACHE_BYTES  64
+#elif defined(CONFIG_M686_L1_128)
+#define        L1_CACHE_BYTES  128
+#elif CPU==586 || CPU==686
 #define        L1_CACHE_BYTES  32
 #else
 #define        L1_CACHE_BYTES  16
diff -urN 2.2.19pre2/include/asm-i386/processor.h cacheline/include/asm-i386/processor.h
--- 2.2.19pre2/include/asm-i386/processor.h	Wed Dec 20 02:31:11 2000
+++ cacheline/include/asm-i386/processor.h	Wed Dec 20 03:13:09 2000
@@ -40,7 +40,7 @@
 	unsigned long *pgd_quick;
 	unsigned long *pte_quick;
 	unsigned long pgtable_cache_sz;
-};
+} __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 #define X86_VENDOR_INTEL 0
 #define X86_VENDOR_CYRIX 1