From: Roland Dreier First half of the MSI rewrite: pure cleanup. Use proper pci_read_config_xxx() and pci_write_config_xxx() functions instead of accessing raw dev->bus->ops. Signed-off-by: Andrew Morton --- 25-akpm/drivers/pci/msi.c | 103 ++++++++++++++++++++-------------------------- 1 files changed, 45 insertions(+), 58 deletions(-) diff -puN drivers/pci/msi.c~msi-stop-using-dev-bus-ops-directly-in-msic drivers/pci/msi.c --- 25/drivers/pci/msi.c~msi-stop-using-dev-bus-ops-directly-in-msic Wed Jul 28 15:18:53 2004 +++ 25-akpm/drivers/pci/msi.c Wed Jul 28 15:18:53 2004 @@ -64,15 +64,13 @@ static void msi_set_mask_bit(unsigned in case PCI_CAP_ID_MSI: { int pos; - unsigned int mask_bits; + u32 mask_bits; pos = entry->mask_base; - entry->dev->bus->ops->read(entry->dev->bus, entry->dev->devfn, - pos, 4, &mask_bits); + pci_read_config_dword(entry->dev, pos, &mask_bits); mask_bits &= ~(1); mask_bits |= flag; - entry->dev->bus->ops->write(entry->dev->bus, entry->dev->devfn, - pos, 4, mask_bits); + pci_write_config_dword(entry->dev, pos, mask_bits); break; } case PCI_CAP_ID_MSIX: @@ -105,15 +103,13 @@ static void set_msi_affinity(unsigned in if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI))) return; - entry->dev->bus->ops->read(entry->dev->bus, entry->dev->devfn, - msi_lower_address_reg(pos), 4, + pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), &address.lo_address.value); address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) << MSI_TARGET_CPU_SHIFT); entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask); - entry->dev->bus->ops->write(entry->dev->bus, entry->dev->devfn, - msi_lower_address_reg(pos), 4, + pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), address.lo_address.value); break; } @@ -383,51 +379,45 @@ static void irq_handler_init(int cap_id, static void enable_msi_mode(struct pci_dev *dev, int pos, int type) { - u32 control; + u16 control; - dev->bus->ops->read(dev->bus, dev->devfn, - msi_control_reg(pos), 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); if (type == PCI_CAP_ID_MSI) { /* Set enabled bits to single MSI & enable MSI_enable bit */ msi_enable(control, 1); - dev->bus->ops->write(dev->bus, dev->devfn, - msi_control_reg(pos), 2, control); + pci_write_config_word(dev, msi_control_reg(pos), control); } else { msix_enable(control); - dev->bus->ops->write(dev->bus, dev->devfn, - msi_control_reg(pos), 2, control); + pci_write_config_word(dev, msi_control_reg(pos), control); } if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { /* PCI Express Endpoint device detected */ - u32 cmd; - dev->bus->ops->read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); + u16 cmd; + pci_read_config_word(dev, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_INTX_DISABLE; - dev->bus->ops->write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); } } static void disable_msi_mode(struct pci_dev *dev, int pos, int type) { - u32 control; + u16 control; - dev->bus->ops->read(dev->bus, dev->devfn, - msi_control_reg(pos), 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); if (type == PCI_CAP_ID_MSI) { /* Set enabled bits to single MSI & enable MSI_enable bit */ msi_disable(control); - dev->bus->ops->write(dev->bus, dev->devfn, - msi_control_reg(pos), 2, control); + pci_write_config_word(dev, msi_control_reg(pos), control); } else { msix_disable(control); - dev->bus->ops->write(dev->bus, dev->devfn, - msi_control_reg(pos), 2, control); + pci_write_config_word(dev, msi_control_reg(pos), control); } if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { /* PCI Express Endpoint device detected */ - u32 cmd; - dev->bus->ops->read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); + u16 cmd; + pci_read_config_word(dev, PCI_COMMAND, &cmd); cmd &= ~PCI_COMMAND_INTX_DISABLE; - dev->bus->ops->write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); } } @@ -480,14 +470,13 @@ static int msi_capability_init(struct pc struct msg_address address; struct msg_data data; int pos, vector; - u32 control; + u16 control; pos = pci_find_capability(dev, PCI_CAP_ID_MSI); if (!pos) return -EINVAL; - dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), - 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); if (control & PCI_MSI_FLAGS_ENABLE) return 0; @@ -521,27 +510,27 @@ static int msi_capability_init(struct pc msi_data_init(&data, vector); entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >> MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); - dev->bus->ops->write(dev->bus, dev->devfn, msi_lower_address_reg(pos), - 4, address.lo_address.value); + pci_write_config_dword(dev, msi_lower_address_reg(pos), + address.lo_address.value); if (is_64bit_address(control)) { - dev->bus->ops->write(dev->bus, dev->devfn, - msi_upper_address_reg(pos), 4, address.hi_address); - dev->bus->ops->write(dev->bus, dev->devfn, - msi_data_reg(pos, 1), 2, *((u32*)&data)); + pci_write_config_dword(dev, + msi_upper_address_reg(pos), address.hi_address); + pci_write_config_word(dev, + msi_data_reg(pos, 1), *((u32*)&data)); } else - dev->bus->ops->write(dev->bus, dev->devfn, - msi_data_reg(pos, 0), 2, *((u32*)&data)); + pci_write_config_word(dev, + msi_data_reg(pos, 0), *((u32*)&data)); if (entry->msi_attrib.maskbit) { unsigned int maskbits, temp; /* All MSIs are unmasked by default, Mask them all */ - dev->bus->ops->read(dev->bus, dev->devfn, - msi_mask_bits_reg(pos, is_64bit_address(control)), 4, + pci_read_config_dword(dev, + msi_mask_bits_reg(pos, is_64bit_address(control)), &maskbits); temp = (1 << multi_msi_capable(control)); temp = ((temp - 1) & ~temp); maskbits |= temp; - dev->bus->ops->write(dev->bus, dev->devfn, - msi_mask_bits_reg(pos, is_64bit_address(control)), 4, + pci_write_config_dword(dev, + msi_mask_bits_reg(pos, is_64bit_address(control)), maskbits); } attach_msi_entry(entry, vector); @@ -571,7 +560,7 @@ static int msix_capability_init(struct p struct msg_data data; int vector = 0, pos, dev_msi_cap, i; u32 phys_addr, table_offset; - u32 control; + u16 control; u8 bir; void *base; @@ -580,8 +569,7 @@ static int msix_capability_init(struct p return -EINVAL; /* Request & Map MSI-X table region */ - dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2, - &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); if (control & PCI_MSIX_FLAGS_ENABLE) return 0; @@ -592,8 +580,8 @@ static int msix_capability_init(struct p } dev_msi_cap = multi_msix_capable(control); - dev->bus->ops->read(dev->bus, dev->devfn, - msix_table_offset_reg(pos), 4, &table_offset); + pci_read_config_dword(dev, msix_table_offset_reg(pos), + &table_offset); bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); phys_addr = pci_resource_start (dev, bir); phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK); @@ -728,7 +716,8 @@ static int msi_alloc_vector(struct pci_d struct msg_address address; struct msg_data data; int i, offset, pos, dev_msi_cap, vector; - u32 low_address, control; + u32 low_address; + u16 control; unsigned long base = 0L; unsigned long flags; @@ -742,8 +731,7 @@ static int msi_alloc_vector(struct pci_d spin_unlock_irqrestore(&msi_lock, flags); pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); - dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), - 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); dev_msi_cap = multi_msix_capable(control); for (i = 1; i < dev_msi_cap; i++) { if (!(low_address = readl(base + i * PCI_MSIX_ENTRY_SIZE))) @@ -838,7 +826,7 @@ int msi_alloc_vectors(struct pci_dev* de struct msi_desc *entry; int i, head, pos, vec, free_vectors, alloc_vectors; int *vectors = (int *)vector; - u32 control; + u16 control; unsigned long flags; if (!pci_msi_enable || !dev) @@ -847,7 +835,7 @@ int msi_alloc_vectors(struct pci_dev* de if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX))) return -EINVAL; - dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); if (nvec > multi_msix_capable(control)) return -EINVAL; @@ -980,14 +968,13 @@ void msi_remove_pci_irq_vectors(struct p if (type == PCI_CAP_ID_MSIX) { int i, pos, dev_msi_cap; u32 phys_addr, table_offset; - u32 control; + u16 control; u8 bir; pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); - dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2, &control); + pci_read_config_word(dev, msi_control_reg(pos), &control); dev_msi_cap = multi_msix_capable(control); - dev->bus->ops->read(dev->bus, dev->devfn, - msix_table_offset_reg(pos), 4, &table_offset); + pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); phys_addr = pci_resource_start (dev, bir); phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK); _