# This is a BitKeeper generated diff -Nru style patch.
#
# ChangeSet
# 2004/04/02 13:17:06-05:00 jgarzik@redhat.com
# Merge redhat.com:/spare/repo/linux-2.6
# into redhat.com:/spare/repo/net-drivers-2.6
#
# include/linux/pci_ids.h
# 2004/04/02 13:17:03-05:00 jgarzik@redhat.com +0 -0
# Auto merged
#
# MAINTAINERS
# 2004/04/02 13:17:03-05:00 jgarzik@redhat.com +0 -0
# Auto merged
#
# ChangeSet
# 2004/04/01 13:32:07-05:00 akpm@osdl.org
# [PATCH] com20020-isa.c warning fix
#
# From: "Luiz Fernando N. Capitulino" <lcapitulino@prefeitura.sp.gov.br>
#
# drivers/net/arcnet/com20020-isa.c:188: warning: unused variable `dev'
# drivers/net/arcnet/com20020-isa.c:189: warning: unused variable `lp'
#
# drivers/net/arcnet/com20020-isa.c
# 2004/03/31 10:25:39-05:00 akpm@osdl.org +0 -2
# com20020-isa.c warning fix
#
# ChangeSet
# 2004/04/01 13:31:58-05:00 scott.feldman@intel.com
# [PATCH] Update MAINTAINERS with new e100/e1000/ixgb maintainers
#
# Jeff, Adding John/Ganesh/Ayyappan for e100/e100/ixgb in 2.6. Keeping
# myself on for e100 for a couple more 2.6.x releases.
#
# -scott
#
# MAINTAINERS
# 2004/03/26 13:11:51-05:00 scott.feldman@intel.com +15 -5
# Update MAINTAINERS with new e100/e1000/ixgb maintainers
#
# ChangeSet
# 2004/03/23 12:55:45-05:00 jgarzik@redhat.com
# [netdrvr natsemi] correct DP83816 IntrHoldoff register offset
#
# Spotted by Manfred Spraul.
#
# drivers/net/natsemi.c
# 2004/03/23 12:55:40-05:00 jgarzik@redhat.com +1 -1
# [netdrvr natsemi] correct DP83816 IntrHoldoff register offset
#
# ChangeSet
# 2004/03/23 10:51:26-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] better dev->close() handling, and misc related stuff
#
# * don't synchronize_irq() in cp_stop_hw(). when necessary, do so
# in the callers.
# * call synchronize_irq() in cp_close(), after releasing the spinlock.
# * move netif_stop_queue() and netif_carrier_off() calls inside lock
# * flush last interrupt status write, in cp_stop_hw()
# * add unlikely() check for dev==NULL, first thing in the irq handler
#
# drivers/net/8139cp.c
# 2004/03/23 10:51:21-05:00 jgarzik@redhat.com +11 -11
# [netdrvr 8139cp] better dev->close() handling, and misc related stuff
#
# * don't synchronize_irq() in cp_stop_hw(). when necessary, do so
# in the callers.
# * call synchronize_irq() in cp_close(), after releasing the spinlock.
# * move netif_stop_queue() and netif_carrier_off() calls inside lock
# * flush last interrupt status write, in cp_stop_hw()
# * add unlikely() check for dev==NULL, first thing in the irq handler
#
# ChangeSet
# 2004/03/22 23:11:23-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] complete 64-bit DMA (PCI DAC) support
#
# drivers/net/8139cp.c
# 2004/03/22 23:11:18-05:00 jgarzik@redhat.com +22 -7
# [netdrvr 8139cp] complete 64-bit DMA (PCI DAC) support
#
# ChangeSet
# 2004/03/22 22:46:23-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] use netdev_priv()
#
# drivers/net/8139cp.c
# 2004/03/22 22:46:18-05:00 jgarzik@redhat.com +30 -30
# [netdrvr 8139cp] use netdev_priv()
#
# ChangeSet
# 2004/03/22 22:42:50-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] minor cleanups
#
# * update version, copyright date
# * remove unportable "pci_dev->irq < 2" check in ->probe
# * don't use ioremap_nocache() without a real reason
#
# drivers/net/8139cp.c
# 2004/03/22 22:42:44-05:00 jgarzik@redhat.com +4 -10
# [netdrvr 8139cp] minor cleanups
#
# * update version, copyright date
# * remove unportable "pci_dev->irq < 2" check in ->probe
# * don't use ioremap_nocache() without a real reason
#
# ChangeSet
# 2004/03/22 22:35:30-05:00 jgarzik@redhat.com
# [NET] define HAVE_NETDEV_PRIV back-compat hook
#
# include/linux/netdevice.h
# 2004/03/22 22:35:25-05:00 jgarzik@redhat.com +3 -2
# [NET] define HAVE_NETDEV_PRIV back-compat hook
#
# ChangeSet
# 2004/03/22 22:25:14-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] locking cleanups
#
# * s/spin_lock_irq/spin_lock_irqsave/ where it was simple and
# easy to verify.
# * release spinlock earlier in interrupt routine.
#
# drivers/net/8139cp.c
# 2004/03/22 22:25:09-05:00 jgarzik@redhat.com +44 -29
# [netdrvr 8139cp] locking cleanups
#
# * s/spin_lock_irq/spin_lock_irqsave/ where it was simple and
# easy to verify.
# * release spinlock earlier in interrupt routine.
#
# ChangeSet
# 2004/03/22 22:06:12-05:00 jgarzik@redhat.com
# [netdrvr s2io] NAPI build fixes
#
# drivers/net/s2io.c
# 2004/03/22 22:06:07-05:00 jgarzik@redhat.com +7 -0
# [netdrvr s2io] NAPI build fixes
#
# ChangeSet
# 2004/03/22 22:05:19-05:00 jgarzik@redhat.com
# [netdrvr 8139cp] rearrange priv struct, add cacheline-align markers
#
# suggested by Jes Sorensen.
#
# drivers/net/8139cp.c
# 2004/03/22 22:03:03-05:00 jgarzik@redhat.com +18 -17
# [netdrvr 8139cp] rearrange priv struct, add cacheline-align markers
#
# suggested by Jes Sorensen.
#
# ChangeSet
# 2004/03/22 17:21:13-05:00 jgarzik@redhat.com
# [net/fc iph5526] s/rx_dropped/tx_dropped/ in TX routines
#
# Spotted by Denis Valesko(sp?).
#
# Maybe one day we'll either kill this driver, or someone will fix it
# up for the current SCSI API.
#
# drivers/net/fc/iph5526.c
# 2004/03/22 17:21:08-05:00 jgarzik@redhat.com +2 -2
# [net/fc iph5526] s/rx_dropped/tx_dropped/ in TX routines
#
# Spotted by Denis Valesko(sp?).
#
# Maybe one day we'll either kill this driver, or someone will fix it
# up for the current SCSI API.
#
# ChangeSet
# 2004/03/21 14:52:06-05:00 daniel.ritz@gmx.ch
# [PATCH] netdev_priv for xirc2ps_cs, nmclan_cs
#
# s/dev->priv/netdev_priv(dev)/ for xirc2ps_cs.c and nmclan_cs.c
# xircom one is tested. against 2.6.4-bk
#
# drivers/net/pcmcia/xirc2ps_cs.c
# 2004/03/14 11:01:12-05:00 daniel.ritz@gmx.ch +16 -16
# netdev_priv for xirc2ps_cs, nmclan_cs
#
# drivers/net/pcmcia/nmclan_cs.c
# 2004/03/14 11:05:00-05:00 daniel.ritz@gmx.ch +16 -16
# netdev_priv for xirc2ps_cs, nmclan_cs
#
# ChangeSet
# 2004/03/21 12:39:20-05:00 muizelaar@rogers.com
# [PATCH] tc35815 cleanup
#
# drivers/net/tc35815.c
# 2004/03/20 22:35:00-05:00 muizelaar@rogers.com +1 -6
# tc35815 cleanup
#
# ChangeSet
# 2004/03/20 05:01:41-05:00 jgarzik@redhat.com
# [netdrvr s2io] correct an incorrect cleanup I made
#
# drivers/net/s2io.h
# 2004/03/20 05:01:36-05:00 jgarzik@redhat.com +1 -1
# [netdrvr s2io] correct an incorrect cleanup I made
#
# ChangeSet
# 2004/03/20 04:49:18-05:00 jgarzik@redhat.com
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# Documentation/networking/s2io.txt
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +48 -0
#
# include/linux/pci_ids.h
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +4 -0
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# drivers/net/s2io.h
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +4 -4
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# drivers/net/s2io.c
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +1 -1
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# drivers/net/Makefile
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +1 -0
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# drivers/net/Kconfig
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +12 -0
# [netdrvr] Add S2IO 10gige network driver.
#
# Contributed by Leonid Grossman @ S2IO
#
# Documentation/networking/s2io.txt
# 2004/03/20 04:47:53-05:00 jgarzik@redhat.com +0 -0
# BitKeeper file /spare/repo/net-drivers-2.6/Documentation/networking/s2io.txt
#
# drivers/net/s2io.h
# 2004/03/20 04:38:16-05:00 jgarzik@redhat.com +855 -0
#
# drivers/net/s2io-regs.h
# 2004/03/20 04:38:16-05:00 jgarzik@redhat.com +775 -0
#
# drivers/net/s2io.h
# 2004/03/20 04:38:16-05:00 jgarzik@redhat.com +0 -0
# BitKeeper file /spare/repo/net-drivers-2.6/drivers/net/s2io.h
#
# drivers/net/s2io.c
# 2004/03/20 04:38:15-05:00 jgarzik@redhat.com +4389 -0
#
# drivers/net/s2io-regs.h
# 2004/03/20 04:38:16-05:00 jgarzik@redhat.com +0 -0
# BitKeeper file /spare/repo/net-drivers-2.6/drivers/net/s2io-regs.h
#
# drivers/net/s2io.c
# 2004/03/20 04:38:15-05:00 jgarzik@redhat.com +0 -0
# BitKeeper file /spare/repo/net-drivers-2.6/drivers/net/s2io.c
#
diff -Nru a/Documentation/networking/s2io.txt b/Documentation/networking/s2io.txt
--- /dev/null Wed Dec 31 16:00:00 1969
+++ b/Documentation/networking/s2io.txt Sun Apr 4 18:58:15 2004
@@ -0,0 +1,48 @@
+S2IO Technologies XFrame 10 Gig adapter.
+-------------------------------------------
+
+I. Module loadable parameters.
+When loaded as a module, the driver provides a host of Module loadable
+parameters, so the device can be tuned as per the users needs.
+A list of the Module params is given below.
+(i) ring_num: This can be used to program the number of
+ receive rings used in the driver.
+(ii) ring_len: This defines the number of descriptors each ring
+ can have. There can be a maximum of 8 rings.
+(iii) frame_len: This is an array of size 8. Using this we can
+ set the maximum size of the received frame that can
+ be steered into the corrsponding receive ring.
+(iv) fifo_num: This defines the number of Tx FIFOs thats used in
+ the driver.
+(v) fifo_len: Each element defines the number of
+ Tx descriptors that can be associated with each
+ corresponding FIFO. There are a maximum of 8 FIFOs.
+(vi) tx_prio: This is a bool, if module is loaded with a non-zero
+ value for tx_prio multi FIFO scheme is activated.
+(vii) rx_prio: This is a bool, if module is loaded with a non-zero
+ value for tx_prio multi RING scheme is activated.
+(viii) latency_timer: The value given against this param will be
+ loaded into the latency timer register in PCI Config
+ space, else the register is left with its reset value.
+
+II. Performance tuning.
+ By changing a few sysctl parameters.
+ Copy the following lines into a file and run the following command,
+ "sysctl -p <file_name>"
+### IPV4 specific settings
+net.ipv4.tcp_timestamps = 0 # turns TCP timestamp support off, default 1, reduces CPU use
+net.ipv4.tcp_sack = 0 # turn SACK support off, default on
+# on systems with a VERY fast bus -> memory interface this is the big gainer
+net.ipv4.tcp_rmem = 10000000 10000000 10000000 # sets min/default/max TCP read buffer, default 4096 87380 174760
+net.ipv4.tcp_wmem = 10000000 10000000 10000000 # sets min/pressure/max TCP write buffer, default 4096 16384 131072
+net.ipv4.tcp_mem = 10000000 10000000 10000000 # sets min/pressure/max TCP buffer space, default 31744 32256 32768
+
+### CORE settings (mostly for socket and UDP effect)
+net.core.rmem_max = 524287 # maximum receive socket buffer size, default 131071
+net.core.wmem_max = 524287 # maximum send socket buffer size, default 131071
+net.core.rmem_default = 524287 # default receive socket buffer size, default 65535
+net.core.wmem_default = 524287 # default send socket buffer size, default 65535
+net.core.optmem_max = 524287 # maximum amount of option memory buffers, default 10240
+net.core.netdev_max_backlog = 300000 # number of unprocessed input packets before kernel starts dropping them, default 300
+---End of performance tuning file---
+
diff -Nru a/MAINTAINERS b/MAINTAINERS
--- a/MAINTAINERS Sun Apr 4 18:58:15 2004
+++ b/MAINTAINERS Sun Apr 4 18:58:15 2004
@@ -1055,23 +1055,33 @@
S: Maintained
INTEL PRO/100 ETHERNET SUPPORT
+P: John Ronciak
+M: john.ronciak@intel.com
+P: Ganesh Venkatesan
+M: ganesh.venkatesan@intel.com
P: Scott Feldman
M: scott.feldman@intel.com
+W: http://sourceforge.net/projects/e1000/
S: Supported
INTEL PRO/1000 GIGABIT ETHERNET SUPPORT
P: Jeb Cramer
M: cramerj@intel.com
-P: Scott Feldman
-M: scott.feldman@intel.com
+P: John Ronciak
+M: john.ronciak@intel.com
+P: Ganesh Venkatesan
+M: ganesh.venkatesan@intel.com
W: http://sourceforge.net/projects/e1000/
S: Supported
INTEL PRO/10GbE SUPPORT
+P: Ayyappan Veeraiyan
+M: ayyappan.veeraiyan@intel.com
P: Ganesh Venkatesan
-M: Ganesh.Venkatesan@intel.com
-P: Scott Feldman
-M: scott.feldman@intel.com
+M: ganesh.venkatesan@intel.com
+P: John Ronciak
+M: john.ronciak@intel.com
+W: http://sourceforge.net/projects/e1000/
S: Supported
INTERMEZZO FILE SYSTEM
diff -Nru a/drivers/net/8139cp.c b/drivers/net/8139cp.c
--- a/drivers/net/8139cp.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/8139cp.c Sun Apr 4 18:58:15 2004
@@ -1,6 +1,6 @@
/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
/*
- Copyright 2001,2002 Jeff Garzik <jgarzik@pobox.com>
+ Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
@@ -48,8 +48,8 @@
*/
#define DRV_NAME "8139cp"
-#define DRV_VERSION "1.1"
-#define DRV_RELDATE "Aug 30, 2003"
+#define DRV_VERSION "1.2"
+#define DRV_RELDATE "Mar 22, 2004"
#include <linux/config.h>
@@ -69,6 +69,7 @@
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/udp.h>
+#include <linux/cache.h>
#include <asm/io.h>
#include <asm/uaccess.h>
@@ -334,36 +335,36 @@
};
struct cp_private {
- unsigned tx_head;
- unsigned tx_tail;
- unsigned rx_tail;
-
void *regs;
struct net_device *dev;
spinlock_t lock;
+ u32 msg_enable;
+
+ struct pci_dev *pdev;
+ u32 rx_config;
+ u16 cpcmd;
+
+ struct net_device_stats net_stats;
+ struct cp_extra_stats cp_stats;
+ struct cp_dma_stats *nic_stats;
+ dma_addr_t nic_stats_dma;
+ unsigned rx_tail ____cacheline_aligned;
struct cp_desc *rx_ring;
- struct cp_desc *tx_ring;
- struct ring_info tx_skb[CP_TX_RING_SIZE];
struct ring_info rx_skb[CP_RX_RING_SIZE];
unsigned rx_buf_sz;
+
+ unsigned tx_head ____cacheline_aligned;
+ unsigned tx_tail;
+
+ struct cp_desc *tx_ring;
+ struct ring_info tx_skb[CP_TX_RING_SIZE];
dma_addr_t ring_dma;
#if CP_VLAN_TAG_USED
struct vlan_group *vlgrp;
#endif
- u32 msg_enable;
-
- struct net_device_stats net_stats;
- struct cp_extra_stats cp_stats;
- struct cp_dma_stats *nic_stats;
- dma_addr_t nic_stats_dma;
-
- struct pci_dev *pdev;
- u32 rx_config;
- u16 cpcmd;
-
unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
u32 power_state[16];
@@ -424,25 +425,27 @@
#if CP_VLAN_TAG_USED
static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
cp->vlgrp = grp;
cp->cpcmd |= RxVlanOn;
cpw16(CpCmd, cp->cpcmd);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
}
static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
cp->cpcmd &= ~RxVlanOn;
cpw16(CpCmd, cp->cpcmd);
if (cp->vlgrp)
cp->vlgrp->vlan_devices[vid] = NULL;
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
}
#endif /* CP_VLAN_TAG_USED */
@@ -510,7 +513,7 @@
static int cp_rx_poll (struct net_device *dev, int *budget)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
unsigned rx_tail = cp->rx_tail;
unsigned rx_work = dev->quota;
unsigned rx;
@@ -630,9 +633,13 @@
cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
{
struct net_device *dev = dev_instance;
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp;
u16 status;
+ if (unlikely(dev == NULL))
+ return IRQ_NONE;
+ cp = netdev_priv(dev);
+
status = cpr16(IntrStatus);
if (!status || (status == 0xFFFF))
return IRQ_NONE;
@@ -648,20 +655,23 @@
/* close possible race's with dev_close */
if (unlikely(!netif_running(dev))) {
cpw16(IntrMask, 0);
- goto out;
+ spin_unlock(&cp->lock);
+ return IRQ_HANDLED;
}
- if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr)) {
+ if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
if (netif_rx_schedule_prep(dev)) {
cpw16_f(IntrMask, cp_norx_intr_mask);
__netif_rx_schedule(dev);
}
- }
+
if (status & (TxOK | TxErr | TxEmpty | SWInt))
cp_tx(cp);
if (status & LinkChg)
mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
+ spin_unlock(&cp->lock);
+
if (status & PciErr) {
u16 pci_status;
@@ -672,8 +682,7 @@
/* TODO: reset hardware */
}
-out:
- spin_unlock(&cp->lock);
+
return IRQ_HANDLED;
}
@@ -736,7 +745,7 @@
static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
unsigned entry;
u32 eor;
#if CP_VLAN_TAG_USED
@@ -894,7 +903,7 @@
static void __cp_set_rx_mode (struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
u32 mc_filter[2]; /* Multicast hash filter */
int i, rx_mode;
u32 tmp;
@@ -939,7 +948,7 @@
static void cp_set_rx_mode (struct net_device *dev)
{
unsigned long flags;
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
spin_lock_irqsave (&cp->lock, flags);
__cp_set_rx_mode(dev);
@@ -955,35 +964,28 @@
static struct net_device_stats *cp_get_stats(struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
/* The chip only need report frame silently dropped. */
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
if (netif_running(dev) && netif_device_present(dev))
__cp_get_stats(cp);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
return &cp->net_stats;
}
static void cp_stop_hw (struct cp_private *cp)
{
- struct net_device *dev = cp->dev;
-
cpw16(IntrStatus, ~(cpr16(IntrStatus)));
cpw16_f(IntrMask, 0);
cpw8(Cmd, 0);
cpw16_f(CpCmd, 0);
- cpw16(IntrStatus, ~(cpr16(IntrStatus)));
- synchronize_irq(dev->irq);
- udelay(10);
+ cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
cp->rx_tail = 0;
cp->tx_head = cp->tx_tail = 0;
-
- (void) dev; /* avoid compiler warning when synchronize_irq()
- * disappears during !CONFIG_SMP
- */
}
static void cp_reset_hw (struct cp_private *cp)
@@ -1012,6 +1014,7 @@
static void cp_init_hw (struct cp_private *cp)
{
struct net_device *dev = cp->dev;
+ dma_addr_t ring_dma;
cp_reset_hw(cp);
@@ -1037,10 +1040,13 @@
cpw32_f(HiTxRingAddr, 0);
cpw32_f(HiTxRingAddr + 4, 0);
- cpw32_f(RxRingAddr, cp->ring_dma);
- cpw32_f(RxRingAddr + 4, 0); /* FIXME: 64-bit PCI */
- cpw32_f(TxRingAddr, cp->ring_dma + (sizeof(struct cp_desc) * CP_RX_RING_SIZE));
- cpw32_f(TxRingAddr + 4, 0); /* FIXME: 64-bit PCI */
+ ring_dma = cp->ring_dma;
+ cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
+ cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
+
+ ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
+ cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
+ cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
cpw16(MultiIntr, 0);
@@ -1154,7 +1160,7 @@
static int cp_open (struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
int rc;
if (netif_msg_ifup(cp))
@@ -1184,19 +1190,24 @@
static int cp_close (struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
if (netif_msg_ifdown(cp))
printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
+ spin_lock_irqsave(&cp->lock, flags);
+
netif_stop_queue(dev);
netif_carrier_off(dev);
- spin_lock_irq(&cp->lock);
cp_stop_hw(cp);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
+
+ synchronize_irq(dev->irq);
free_irq(dev->irq, dev);
+
cp_free_rings(cp);
return 0;
}
@@ -1204,8 +1215,9 @@
#ifdef BROKEN
static int cp_change_mtu(struct net_device *dev, int new_mtu)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
int rc;
+ unsigned long flags;
/* check for invalid MTU, according to hardware limits */
if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
@@ -1218,7 +1230,7 @@
return 0;
}
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
cp_stop_hw(cp); /* stop h/w and free rings */
cp_clean_rings(cp);
@@ -1229,7 +1241,7 @@
rc = cp_init_rings(cp); /* realloc and restart h/w */
cp_start_hw(cp);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
return rc;
}
@@ -1248,7 +1260,7 @@
static int mdio_read(struct net_device *dev, int phy_id, int location)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
return location < 8 && mii_2_8139_map[location] ?
readw(cp->regs + mii_2_8139_map[location]) : 0;
@@ -1258,7 +1270,7 @@
static void mdio_write(struct net_device *dev, int phy_id, int location,
int value)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
if (location == 0) {
cpw8(Cfg9346, Cfg9346_Unlock);
@@ -1326,7 +1338,7 @@
static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
strcpy (info->driver, DRV_NAME);
strcpy (info->version, DRV_VERSION);
@@ -1345,55 +1357,57 @@
static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
int rc;
+ unsigned long flags;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
rc = mii_ethtool_gset(&cp->mii_if, cmd);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
return rc;
}
static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
int rc;
+ unsigned long flags;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
rc = mii_ethtool_sset(&cp->mii_if, cmd);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
return rc;
}
static int cp_nway_reset(struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
return mii_nway_restart(&cp->mii_if);
}
static u32 cp_get_msglevel(struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
return cp->msg_enable;
}
static void cp_set_msglevel(struct net_device *dev, u32 value)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
cp->msg_enable = value;
}
static u32 cp_get_rx_csum(struct net_device *dev)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
}
static int cp_set_rx_csum(struct net_device *dev, u32 data)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
u16 cmd = cp->cpcmd, newcmd;
newcmd = cmd;
@@ -1404,10 +1418,12 @@
newcmd &= ~RxChkSum;
if (newcmd != cmd) {
- spin_lock_irq(&cp->lock);
+ unsigned long flags;
+
+ spin_lock_irqsave(&cp->lock, flags);
cp->cpcmd = newcmd;
cpw16_f(CpCmd, newcmd);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
}
return 0;
@@ -1416,35 +1432,38 @@
static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
void *p)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
if (regs->len < CP_REGS_SIZE)
return /* -EINVAL */;
regs->version = CP_REGS_VER;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
}
static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
- spin_lock_irq (&cp->lock);
+ spin_lock_irqsave (&cp->lock, flags);
netdev_get_wol (cp, wol);
- spin_unlock_irq (&cp->lock);
+ spin_unlock_irqrestore (&cp->lock, flags);
}
static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
+ unsigned long flags;
int rc;
- spin_lock_irq (&cp->lock);
+ spin_lock_irqsave (&cp->lock, flags);
rc = netdev_set_wol (cp, wol);
- spin_unlock_irq (&cp->lock);
+ spin_unlock_irqrestore (&cp->lock, flags);
return rc;
}
@@ -1464,13 +1483,13 @@
static void cp_get_ethtool_stats (struct net_device *dev,
struct ethtool_stats *estats, u64 *tmp_stats)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
unsigned int work = 100;
int i;
/* begin NIC statistics dump */
- cpw32(StatsAddr + 4, 0); /* FIXME: 64-bit PCI */
- cpw32(StatsAddr, cp->nic_stats_dma | DumpStats);
+ cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
+ cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
cpr32(StatsAddr);
while (work-- > 0) {
@@ -1526,16 +1545,17 @@
static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
{
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
struct mii_ioctl_data *mii = (struct mii_ioctl_data *) &rq->ifr_data;
int rc;
+ unsigned long flags;
if (!netif_running(dev))
return -EINVAL;
- spin_lock_irq(&cp->lock);
+ spin_lock_irqsave(&cp->lock, flags);
rc = generic_mii_ioctl(&cp->mii_if, mii, cmd, NULL);
- spin_unlock_irq(&cp->lock);
+ spin_unlock_irqrestore(&cp->lock, flags);
return rc;
}
@@ -1639,7 +1659,7 @@
SET_MODULE_OWNER(dev);
SET_NETDEV_DEV(dev, &pdev->dev);
- cp = dev->priv;
+ cp = netdev_priv(dev);
cp->pdev = pdev;
cp->dev = dev;
cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
@@ -1664,12 +1684,6 @@
if (rc)
goto err_out_mwi;
- if (pdev->irq < 2) {
- rc = -EIO;
- printk(KERN_ERR PFX "invalid irq (%d) for pci dev %s\n",
- pdev->irq, pci_name(pdev));
- goto err_out_res;
- }
pciaddr = pci_resource_start(pdev, 1);
if (!pciaddr) {
rc = -EIO;
@@ -1686,22 +1700,30 @@
/* Configure DMA attributes. */
if ((sizeof(dma_addr_t) > 32) &&
+ !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
pci_using_dac = 1;
} else {
+ pci_using_dac = 0;
+
rc = pci_set_dma_mask(pdev, 0xffffffffULL);
if (rc) {
printk(KERN_ERR PFX "No usable DMA configuration, "
"aborting.\n");
goto err_out_res;
}
- pci_using_dac = 0;
+ rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
+ if (rc) {
+ printk(KERN_ERR PFX "No usable consistent DMA configuration, "
+ "aborting.\n");
+ goto err_out_res;
+ }
}
cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
- regs = ioremap_nocache(pciaddr, CP_REGS_SIZE);
+ regs = ioremap(pciaddr, CP_REGS_SIZE);
if (!regs) {
rc = -EIO;
printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
@@ -1742,6 +1764,9 @@
dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
#endif
+ if (pci_using_dac)
+ dev->features |= NETIF_F_HIGHDMA;
+
dev->irq = pdev->irq;
rc = register_netdev(dev);
@@ -1783,7 +1808,7 @@
static void cp_remove_one (struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
- struct cp_private *cp = dev->priv;
+ struct cp_private *cp = netdev_priv(dev);
if (!dev)
BUG();
@@ -1805,7 +1830,7 @@
unsigned long flags;
dev = pci_get_drvdata (pdev);
- cp = dev->priv;
+ cp = netdev_priv(dev);
if (!dev || !netif_running (dev)) return 0;
@@ -1834,7 +1859,7 @@
struct cp_private *cp;
dev = pci_get_drvdata (pdev);
- cp = dev->priv;
+ cp = netdev_priv(dev);
netif_device_attach (dev);
diff -Nru a/drivers/net/Kconfig b/drivers/net/Kconfig
--- a/drivers/net/Kconfig Sun Apr 4 18:58:15 2004
+++ b/drivers/net/Kconfig Sun Apr 4 18:58:15 2004
@@ -2101,6 +2101,18 @@
bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
depends on IXGB && EXPERIMENTAL
+config S2IO
+ tristate "S2IO 10Gbe XFrame NIC"
+ depends on PCI
+ ---help---
+ This driver supports the 10Gbe XFrame NIC of S2IO.
+ For help regarding driver compilation, installation and
+ tuning please look into ~/drivers/net/s2io/README.txt.
+
+config S2IO_NAPI
+ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
+ depends on S2IO && EXPERIMENTAL
+
endmenu
diff -Nru a/drivers/net/Makefile b/drivers/net/Makefile
--- a/drivers/net/Makefile Sun Apr 4 18:58:15 2004
+++ b/drivers/net/Makefile Sun Apr 4 18:58:15 2004
@@ -175,6 +175,7 @@
obj-$(CONFIG_R8169) += r8169.o
obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
obj-$(CONFIG_IBMVETH) += ibmveth.o
+obj-$(CONFIG_S2IO) += s2io.o
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_NET_FC) += fc/
diff -Nru a/drivers/net/arcnet/com20020-isa.c b/drivers/net/arcnet/com20020-isa.c
--- a/drivers/net/arcnet/com20020-isa.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/arcnet/com20020-isa.c Sun Apr 4 18:58:15 2004
@@ -185,8 +185,6 @@
#ifndef MODULE
static int __init com20020isa_setup(char *s)
{
- struct net_device *dev;
- struct arcnet_local *lp;
int ints[8];
s = get_options(s, 8, ints);
diff -Nru a/drivers/net/fc/iph5526.c b/drivers/net/fc/iph5526.c
--- a/drivers/net/fc/iph5526.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/fc/iph5526.c Sun Apr 4 18:58:15 2004
@@ -2910,7 +2910,7 @@
{
struct fc_info *fi = dev->priv;
printk(KERN_WARNING "%s: timed out on send.\n", dev->name);
- fi->fc_stats.rx_dropped++;
+ fi->fc_stats.tx_dropped++;
dev->trans_start = jiffies;
netif_wake_queue(dev);
}
@@ -2953,7 +2953,7 @@
fi->fc_stats.tx_packets++;
}
else
- fi->fc_stats.rx_dropped++;
+ fi->fc_stats.tx_dropped++;
dev->trans_start = jiffies;
/* We free up the IP buffers in the OCI_interrupt handler.
* status == 0 implies that the frame was not transmitted. So the
diff -Nru a/drivers/net/natsemi.c b/drivers/net/natsemi.c
--- a/drivers/net/natsemi.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/natsemi.c Sun Apr 4 18:58:15 2004
@@ -387,7 +387,7 @@
IntrStatus = 0x10,
IntrMask = 0x14,
IntrEnable = 0x18,
- IntrHoldoff = 0x16, /* DP83816 only */
+ IntrHoldoff = 0x1C, /* DP83816 only */
TxRingPtr = 0x20,
TxConfig = 0x24,
RxRingPtr = 0x30,
diff -Nru a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c
--- a/drivers/net/pcmcia/nmclan_cs.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/pcmcia/nmclan_cs.c Sun Apr 4 18:58:15 2004
@@ -470,7 +470,7 @@
dev = alloc_etherdev(sizeof(mace_private));
if (!dev)
return NULL;
- lp = dev->priv;
+ lp = netdev_priv(dev);
link = &lp->link;
link->priv = dev;
@@ -707,7 +707,7 @@
{
client_handle_t handle = link->handle;
struct net_device *dev = link->priv;
- mace_private *lp = dev->priv;
+ mace_private *lp = netdev_priv(dev);
tuple_t tuple;
cisparse_t parse;
u_char buf[64];
@@ -875,7 +875,7 @@
---------------------------------------------------------------------------- */
static void nmclan_reset(struct net_device *dev)
{
- mace_private *lp = dev->priv;
+ mace_private *lp = netdev_priv(dev);
#if RESET_XILINX
dev_link_t *link = &lp->link;
@@ -944,7 +944,7 @@
static int mace_open(struct net_device *dev)
{
ioaddr_t ioaddr = dev->base_addr;
- mace_private *lp = dev->priv;
+ mace_private *lp = netdev_priv(dev);
dev_link_t *link = &lp->link;
if (!DEV_OK(link))
@@ -967,7 +967,7 @@
static int mace_close(struct net_device *dev)
{
ioaddr_t ioaddr = dev->base_addr;
- mace_private *lp = dev->priv;
+ mace_private *lp = netdev_priv(dev);
dev_link_t *link = &lp->link;
DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
@@ -1022,7 +1022,7 @@
static void mace_tx_timeout(struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
dev_link_t *link = &lp->link;
printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
@@ -1038,7 +1038,7 @@
static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
netif_stop_queue(dev);
@@ -1099,7 +1099,7 @@
static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = (struct net_device *) dev_id;
- mace_private *lp = dev->priv;
+ mace_private *lp = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
int status;
int IntrCnt = MACE_MAX_IR_ITERATIONS;
@@ -1241,7 +1241,7 @@
---------------------------------------------------------------------------- */
static int mace_rx(struct net_device *dev, unsigned char RxCnt)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
unsigned char rx_framecnt;
unsigned short rx_status;
@@ -1408,7 +1408,7 @@
---------------------------------------------------------------------------- */
static void update_stats(ioaddr_t ioaddr, struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
@@ -1454,7 +1454,7 @@
---------------------------------------------------------------------------- */
static struct net_device_stats *mace_get_stats(struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
update_stats(dev->base_addr, dev);
@@ -1549,7 +1549,7 @@
---------------------------------------------------------------------------- */
static void restore_multicast_list(struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
int num_addrs = lp->multicast_num_addrs;
int *ladrf = lp->multicast_ladrf;
ioaddr_t ioaddr = dev->base_addr;
@@ -1606,7 +1606,7 @@
static void set_multicast_list(struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
int i;
struct dev_mc_list *dmi = dev->mc_list;
@@ -1645,10 +1645,10 @@
static void restore_multicast_list(struct net_device *dev)
{
ioaddr_t ioaddr = dev->base_addr;
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
- ((mace_private *)(dev->priv))->multicast_num_addrs);
+ lp->multicast_num_addrs);
if (dev->flags & IFF_PROMISC) {
/* Promiscuous mode: receive all packets */
@@ -1665,7 +1665,7 @@
static void set_multicast_list(struct net_device *dev)
{
- mace_private *lp = (mace_private *)dev->priv;
+ mace_private *lp = netdev_priv(dev);
#ifdef PCMCIA_DEBUG
if (pc_debug > 1) {
diff -Nru a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c
--- a/drivers/net/pcmcia/xirc2ps_cs.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/pcmcia/xirc2ps_cs.c Sun Apr 4 18:58:15 2004
@@ -595,7 +595,7 @@
dev = alloc_etherdev(sizeof(local_info_t));
if (!dev)
return NULL;
- local = dev->priv;
+ local = netdev_priv(dev);
link = &local->link;
link->priv = dev;
@@ -710,7 +710,7 @@
set_card_type(dev_link_t *link, const void *s)
{
struct net_device *dev = link->priv;
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
#ifdef PCMCIA_DEBUG
unsigned cisrev = ((const unsigned char *)s)[2];
#endif
@@ -805,7 +805,7 @@
{
client_handle_t handle = link->handle;
struct net_device *dev = link->priv;
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
tuple_t tuple;
cisparse_t parse;
ioaddr_t ioaddr;
@@ -1159,7 +1159,7 @@
if (link->win) {
struct net_device *dev = link->priv;
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
if (local->dingo)
iounmap(local->dingo_ccr - 0x0800);
pcmcia_release_window(link->win);
@@ -1246,7 +1246,7 @@
xirc2ps_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = (struct net_device *)dev_id;
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
ioaddr_t ioaddr;
u_char saved_page;
unsigned bytes_rcvd;
@@ -1468,7 +1468,7 @@
static void
do_tx_timeout(struct net_device *dev)
{
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
printk(KERN_NOTICE "%s: transmit timed out\n", dev->name);
lp->stats.tx_errors++;
/* reset the card */
@@ -1480,7 +1480,7 @@
static int
do_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
int okay;
unsigned freespace;
@@ -1537,7 +1537,7 @@
static struct net_device_stats *
do_get_stats(struct net_device *dev)
{
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
/* lp->stats.rx_missed_errors = GetByte(?) */
return &lp->stats;
@@ -1552,7 +1552,7 @@
set_addresses(struct net_device *dev)
{
ioaddr_t ioaddr = dev->base_addr;
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
struct dev_mc_list *dmi = dev->mc_list;
char *addr;
int i,j,k,n;
@@ -1617,7 +1617,7 @@
static int
do_config(struct net_device *dev, struct ifmap *map)
{
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
DEBUG(0, "do_config(%p)\n", dev);
if (map->port != 255 && map->port != dev->if_port) {
@@ -1643,7 +1643,7 @@
static int
do_open(struct net_device *dev)
{
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
dev_link_t *link = &lp->link;
DEBUG(0, "do_open(%p)\n", dev);
@@ -1676,7 +1676,7 @@
static int
do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
u16 *data = (u16 *)&rq->ifr_data;
@@ -1708,7 +1708,7 @@
static void
hardreset(struct net_device *dev)
{
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
SelectPage(4);
@@ -1725,7 +1725,7 @@
static void
do_reset(struct net_device *dev, int full)
{
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
unsigned value;
@@ -1886,7 +1886,7 @@
static int
init_mii(struct net_device *dev)
{
- local_info_t *local = dev->priv;
+ local_info_t *local = netdev_priv(dev);
ioaddr_t ioaddr = dev->base_addr;
unsigned control, status, linkpartner;
int i;
@@ -1973,7 +1973,7 @@
do_stop(struct net_device *dev)
{
ioaddr_t ioaddr = dev->base_addr;
- local_info_t *lp = dev->priv;
+ local_info_t *lp = netdev_priv(dev);
dev_link_t *link = &lp->link;
DEBUG(0, "do_stop(%p)\n", dev);
diff -Nru a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
--- /dev/null Wed Dec 31 16:00:00 1969
+++ b/drivers/net/s2io-regs.h Sun Apr 4 18:58:15 2004
@@ -0,0 +1,775 @@
+/************************************************************************
+ * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
+ * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
+
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ * Drivers based on or derived from this code fall under the GPL and must
+ * retain the authorship, copyright and license notice. This file is not
+ * a complete program and may only be used when the entire operating
+ * system is licensed under the GPL.
+ * See the file COPYING in this distribution for more information.
+ ************************************************************************/
+#ifndef _REGS_H
+#define _REGS_H
+
+#define TBD 0
+
+typedef struct _XENA_dev_config {
+/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
+
+/* General Control-Status Registers */
+ u64 general_int_status;
+#define GEN_INTR_TXPIC BIT(0)
+#define GEN_INTR_TXDMA BIT(1)
+#define GEN_INTR_TXMAC BIT(2)
+#define GEN_INTR_TXXGXS BIT(3)
+#define GEN_INTR_TXTRAFFIC BIT(8)
+#define GEN_INTR_RXPIC BIT(32)
+#define GEN_INTR_RXDMA BIT(33)
+#define GEN_INTR_RXMAC BIT(34)
+#define GEN_INTR_MC BIT(35)
+#define GEN_INTR_RXXGXS BIT(36)
+#define GEN_INTR_RXTRAFFIC BIT(40)
+#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
+ GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
+ GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
+ GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
+ GEN_INTR_MC
+
+ u64 general_int_mask;
+
+ u8 unused0[0x100 - 0x10];
+
+ u64 sw_reset;
+/* XGXS must be removed from reset only once. */
+#define SW_RESET_XENA vBIT(0xA5,0,8)
+#define SW_RESET_FLASH vBIT(0xA5,8,8)
+#define SW_RESET_EOI vBIT(0xA5,16,8)
+#define SW_RESET_ALL (SW_RESET_XENA | \
+ SW_RESET_FLASH | \
+ SW_RESET_EOI)
+/* The SW_RESET register must read this value after a successful reset. */
+#define SW_RESET_RAW_VAL 0xA5000000
+
+
+ u64 adapter_status;
+#define ADAPTER_STATUS_TDMA_READY BIT(0)
+#define ADAPTER_STATUS_RDMA_READY BIT(1)
+#define ADAPTER_STATUS_PFC_READY BIT(2)
+#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
+#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
+#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
+#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
+#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
+#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
+#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
+#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
+#define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
+#define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
+
+ u64 adapter_control;
+#define ADAPTER_CNTL_EN BIT(7)
+#define ADAPTER_EOI_TX_ON BIT(15)
+#define ADAPTER_LED_ON BIT(23)
+#define ADAPTER_UDPI(val) vBIT(val,36,4)
+#define ADAPTER_WAIT_INT BIT(48)
+#define ADAPTER_ECC_EN BIT(55)
+
+ u64 serr_source;
+#define SERR_SOURCE_PIC BIT(0)
+#define SERR_SOURCE_TXDMA BIT(1)
+#define SERR_SOURCE_RXDMA BIT(2)
+#define SERR_SOURCE_MAC BIT(3)
+#define SERR_SOURCE_MC BIT(4)
+#define SERR_SOURCE_XGXS BIT(5)
+#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
+ SERR_SOURCE_TXDMA | \
+ SERR_SOURCE_RXDMA | \
+ SERR_SOURCE_MAC | \
+ SERR_SOURCE_MC | \
+ SERR_SOURCE_XGXS)
+
+
+ u8 unused_0[0x800 - 0x120];
+
+/* PCI-X Controller registers */
+ u64 pic_int_status;
+ u64 pic_int_mask;
+#define PIC_INT_TX BIT(0)
+#define PIC_INT_FLSH BIT(1)
+#define PIC_INT_MDIO BIT(2)
+#define PIC_INT_IIC BIT(3)
+#define PIC_INT_GPIO BIT(4)
+#define PIC_INT_RX BIT(32)
+
+ u64 txpic_int_reg;
+ u64 txpic_int_mask;
+#define PCIX_INT_REG_ECC_SG_ERR BIT(0)
+#define PCIX_INT_REG_ECC_DB_ERR BIT(1)
+#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
+#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
+#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
+#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
+#define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
+#define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
+#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
+#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
+#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
+#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
+#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
+/*
+#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
+#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
+#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
+*/
+ u64 txpic_alarms;
+ u64 rxpic_int_reg;
+ u64 rxpic_int_mask;
+ u64 rxpic_alarms;
+
+ u64 flsh_int_reg;
+ u64 flsh_int_mask;
+#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
+#define PIC_FLSH_INT_REG_ERR BIT(62)
+ u64 flash_alarms;
+
+ u64 mdio_int_reg;
+ u64 mdio_int_mask;
+#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
+#define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
+#define MDIO_INT_REG_LASI BIT(39)
+ u64 mdio_alarms;
+
+ u64 iic_int_reg;
+ u64 iic_int_mask;
+#define IIC_INT_REG_BUS_FSM_ERR BIT(4)
+#define IIC_INT_REG_BIT_FSM_ERR BIT(5)
+#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
+#define IIC_INT_REG_REQ_FSM_ERR BIT(7)
+#define IIC_INT_REG_ACK_ERR BIT(8)
+ u64 iic_alarms;
+
+ u8 unused4[0x08];
+
+ u64 gpio_int_reg;
+ u64 gpio_int_mask;
+ u64 gpio_alarms;
+
+ u8 unused5[0x38];
+
+ u64 tx_traffic_int;
+#define TX_TRAFFIC_INT_n(n) BIT(n)
+ u64 tx_traffic_mask;
+
+ u64 rx_traffic_int;
+#define RX_TRAFFIC_INT_n(n) BIT(n)
+ u64 rx_traffic_mask;
+
+/* PIC Control registers */
+ u64 pic_control;
+#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
+#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
+
+ u64 swapper_ctrl;
+#define SWAPPER_CTRL_PIF_R_FE BIT(0)
+#define SWAPPER_CTRL_PIF_R_SE BIT(1)
+#define SWAPPER_CTRL_PIF_W_FE BIT(8)
+#define SWAPPER_CTRL_PIF_W_SE BIT(9)
+#define SWAPPER_CTRL_TXP_FE BIT(16)
+#define SWAPPER_CTRL_TXP_SE BIT(17)
+#define SWAPPER_CTRL_TXD_R_FE BIT(18)
+#define SWAPPER_CTRL_TXD_R_SE BIT(19)
+#define SWAPPER_CTRL_TXD_W_FE BIT(20)
+#define SWAPPER_CTRL_TXD_W_SE BIT(21)
+#define SWAPPER_CTRL_TXF_R_FE BIT(22)
+#define SWAPPER_CTRL_TXF_R_SE BIT(23)
+#define SWAPPER_CTRL_RXD_R_FE BIT(32)
+#define SWAPPER_CTRL_RXD_R_SE BIT(33)
+#define SWAPPER_CTRL_RXD_W_FE BIT(34)
+#define SWAPPER_CTRL_RXD_W_SE BIT(35)
+#define SWAPPER_CTRL_RXF_W_FE BIT(36)
+#define SWAPPER_CTRL_RXF_W_SE BIT(37)
+#define SWAPPER_CTRL_XMSI_FE BIT(40)
+#define SWAPPER_CTRL_XMSI_SE BIT(41)
+#define SWAPPER_CTRL_STATS_FE BIT(48)
+#define SWAPPER_CTRL_STATS_SE BIT(49)
+
+ u64 pif_rd_swapper_fb;
+#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
+
+ u64 scheduled_int_ctrl;
+#define SCHED_INT_CTRL_TIMER_EN BIT(0)
+#define SCHED_INT_CTRL_ONE_SHOT BIT(1)
+#define SCHED_INT_CTRL_INT2MSI TBD
+#define SCHED_INT_PERIOD TBD
+
+ u64 txreqtimeout;
+#define TXREQTO_VAL(val) vBIT(val,0,32)
+#define TXREQTO_EN BIT(63)
+
+ u64 statsreqtimeout;
+#define STATREQTO_VAL(n) TBD
+#define STATREQTO_EN BIT(63)
+
+ u64 read_retry_delay;
+ u64 read_retry_acceleration;
+ u64 write_retry_delay;
+ u64 write_retry_acceleration;
+
+ u64 xmsi_control;
+ u64 xmsi_access;
+ u64 xmsi_address;
+ u64 xmsi_data;
+
+ u64 rx_mat;
+
+ u8 unused6[0x8];
+
+ u64 tx_mat0_7;
+ u64 tx_mat8_15;
+ u64 tx_mat16_23;
+ u64 tx_mat24_31;
+ u64 tx_mat32_39;
+ u64 tx_mat40_47;
+ u64 tx_mat48_55;
+ u64 tx_mat56_63;
+
+ u8 unused_1[0x10];
+
+ /* Automated statistics collection */
+ u64 stat_cfg;
+#define STAT_CFG_STAT_EN BIT(0)
+#define STAT_CFG_ONE_SHOT_EN BIT(1)
+#define STAT_CFG_STAT_NS_EN BIT(8)
+#define STAT_CFG_STAT_RO BIT(9)
+#define STAT_TRSF_PER(n) TBD
+#define PER_SEC 0x208d5
+#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
+
+ u64 stat_addr;
+
+ /* General Configuration */
+ u64 mdio_control;
+
+ u64 dtx_control;
+
+ u64 i2c_control;
+#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
+#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
+#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
+#define I2C_CONTROL_READ BIT(24)
+#define I2C_CONTROL_NACK BIT(25)
+#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
+#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
+#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
+#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
+
+ u64 gpio_control;
+#define GPIO_CTRL_GPIO_0 BIT(8)
+
+ u8 unused7[0x600];
+
+/* TxDMA registers */
+ u64 txdma_int_status;
+ u64 txdma_int_mask;
+#define TXDMA_PFC_INT BIT(0)
+#define TXDMA_TDA_INT BIT(1)
+#define TXDMA_PCC_INT BIT(2)
+#define TXDMA_TTI_INT BIT(3)
+#define TXDMA_LSO_INT BIT(4)
+#define TXDMA_TPA_INT BIT(5)
+#define TXDMA_SM_INT BIT(6)
+ u64 pfc_err_reg;
+ u64 pfc_err_mask;
+ u64 pfc_err_alarm;
+
+ u64 tda_err_reg;
+ u64 tda_err_mask;
+ u64 tda_err_alarm;
+
+ u64 pcc_err_reg;
+ u64 pcc_err_mask;
+ u64 pcc_err_alarm;
+
+ u64 tti_err_reg;
+ u64 tti_err_mask;
+ u64 tti_err_alarm;
+
+ u64 lso_err_reg;
+ u64 lso_err_mask;
+ u64 lso_err_alarm;
+
+ u64 tpa_err_reg;
+ u64 tpa_err_mask;
+ u64 tpa_err_alarm;
+
+ u64 sm_err_reg;
+ u64 sm_err_mask;
+ u64 sm_err_alarm;
+
+ u8 unused8[0x100 - 0xB8];
+
+/* TxDMA arbiter */
+ u64 tx_dma_wrap_stat;
+
+/* Tx FIFO controller */
+#define X_MAX_FIFOS 8
+#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
+ u64 tx_fifo_partition_0;
+#define TX_FIFO_PARTITION_EN BIT(0)
+#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
+#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
+#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
+#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
+
+ u64 tx_fifo_partition_1;
+#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
+#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
+#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
+#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
+
+ u64 tx_fifo_partition_2;
+#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
+#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
+#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
+#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
+
+ u64 tx_fifo_partition_3;
+#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
+#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
+#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
+#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
+
+#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
+#define TX_FIFO_PARTITION_PRI_1 1
+#define TX_FIFO_PARTITION_PRI_2 2
+#define TX_FIFO_PARTITION_PRI_3 3
+#define TX_FIFO_PARTITION_PRI_4 4
+#define TX_FIFO_PARTITION_PRI_5 5
+#define TX_FIFO_PARTITION_PRI_6 6
+#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
+
+ u64 tx_w_round_robin_0;
+ u64 tx_w_round_robin_1;
+ u64 tx_w_round_robin_2;
+ u64 tx_w_round_robin_3;
+ u64 tx_w_round_robin_4;
+
+ u64 tti_command_mem;
+#define TTI_CMD_MEM_WE BIT(7)
+#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
+#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
+#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
+
+ u64 tti_data1_mem;
+#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
+#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
+#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
+#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
+#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
+#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
+#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
+
+ u64 tti_data2_mem;
+#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
+#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
+#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
+#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
+
+/* Tx Protocol assist */
+ u64 tx_pa_cfg;
+#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
+#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
+#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
+#define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
+
+/* Recent add, used only debug purposes. */
+ u64 pcc_enable;
+
+ u8 unused9[0x700 - 0x178];
+
+ u64 txdma_debug_ctrl;
+
+ u8 unused10[0x1800 - 0x1708];
+
+/* RxDMA Registers */
+ u64 rxdma_int_status;
+ u64 rxdma_int_mask;
+#define RXDMA_INT_RC_INT_M BIT(0)
+#define RXDMA_INT_RPA_INT_M BIT(1)
+#define RXDMA_INT_RDA_INT_M BIT(2)
+#define RXDMA_INT_RTI_INT_M BIT(3)
+
+ u64 rda_err_reg;
+ u64 rda_err_mask;
+ u64 rda_err_alarm;
+
+ u64 rc_err_reg;
+ u64 rc_err_mask;
+ u64 rc_err_alarm;
+
+ u64 prc_pcix_err_reg;
+ u64 prc_pcix_err_mask;
+ u64 prc_pcix_err_alarm;
+
+ u64 rpa_err_reg;
+ u64 rpa_err_mask;
+ u64 rpa_err_alarm;
+
+ u64 rti_err_reg;
+ u64 rti_err_mask;
+ u64 rti_err_alarm;
+
+ u8 unused11[0x100 - 0x88];
+
+/* DMA arbiter */
+ u64 rx_queue_priority;
+#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
+#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
+#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
+#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
+#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
+#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
+#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
+#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
+
+#define RX_QUEUE_PRI_0 0 /* highest */
+#define RX_QUEUE_PRI_1 1
+#define RX_QUEUE_PRI_2 2
+#define RX_QUEUE_PRI_3 3
+#define RX_QUEUE_PRI_4 4
+#define RX_QUEUE_PRI_5 5
+#define RX_QUEUE_PRI_6 6
+#define RX_QUEUE_PRI_7 7 /* lowest */
+
+ u64 rx_w_round_robin_0;
+ u64 rx_w_round_robin_1;
+ u64 rx_w_round_robin_2;
+ u64 rx_w_round_robin_3;
+ u64 rx_w_round_robin_4;
+
+ /* Per-ring controller regs */
+#define RX_MAX_RINGS 8
+#if 0
+#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
+#define RX_MIN_RINGS_SZ 0x3F /* 63 */
+#endif
+ u64 prc_rxd0_n[RX_MAX_RINGS];
+ u64 prc_ctrl_n[RX_MAX_RINGS];
+#define PRC_CTRL_RC_ENABLED BIT(7)
+#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
+#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
+#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
+#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
+#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
+#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
+#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
+#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
+#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
+
+ u64 prc_alarm_action;
+#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
+#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
+#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
+#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
+#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
+#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
+#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
+#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
+#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
+#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
+#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
+#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
+#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
+#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
+#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
+#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
+
+/* Receive traffic interrupts */
+ u64 rti_command_mem;
+#define RTI_CMD_MEM_WE BIT(7)
+#define RTI_CMD_MEM_STROBE BIT(15)
+#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
+#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
+#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
+
+ u64 rti_data1_mem;
+#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
+#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
+#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
+#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
+#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
+#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
+
+ u64 rti_data2_mem;
+#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
+#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
+#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
+#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
+
+ u64 rx_pa_cfg;
+#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
+#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
+#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
+
+ u8 unused12[0x700 - 0x1D8];
+
+ u64 rxdma_debug_ctrl;
+
+ u8 unused13[0x2000 - 0x1f08];
+
+/* Media Access Controller Register */
+ u64 mac_int_status;
+ u64 mac_int_mask;
+#define MAC_INT_STATUS_TMAC_INT BIT(0)
+#define MAC_INT_STATUS_RMAC_INT BIT(1)
+
+ u64 mac_tmac_err_reg;
+#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
+#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
+#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
+ u64 mac_tmac_err_mask;
+ u64 mac_tmac_err_alarm;
+
+ u64 mac_rmac_err_reg;
+#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
+#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
+#define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
+#define RMAC_LINK_STATE_CHANGE_INT BIT(31)
+ u64 mac_rmac_err_mask;
+ u64 mac_rmac_err_alarm;
+
+ u8 unused14[0x100 - 0x40];
+
+ u64 mac_cfg;
+#define MAC_CFG_TMAC_ENABLE BIT(0)
+#define MAC_CFG_RMAC_ENABLE BIT(1)
+#define MAC_CFG_LAN_NOT_WAN BIT(2)
+#define MAC_CFG_TMAC_LOOPBACK BIT(3)
+#define MAC_CFG_TMAC_APPEND_PAD BIT(4)
+#define MAC_CFG_RMAC_STRIP_FCS BIT(5)
+#define MAC_CFG_RMAC_STRIP_PAD BIT(6)
+#define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
+#define MAC_RMAC_DISCARD_PFRM BIT(8)
+#define MAC_RMAC_BCAST_ENABLE BIT(9)
+#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
+#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
+
+ u64 tmac_avg_ipg;
+#define TMAC_AVG_IPG(val) vBIT(val,0,8)
+
+ u64 rmac_max_pyld_len;
+#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
+#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
+#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
+
+ u64 rmac_err_cfg;
+#define RMAC_ERR_FCS BIT(0)
+#define RMAC_ERR_FCS_ACCEPT BIT(1)
+#define RMAC_ERR_TOO_LONG BIT(1)
+#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
+#define RMAC_ERR_RUNT BIT(2)
+#define RMAC_ERR_RUNT_ACCEPT BIT(2)
+#define RMAC_ERR_LEN_MISMATCH BIT(3)
+#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
+
+ u64 rmac_cfg_key;
+#define RMAC_CFG_KEY(val) vBIT(val,0,16)
+
+#define MAX_MAC_ADDRESSES 16
+#define MAX_MC_ADDRESSES 32 /* Multicast addresses */
+#define MAC_MAC_ADDR_START_OFFSET 0
+#define MAC_MC_ADDR_START_OFFSET 16
+#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
+ u64 rmac_addr_cmd_mem;
+#define RMAC_ADDR_CMD_MEM_WE BIT(7)
+#define RMAC_ADDR_CMD_MEM_RD 0
+#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
+#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
+#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
+
+ u64 rmac_addr_data0_mem;
+#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
+#define RMAC_ADDR_DATA0_MEM_USER BIT(48)
+
+ u64 rmac_addr_data1_mem;
+#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
+
+ u8 unused15[0x8];
+
+/*
+ u64 rmac_addr_cfg;
+#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
+#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
+#define RMAC_ADDR_BCAST_EN vBIT(0)_48
+#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
+*/
+ u64 tmac_ipg_cfg;
+
+ u64 rmac_pause_cfg;
+#define RMAC_PAUSE_GEN BIT(0)
+#define RMAC_PAUSE_GEN_ENABLE BIT(0)
+#define RMAC_PAUSE_RX BIT(1)
+#define RMAC_PAUSE_RX_ENABLE BIT(1)
+#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
+#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
+
+ u64 rmac_red_cfg;
+
+ u64 rmac_red_rate_q0q3;
+ u64 rmac_red_rate_q4q7;
+
+ u64 mac_link_util;
+#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
+#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
+#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
+#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
+#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
+#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
+
+#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
+ MAC_RX_LINK_UTIL_DISABLE
+
+ u64 rmac_invalid_ipg;
+
+/* rx traffic steering */
+#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
+ u64 rts_frm_len_n[8];
+
+ u64 rts_qos_steering;
+
+#define MAX_DIX_MAP 4
+ u64 rts_dix_map_n[MAX_DIX_MAP];
+#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
+#define RTS_DIX_MAP_SCW(val) BIT(val,21)
+
+ u64 rts_q_alternates;
+ u64 rts_default_q;
+
+ u64 rts_ctrl;
+#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
+#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
+
+ u64 rts_pn_cam_ctrl;
+#define RTS_PN_CAM_CTRL_WE BIT(7)
+#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
+#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
+#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
+ u64 rts_pn_cam_data;
+#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
+#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
+#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
+
+ u64 rts_ds_mem_ctrl;
+#define RTS_DS_MEM_CTRL_WE BIT(7)
+#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
+#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
+#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
+ u64 rts_ds_mem_data;
+#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
+
+ u8 unused16[0x700 - 0x220];
+
+ u64 mac_debug_ctrl;
+#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
+
+ u8 unused17[0x2800 - 0x2708];
+
+/* memory controller registers */
+ u64 mc_int_status;
+#define MC_INT_STATUS_MC_INT BIT(0)
+ u64 mc_int_mask;
+#define MC_INT_MASK_MC_INT BIT(0)
+
+ u64 mc_err_reg;
+#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
+#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
+#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
+#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
+#define MC_ERR_REG_SM_ERR BIT(31)
+ u64 mc_err_mask;
+ u64 mc_err_alarm;
+
+ u8 unused18[0x100 - 0x28];
+
+/* MC configuration */
+ u64 rx_queue_cfg;
+#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
+#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
+#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
+#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
+#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
+#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
+#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
+#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
+
+ u64 mc_rldram_mrs;
+#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
+#define MC_RLDRAM_MRS_ENABLE BIT(47)
+
+ u64 mc_rldram_interleave;
+
+ u64 mc_pause_thresh_q0q3;
+ u64 mc_pause_thresh_q4q7;
+
+ u64 mc_red_thresh_q[8];
+
+ u8 unused19[0x200 - 0x168];
+ u64 mc_rldram_ref_per;
+ u8 unused20[0x220 - 0x208];
+ u64 mc_rldram_test_ctrl;
+#define MC_RLDRAM_TEST_MODE BIT(47)
+#define MC_RLDRAM_TEST_WRITE BIT(7)
+#define MC_RLDRAM_TEST_GO BIT(15)
+#define MC_RLDRAM_TEST_DONE BIT(23)
+#define MC_RLDRAM_TEST_PASS BIT(31)
+
+ u8 unused21[0x240 - 0x228];
+ u64 mc_rldram_test_add;
+ u8 unused22[0x260 - 0x248];
+ u64 mc_rldram_test_d0;
+ u8 unused23[0x280 - 0x268];
+ u64 mc_rldram_test_d1;
+ u8 unused24[0x300 - 0x288];
+ u64 mc_rldram_test_d2;
+ u8 unused25[0x700 - 0x308];
+ u64 mc_debug_ctrl;
+
+ u8 unused26[0x3000 - 0x2f08];
+
+/* XGXG */
+ /* XGXS control registers */
+
+ u64 xgxs_int_status;
+#define XGXS_INT_STATUS_TXGXS BIT(0)
+#define XGXS_INT_STATUS_RXGXS BIT(1)
+ u64 xgxs_int_mask;
+#define XGXS_INT_MASK_TXGXS BIT(0)
+#define XGXS_INT_MASK_RXGXS BIT(1)
+
+ u64 xgxs_txgxs_err_reg;
+#define TXGXS_ECC_DB_ERR BIT(15)
+ u64 xgxs_txgxs_err_mask;
+ u64 xgxs_txgxs_err_alarm;
+
+ u64 xgxs_rxgxs_err_reg;
+ u64 xgxs_rxgxs_err_mask;
+ u64 xgxs_rxgxs_err_alarm;
+
+ u8 unused27[0x100 - 0x40];
+
+ u64 xgxs_cfg;
+ u64 xgxs_status;
+
+ u64 xgxs_cfg_key;
+ u64 xgxs_efifo_cfg; /* CHANGED */
+ u64 rxgxs_ber_0; /* CHANGED */
+ u64 rxgxs_ber_1; /* CHANGED */
+
+} XENA_dev_config_t;
+
+#define XENA_REG_SPACE sizeof(XENA_dev_config_t)
+#define XENA_EEPROM_SPACE (0x01 << 11)
+
+#endif /* _REGS_H */
diff -Nru a/drivers/net/s2io.c b/drivers/net/s2io.c
--- /dev/null Wed Dec 31 16:00:00 1969
+++ b/drivers/net/s2io.c Sun Apr 4 18:58:15 2004
@@ -0,0 +1,4396 @@
+/************************************************************************
+ * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
+ * Copyright(c) 2002-2005 S2IO Technologies
+
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ * Drivers based on or derived from this code fall under the GPL and must
+ * retain the authorship, copyright and license notice. This file is not
+ * a complete program and may only be used when the entire operating
+ * system is licensed under the GPL.
+ * See the file COPYING in this distribution for more information.
+ *
+ * Credits:
+ * Jeff Garzik : For pointing out the improper error condition
+ * check in the s2io_xmit routine and also some
+ * issues in the Tx watch dog function. Also for
+ * patiently answering all those innumerable
+ * questions regaring the 2.6 porting issues.
+ * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
+ * macros available only in 2.6 Kernel.
+ * Francois Romieu : For pointing out all code part that were
+ * deprecated and also styling related comments.
+ * Grant Grundler : For helping me get rid of some Architecture
+ * dependent code.
+ * Christopher Hellwig : Some more 2.6 specific issues in the driver.
+ *
+ * The module loadable parameters that are supported by the driver and a brief
+ * explaination of all the variables.
+ * ring_num : This can be used to program the number of receive rings used
+ * in the driver.
+ * frame_len: This is an array of size 8. Using this we can set the maximum
+ * size of the received frame that can be steered into the corrsponding
+ * receive ring.
+ * ring_len: This defines the number of descriptors each ring can have. This
+ * is also an array of size 8.
+ * fifo_num: This defines the number of Tx FIFOs thats used int the driver.
+ * fifo_len: This too is an array of 8. Each element defines the number of
+ * Tx descriptors that can be associated with each corresponding FIFO.
+ * latency_timer: This input is programmed into the Latency timer register
+ * in PCI Configuration space.
+ ************************************************************************/
+
+#include<linux/config.h>
+#include<linux/module.h>
+#include<linux/types.h>
+#include<linux/errno.h>
+#include<linux/ioport.h>
+#include<linux/pci.h>
+#include<linux/kernel.h>
+#include<linux/netdevice.h>
+#include<linux/etherdevice.h>
+#include<linux/skbuff.h>
+#include<linux/init.h>
+#include<linux/delay.h>
+#include<linux/stddef.h>
+#include<linux/ioctl.h>
+#include<linux/timex.h>
+#include<linux/sched.h>
+#include<linux/ethtool.h>
+#include<asm/system.h>
+#include<asm/uaccess.h>
+#include<linux/version.h>
+#include<asm/io.h>
+#include<linux/workqueue.h>
+
+/* local include */
+#include "s2io.h"
+#include "s2io-regs.h"
+
+/* S2io Driver name & version. */
+static char s2io_driver_name[] = "s2io";
+static char s2io_driver_version[] = "Version 1.0";
+
+#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
+ ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
+#define TASKLET_IN_USE test_and_set_bit(0, \
+ (unsigned long *)(&sp->tasklet_status))
+#define PANIC 1
+#define LOW 2
+static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
+{
+ int level = 0;
+ if ((sp->pkt_cnt[ring] - rxb_size) > 128) {
+ level = LOW;
+ if (rxb_size < sp->pkt_cnt[ring] / 8)
+ level = PANIC;
+ }
+
+ return level;
+}
+
+/* Ethtool related variables and Macros. */
+static char s2io_gstrings[][ETH_GSTRING_LEN] = {
+ "Register test\t(offline)",
+ "Eeprom test\t(offline)",
+ "Link test\t(online)",
+ "RLDRAM test\t(offline)",
+ "BIST Test\t(offline)"
+};
+
+static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
+ {"tmac_frms"},
+ {"tmac_data_octets"},
+ {"tmac_drop_frms"},
+ {"tmac_mcst_frms"},
+ {"tmac_bcst_frms"},
+ {"tmac_pause_ctrl_frms"},
+ {"tmac_any_err_frms"},
+ {"tmac_vld_ip_octets"},
+ {"tmac_vld_ip"},
+ {"tmac_drop_ip"},
+ {"tmac_icmp"},
+ {"tmac_rst_tcp"},
+ {"tmac_tcp"},
+ {"tmac_udp"},
+ {"rmac_vld_frms"},
+ {"rmac_data_octets"},
+ {"rmac_fcs_err_frms"},
+ {"rmac_drop_frms"},
+ {"rmac_vld_mcst_frms"},
+ {"rmac_vld_bcst_frms"},
+ {"rmac_in_rng_len_err_frms"},
+ {"rmac_long_frms"},
+ {"rmac_pause_ctrl_frms"},
+ {"rmac_discarded_frms"},
+ {"rmac_usized_frms"},
+ {"rmac_osized_frms"},
+ {"rmac_frag_frms"},
+ {"rmac_jabber_frms"},
+ {"rmac_ip"},
+ {"rmac_ip_octets"},
+ {"rmac_hdr_err_ip"},
+ {"rmac_drop_ip"},
+ {"rmac_icmp"},
+ {"rmac_tcp"},
+ {"rmac_udp"},
+ {"rmac_err_drp_udp"},
+ {"rmac_pause_cnt"},
+ {"rmac_accepted_ip"},
+ {"rmac_err_tcp"},
+};
+
+#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
+#define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
+
+#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
+#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
+
+
+/* Constants to be programmed into the Xena's registers to configure
+ * the XAUI.
+ */
+
+#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
+#define END_SIGN 0x0
+
+static u64 default_mdio_cfg[] = {
+ /* Reset PMA PLL */
+ 0xC001010000000000ULL, 0xC0010100000000E0ULL,
+ 0xC0010100008000E4ULL,
+ /* Remove Reset from PMA PLL */
+ 0xC001010000000000ULL, 0xC0010100000000E0ULL,
+ 0xC0010100000000E4ULL,
+ END_SIGN
+};
+
+static u64 default_dtx_cfg[] = {
+ 0x8000051500000000ULL, 0x80000515000000E0ULL,
+ 0x80000515D93500E4ULL, 0x8001051500000000ULL,
+ 0x80010515000000E0ULL, 0x80010515001E00E4ULL,
+ 0x8002051500000000ULL, 0x80020515000000E0ULL,
+ 0x80020515F21000E4ULL,
+ /* Set PADLOOPBACKN */
+ 0x8002051500000000ULL, 0x80020515000000E0ULL,
+ 0x80020515B20000E4ULL, 0x8003051500000000ULL,
+ 0x80030515000000E0ULL, 0x80030515B20000E4ULL,
+ 0x8004051500000000ULL, 0x80040515000000E0ULL,
+ 0x80040515B20000E4ULL, 0x8005051500000000ULL,
+ 0x80050515000000E0ULL, 0x80050515B20000E4ULL,
+ SWITCH_SIGN,
+ /* Remove PADLOOPBACKN */
+ 0x8002051500000000ULL, 0x80020515000000E0ULL,
+ 0x80020515F20000E4ULL, 0x8003051500000000ULL,
+ 0x80030515000000E0ULL, 0x80030515F20000E4ULL,
+ 0x8004051500000000ULL, 0x80040515000000E0ULL,
+ 0x80040515F20000E4ULL, 0x8005051500000000ULL,
+ 0x80050515000000E0ULL, 0x80050515F20000E4ULL,
+ END_SIGN
+};
+
+/* Constants for Fixing the MacAddress problem seen mostly on
+ * Alpha machines.
+ */
+static u64 fix_mac[] = {
+ 0x0060000000000000ULL, 0x0060600000000000ULL,
+ 0x0040600000000000ULL, 0x0000600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0060600000000000ULL,
+ 0x0020600000000000ULL, 0x0000600000000000ULL,
+ 0x0040600000000000ULL, 0x0060600000000000ULL,
+ END_SIGN
+};
+
+
+/* Module Loadable parameters. */
+static u32 ring_num;
+static u32 frame_len[MAX_RX_RINGS];
+static u32 ring_len[MAX_RX_RINGS];
+static u32 fifo_num;
+static u32 fifo_len[MAX_TX_FIFOS];
+static u32 rx_prio;
+static u32 tx_prio;
+static u8 latency_timer = 0;
+
+/*
+ * S2IO device table.
+ * This table lists all the devices that this driver supports.
+ */
+static struct pci_device_id s2io_tbl[] __devinitdata = {
+ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
+ PCI_ANY_ID, PCI_ANY_ID},
+ {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
+ PCI_ANY_ID, PCI_ANY_ID},
+ {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, s2io_tbl);
+
+static struct pci_driver s2io_driver = {
+ name:"S2IO",
+ id_table:s2io_tbl,
+ probe:s2io_init_nic,
+ remove:s2io_rem_nic,
+};
+
+/*
+ * Input Arguments:
+ * Device private variable.
+ * Return Value:
+ * SUCCESS on success and an appropriate -ve value on failure.
+ * Description:
+ * The function allocates the all memory areas shared
+ * between the NIC and the driver. This includes Tx descriptors,
+ * Rx descriptors and the statistics block.
+ */
+static int initSharedMem(struct s2io_nic *nic)
+{
+ u32 size;
+ void *tmp_v_addr, *tmp_v_addr_next;
+ dma_addr_t tmp_p_addr, tmp_p_addr_next;
+ RxD_block_t *pre_rxd_blk = NULL;
+ int i, j, blk_cnt;
+ struct net_device *dev = nic->dev;
+
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+
+ /* Allocation and initialization of TXDLs in FIOFs */
+ size = 0;
+ for (i = 0; i < config->TxFIFONum; i++) {
+ size += config->TxCfg[i].FifoLen;
+ }
+ if (size > MAX_AVAILABLE_TXDS) {
+ DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "exceeds the maximum value ");
+ DBG_PRINT(ERR_DBG, "that can be used\n");
+ return FAILURE;
+ }
+ size *= (sizeof(TxD_t) * config->MaxTxDs);
+
+ mac_control->txd_list_mem = pci_alloc_consistent
+ (nic->pdev, size, &mac_control->txd_list_mem_phy);
+ if (!mac_control->txd_list_mem) {
+ return -ENOMEM;
+ }
+ mac_control->txd_list_mem_sz = size;
+
+ tmp_v_addr = mac_control->txd_list_mem;
+ tmp_p_addr = mac_control->txd_list_mem_phy;
+ memset(tmp_v_addr, 0, size);
+
+ DBG_PRINT(INIT_DBG, "%s:List Mem PHY: 0x%llx\n", dev->name,
+ (unsigned long long) tmp_p_addr);
+
+ for (i = 0; i < config->TxFIFONum; i++) {
+ mac_control->txdl_start_phy[i] = tmp_p_addr;
+ mac_control->txdl_start[i] = (TxD_t *) tmp_v_addr;
+ mac_control->tx_curr_put_info[i].offset = 0;
+ mac_control->tx_curr_put_info[i].fifo_len =
+ config->TxCfg[i].FifoLen - 1;
+ mac_control->tx_curr_get_info[i].offset = 0;
+ mac_control->tx_curr_get_info[i].fifo_len =
+ config->TxCfg[i].FifoLen - 1;
+
+ tmp_p_addr +=
+ (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
+ config->MaxTxDs);
+ tmp_v_addr +=
+ (config->TxCfg[i].FifoLen * (sizeof(TxD_t)) *
+ config->MaxTxDs);
+ }
+
+ /* Allocation and initialization of RXDs in Rings */
+ size = 0;
+ for (i = 0; i < config->RxRingNum; i++) {
+ if (config->RxCfg[i].NumRxd % (MAX_RXDS_PER_BLOCK + 1)) {
+ DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
+ DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
+ i);
+ DBG_PRINT(ERR_DBG, "RxDs per Block");
+ return FAILURE;
+ }
+ size += config->RxCfg[i].NumRxd;
+ nic->block_count[i] =
+ config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ nic->pkt_cnt[i] =
+ config->RxCfg[i].NumRxd - nic->block_count[i];
+ }
+ size = (size * (sizeof(RxD_t)));
+ mac_control->rxd_ring_mem_sz = size;
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ mac_control->rx_curr_get_info[i].block_index = 0;
+ mac_control->rx_curr_get_info[i].offset = 0;
+ mac_control->rx_curr_get_info[i].ring_len =
+ config->RxCfg[i].NumRxd - 1;
+ mac_control->rx_curr_put_info[i].block_index = 0;
+ mac_control->rx_curr_put_info[i].offset = 0;
+ mac_control->rx_curr_put_info[i].ring_len =
+ config->RxCfg[i].NumRxd - 1;
+ blk_cnt =
+ config->RxCfg[i].NumRxd / (MAX_RXDS_PER_BLOCK + 1);
+ /* Allocating all the Rx blocks */
+ for (j = 0; j < blk_cnt; j++) {
+ size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
+ tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
+ &tmp_p_addr);
+ if (tmp_v_addr == NULL) {
+ /* In case of failure, freeSharedMem()
+ * is called, which should free any
+ * memory that was alloced till the
+ * failure happened.
+ */
+ nic->rx_blocks[i][j].block_virt_addr =
+ tmp_v_addr;
+ return -ENOMEM;
+ }
+ memset(tmp_v_addr, 0, size);
+ nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr;
+ nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr;
+ }
+ /* Interlinking all Rx Blocks */
+ for (j = 0; j < blk_cnt; j++) {
+ tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
+ tmp_v_addr_next =
+ nic->rx_blocks[i][(j + 1) %
+ blk_cnt].block_virt_addr;
+ tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
+ tmp_p_addr_next =
+ nic->rx_blocks[i][(j + 1) %
+ blk_cnt].block_dma_addr;
+
+ pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
+ pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
+ * marker.
+ */
+ pre_rxd_blk->reserved_2_pNext_RxD_block =
+ (unsigned long) tmp_v_addr_next;
+ pre_rxd_blk->pNext_RxD_Blk_physical =
+ (u64) tmp_p_addr_next;
+ }
+ }
+
+ /* Allocation and initialization of Statistics block */
+ size = sizeof(StatInfo_t);
+ mac_control->stats_mem = pci_alloc_consistent
+ (nic->pdev, size, &mac_control->stats_mem_phy);
+
+ if (!mac_control->stats_mem) {
+ /* In case of failure, freeSharedMem() is called, which
+ * should free any memory that was alloced till the
+ * failure happened.
+ */
+ return -ENOMEM;
+ }
+ mac_control->stats_mem_sz = size;
+
+ tmp_v_addr = mac_control->stats_mem;
+ mac_control->StatsInfo = (StatInfo_t *) tmp_v_addr;
+ memset(tmp_v_addr, 0, size);
+
+ DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
+ (unsigned long long) tmp_p_addr);
+
+ return SUCCESS;
+}
+
+/*
+ * Input Arguments:
+ * Device peivate variable.
+ * Return Value:
+ * NONE
+ * Description:
+ * This function is to free all memory locations allocated by
+ * the initSharedMem() function and return it to the kernel.
+ */
+static void freeSharedMem(struct s2io_nic *nic)
+{
+ int i, j, blk_cnt, size;
+ void *tmp_v_addr;
+ dma_addr_t tmp_p_addr;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+
+ if (!nic)
+ return;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ if (mac_control->txd_list_mem) {
+ pci_free_consistent(nic->pdev,
+ mac_control->txd_list_mem_sz,
+ mac_control->txd_list_mem,
+ mac_control->txd_list_mem_phy);
+ }
+
+ size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
+ for (i = 0; i < config->RxRingNum; i++) {
+ blk_cnt = nic->block_count[i];
+ for (j = 0; j < blk_cnt; j++) {
+ tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
+ tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
+ if (tmp_v_addr == NULL)
+ break;
+ pci_free_consistent(nic->pdev, size,
+ tmp_v_addr, tmp_p_addr);
+ }
+ }
+
+ if (mac_control->stats_mem) {
+ pci_free_consistent(nic->pdev,
+ mac_control->stats_mem_sz,
+ mac_control->stats_mem,
+ mac_control->stats_mem_phy);
+ }
+}
+
+/*
+ * Input Arguments:
+ * device peivate variable
+ * Return Value:
+ * SUCCESS on success and '-1' on failure (endian settings incorrect).
+ * Description:
+ * The function sequentially configures every block
+ * of the H/W from their reset values.
+ */
+static int initNic(struct s2io_nic *nic)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ struct net_device *dev = nic->dev;
+ register u64 val64 = 0;
+ void *add;
+ u32 time;
+ int i, j;
+ mac_info_t *mac_control;
+ struct config_param *config;
+ int mdio_cnt = 0, dtx_cnt = 0;
+ unsigned long long print_var, mem_share;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ /* Set proper endian settings and verify the same by
+ * reading the PIF Feed-back register.
+ */
+#ifdef __BIG_ENDIAN
+ /* The device by default set to a big endian format, so
+ * a big endian driver need not set anything.
+ */
+ writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
+ val64 = (SWAPPER_CTRL_PIF_R_FE |
+ SWAPPER_CTRL_PIF_R_SE |
+ SWAPPER_CTRL_PIF_W_FE |
+ SWAPPER_CTRL_PIF_W_SE |
+ SWAPPER_CTRL_TXP_FE |
+ SWAPPER_CTRL_TXP_SE |
+ SWAPPER_CTRL_TXD_R_FE |
+ SWAPPER_CTRL_TXD_W_FE |
+ SWAPPER_CTRL_TXF_R_FE |
+ SWAPPER_CTRL_RXD_R_FE |
+ SWAPPER_CTRL_RXD_W_FE |
+ SWAPPER_CTRL_RXF_W_FE |
+ SWAPPER_CTRL_XMSI_FE |
+ SWAPPER_CTRL_XMSI_SE |
+ SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
+ writeq(val64, &bar0->swapper_ctrl);
+#else
+ /* Initially we enable all bits to make it accessible by
+ * the driver, then we selectively enable only those bits
+ * that we want to set.
+ */
+ writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
+ val64 = (SWAPPER_CTRL_PIF_R_FE |
+ SWAPPER_CTRL_PIF_R_SE |
+ SWAPPER_CTRL_PIF_W_FE |
+ SWAPPER_CTRL_PIF_W_SE |
+ SWAPPER_CTRL_TXP_FE |
+ SWAPPER_CTRL_TXP_SE |
+ SWAPPER_CTRL_TXD_R_FE |
+ SWAPPER_CTRL_TXD_R_SE |
+ SWAPPER_CTRL_TXD_W_FE |
+ SWAPPER_CTRL_TXD_W_SE |
+ SWAPPER_CTRL_TXF_R_FE |
+ SWAPPER_CTRL_RXD_R_FE |
+ SWAPPER_CTRL_RXD_R_SE |
+ SWAPPER_CTRL_RXD_W_FE |
+ SWAPPER_CTRL_RXD_W_SE |
+ SWAPPER_CTRL_RXF_W_FE |
+ SWAPPER_CTRL_XMSI_FE |
+ SWAPPER_CTRL_XMSI_SE |
+ SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
+ writeq(val64, &bar0->swapper_ctrl);
+#endif
+
+ /* Verifying if endian settings are accurate by reading
+ * a feedback register.
+ */
+ val64 = readq(&bar0->pif_rd_swapper_fb);
+ if (val64 != 0x0123456789ABCDEFULL) {
+ /* Endian settings are incorrect, calls for another dekko. */
+ print_var = (unsigned long long) val64;
+ DBG_PRINT(INIT_DBG, "%s: Endian settings are wrong",
+ dev->name);
+ DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var);
+
+ return FAILURE;
+ }
+
+ /* Remove XGXS from reset state */
+ val64 = 0;
+ writeq(val64, &bar0->sw_reset);
+ val64 = readq(&bar0->sw_reset);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 2);
+
+ /* Enable Receiving broadcasts */
+ val64 = readq(&bar0->mac_cfg);
+ val64 |= MAC_RMAC_BCAST_ENABLE;
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writeq(val64, &bar0->mac_cfg);
+
+ /* Read registers in all blocks */
+ val64 = readq(&bar0->mac_int_mask);
+ val64 = readq(&bar0->mc_int_mask);
+ val64 = readq(&bar0->xgxs_int_mask);
+
+ /* Set MTU */
+ val64 = dev->mtu;
+ writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
+
+ /* Configuring the XAUI Interface of Xena.
+ *****************************************
+ * To Configure the Xena's XAUI, one has to write a series
+ * of 64 bit values into two registers in a particular
+ * sequence. Hence a macro 'SWITCH_SIGN' has been defined
+ * which will be defined in the array of configuration values
+ * (default_dtx_cfg & default_mdio_cfg) at appropriate places
+ * to switch writing from one regsiter to another. We continue
+ * writing these values until we encounter the 'END_SIGN' macro.
+ * For example, After making a series of 21 writes into
+ * dtx_control register the 'SWITCH_SIGN' appears and hence we
+ * start writing into mdio_control until we encounter END_SIGN.
+ */
+ while (1) {
+ dtx_cfg:
+ while (default_dtx_cfg[dtx_cnt] != END_SIGN) {
+ if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
+ dtx_cnt++;
+ goto mdio_cfg;
+ }
+ writeq(default_dtx_cfg[dtx_cnt],
+ &bar0->dtx_control);
+ val64 = readq(&bar0->dtx_control);
+ dtx_cnt++;
+ }
+ mdio_cfg:
+ while (default_mdio_cfg[mdio_cnt] != END_SIGN) {
+ if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
+ mdio_cnt++;
+ goto dtx_cfg;
+ }
+ writeq(default_mdio_cfg[mdio_cnt],
+ &bar0->mdio_control);
+ val64 = readq(&bar0->mdio_control);
+ mdio_cnt++;
+ }
+ if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
+ (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
+ break;
+ } else {
+ goto dtx_cfg;
+ }
+ }
+
+ /* Tx DMA Initialization */
+ val64 = 0;
+ writeq(val64, &bar0->tx_fifo_partition_0);
+ writeq(val64, &bar0->tx_fifo_partition_1);
+ writeq(val64, &bar0->tx_fifo_partition_2);
+ writeq(val64, &bar0->tx_fifo_partition_3);
+
+
+ for (i = 0, j = 0; i < config->TxFIFONum; i++) {
+ val64 |=
+ vBIT(config->TxCfg[i].FifoLen - 1, ((i * 32) + 19),
+ 13) | vBIT(config->TxCfg[i].FifoPriority,
+ ((i * 32) + 5), 3);
+
+ if (i == (config->TxFIFONum - 1)) {
+ if (i % 2 == 0)
+ i++;
+ }
+
+ switch (i) {
+ case 1:
+ writeq(val64, &bar0->tx_fifo_partition_0);
+ val64 = 0;
+ break;
+ case 3:
+ writeq(val64, &bar0->tx_fifo_partition_1);
+ val64 = 0;
+ break;
+ case 5:
+ writeq(val64, &bar0->tx_fifo_partition_2);
+ val64 = 0;
+ break;
+ case 7:
+ writeq(val64, &bar0->tx_fifo_partition_3);
+ break;
+ }
+ }
+
+ /* Enable Tx FIFO partition 0. */
+ val64 = readq(&bar0->tx_fifo_partition_0);
+ val64 |= BIT(0); /* To enable the FIFO partition. */
+ writeq(val64, &bar0->tx_fifo_partition_0);
+
+ val64 = readq(&bar0->tx_fifo_partition_0);
+ DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
+ &bar0->tx_fifo_partition_0, (unsigned long long) val64);
+
+ /*
+ * Initialization of Tx_PA_CONFIG register to ignore packet
+ * integrity checking.
+ */
+ val64 = readq(&bar0->tx_pa_cfg);
+ val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
+ TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
+ writeq(val64, &bar0->tx_pa_cfg);
+
+ /* Rx DMA intialization. */
+ val64 = 0;
+ for (i = 0; i < config->RxRingNum; i++) {
+ val64 |=
+ vBIT(config->RxCfg[i].RingPriority, (5 + (i * 8)), 3);
+ }
+ writeq(val64, &bar0->rx_queue_priority);
+
+ /* Allocating equal share of memory to all the configured
+ * Rings.
+ */
+ val64 = 0;
+ for (i = 0; i < config->RxRingNum; i++) {
+ switch (i) {
+ case 0:
+ mem_share = (64 / config->RxRingNum +
+ 64 % config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
+ continue;
+ case 1:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
+ continue;
+ case 2:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
+ continue;
+ case 3:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
+ continue;
+ case 4:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
+ continue;
+ case 5:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
+ continue;
+ case 6:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
+ continue;
+ case 7:
+ mem_share = (64 / config->RxRingNum);
+ val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
+ continue;
+ }
+ }
+ writeq(val64, &bar0->rx_queue_cfg);
+
+ /* Initializing the Tx round robin registers to 0.
+ * Filling Tx and Rx round robin registers as per the
+ * number of FIFOs and Rings is still TODO.
+ */
+ writeq(0, &bar0->tx_w_round_robin_0);
+ writeq(0, &bar0->tx_w_round_robin_1);
+ writeq(0, &bar0->tx_w_round_robin_2);
+ writeq(0, &bar0->tx_w_round_robin_3);
+ writeq(0, &bar0->tx_w_round_robin_4);
+
+ /* Disable Rx steering. Hard coding all packets be steered to
+ * Queue 0 for now.
+ * TODO*/
+ if (rx_prio) {
+ u64 def = 0x8000000000000000ULL, tmp;
+ for (i = 0; i < MAX_RX_RINGS; i++) {
+ tmp = (u64) (def >> (i % config->RxRingNum));
+ val64 |= (u64) (tmp >> (i * 8));
+ }
+ writeq(val64, &bar0->rts_qos_steering);
+ } else {
+ val64 = 0x8080808080808080ULL;
+ writeq(val64, &bar0->rts_qos_steering);
+ }
+
+ /* UDP Fix */
+ val64 = 0;
+ for (i = 1; i < 8; i++)
+ writeq(val64, &bar0->rts_frm_len_n[i]);
+
+ /* Set rts_frm_len register for fifo 0 */
+ writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22),
+ &bar0->rts_frm_len_n[0]);
+
+ /* Enable statistics */
+ writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
+ val64 = SET_UPDT_PERIOD(8) | STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
+ writeq(val64, &bar0->stat_cfg);
+
+ /* Initializing the sampling rate for the device to calculate the
+ * bandwidth utilization.
+ */
+ val64 = MAC_TX_LINK_UTIL_VAL(0x5) | MAC_RX_LINK_UTIL_VAL(0x5);
+ writeq(val64, &bar0->mac_link_util);
+
+
+ /* Initializing the Transmit and Receive Traffic Interrupt
+ * Scheme.
+ */
+ /* TTI Initialization */
+ val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) |
+ TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) |
+ TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
+ writeq(val64, &bar0->tti_data1_mem);
+
+ val64 =
+ TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) |
+ TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
+ writeq(val64, &bar0->tti_data2_mem);
+
+ val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
+ writeq(val64, &bar0->tti_command_mem);
+
+ /* Once the operation completes, the Strobe bit of the command
+ * register will be reset. We poll for this particular condition
+ * We wait for a maximum of 500ms for the operation to complete,
+ * if it's not complete by then we return error.
+ */
+ time = 0;
+ while (TRUE) {
+ val64 = readq(&bar0->tti_command_mem);
+ if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
+ break;
+ }
+ if (time > 10) {
+ DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
+ dev->name);
+ return -1;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ time++;
+ }
+
+ /* RTI Initialization */
+ val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) |
+ RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) |
+ RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
+ writeq(val64, &bar0->rti_data1_mem);
+
+ val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) |
+ RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
+ writeq(val64, &bar0->rti_data2_mem);
+
+ val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
+ writeq(val64, &bar0->rti_command_mem);
+
+ /* Once the operation completes, the Strobe bit of the command
+ * register will be reset. We poll for this particular condition
+ * We wait for a maximum of 500ms for the operation to complete,
+ * if it's not complete by then we return error.
+ */
+ time = 0;
+ while (TRUE) {
+ val64 = readq(&bar0->rti_command_mem);
+ if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
+ break;
+ }
+ if (time > 10) {
+ DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
+ dev->name);
+ return -1;
+ }
+ time++;
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ }
+
+ /* Initializing proper values as Pause threshold into all
+ * the 8 Queues on Rx side.
+ */
+ writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
+ writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
+
+ /* Disable RMAC PAD STRIPPING */
+ add = (void *) &bar0->mac_cfg;
+ val64 = readq(&bar0->mac_cfg);
+ val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) (val64), add);
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) (val64 >> 32), (add + 4));
+ val64 = readq(&bar0->mac_cfg);
+
+ return SUCCESS;
+}
+
+/*
+ * Input Arguments:
+ * device private variable,
+ * A mask indicating which Intr block must be modified and,
+ * A flag indicating whether to enable or disable the Intrs.
+ * Return Value:
+ * NONE.
+ * Description:
+ * This function will either disable or enable the interrupts
+ * depending on the flag argument. The mask argument can be used to
+ * enable/disable any Intr block.
+ */
+static void en_dis_able_NicIntrs(struct s2io_nic *nic, u16 mask, int flag)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ register u64 val64 = 0, temp64 = 0;
+
+ /* Top level interrupt classification */
+ /* PIC Interrupts */
+ if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
+ /* Enable PIC Intrs in the general intr mask register */
+ val64 = TXPIC_INT_M | PIC_RX_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* Disabled all PCIX, Flash, MDIO, IIC and GPIO
+ * interrupts for now.
+ * TODO */
+ writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
+ /* No MSI Support is available presently, so TTI and
+ * RTI interrupts are also disabled.
+ */
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable PIC Intrs in the general intr mask register
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* DMA Interrupts */
+ /* Enabling/Disabling Tx DMA interrupts */
+ if (mask & TX_DMA_INTR) {
+ /* Enable TxDMA Intrs in the general intr mask register */
+ val64 = TXDMA_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* Disable all interrupts other than PFC interrupt in
+ * DMA level.
+ */
+ val64 = DISABLE_ALL_INTRS & (~TXDMA_PFC_INT_M);
+ writeq(val64, &bar0->txdma_int_mask);
+ /* Enable only the MISC error 1 interrupt in PFC block
+ */
+ val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
+ writeq(val64, &bar0->pfc_err_mask);
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable TxDMA Intrs in the general intr mask
+ * register */
+ writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
+ writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* Enabling/Disabling Rx DMA interrupts */
+ if (mask & RX_DMA_INTR) {
+ /* Enable RxDMA Intrs in the general intr mask register */
+ val64 = RXDMA_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* All RxDMA block interrupts are disabled for now
+ * TODO */
+ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable RxDMA Intrs in the general intr mask
+ * register */
+ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* MAC Interrupts */
+ /* Enabling/Disabling MAC interrupts */
+ if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
+ val64 = TXMAC_INT_M | RXMAC_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* All MAC block error interrupts are disabled for now
+ * except the link status change interrupt.
+ * TODO*/
+ val64 = MAC_INT_STATUS_RMAC_INT;
+ temp64 = readq(&bar0->mac_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->mac_int_mask);
+
+ val64 = readq(&bar0->mac_rmac_err_mask);
+ val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
+ writeq(val64, &bar0->mac_rmac_err_mask);
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable MAC Intrs in the general intr mask register
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
+ writeq(DISABLE_ALL_INTRS,
+ &bar0->mac_rmac_err_mask);
+
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* XGXS Interrupts */
+ if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
+ val64 = TXXGXS_INT_M | RXXGXS_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* All XGXS block error interrupts are disabled for now
+ * TODO */
+ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable MC Intrs in the general intr mask register
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* Memory Controller(MC) interrupts */
+ if (mask & MC_INTR) {
+ val64 = MC_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* All MC block error interrupts are disabled for now
+ * TODO */
+ writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable MC Intrs in the general intr mask register
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+
+ /* Tx traffic interrupts */
+ if (mask & TX_TRAFFIC_INTR) {
+ val64 = TXTRAFFIC_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ /* Enable all the Tx side interrupts */
+ writeq(0x0, &bar0->tx_traffic_mask); /* '0' Enables
+ * all 64 TX
+ * interrupt
+ * levels.
+ */
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable Tx Traffic Intrs in the general intr mask
+ * register.
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+
+ /* Rx traffic interrupts */
+ if (mask & RX_TRAFFIC_INTR) {
+ val64 = RXTRAFFIC_INT_M;
+ if (flag == ENABLE_INTRS) {
+ temp64 = readq(&bar0->general_int_mask);
+ temp64 &= ~((u64) val64);
+ writeq(temp64, &bar0->general_int_mask);
+ writeq(0x0, &bar0->rx_traffic_mask); /* '0' Enables
+ * all 8 RX
+ * interrupt
+ * levels.
+ */
+ } else if (flag == DISABLE_INTRS) {
+ /* Disable Rx Traffic Intrs in the general intr mask
+ * register.
+ */
+ writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
+ temp64 = readq(&bar0->general_int_mask);
+ val64 |= temp64;
+ writeq(val64, &bar0->general_int_mask);
+ }
+ }
+}
+
+/*
+ * Input Arguments:
+ * val64 - Value read from adapter status register.
+ * flag - indicates if the adapter enable bit was ever written once before.
+ * Return Value:
+ * void.
+ * Description:
+ * Returns whether the H/W is ready to go or not. Depending on whether
+ * adapter enable bit was written or not the comparison differs and the
+ * calling function passes the input argument flag to indicate this.
+ */
+static int verify_xena_quiescence(u64 val64, int flag)
+{
+ int ret = 0;
+ u64 tmp64 = ~((u64) val64);
+
+ if (!
+ (tmp64 &
+ (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
+ ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
+ ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
+ ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
+ ADAPTER_STATUS_P_PLL_LOCK))) {
+ if (flag == FALSE) {
+ if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
+ ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
+ ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
+
+ ret = 1;
+
+ }
+ } else {
+ if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
+ ADAPTER_STATUS_RMAC_PCC_IDLE) &&
+ (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
+ ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
+ ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
+
+ ret = 1;
+
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * New procedure to clear mac address reading problems on Alpha platforms
+ *
+ */
+void FixMacAddress(nic_t * sp)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+ int i = 0;
+
+ while (fix_mac[i] != END_SIGN) {
+ writeq(fix_mac[i++], &bar0->gpio_control);
+ val64 = readq(&bar0->gpio_control);
+ }
+}
+
+/*
+ * Input Arguments:
+ * device private variable.
+ * Return Value:
+ * SUCCESS on success and -1 on failure.
+ * Description:
+ * This function actually turns the device on. Before this
+ * function is called, all Registers are configured from their reset states
+ * and shared memory is allocated but the NIC is still quiescent. On
+ * calling this function, the device interrupts are cleared and the NIC is
+ * literally switched on by writing into the adapter control register.
+ */
+static int startNic(struct s2io_nic *nic)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ struct net_device *dev = nic->dev;
+ register u64 val64 = 0;
+ u16 interruptible, i;
+ u16 subid;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ /* PRC Initialization and configuration */
+ for (i = 0; i < config->RxRingNum; i++) {
+ writeq((u64) nic->rx_blocks[i][0].block_dma_addr,
+ &bar0->prc_rxd0_n[i]);
+
+ val64 = readq(&bar0->prc_ctrl_n[i]);
+ val64 |= PRC_CTRL_RC_ENABLED;
+ writeq(val64, &bar0->prc_ctrl_n[i]);
+ }
+
+ /* Enabling MC-RLDRAM. After enabling the device, we timeout
+ * for around 100ms, which is approximately the time required
+ * for the device to be ready for operation.
+ */
+ val64 = readq(&bar0->mc_rldram_mrs);
+ val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
+ writeq(val64, &bar0->mc_rldram_mrs);
+ val64 = readq(&bar0->mc_rldram_mrs);
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 10); /* Delay by around 100 ms. */
+
+ /* Enabling ECC Protection. */
+ val64 = readq(&bar0->adapter_control);
+ val64 &= ~ADAPTER_ECC_EN;
+ writeq(val64, &bar0->adapter_control);
+
+ /* Clearing any possible Link state change interrupts that
+ * could have popped up just before Enabling the card.
+ */
+ val64 = readq(&bar0->mac_rmac_err_reg);
+ if (val64)
+ writeq(val64, &bar0->mac_rmac_err_reg);
+
+ /* Verify if the device is ready to be enabled, if so enable
+ * it.
+ */
+ val64 = readq(&bar0->adapter_status);
+ if (!verify_xena_quiescence(val64, nic->device_enabled_once)) {
+ DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
+ DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
+ (unsigned long long) val64);
+ return FAILURE;
+ }
+
+ /* Enable select interrupts */
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
+ RX_MAC_INTR;
+ en_dis_able_NicIntrs(nic, interruptible, ENABLE_INTRS);
+
+ /* With some switches, link might be already up at this point.
+ * Because of this weird behavior, when we enable laser,
+ * we may not get link. We need to handle this. We cannot
+ * figure out which switch is misbehaving. So we are forced to
+ * make a global change.
+ */
+
+ /* Enabling Laser. */
+ val64 = readq(&bar0->adapter_control);
+ val64 |= ADAPTER_EOI_TX_ON;
+ writeq(val64, &bar0->adapter_control);
+
+ /* SXE-002: Initialize link and activity LED */
+ subid = nic->pdev->subsystem_device;
+ if ((subid & 0xFF) >= 0x07) {
+ val64 = readq(&bar0->gpio_control);
+ val64 |= 0x0000800000000000ULL;
+ writeq(val64, &bar0->gpio_control);
+ val64 = 0x0411040400000000ULL;
+ writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
+ }
+
+ /*
+ * Here we are performing soft reset on XGXS to
+ * force link down. Since link is already up, we will get
+ * link state change interrupt after this reset
+ */
+ writeq(0x8007051500000000ULL, &bar0->dtx_control);
+ val64 = readq(&bar0->dtx_control);
+ writeq(0x80070515000000E0ULL, &bar0->dtx_control);
+ val64 = readq(&bar0->dtx_control);
+ writeq(0x80070515001F00E4ULL, &bar0->dtx_control);
+ val64 = readq(&bar0->dtx_control);
+
+ return SUCCESS;
+}
+
+/*
+ * Input Arguments:
+ * nic - device private variable.
+ * Return Value:
+ * void.
+ * Description:
+ * Free all queued Tx buffers.
+ */
+void freeTxBuffers(struct s2io_nic *nic)
+{
+ struct net_device *dev = nic->dev;
+ struct sk_buff *skb;
+ TxD_t *txdp;
+ int i, j;
+#if DEBUG_ON
+ int cnt = 0;
+#endif
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ for (i = 0; i < config->TxFIFONum; i++) {
+ for (j = 0; j < config->TxCfg[i].FifoLen - 1; j++) {
+ txdp = mac_control->txdl_start[i] +
+ (config->MaxTxDs * j);
+
+ if (!(txdp->Control_1 & TXD_LIST_OWN_XENA)) {
+ /* If owned by host, ignore */
+ continue;
+ }
+ skb =
+ (struct sk_buff *) ((unsigned long) txdp->
+ Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: NULL skb ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "in Tx Int\n");
+ return;
+ }
+#if DEBUG_ON
+ cnt++;
+#endif
+ dev_kfree_skb(skb);
+ memset(txdp, 0, sizeof(TxD_t));
+ }
+#if DEBUG_ON
+ DBG_PRINT(INTR_DBG,
+ "%s:forcibly freeing %d skbs on FIFO%d\n",
+ dev->name, cnt, i);
+#endif
+ }
+}
+
+/*
+ * Input Arguments:
+ * nic - device private variable.
+ * Return Value:
+ * void.
+ * Description:
+ * This function does exactly the opposite of what the startNic()
+ * function does. This function is called to stop
+ * the device.
+ */
+static void stopNic(struct s2io_nic *nic)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ register u64 val64 = 0;
+ u16 interruptible, i;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+/* Disable all interrupts */
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
+ RX_MAC_INTR;
+ en_dis_able_NicIntrs(nic, interruptible, DISABLE_INTRS);
+
+/* Disable PRCs */
+ for (i = 0; i < config->RxRingNum; i++) {
+ val64 = readq(&bar0->prc_ctrl_n[i]);
+ val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
+ writeq(val64, &bar0->prc_ctrl_n[i]);
+ }
+}
+
+/*
+ * Input Arguments:
+ * device private variable
+ * Return Value:
+ * SUCCESS on success or an appropriate -ve value on failure.
+ * Description:
+ * The function allocates Rx side skbs and puts the physical
+ * address of these buffers into the RxD buffer pointers, so that the NIC
+ * can DMA the received frame into these locations.
+ * The NIC supports 3 receive modes, viz
+ * 1. single buffer,
+ * 2. three buffer and
+ * 3. Five buffer modes.
+ * Each mode defines how many fragments the received frame will be split
+ * up into by the NIC. The frame is split into L3 header, L4 Header,
+ * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
+ * is split into 3 fragments. As of now only single buffer mode is supported.
+ */
+int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
+{
+ struct net_device *dev = nic->dev;
+ struct sk_buff *skb;
+ RxD_t *rxdp;
+ int off, off1, size, block_no, block_no1;
+ int offset, offset1;
+ u32 alloc_tab = 0;
+ u32 alloc_cnt = nic->pkt_cnt[ring_no] -
+ atomic_read(&nic->rx_bufs_left[ring_no]);
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ if (frame_len[ring_no]) {
+ if (frame_len[ring_no] > dev->mtu)
+ dev->mtu = frame_len[ring_no];
+ size = frame_len[ring_no] + HEADER_ETHERNET_II_802_3_SIZE +
+ HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
+ } else {
+ size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
+ HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
+ }
+
+ while (alloc_tab < alloc_cnt) {
+ block_no = mac_control->rx_curr_put_info[ring_no].
+ block_index;
+ block_no1 = mac_control->rx_curr_get_info[ring_no].
+ block_index;
+ off = mac_control->rx_curr_put_info[ring_no].offset;
+ off1 = mac_control->rx_curr_get_info[ring_no].offset;
+ offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
+ offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
+
+ rxdp = nic->rx_blocks[ring_no][block_no].
+ block_virt_addr + off;
+ if ((offset == offset1) && (rxdp->Host_Control)) {
+ DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
+ DBG_PRINT(INTR_DBG, " info equated\n");
+ goto end;
+ }
+
+ if (rxdp->Control_1 == END_OF_BLOCK) {
+ mac_control->rx_curr_put_info[ring_no].
+ block_index++;
+ mac_control->rx_curr_put_info[ring_no].
+ block_index %= nic->block_count[ring_no];
+ block_no = mac_control->rx_curr_put_info
+ [ring_no].block_index;
+ off++;
+ off %= (MAX_RXDS_PER_BLOCK + 1);
+ mac_control->rx_curr_put_info[ring_no].offset =
+ off;
+ /*rxdp = nic->rx_blocks[ring_no][block_no].
+ block_virt_addr + off; */
+ rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
+ DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
+ dev->name, rxdp);
+ }
+
+ if (rxdp->Control_1 & RXD_OWN_XENA) {
+ mac_control->rx_curr_put_info[ring_no].
+ offset = off;
+ goto end;
+ }
+
+ skb = dev_alloc_skb(size + HEADER_ALIGN_LAYER_3);
+ if (!skb) {
+ DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
+ DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
+ return -ENOMEM;
+ }
+ skb_reserve(skb, HEADER_ALIGN_LAYER_3);
+ memset(rxdp, 0, sizeof(RxD_t));
+ rxdp->Buffer0_ptr = pci_map_single
+ (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
+ rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
+ rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
+ rxdp->Host_Control = (unsigned long) (skb);
+ rxdp->Control_1 |= RXD_OWN_XENA;
+ off++;
+ off %= (MAX_RXDS_PER_BLOCK + 1);
+ mac_control->rx_curr_put_info[ring_no].offset = off;
+ atomic_inc(&nic->rx_bufs_left[ring_no]);
+ alloc_tab++;
+ }
+
+ end:
+ return SUCCESS;
+}
+
+/*
+ * Input Arguments:
+ * device private variable.
+ * Return Value:
+ * NONE.
+ * Description:
+ * This function will free all Rx buffers allocated by host.
+ */
+static void freeRxBuffers(struct s2io_nic *sp)
+{
+ struct net_device *dev = sp->dev;
+ int i, j, blk = 0, off, buf_cnt = 0;
+ RxD_t *rxdp;
+ struct sk_buff *skb;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ for (j = 0, blk = 0; j < config->RxCfg[i].NumRxd; j++) {
+ off = j % (MAX_RXDS_PER_BLOCK + 1);
+ rxdp = sp->rx_blocks[i][blk].block_virt_addr + off;
+
+ if (rxdp->Control_1 == END_OF_BLOCK) {
+ rxdp =
+ (RxD_t *) ((unsigned long) rxdp->
+ Control_2);
+ j++;
+ blk++;
+ }
+
+ skb =
+ (struct sk_buff *) ((unsigned long) rxdp->
+ Host_Control);
+ if (skb) {
+ pci_unmap_single(sp->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ dev->mtu +
+ HEADER_ETHERNET_II_802_3_SIZE
+ + HEADER_802_2_SIZE +
+ HEADER_SNAP_SIZE,
+ PCI_DMA_FROMDEVICE);
+ dev_kfree_skb(skb);
+ atomic_dec(&sp->rx_bufs_left[i]);
+ buf_cnt++;
+ }
+ memset(rxdp, 0, sizeof(RxD_t));
+ }
+ mac_control->rx_curr_put_info[i].block_index = 0;
+ mac_control->rx_curr_get_info[i].block_index = 0;
+ mac_control->rx_curr_put_info[i].offset = 0;
+ mac_control->rx_curr_get_info[i].offset = 0;
+ atomic_set(&sp->rx_bufs_left[i], 0);
+ DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
+ dev->name, buf_cnt, i);
+ }
+}
+
+/*
+ * Input Argument:
+ * dev - pointer to the device structure.
+ * budget - The number of packets that were budgeted to be processed during
+ * one pass through the 'Poll" function.
+ * Return value:
+ * 0 on success and 1 if there are No Rx packets to be processed.
+ * Description:
+ * Comes into picture only if NAPI support has been incorporated. It does
+ * the same thing that rxIntrHandler does, but not in a interrupt context
+ * also It will process only a given number of packets.
+ */
+#ifdef CONFIG_S2IO_NAPI
+static int s2io_poll(struct net_device *dev, int *budget)
+{
+ nic_t *nic = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ int pkts_to_process = *budget, pkt_cnt = 0;
+ register u64 val64 = 0;
+ rx_curr_get_info_t offset_info;
+ int i, block_no;
+ u16 val16, cksum;
+ struct sk_buff *skb;
+ RxD_t *rxdp;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ if (pkts_to_process > dev->quota)
+ pkts_to_process = dev->quota;
+
+ val64 = readq(&bar0->rx_traffic_int);
+ writeq(val64, &bar0->rx_traffic_int);
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ if (--pkts_to_process < 0) {
+ goto no_rx;
+ }
+ offset_info = mac_control->rx_curr_get_info[i];
+ block_no = offset_info.block_index;
+ rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
+ offset_info.offset;
+ while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
+ if (rxdp->Control_1 == END_OF_BLOCK) {
+ rxdp =
+ (RxD_t *) ((unsigned long) rxdp->
+ Control_2);
+ offset_info.offset++;
+ offset_info.offset %=
+ (MAX_RXDS_PER_BLOCK + 1);
+ block_no++;
+ block_no %= nic->block_count[i];
+ mac_control->rx_curr_get_info[i].
+ offset = offset_info.offset;
+ mac_control->rx_curr_get_info[i].
+ block_index = block_no;
+ continue;
+ }
+ skb =
+ (struct sk_buff *) ((unsigned long) rxdp->
+ Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: The skb is ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
+ return 0;
+ }
+ val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
+ val16 = (u16) (val64 >> 48);
+ cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ dev->mtu +
+ HEADER_ETHERNET_II_802_3_SIZE +
+ HEADER_802_2_SIZE +
+ HEADER_SNAP_SIZE,
+ PCI_DMA_FROMDEVICE);
+ rxOsmHandler(nic, val16, rxdp, i);
+ pkt_cnt++;
+ offset_info.offset++;
+ offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
+ rxdp =
+ nic->rx_blocks[i][block_no].block_virt_addr +
+ offset_info.offset;
+ mac_control->rx_curr_get_info[i].offset =
+ offset_info.offset;
+ }
+ }
+ if (!pkt_cnt)
+ pkt_cnt = 1;
+
+ for (i = 0; i < config->RxRingNum; i++)
+ fill_rx_buffers(nic, i);
+
+ dev->quota -= pkt_cnt;
+ *budget -= pkt_cnt;
+ netif_rx_complete(dev);
+
+/* Re enable the Rx interrupts. */
+ en_dis_able_NicIntrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
+ return 0;
+
+ no_rx:
+ for (i = 0; i < config->RxRingNum; i++)
+ fill_rx_buffers(nic, i);
+ dev->quota -= pkt_cnt;
+ *budget -= pkt_cnt;
+ return 1;
+}
+#else
+/*
+ * Input Arguments:
+ * device private variable.
+ * Return Value:
+ * NONE.
+ * Description:
+ * If the interrupt is because of a received frame or if the
+ * receive ring contains fresh as yet un-processed frames, this function is
+ * called. It picks out the RxD at which place the last Rx processing had
+ * stopped and sends the skb to the OSM's Rx handler and then increments
+ * the offset.
+ */
+static void rxIntrHandler(struct s2io_nic *nic)
+{
+ struct net_device *dev = (struct net_device *) nic->dev;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ rx_curr_get_info_t offset_info;
+ RxD_t *rxdp;
+ struct sk_buff *skb;
+ u16 val16, cksum;
+ register u64 val64 = 0;
+ int i, block_no;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+#if DEBUG_ON
+ nic->rxint_cnt++;
+#endif
+
+/* rx_traffic_int reg is an R1 register, hence we read and write back
+ * the samevalue in the register to clear it.
+ */
+ val64 = readq(&bar0->rx_traffic_int);
+ writeq(val64, &bar0->rx_traffic_int);
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ offset_info = mac_control->rx_curr_get_info[i];
+ block_no = offset_info.block_index;
+ rxdp = nic->rx_blocks[i][block_no].block_virt_addr +
+ offset_info.offset;
+ while (!(rxdp->Control_1 & RXD_OWN_XENA)) {
+ if (rxdp->Control_1 == END_OF_BLOCK) {
+ rxdp = (RxD_t *) ((unsigned long)
+ rxdp->Control_2);
+ offset_info.offset++;
+ offset_info.offset %=
+ (MAX_RXDS_PER_BLOCK + 1);
+ block_no++;
+ block_no %= nic->block_count[i];
+ mac_control->rx_curr_get_info[i].
+ offset = offset_info.offset;
+ mac_control->rx_curr_get_info[i].
+ block_index = block_no;
+ continue;
+ }
+ skb = (struct sk_buff *) ((unsigned long)
+ rxdp->Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: The skb is ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
+ return;
+ }
+ val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
+ val16 = (u16) (val64 >> 48);
+ cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ rxdp->Buffer0_ptr,
+ dev->mtu +
+ HEADER_ETHERNET_II_802_3_SIZE +
+ HEADER_802_2_SIZE +
+ HEADER_SNAP_SIZE,
+ PCI_DMA_FROMDEVICE);
+ rxOsmHandler(nic, val16, rxdp, i);
+ offset_info.offset++;
+ offset_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
+ rxdp =
+ nic->rx_blocks[i][block_no].block_virt_addr +
+ offset_info.offset;
+ mac_control->rx_curr_get_info[i].offset =
+ offset_info.offset;
+ }
+ }
+}
+#endif
+
+/*
+ * Input Arguments:
+ * device private variable
+ * Return Value:
+ * NONE
+ * Description:
+ * If an interrupt was raised to indicate DMA complete of the
+ * Tx packet, this function is called. It identifies the last TxD whose buffer
+ * was freed and frees all skbs whose data have already DMA'ed into the NICs
+ * internal memory.
+ */
+static void txIntrHandler(struct s2io_nic *nic)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ struct net_device *dev = (struct net_device *) nic->dev;
+ tx_curr_get_info_t offset_info, offset_info1;
+ struct sk_buff *skb;
+ TxD_t *txdlp;
+ register u64 val64 = 0;
+ int i;
+ u16 j, frg_cnt;
+ mac_info_t *mac_control;
+ struct config_param *config;
+#if DEBUG_ON
+ int cnt = 0;
+ nic->txint_cnt++;
+#endif
+
+ mac_control = &nic->mac_control;
+ config = &nic->config;
+
+ /* tx_traffic_int reg is an R1 register, hence we read and write
+ * back the samevalue in the register to clear it.
+ */
+ val64 = readq(&bar0->tx_traffic_int);
+ writeq(val64, &bar0->tx_traffic_int);
+
+ for (i = 0; i < config->TxFIFONum; i++) {
+ offset_info = mac_control->tx_curr_get_info[i];
+ offset_info1 = mac_control->tx_curr_put_info[i];
+ txdlp = mac_control->txdl_start[i] +
+ (config->MaxTxDs * offset_info.offset);
+ while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
+ (offset_info.offset != offset_info1.offset) &&
+ (txdlp->Host_Control)) {
+ /* Check for TxD errors */
+ if (txdlp->Control_1 & TXD_T_CODE) {
+ unsigned long long err;
+ err = txdlp->Control_1 & TXD_T_CODE;
+ DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
+ err);
+ }
+
+ skb = (struct sk_buff *) ((unsigned long)
+ txdlp->Host_Control);
+ if (skb == NULL) {
+ DBG_PRINT(ERR_DBG, "%s: Null skb ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
+ return;
+ }
+ nic->tx_pkt_count++;
+
+ frg_cnt = skb_shinfo(skb)->nr_frags;
+
+ /* For unfragmented skb */
+ pci_unmap_single(nic->pdev, (dma_addr_t)
+ txdlp->Buffer_Pointer,
+ skb->len - skb->data_len,
+ PCI_DMA_TODEVICE);
+ if (frg_cnt) {
+ TxD_t *temp = txdlp;
+ txdlp++;
+ for (j = 0; j < frg_cnt; j++, txdlp++) {
+ skb_frag_t *frag =
+ &skb_shinfo(skb)->frags[j];
+ pci_unmap_page(nic->pdev,
+ (dma_addr_t)
+ txdlp->
+ Buffer_Pointer,
+ frag->size,
+ PCI_DMA_TODEVICE);
+ }
+ txdlp = temp;
+ }
+ memset(txdlp, 0,
+ (sizeof(TxD_t) * config->MaxTxDs));
+
+ /* Updating the statistics block */
+ nic->stats.tx_packets++;
+ nic->stats.tx_bytes += skb->len;
+#if DEBUG_ON
+ nic->txpkt_bytes += skb->len;
+ cnt++;
+#endif
+ dev_kfree_skb_irq(skb);
+
+ offset_info.offset++;
+ offset_info.offset %= offset_info.fifo_len + 1;
+ txdlp = mac_control->txdl_start[i] +
+ (config->MaxTxDs * offset_info.offset);
+ mac_control->tx_curr_get_info[i].offset =
+ offset_info.offset;
+ }
+#if DEBUG_ON
+ DBG_PRINT(INTR_DBG, "%s: freed %d Tx Pkts\n", dev->name,
+ cnt);
+#endif
+ }
+
+ spin_lock(&nic->tx_lock);
+ if (netif_queue_stopped(dev))
+ netif_wake_queue(dev);
+ spin_unlock(&nic->tx_lock);
+}
+
+/*
+ * Input Arguments:
+ * device private variable
+ * Return Value:
+ * NONE
+ * Description:
+ * If the interrupt was neither because of Rx packet or Tx
+ * complete, this function is called. If the interrupt was to indicate a loss
+ * of link, the OSM link status handler is invoked for any other alarm
+ * interrupt the block that raised the interrupt is displayed and a H/W reset
+ * is issued.
+ */
+static void alarmIntrHandler(struct s2io_nic *nic)
+{
+ struct net_device *dev = (struct net_device *) nic->dev;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ register u64 val64 = 0, err_reg = 0;
+
+
+ /* Handling link status change error Intr */
+ err_reg = readq(&bar0->mac_rmac_err_reg);
+ if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
+ schedule_work(&nic->set_link_task);
+ }
+
+ /* Handling SERR errors by stopping device Xmit queue and forcing
+ * a H/W reset.
+ */
+ val64 = readq(&bar0->serr_source);
+ if (val64 & SERR_SOURCE_ANY) {
+ DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
+ DBG_PRINT(ERR_DBG, "serious error!!\n");
+ netif_stop_queue(dev);
+ }
+/* Other type of interrupts are not being handled now, TODO*/
+}
+
+/*
+ * Input Argument:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * Return value:
+ * SUCCESS on success and FAILURE on failure.
+ * Description:
+ * Function that waits for a command to Write into RMAC ADDR DATA registers
+ * to be completed and returns either success or error depending on whether
+ * the command was complete or not.
+ */
+int waitForCmdComplete(nic_t * sp)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ int ret = FAILURE, cnt = 0;
+ u64 val64;
+
+ while (TRUE) {
+ val64 =
+ RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
+ | RMAC_ADDR_CMD_MEM_OFFSET(0);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+ val64 = readq(&bar0->rmac_addr_cmd_mem);
+ if (!val64) {
+ ret = SUCCESS;
+ break;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ if (cnt++ > 10)
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Input Argument:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * Return value:
+ * void.
+ * Description:
+ * Function to Reset the card. This function then also restores the previously
+ * saved PCI configuration space registers as the card reset also resets the
+ * Configration space.
+ */
+void s2io_reset(nic_t * sp)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+ u16 subid;
+
+ val64 = SW_RESET_ALL;
+ writeq(val64, &bar0->sw_reset);
+
+ /* At this stage, if the PCI write is indeed completed, the
+ * card is reset and so is the PCI Config space of the device.
+ * So a read cannot be issued at this stage on any of the
+ * registers to ensure the write into "sw_reset" register
+ * has gone through.
+ * Question: Is there any system call that will explicitly force
+ * all the write commands still pending on the bus to be pushed
+ * through?
+ * As of now I'am just giving a 250ms delay and hoping that the
+ * PCI write to sw_reset register is done by this time.
+ */
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 4);
+
+ /* Restore the PCI state saved during initializarion. */
+ pci_restore_state(sp->pdev, sp->config_space);
+ s2io_init_pci(sp);
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 4);
+
+ /* SXE-002: Configure link and activity LED to turn it off */
+ subid = sp->pdev->subsystem_device;
+ if ((subid & 0xFF) >= 0x07) {
+ val64 = readq(&bar0->gpio_control);
+ val64 |= 0x0000800000000000ULL;
+ writeq(val64, &bar0->gpio_control);
+ val64 = 0x0411040400000000ULL;
+ writeq(val64, (void *) ((u8 *) bar0 + 0x2700));
+ }
+
+ sp->device_enabled_once = FALSE;
+}
+
+/*
+ * Input Argument:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * Return value:
+ * SUCCESS on success and FAILURE on failure.
+ * Description:
+ * Function to set the swapper control on the card correctly depending on the
+ * 'endianness' of the system.
+ */
+int s2io_set_swapper(nic_t * sp)
+{
+ struct net_device *dev = sp->dev;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+
+/* Set proper endian settings and verify the same by reading the PIF
+ * Feed-back register.
+ */
+#ifdef __BIG_ENDIAN
+/* The device by default set to a big endian format, so a big endian
+ * driver need not set anything.
+ */
+ writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
+ val64 = (SWAPPER_CTRL_PIF_R_FE |
+ SWAPPER_CTRL_PIF_R_SE |
+ SWAPPER_CTRL_PIF_W_FE |
+ SWAPPER_CTRL_PIF_W_SE |
+ SWAPPER_CTRL_TXP_FE |
+ SWAPPER_CTRL_TXP_SE |
+ SWAPPER_CTRL_TXD_R_FE |
+ SWAPPER_CTRL_TXD_W_FE |
+ SWAPPER_CTRL_TXF_R_FE |
+ SWAPPER_CTRL_RXD_R_FE |
+ SWAPPER_CTRL_RXD_W_FE |
+ SWAPPER_CTRL_RXF_W_FE |
+ SWAPPER_CTRL_XMSI_FE |
+ SWAPPER_CTRL_XMSI_SE |
+ SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
+ writeq(val64, &bar0->swapper_ctrl);
+#else
+/* Initially we enable all bits to make it accessible by the driver,
+ * then we selectively enable only those bits that we want to set.
+ */
+ writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
+ val64 = (SWAPPER_CTRL_PIF_R_FE |
+ SWAPPER_CTRL_PIF_R_SE |
+ SWAPPER_CTRL_PIF_W_FE |
+ SWAPPER_CTRL_PIF_W_SE |
+ SWAPPER_CTRL_TXP_FE |
+ SWAPPER_CTRL_TXP_SE |
+ SWAPPER_CTRL_TXD_R_FE |
+ SWAPPER_CTRL_TXD_R_SE |
+ SWAPPER_CTRL_TXD_W_FE |
+ SWAPPER_CTRL_TXD_W_SE |
+ SWAPPER_CTRL_TXF_R_FE |
+ SWAPPER_CTRL_RXD_R_FE |
+ SWAPPER_CTRL_RXD_R_SE |
+ SWAPPER_CTRL_RXD_W_FE |
+ SWAPPER_CTRL_RXD_W_SE |
+ SWAPPER_CTRL_RXF_W_FE |
+ SWAPPER_CTRL_XMSI_FE |
+ SWAPPER_CTRL_XMSI_SE |
+ SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
+ writeq(val64, &bar0->swapper_ctrl);
+#endif
+
+/* Verifying if endian settings are accurate by reading a feedback
+ * register.
+ */
+ val64 = readq(&bar0->pif_rd_swapper_fb);
+ if (val64 != 0x0123456789ABCDEFULL) {
+ /* Endian settings are incorrect, calls for another dekko. */
+ DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "feedback read %llx\n",
+ (unsigned long long) val64);
+ return FAILURE;
+ }
+
+ return SUCCESS;
+}
+
+/* ********************************************************* *
+ * Functions defined below concern the OS part of the driver *
+ * ********************************************************* */
+
+/*
+ * Input Argument:
+ * dev - pointer to the device structure.
+ * Return value:
+ * '0' on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ * Description:
+ * This function is the open entry point of the driver. It mainly calls a
+ * function to allocate Rx buffers and inserts them into the buffer
+ * descriptors and then enables the Rx part of the NIC.
+ */
+int s2io_open(struct net_device *dev)
+{
+ nic_t *sp = dev->priv;
+ int i, ret = 0, err = 0;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+
+/* Make sure you have link off by default every time Nic is initialized*/
+ netif_carrier_off(dev);
+ sp->last_link_state = LINK_DOWN;
+
+/* Initialize the H/W I/O registers */
+ if (initNic(sp) != 0) {
+ DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
+ dev->name);
+ return -ENODEV;
+ }
+
+/* After proper initialization of H/W, register ISR */
+ err =
+ request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, sp->name, dev);
+ if (err) {
+ s2io_reset(sp);
+ DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
+ dev->name);
+ return err;
+ }
+ if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
+ DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
+ s2io_reset(sp);
+ return -ENODEV;
+ }
+
+
+/* Setting its receive mode */
+ s2io_set_multicast(dev);
+
+/* Initializing the Rx buffers. For now we are considering only 1 Rx ring
+ * and initializing buffers into 1016 RxDs or 8 Rx blocks
+ */
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ if ((ret = fill_rx_buffers(sp, i))) {
+ DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
+ dev->name);
+ s2io_reset(sp);
+ free_irq(dev->irq, dev);
+ freeRxBuffers(sp);
+ return -ENOMEM;
+ }
+ DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
+ atomic_read(&sp->rx_bufs_left[i]));
+ }
+
+/* Enable tasklet for the device */
+ tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
+
+/* Enable Rx Traffic and interrupts on the NIC */
+ if (startNic(sp)) {
+ DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
+ tasklet_kill(&sp->task);
+ s2io_reset(sp);
+ free_irq(dev->irq, dev);
+ freeRxBuffers(sp);
+ return -ENODEV;
+ }
+
+ sp->device_close_flag = FALSE; /* Device is up and running. */
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * dev - device pointer.
+ * Return value:
+ * '0' on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ * Description:
+ * This is the stop entry point of the driver. It needs to undo exactly
+ * whatever was done by the open entry point, thus it's usually referred to
+ * as the close function. Among other things this function mainly stops the
+ * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
+ */
+int s2io_close(struct net_device *dev)
+{
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ register u64 val64 = 0;
+ u16 cnt = 0;
+
+ spin_lock(&sp->isr_lock);
+ netif_stop_queue(dev);
+
+/* disable Tx and Rx traffic on the NIC */
+ stopNic(sp);
+
+ spin_unlock(&sp->isr_lock);
+
+/* If the device tasklet is running, wait till its done before killing it */
+ while (atomic_read(&(sp->tasklet_status))) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 10);
+ }
+ tasklet_kill(&sp->task);
+
+/* Check if the device is Quiescent and then Reset the NIC */
+ do {
+ val64 = readq(&bar0->adapter_status);
+ if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
+ break;
+ }
+
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ cnt++;
+ if (cnt == 10) {
+ DBG_PRINT(ERR_DBG,
+ "s2io_close:Device not Quiescent ");
+ DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
+ (unsigned long long) val64);
+ break;
+ }
+ } while (1);
+ s2io_reset(sp);
+
+/* Free the Registered IRQ */
+ free_irq(dev->irq, dev);
+
+/* Free all Tx Buffers waiting for transmission */
+ freeTxBuffers(sp);
+
+/* Free all Rx buffers allocated by host */
+ freeRxBuffers(sp);
+
+ sp->device_close_flag = TRUE; /* Device is shut down. */
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * skb - the socket buffer containing the Tx data.
+ * dev - device pointer.
+ * Return value:
+ * '0' on success & 1 on failure.
+ * NOTE: when device cant queue the pkt, just the trans_start variable will
+ * not be upadted.
+ * Description:
+ * This function is the Tx entry point of the driver. S2IO NIC supports
+ * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
+ */
+int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ nic_t *sp = dev->priv;
+ u16 off, txd_len, frg_cnt, frg_len, i, queue, off1, queue_len;
+ register u64 val64;
+ TxD_t *txdp;
+ TxFIFO_element_t *tx_fifo;
+ unsigned long flags;
+#ifdef NETIF_F_TSO
+ int mss;
+#endif
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name);
+
+ spin_lock_irqsave(&sp->tx_lock, flags);
+ queue = 0;
+ /* Multi FIFO Tx is disabled for now. */
+ if (!queue && tx_prio) {
+ u8 x = (skb->data)[5];
+ queue = x % config->TxFIFONum;
+ }
+
+
+ off = (u16) mac_control->tx_curr_put_info[queue].offset;
+ off1 = (u16) mac_control->tx_curr_get_info[queue].offset;
+ txd_len = mac_control->txdl_len;
+ txdp = mac_control->txdl_start[queue] + (config->MaxTxDs * off);
+
+ queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1;
+ /* Avoid "put" pointer going beyond "get" pointer */
+ if (txdp->Host_Control || (((off + 1) % queue_len) == off1)) {
+ DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
+ netif_stop_queue(dev);
+ dev_kfree_skb(skb);
+ spin_unlock_irqrestore(&sp->tx_lock, flags);
+ return 0;
+ }
+
+#ifdef NETIF_F_TSO
+ mss = skb_shinfo(skb)->tso_size;
+ if (mss) {
+ txdp->Control_1 |= TXD_TCP_LSO_EN;
+ txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
+ }
+#endif
+
+ frg_cnt = skb_shinfo(skb)->nr_frags;
+ frg_len = skb->len - skb->data_len;
+
+ txdp->Host_Control = (unsigned long) skb;
+ txdp->Buffer_Pointer = pci_map_single
+ (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
+ if (skb->ip_summed == CHECKSUM_HW) {
+ txdp->Control_2 |=
+ (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
+ TXD_TX_CKO_UDP_EN);
+ }
+
+ txdp->Control_2 |= config->TxIntrType;
+
+ txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
+ TXD_GATHER_CODE_FIRST);
+ txdp->Control_1 |= TXD_LIST_OWN_XENA;
+
+ /* For fragmented SKB. */
+ for (i = 0; i < frg_cnt; i++) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+ txdp++;
+ txdp->Buffer_Pointer = (u64) pci_map_page
+ (sp->pdev, frag->page, frag->page_offset,
+ frag->size, PCI_DMA_TODEVICE);
+ txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
+ }
+ txdp->Control_1 |= TXD_GATHER_CODE_LAST;
+
+ tx_fifo = mac_control->tx_FIFO_start[queue];
+ val64 = (mac_control->txdl_start_phy[queue] +
+ (sizeof(TxD_t) * txd_len * off));
+ writeq(val64, &tx_fifo->TxDL_Pointer);
+
+ val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
+ TX_FIFO_LAST_LIST);
+#ifdef NETIF_F_TSO
+ if (mss)
+ val64 |= TX_FIFO_SPECIAL_FUNC;
+#endif
+ writeq(val64, &tx_fifo->List_Control);
+
+ off++;
+ off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
+ mac_control->tx_curr_put_info[queue].offset = off;
+
+ /* Avoid "put" pointer going beyond "get" pointer */
+ if (((off + 1) % queue_len) == off1) {
+ DBG_PRINT(TX_DBG,
+ "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
+ off, off1);
+ netif_stop_queue(dev);
+ }
+
+ dev->trans_start = jiffies;
+ spin_unlock_irqrestore(&sp->tx_lock, flags);
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * irq: the irq of the device.
+ * dev_id: a void pointer to the dev structure of the NIC.
+ * ptregs: pointer to the registers pushed on the stack.
+ * Return value:
+ * void.
+ * Description:
+ * This function is the ISR handler of the device. It identifies the reason
+ * for the interrupt and calls the relevant service routines.
+ * As a contongency measure, this ISR allocates the recv buffers, if their
+ * numbers are below the panic value which is presently set to 25% of the
+ * original number of rcv buffers allocated.
+ */
+
+static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct net_device *dev = (struct net_device *) dev_id;
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+#ifndef CONFIG_S2IO_NAPI
+ int i, ret;
+#endif
+ u64 reason = 0, general_mask = 0;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ spin_lock(&sp->isr_lock);
+
+ /* Identify the cause for interrupt and call the appropriate
+ * interrupt handler. Causes for the interrupt could be;
+ * 1. Rx of packet.
+ * 2. Tx complete.
+ * 3. Link down.
+ * 4. Error in any functional blocks of the NIC.
+ */
+ reason = readq(&bar0->general_int_status);
+
+ if (!reason) {
+ /* The interrupt was not raised by Xena. */
+ spin_unlock(&sp->isr_lock);
+ return IRQ_NONE;
+ }
+ /* Mask the interrupts on the NIC */
+ general_mask = readq(&bar0->general_int_mask);
+ writeq(0xFFFFFFFFFFFFFFFFULL, &bar0->general_int_mask);
+
+#if DEBUG_ON
+ sp->int_cnt++;
+#endif
+
+ /* If Intr is because of Tx Traffic */
+ if (reason & GEN_INTR_TXTRAFFIC) {
+ txIntrHandler(sp);
+ }
+
+ /* If Intr is because of an error */
+ if (reason & (GEN_ERROR_INTR))
+ alarmIntrHandler(sp);
+
+#ifdef CONFIG_S2IO_NAPI
+ if (reason & GEN_INTR_RXTRAFFIC) {
+ if (netif_rx_schedule_prep(dev)) {
+ en_dis_able_NicIntrs(sp, RX_TRAFFIC_INTR,
+ DISABLE_INTRS);
+ /* We retake the snap shot of the general interrupt
+ * register.
+ */
+ general_mask = readq(&bar0->general_int_mask);
+ __netif_rx_schedule(dev);
+ }
+ }
+#else
+ /* If Intr is because of Rx Traffic */
+ if (reason & GEN_INTR_RXTRAFFIC) {
+ rxIntrHandler(sp);
+ }
+#endif
+
+/* If the Rx buffer count is below the panic threshold then reallocate the
+ * buffers from the interrupt handler itself, else schedule a tasklet to
+ * reallocate the buffers.
+ */
+#if 1
+ {
+ int i;
+
+ for (i = 0; i < config->RxRingNum; i++) {
+ int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
+ int level = rx_buffer_level(sp, rxb_size, i);
+
+ if ((level == PANIC) && (!TASKLET_IN_USE)) {
+ int ret;
+
+ DBG_PRINT(ERR_DBG, "%s: Rx BD hit ", dev->name);
+ DBG_PRINT(ERR_DBG, "PANIC levels\n");
+ if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
+ DBG_PRINT(ERR_DBG, "%s:Out of memory",
+ dev->name);
+ DBG_PRINT(ERR_DBG, " in ISR!!\n");
+ writeq(general_mask,
+ &bar0->general_int_mask);
+ spin_unlock(&sp->isr_lock);
+ return IRQ_HANDLED;
+ }
+ clear_bit(0,
+ (unsigned long *) (&sp->tasklet_status));
+ } else if ((level == LOW)
+ && (!atomic_read(&sp->tasklet_status))) {
+ tasklet_schedule(&sp->task);
+ }
+
+ }
+
+ }
+#else
+ tasklet_schedule(&sp->task);
+#endif
+
+ /* Unmask all the previously enabled interrupts on the NIC */
+ writeq(general_mask, &bar0->general_int_mask);
+
+ spin_unlock(&sp->isr_lock);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Input Argument/s:
+ * dev - pointer to the device structure.
+ * Return value:
+ * pointer to the updated net_device_stats structure.
+ * Description:
+ * This function updates the device statistics structure in the s2io_nic
+ * structure and returns a pointer to the same.
+ */
+struct net_device_stats *s2io_get_stats(struct net_device *dev)
+{
+ nic_t *sp = dev->priv;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ sp->stats.tx_errors = mac_control->StatsInfo->tmac_any_err_frms;
+ sp->stats.rx_errors = mac_control->StatsInfo->rmac_drop_frms;
+ sp->stats.multicast = mac_control->StatsInfo->rmac_vld_mcst_frms;
+ sp->stats.rx_length_errors =
+ mac_control->StatsInfo->rmac_long_frms;
+
+ return (&sp->stats);
+}
+
+/*
+ * Input Argument/s:
+ * dev - pointer to the device structure
+ * Return value:
+ * void.
+ * Description:
+ * This function is a driver entry point which gets called by the kernel
+ * whenever multicast addresses must be enabled/disabled. This also gets
+ * called to set/reset promiscuous mode. Depending on the deivce flag, we
+ * determine, if multicast address must be enabled or if promiscuous mode
+ * is to be disabled etc.
+ */
+static void s2io_set_multicast(struct net_device *dev)
+{
+ int i, j, prev_cnt;
+ struct dev_mc_list *mclist;
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
+ 0xfeffffffffffULL;
+ u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
+ void *add;
+
+ if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
+ /* Enable all Multicast addresses */
+ writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
+ &bar0->rmac_addr_data0_mem);
+ writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
+ &bar0->rmac_addr_data1_mem);
+ val64 = RMAC_ADDR_CMD_MEM_WE |
+ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+ /* Wait till command completes */
+ waitForCmdComplete(sp);
+
+ sp->m_cast_flg = 1;
+ sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
+ } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
+ /* Disable all Multicast addresses */
+ writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
+ &bar0->rmac_addr_data0_mem);
+ val64 = RMAC_ADDR_CMD_MEM_WE |
+ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+ /* Wait till command completes */
+ waitForCmdComplete(sp);
+
+ sp->m_cast_flg = 0;
+ sp->all_multi_pos = 0;
+ }
+
+ if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
+ /* Put the NIC into promiscuous mode */
+ add = (void *) &bar0->mac_cfg;
+ val64 = readq(&bar0->mac_cfg);
+ val64 |= MAC_CFG_RMAC_PROM_ENABLE;
+
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) val64, add);
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) (val64 >> 32), (add + 4));
+
+ val64 = readq(&bar0->mac_cfg);
+ sp->promisc_flg = 1;
+ DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n",
+ dev->name);
+ } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
+ /* Remove the NIC from promiscuous mode */
+ add = (void *) &bar0->mac_cfg;
+ val64 = readq(&bar0->mac_cfg);
+ val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
+
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) val64, add);
+ writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
+ writel((u32) (val64 >> 32), (add + 4));
+
+ val64 = readq(&bar0->mac_cfg);
+ sp->promisc_flg = 0;
+ DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n",
+ dev->name);
+ }
+
+ /* Update individual M_CAST address list */
+ if ((!sp->m_cast_flg) && dev->mc_count) {
+ if (dev->mc_count >
+ (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
+ DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "can be added, please enable ");
+ DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
+ return;
+ }
+
+ prev_cnt = sp->mc_addr_count;
+ sp->mc_addr_count = dev->mc_count;
+
+ /* Clear out the previous list of Mc in the H/W. */
+ for (i = 0; i < prev_cnt; i++) {
+ writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
+ &bar0->rmac_addr_data0_mem);
+ val64 = RMAC_ADDR_CMD_MEM_WE |
+ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET
+ (MAC_MC_ADDR_START_OFFSET + i);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+
+ /* Wait for command completes */
+ if (waitForCmdComplete(sp)) {
+ DBG_PRINT(ERR_DBG, "%s: Adding ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Multicasts failed\n");
+ return;
+ }
+ }
+
+ /* Create the new Rx filter list and update the same in H/W. */
+ for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
+ i++, mclist = mclist->next) {
+ memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
+ ETH_ALEN);
+ for (j = 0; j < ETH_ALEN; j++) {
+ mac_addr |= mclist->dmi_addr[j];
+ mac_addr <<= 8;
+ }
+ writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
+ &bar0->rmac_addr_data0_mem);
+
+ val64 = RMAC_ADDR_CMD_MEM_WE |
+ RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET
+ (i + MAC_MC_ADDR_START_OFFSET);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+
+ /* Wait for command completes */
+ if (waitForCmdComplete(sp)) {
+ DBG_PRINT(ERR_DBG, "%s: Adding ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "Multicasts failed\n");
+ return;
+ }
+ }
+ }
+}
+
+/*
+ * Input Argument/s:
+ * dev - pointer to the device structure.
+ * new_mac - a uchar pointer to the new mac address which is to be set.
+ * Return value:
+ * SUCCESS on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ * Description:
+ * This procedure will program the Xframe to receive frames with new
+ * Mac Address
+ */
+int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
+{
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ register u64 val64, mac_addr = 0;
+ int i;
+
+ /*
+ * Set the new MAC address as the new unicast filter and reflect this
+ * change on the device address registered with the OS. It will be
+ * at offset 0.
+ */
+ for (i = 0; i < ETH_ALEN; i++) {
+ mac_addr <<= 8;
+ mac_addr |= addr[i];
+ }
+
+ writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
+ &bar0->rmac_addr_data0_mem);
+
+ val64 =
+ RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET(0);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+ /* Wait till command completes */
+ if (waitForCmdComplete(sp)) {
+ DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
+ return FAILURE;
+ }
+
+ return SUCCESS;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * info - pointer to the structure with parameters given by ethtool to set
+ * link information.
+ * Return value:
+ * 0 on success.
+ * Description:
+ * The function sets different link parameters provided by the user onto
+ * the NIC.
+ */
+static int s2io_ethtool_sset(struct net_device *dev,
+ struct ethtool_cmd *info)
+{
+ nic_t *sp = dev->priv;
+ if ((info->autoneg == AUTONEG_ENABLE) ||
+ (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
+ return -EINVAL;
+ else {
+ s2io_close(sp->dev);
+ s2io_open(sp->dev);
+ }
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * info - pointer to the structure with parameters given by ethtool to return
+ * link information.
+ * Return value:
+ * void
+ * Description:
+ * Returns link specefic information like speed, duplex etc.. to ethtool.
+ */
+int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
+{
+ nic_t *sp = dev->priv;
+ info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
+ info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
+ info->port = PORT_FIBRE;
+ /* info->transceiver?? TODO */
+
+ if (netif_carrier_ok(sp->dev)) {
+ info->speed = 10000;
+ info->duplex = DUPLEX_FULL;
+ } else {
+ info->speed = -1;
+ info->duplex = -1;
+ }
+
+ info->autoneg = AUTONEG_DISABLE;
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * info - pointer to the structure with parameters given by ethtool to return
+ * driver information.
+ * Return value:
+ * void
+ * Description:
+ * Returns driver specefic information like name, version etc.. to ethtool.
+ */
+static void s2io_ethtool_gdrvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ nic_t *sp = dev->priv;
+
+ strncpy(info->driver, s2io_driver_name, sizeof(s2io_driver_name));
+ strncpy(info->version, s2io_driver_version,
+ sizeof(s2io_driver_version));
+ strncpy(info->fw_version, "", 32);
+ strncpy(info->bus_info, sp->pdev->slot_name, 32);
+ info->regdump_len = XENA_REG_SPACE;
+ info->eedump_len = XENA_EEPROM_SPACE;
+ info->testinfo_len = S2IO_TEST_LEN;
+ info->n_stats = S2IO_STAT_LEN;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * regs - pointer to the structure with parameters given by ethtool for
+ * dumping the registers.
+ * reg_space - The input argumnet into which all the registers are dumped.
+ * Return value:
+ * void
+ * Description:
+ * Dumps the entire register space of xFrame NIC into the user given buffer
+ * area.
+ */
+static void s2io_ethtool_gregs(struct net_device *dev,
+ struct ethtool_regs *regs, void *space)
+{
+ int i;
+ u64 reg;
+ u8 *reg_space = (u8 *) space;
+ nic_t *sp = dev->priv;
+
+ regs->len = XENA_REG_SPACE;
+ regs->version = sp->pdev->subsystem_device;
+
+ for (i = 0; i < regs->len; i += 8) {
+ reg = readq((void *) (sp->bar0 + i));
+ memcpy((reg_space + i), ®, 8);
+ }
+}
+
+/*
+ * Input Argument/s:
+ * data - address of the private member of the device structure, which
+ * is a pointer to the s2io_nic structure, provided as an u32.
+ * Return value:
+ * void
+ * Description:
+ * This is actually the timer function that alternates the adapter LED bit
+ * of the adapter control bit to set/reset every time on invocation.
+ * The timer is set for 1/2 a second, hence tha NIC blinks once every second.
+ */
+static void s2io_phy_id(unsigned long data)
+{
+ nic_t *sp = (nic_t *) data;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64 = 0;
+ u16 subid;
+
+ subid = sp->pdev->subsystem_device;
+ if ((subid & 0xFF) >= 0x07) {
+ val64 = readq(&bar0->gpio_control);
+ val64 ^= GPIO_CTRL_GPIO_0;
+ writeq(val64, &bar0->gpio_control);
+ } else {
+ val64 = readq(&bar0->adapter_control);
+ val64 ^= ADAPTER_LED_ON;
+ writeq(val64, &bar0->adapter_control);
+ }
+
+ mod_timer(&sp->id_timer, jiffies + HZ / 2);
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * id - pointer to the structure with identification parameters given by
+ * ethtool.
+ * Return value:
+ * int , returns '0' on success
+ * Description:
+ * Used to physically identify the NIC on the system. The Link LED will blink
+ * for a time specified by the user for identification.
+ * NOTE: The Link has to be Up to be able to blink the LED. Hence
+ * identification is possible only if it's link is up.
+ */
+static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
+{
+ u64 val64 = 0;
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u16 subid;
+
+ subid = sp->pdev->subsystem_device;
+ if ((subid & 0xFF) < 0x07) {
+ val64 = readq(&bar0->adapter_control);
+ if (!(val64 & ADAPTER_CNTL_EN)) {
+ printk(KERN_ERR
+ "Adapter Link down, cannot blink LED\n");
+ return -EFAULT;
+ }
+ }
+ if (sp->id_timer.function == NULL) {
+ init_timer(&sp->id_timer);
+ sp->id_timer.function = s2io_phy_id;
+ sp->id_timer.data = (unsigned long) sp;
+ }
+ mod_timer(&sp->id_timer, jiffies);
+ set_current_state(TASK_INTERRUPTIBLE);
+ if (data)
+ schedule_timeout(data * HZ);
+ else
+ schedule_timeout(MAX_SCHEDULE_TIMEOUT);
+ del_timer_sync(&sp->id_timer);
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * ep - pointer to the structure with pause parameters given by ethtool.
+ * Return value:
+ * void
+ * Description:
+ * Returns the Pause frame generation and reception capability of the NIC.
+ */
+static void s2io_ethtool_getpause_data(struct net_device *dev,
+ struct ethtool_pauseparam *ep)
+{
+ u64 val64;
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+
+ val64 = readq(&bar0->rmac_pause_cfg);
+ if (val64 & RMAC_PAUSE_GEN_ENABLE)
+ ep->tx_pause = TRUE;
+ if (val64 & RMAC_PAUSE_RX_ENABLE)
+ ep->rx_pause = TRUE;
+ ep->autoneg = FALSE;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * ep - pointer to the structure with pause parameters given by ethtool.
+ * Return value:
+ * int, returns '0' on Success
+ * Description:
+ * It can be used to set or reset Pause frame generation or reception support
+ * of the NIC.
+ */
+int s2io_ethtool_setpause_data(struct net_device *dev,
+ struct ethtool_pauseparam *ep)
+{
+ u64 val64;
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+
+ val64 = readq(&bar0->rmac_pause_cfg);
+ if (ep->tx_pause)
+ val64 |= RMAC_PAUSE_GEN_ENABLE;
+ else
+ val64 &= ~RMAC_PAUSE_GEN_ENABLE;
+ if (ep->rx_pause)
+ val64 |= RMAC_PAUSE_RX_ENABLE;
+ else
+ val64 &= ~RMAC_PAUSE_RX_ENABLE;
+ writeq(val64, &bar0->rmac_pause_cfg);
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * off - offset at which the data must be written
+ * Return value:
+ * -1 on failure and the value read from the Eeprom if successful.
+ * Description:
+ * Will read 4 bytes of data from the user given offset and return the
+ * read data.
+ * NOTE: Will allow to read only part of the EEPROM visible through the
+ * I2C bus.
+ */
+#define S2IO_DEV_ID 5
+static u32 readEeprom(nic_t * sp, int off)
+{
+ u32 data = -1, exit_cnt = 0;
+ u64 val64;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+
+ val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
+ I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
+ I2C_CONTROL_CNTL_START;
+ writeq(val64, &bar0->i2c_control);
+
+ while (exit_cnt < 5) {
+ val64 = readq(&bar0->i2c_control);
+ if (I2C_CONTROL_CNTL_END(val64)) {
+ data = I2C_CONTROL_GET_DATA(val64);
+ break;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ exit_cnt++;
+ }
+
+ return data;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * off - offset at which the data must be written
+ * data - The data that is to be written
+ * cnt - Number of bytes of the data that are actually to be written into
+ * the Eeprom. (max of 3)
+ * Return value:
+ * '0' on success, -1 on failure.
+ * Description:
+ * Actually writes the relevant part of the data value into the Eeprom
+ * through the I2C bus.
+ */
+static int writeEeprom(nic_t * sp, int off, u32 data, int cnt)
+{
+ int exit_cnt = 0, ret = -1;
+ u64 val64;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+
+ val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
+ I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |
+ I2C_CONTROL_CNTL_START;
+ writeq(val64, &bar0->i2c_control);
+
+ while (exit_cnt < 5) {
+ val64 = readq(&bar0->i2c_control);
+ if (I2C_CONTROL_CNTL_END(val64)) {
+ if (!(val64 & I2C_CONTROL_NACK))
+ ret = 0;
+ break;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 20);
+ exit_cnt++;
+ }
+
+ return ret;
+}
+
+/*
+ * A helper function used to invert the 4 byte u32 data field
+ * byte by byte. This will be used by the Read Eeprom function
+ * for display purposes.
+ */
+u32 inv(u32 data)
+{
+ static u32 ret = 0;
+
+ if (data) {
+ u8 c = data;
+ ret = ((ret << 8) + c);
+ data >>= 8;
+ inv(data);
+ }
+
+ return ret;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * eeprom - pointer to the user level structure provided by ethtool,
+ * containing all relevant information.
+ * data_buf - user defined value to be written into Eeprom.
+ * Return value:
+ * int '0' on success
+ * Description:
+ * Reads the values stored in the Eeprom at given offset for a given length.
+ * Stores these values int the input argument data buffer 'data_buf' and
+ * returns these to the caller (ethtool.)
+ */
+int s2io_ethtool_geeprom(struct net_device *dev,
+ struct ethtool_eeprom *eeprom, u8 * data_buf)
+{
+ u32 data, i, valid;
+ nic_t *sp = dev->priv;
+
+ eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
+
+ if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
+ eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
+
+ for (i = 0; i < eeprom->len; i += 4) {
+ data = readEeprom(sp, eeprom->offset + i);
+ if (data < 0) {
+ DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
+ return -EFAULT;
+ }
+ valid = inv(data);
+ memcpy((data_buf + i), &valid, 4);
+ }
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * eeprom - pointer to the user level structure provided by ethtool,
+ * containing all relevant information.
+ * data_buf - user defined value to be written into Eeprom.
+ * Return value:
+ * '0' on success, -EFAULT on failure.
+ * Description:
+ * Tries to write the user provided value in the Eeprom, at the offset
+ * given by the user.
+ */
+static int s2io_ethtool_seeprom(struct net_device *dev,
+ struct ethtool_eeprom *eeprom,
+ u8 * data_buf)
+{
+ int len = eeprom->len, cnt = 0;
+ u32 valid = 0, data;
+ nic_t *sp = dev->priv;
+
+ if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
+ DBG_PRINT(ERR_DBG,
+ "ETHTOOL_WRITE_EEPROM Err: Magic value ");
+ DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
+ eeprom->magic);
+ return -EFAULT;
+ }
+
+ while (len) {
+ data = (u32) data_buf[cnt] & 0x000000FF;
+ if (data) {
+ valid = (u32) (data << 24);
+ } else
+ valid = data;
+
+ if (writeEeprom(sp, (eeprom->offset + cnt), valid, 0)) {
+ DBG_PRINT(ERR_DBG,
+ "ETHTOOL_WRITE_EEPROM Err: Cannot ");
+ DBG_PRINT(ERR_DBG,
+ "write into the specified offset\n");
+ return -EFAULT;
+ }
+ cnt++;
+ len--;
+ }
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * '0' on success.
+ * Description:
+ * Read and write into all clock domains. The NIC has 3 clock domains,
+ * see that registers in all the three regions are accessible.
+ */
+static int s2io_registerTest(nic_t * sp, uint64_t * data)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64 = 0;
+ int fail = 0;
+
+ val64 = readq(&bar0->pcc_enable);
+ if (val64 != 0xff00000000000000ULL) {
+ fail = 1;
+ DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
+ }
+
+ val64 = readq(&bar0->rmac_pause_cfg);
+ if (val64 != 0xc000ffff00000000ULL) {
+ fail = 1;
+ DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
+ }
+
+ val64 = readq(&bar0->rx_queue_cfg);
+ if (val64 != 0x0808080808080808ULL) {
+ fail = 1;
+ DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
+ }
+
+ val64 = readq(&bar0->xgxs_efifo_cfg);
+ if (val64 != 0x000000001923141EULL) {
+ fail = 1;
+ DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
+ }
+
+ val64 = 0x5A5A5A5A5A5A5A5AULL;
+ writeq(val64, &bar0->xmsi_data);
+ val64 = readq(&bar0->xmsi_data);
+ if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
+ fail = 1;
+ DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
+ }
+
+ val64 = 0xA5A5A5A5A5A5A5A5ULL;
+ writeq(val64, &bar0->xmsi_data);
+ val64 = readq(&bar0->xmsi_data);
+ if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
+ fail = 1;
+ DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
+ }
+
+ *data = fail;
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * '0' on success.
+ * Description:
+ * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
+ * register.
+ */
+static int s2io_eepromTest(nic_t * sp, uint64_t * data)
+{
+ int fail = 0, ret_data;
+
+ /* Test Write Error at offset 0 */
+ if (!writeEeprom(sp, 0, 0, 3))
+ fail = 1;
+
+ /* Test Write at offset 4f0 */
+ if (writeEeprom(sp, 0x4F0, 0x01234567, 3))
+ fail = 1;
+ if ((ret_data = readEeprom(sp, 0x4f0)) < 0)
+ fail = 1;
+
+ if (ret_data != 0x01234567)
+ fail = 1;
+
+ /* Reset the EEPROM data go FFFF */
+ writeEeprom(sp, 0x4F0, 0xFFFFFFFF, 3);
+
+ /* Test Write Request Error at offset 0x7c */
+ if (!writeEeprom(sp, 0x07C, 0, 3))
+ fail = 1;
+
+ /* Test Write Request at offset 0x7fc */
+ if (writeEeprom(sp, 0x7FC, 0x01234567, 3))
+ fail = 1;
+ if ((ret_data = readEeprom(sp, 0x7FC)) < 0)
+ fail = 1;
+
+ if (ret_data != 0x01234567)
+ fail = 1;
+
+ /* Reset the EEPROM data go FFFF */
+ writeEeprom(sp, 0x7FC, 0xFFFFFFFF, 3);
+
+ /* Test Write Error at offset 0x80 */
+ if (!writeEeprom(sp, 0x080, 0, 3))
+ fail = 1;
+
+ /* Test Write Error at offset 0xfc */
+ if (!writeEeprom(sp, 0x0FC, 0, 3))
+ fail = 1;
+
+ /* Test Write Error at offset 0x100 */
+ if (!writeEeprom(sp, 0x100, 0, 3))
+ fail = 1;
+
+ /* Test Write Error at offset 4ec */
+ if (!writeEeprom(sp, 0x4EC, 0, 3))
+ fail = 1;
+
+ *data = fail;
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * '0' on success and -1 on failure.
+ * Description:
+ * This invokes the MemBist test of the card. We give around
+ * 2 secs time for the Test to complete. If it's still not complete
+ * within this peiod, we consider that the test failed.
+ */
+static int s2io_bistTest(nic_t * sp, uint64_t * data)
+{
+ u8 bist = 0;
+ int cnt = 0, ret = -1;
+
+ pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
+ bist |= PCI_BIST_START;
+ pci_write_config_word(sp->pdev, PCI_BIST, bist);
+
+ while (cnt < 20) {
+ pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
+ if (!(bist & PCI_BIST_START)) {
+ *data = (bist & PCI_BIST_CODE_MASK);
+ ret = 0;
+ break;
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 10);
+ cnt++;
+ }
+
+ return ret;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * '0' on success.
+ * Description:
+ * The function verifies the link state of the NIC and updates the input
+ * argument 'data' appropriately.
+ */
+static int s2io_linkTest(nic_t * sp, uint64_t * data)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+
+ val64 = readq(&bar0->adapter_status);
+ if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
+ *data = 1;
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * '0' on success.
+ * Description:
+ * This is one of the offline test that tests the read and write
+ * access to the RldRam chip on the NIC.
+ */
+static int s2io_rldramTest(nic_t * sp, uint64_t * data)
+{
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ u64 val64;
+ int cnt, iteration = 0, test_pass = 0;
+
+ val64 = readq(&bar0->adapter_control);
+ val64 &= ~ADAPTER_ECC_EN;
+ writeq(val64, &bar0->adapter_control);
+
+ val64 = readq(&bar0->mc_rldram_test_ctrl);
+ val64 |= MC_RLDRAM_TEST_MODE;
+ writeq(val64, &bar0->mc_rldram_test_ctrl);
+
+ val64 = readq(&bar0->mc_rldram_mrs);
+ val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
+ writeq(val64, &bar0->mc_rldram_mrs);
+
+ val64 |= MC_RLDRAM_MRS_ENABLE;
+ writeq(val64, &bar0->mc_rldram_mrs);
+
+ while (iteration < 2) {
+ val64 = 0x55555555aaaa0000ULL;
+ if (iteration == 1) {
+ val64 ^= 0xFFFFFFFFFFFF0000ULL;
+ }
+ writeq(val64, &bar0->mc_rldram_test_d0);
+
+ val64 = 0xaaaa5a5555550000ULL;
+ if (iteration == 1) {
+ val64 ^= 0xFFFFFFFFFFFF0000ULL;
+ }
+ writeq(val64, &bar0->mc_rldram_test_d1);
+
+ val64 = 0x55aaaaaaaa5a0000ULL;
+ if (iteration == 1) {
+ val64 ^= 0xFFFFFFFFFFFF0000ULL;
+ }
+ writeq(val64, &bar0->mc_rldram_test_d2);
+
+ val64 = (u64) (0x0000003fffff0000ULL);
+ writeq(val64, &bar0->mc_rldram_test_add);
+
+
+ val64 = MC_RLDRAM_TEST_MODE;
+ writeq(val64, &bar0->mc_rldram_test_ctrl);
+
+ val64 |=
+ MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
+ MC_RLDRAM_TEST_GO;
+ writeq(val64, &bar0->mc_rldram_test_ctrl);
+
+ for (cnt = 0; cnt < 5; cnt++) {
+ val64 = readq(&bar0->mc_rldram_test_ctrl);
+ if (val64 & MC_RLDRAM_TEST_DONE)
+ break;
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 5);
+ }
+
+ if (cnt == 5)
+ break;
+
+ val64 = MC_RLDRAM_TEST_MODE;
+ writeq(val64, &bar0->mc_rldram_test_ctrl);
+
+ val64 |= MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
+ writeq(val64, &bar0->mc_rldram_test_ctrl);
+
+ for (cnt = 0; cnt < 5; cnt++) {
+ val64 = readq(&bar0->mc_rldram_test_ctrl);
+ if (val64 & MC_RLDRAM_TEST_DONE)
+ break;
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 2);
+ }
+
+ if (cnt == 5)
+ break;
+
+ val64 = readq(&bar0->mc_rldram_test_ctrl);
+ if (val64 & MC_RLDRAM_TEST_PASS)
+ test_pass = 1;
+
+ iteration++;
+ }
+
+ if (!test_pass)
+ *data = 1;
+ else
+ *data = 0;
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * ethtest - pointer to a ethtool command specific structure that will be
+ * returned to the user.
+ * data - variable that returns the result of each of the test conducted by
+ * the driver.
+ * Return value:
+ * SUCCESS on success and an appropriate -1 on failure.
+ * Description:
+ * This function conducts 6 tests ( 4 offline and 2 online) to determine
+ * the health of the card.
+ */
+static void s2io_ethtool_test(struct net_device *dev,
+ struct ethtool_test *ethtest,
+ uint64_t * data)
+{
+ nic_t *sp = dev->priv;
+ int orig_state = netif_running(sp->dev);
+
+ if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
+ /* Offline Tests. */
+ if (orig_state) {
+ s2io_close(sp->dev);
+ s2io_set_swapper(sp);
+ } else
+ s2io_set_swapper(sp);
+
+ if (s2io_registerTest(sp, &data[0]))
+ ethtest->flags |= ETH_TEST_FL_FAILED;
+
+ s2io_reset(sp);
+ s2io_set_swapper(sp);
+
+ if (s2io_rldramTest(sp, &data[3]))
+ ethtest->flags |= ETH_TEST_FL_FAILED;
+
+ s2io_reset(sp);
+ s2io_set_swapper(sp);
+
+ if (s2io_eepromTest(sp, &data[1]))
+ ethtest->flags |= ETH_TEST_FL_FAILED;
+
+ if (s2io_bistTest(sp, &data[4]))
+ ethtest->flags |= ETH_TEST_FL_FAILED;
+
+ if (orig_state)
+ s2io_open(sp->dev);
+
+ data[2] = 0;
+ } else {
+ /* Online Tests. */
+ if (!orig_state) {
+ DBG_PRINT(ERR_DBG,
+ "%s: is not up, cannot run test\n",
+ dev->name);
+ data[0] = -1;
+ data[1] = -1;
+ data[2] = -1;
+ data[3] = -1;
+ data[4] = -1;
+ }
+
+ if (s2io_linkTest(sp, &data[2]))
+ ethtest->flags |= ETH_TEST_FL_FAILED;
+
+ data[0] = 0;
+ data[1] = 0;
+ data[3] = 0;
+ data[4] = 0;
+ }
+}
+
+static void s2io_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *estats,
+ u64 * tmp_stats)
+{
+ int i = 0;
+ nic_t *sp = dev->priv;
+ StatInfo_t *stat_info = sp->mac_control.StatsInfo;
+
+ tmp_stats[i++] = stat_info->tmac_frms;
+ tmp_stats[i++] = stat_info->tmac_data_octets;
+ tmp_stats[i++] = stat_info->tmac_drop_frms;
+ tmp_stats[i++] = stat_info->tmac_mcst_frms;
+ tmp_stats[i++] = stat_info->tmac_bcst_frms;
+ tmp_stats[i++] = stat_info->tmac_pause_ctrl_frms;
+ tmp_stats[i++] = stat_info->tmac_any_err_frms;
+ tmp_stats[i++] = stat_info->tmac_vld_ip_octets;
+ tmp_stats[i++] = stat_info->tmac_vld_ip;
+ tmp_stats[i++] = stat_info->tmac_drop_ip;
+ tmp_stats[i++] = stat_info->tmac_icmp;
+ tmp_stats[i++] = stat_info->tmac_rst_tcp;
+ tmp_stats[i++] = stat_info->tmac_tcp;
+ tmp_stats[i++] = stat_info->tmac_udp;
+ tmp_stats[i++] = stat_info->rmac_vld_frms;
+ tmp_stats[i++] = stat_info->rmac_data_octets;
+ tmp_stats[i++] = stat_info->rmac_fcs_err_frms;
+ tmp_stats[i++] = stat_info->rmac_drop_frms;
+ tmp_stats[i++] = stat_info->rmac_vld_mcst_frms;
+ tmp_stats[i++] = stat_info->rmac_vld_bcst_frms;
+ tmp_stats[i++] = stat_info->rmac_in_rng_len_err_frms;
+ tmp_stats[i++] = stat_info->rmac_long_frms;
+ tmp_stats[i++] = stat_info->rmac_pause_ctrl_frms;
+ tmp_stats[i++] = stat_info->rmac_discarded_frms;
+ tmp_stats[i++] = stat_info->rmac_usized_frms;
+ tmp_stats[i++] = stat_info->rmac_osized_frms;
+ tmp_stats[i++] = stat_info->rmac_frag_frms;
+ tmp_stats[i++] = stat_info->rmac_jabber_frms;
+ tmp_stats[i++] = stat_info->rmac_ip;
+ tmp_stats[i++] = stat_info->rmac_ip_octets;
+ tmp_stats[i++] = stat_info->rmac_hdr_err_ip;
+ tmp_stats[i++] = stat_info->rmac_drop_ip;
+ tmp_stats[i++] = stat_info->rmac_icmp;
+ tmp_stats[i++] = stat_info->rmac_tcp;
+ tmp_stats[i++] = stat_info->rmac_udp;
+ tmp_stats[i++] = stat_info->rmac_err_drp_udp;
+ tmp_stats[i++] = stat_info->rmac_pause_cnt;
+ tmp_stats[i++] = stat_info->rmac_accepted_ip;
+ tmp_stats[i++] = stat_info->rmac_err_tcp;
+}
+
+int s2io_ethtool_get_regs_len(struct net_device *dev)
+{
+ return (XENA_REG_SPACE);
+}
+
+
+u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
+{
+ nic_t *sp = dev->priv;
+
+ return (sp->rx_csum);
+}
+int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
+{
+ nic_t *sp = dev->priv;
+
+ if (data)
+ sp->rx_csum = 1;
+ else
+ sp->rx_csum = 0;
+
+ return 0;
+}
+int s2io_get_eeprom_len(struct net_device *dev)
+{
+ return (XENA_EEPROM_SPACE);
+}
+
+int s2io_ethtool_self_test_count(struct net_device *dev)
+{
+ return (S2IO_TEST_LEN);
+}
+void s2io_ethtool_get_strings(struct net_device *dev,
+ u32 stringset, u8 * data)
+{
+ switch (stringset) {
+ case ETH_SS_TEST:
+ memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
+ break;
+ case ETH_SS_STATS:
+ memcpy(data, ðtool_stats_keys,
+ sizeof(ethtool_stats_keys));
+ }
+}
+static int s2io_ethtool_get_stats_count(struct net_device *dev)
+{
+ return (S2IO_STAT_LEN);
+}
+
+static struct ethtool_ops netdev_ethtool_ops = {
+ .get_settings = s2io_ethtool_gset,
+ .set_settings = s2io_ethtool_sset,
+ .get_drvinfo = s2io_ethtool_gdrvinfo,
+ .get_regs_len = s2io_ethtool_get_regs_len,
+ .get_regs = s2io_ethtool_gregs,
+ .get_link = ethtool_op_get_link,
+ .get_eeprom_len = s2io_get_eeprom_len,
+ .get_eeprom = s2io_ethtool_geeprom,
+ .set_eeprom = s2io_ethtool_seeprom,
+ .get_pauseparam = s2io_ethtool_getpause_data,
+ .set_pauseparam = s2io_ethtool_setpause_data,
+ .get_rx_csum = s2io_ethtool_get_rx_csum,
+ .set_rx_csum = s2io_ethtool_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = ethtool_op_set_tx_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+#ifdef NETIF_F_TSO
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = ethtool_op_set_tso,
+#endif
+ .self_test_count = s2io_ethtool_self_test_count,
+ .self_test = s2io_ethtool_test,
+ .get_strings = s2io_ethtool_get_strings,
+ .phys_id = s2io_ethtool_idnic,
+ .get_stats_count = s2io_ethtool_get_stats_count,
+ .get_ethtool_stats = s2io_get_ethtool_stats
+};
+
+/*
+ * Input Argument/s:
+ * dev - Device pointer.
+ * ifr - An IOCTL specefic structure, that can contain a pointer to
+ * a proprietary structure used to pass information to the driver.
+ * cmd - This is used to distinguish between the different commands that
+ * can be passed to the IOCTL functions.
+ * Return value:
+ * '0' on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ * Description:
+ * This function has support for ethtool, adding multiple MAC addresses on
+ * the NIC and some DBG commands for the util tool.
+ */
+int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ return -EOPNOTSUPP;
+}
+
+/*
+ * Input Argument/s:
+ * dev - device pointer.
+ * new_mtu - the new MTU size for the device.
+ * Return value:
+ * '0' on success and an appropriate (-)ve integer as defined in errno.h
+ * file on failure.
+ * Description:
+ * A driver entry point to change MTU size for the device. Before changing
+ * the MTU the device must be stopped.
+ */
+int s2io_change_mtu(struct net_device *dev, int new_mtu)
+{
+ nic_t *sp = dev->priv;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ register u64 val64;
+
+ if (netif_running(dev)) {
+ DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
+ DBG_PRINT(ERR_DBG, "change its MTU \n");
+ return -EBUSY;
+ }
+
+ if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
+ DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
+ dev->name);
+ return -EPERM;
+ }
+
+/* Set the new MTU into the PYLD register of the NIC */
+ val64 = new_mtu;
+ writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
+
+ dev->mtu = new_mtu;
+
+ return 0;
+}
+
+/*
+ * Input Argument/s:
+ * dev_adr - address of the device structure in dma_addr_t format.
+ * Return value:
+ * void.
+ * Description:
+ * This is the tasklet or the bottom half of the ISR. This is
+ * an extension of the ISR which is scheduled by the scheduler to be run
+ * when the load on the CPU is low. All low priority tasks of the ISR can
+ * be pushed into the tasklet. For now the tasklet is used only to
+ * replenish the Rx buffers in the Rx buffer descriptors.
+ */
+static void s2io_tasklet(unsigned long dev_addr)
+{
+ struct net_device *dev = (struct net_device *) dev_addr;
+ nic_t *sp = dev->priv;
+ int i, ret;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ if (!TASKLET_IN_USE) {
+ for (i = 0; i < config->RxRingNum; i++) {
+ ret = fill_rx_buffers(sp, i);
+ if (ret == -ENOMEM) {
+ DBG_PRINT(ERR_DBG, "%s: Out of ",
+ dev->name);
+ DBG_PRINT(ERR_DBG, "memory in tasklet\n");
+ return;
+ } else if (ret == -EFILL) {
+ DBG_PRINT(ERR_DBG,
+ "%s: Rx Ring %d is full\n",
+ dev->name, i);
+ return;
+ }
+ }
+ clear_bit(0, (unsigned long *) (&sp->tasklet_status));
+ }
+}
+
+
+/*
+ * Description:
+ *
+ */
+static void s2io_set_link(unsigned long data)
+{
+ nic_t *nic = (nic_t *) data;
+ struct net_device *dev = nic->dev;
+ XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ register u64 val64, err_reg;
+
+ /* Allow a small delay for the NICs self initiated
+ * cleanup to complete.
+ */
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(HZ / 10);
+
+ val64 = readq(&bar0->adapter_status);
+ if (verify_xena_quiescence(val64, nic->device_enabled_once)) {
+ /* Acknowledge interrupt and clear the R1 register */
+ err_reg = readq(&bar0->mac_rmac_err_reg);
+ writeq(err_reg, &bar0->mac_rmac_err_reg);
+
+ if (LINK_IS_UP(val64)) {
+ val64 = readq(&bar0->adapter_control);
+ val64 |= ADAPTER_CNTL_EN;
+ writeq(val64, &bar0->adapter_control);
+ val64 |= ADAPTER_LED_ON;
+ writeq(val64, &bar0->adapter_control);
+ val64 = readq(&bar0->adapter_status);
+ if (!LINK_IS_UP(val64)) {
+ DBG_PRINT(ERR_DBG, "%s:", dev->name);
+ DBG_PRINT(ERR_DBG, " Link down");
+ DBG_PRINT(ERR_DBG, "after ");
+ DBG_PRINT(ERR_DBG, "enabling ");
+ DBG_PRINT(ERR_DBG, "device \n");
+ }
+ if (nic->device_enabled_once == FALSE) {
+ nic->device_enabled_once = TRUE;
+ }
+ s2io_link(nic, LINK_UP);
+ } else {
+ s2io_link(nic, LINK_DOWN);
+ }
+ } else { /* NIC is not Quiescent. */
+ DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
+ DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
+ netif_stop_queue(dev);
+ }
+}
+
+/*
+ * Description:
+ * This function is scheduled to be run by the s2io_tx_watchdog
+ * function after 0.5 secs to reset the NIC. The idea is to reduce
+ * the run time of the watch dog routine which is run holding a
+ * spin lock.
+ */
+static void s2io_restart_nic(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *) data;
+ nic_t *sp = dev->priv;
+
+ s2io_close(dev);
+ sp->device_close_flag = TRUE;
+ s2io_open(dev);
+ DBG_PRINT(ERR_DBG,
+ "%s: was reset by Tx watchdog timer.\n", dev->name);
+}
+
+/*
+ * Input Argument/s:
+ * dev - device pointer.
+ * Return value:
+ * void
+ * Description:
+ * This function is triggered if the Tx Queue is stopped
+ * for a pre-defined amount of time when the Interface is still up.
+ * If the Interface is jammed in such a situation, the hardware is
+ * reset (by s2io_close) and restarted again (by s2io_open) to
+ * overcome any problem that might have been caused in the hardware.
+ */
+static void s2io_tx_watchdog(struct net_device *dev)
+{
+ nic_t *sp = dev->priv;
+
+ if (netif_carrier_ok(dev)) {
+ schedule_work(&sp->rst_timer_task);
+ }
+}
+
+/*
+ * Input Argument/s:
+ * sp - private member of the device structure, which is a pointer to the
+ * s2io_nic structure.
+ * skb - the socket buffer pointer.
+ * len - length of the packet
+ * cksum - FCS checksum of the frame.
+ * ring_no - the ring from which this RxD was extracted.
+ * Return value:
+ * SUCCESS on success and -1 on failure.
+ * Description:
+ * This function is called by the Tx interrupt serivce routine to perform
+ * some OS related operations on the SKB before passing it to the upper
+ * layers. It mainly checks if the checksum is OK, if so adds it to the
+ * SKBs cksum variable, increments the Rx packet count and passes the SKB
+ * to the upper layer. If the checksum is wrong, it increments the Rx
+ * packet error count, frees the SKB and returns error.
+ */
+static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
+{
+ struct net_device *dev = (struct net_device *) sp->dev;
+ struct sk_buff *skb =
+ (struct sk_buff *) ((unsigned long) rxdp->Host_Control);
+ u16 l3_csum, l4_csum;
+
+ l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
+ if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) {
+ l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
+ if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
+ /* NIC verifies if the Checksum of the received
+ * frame is Ok or not and accordingly returns
+ * a flag in the RxD.
+ */
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ } else {
+ /*
+ * Packet with erroneous checksum, let the
+ * upper layers deal with it.
+ */
+ skb->ip_summed = CHECKSUM_NONE;
+ }
+ } else {
+ skb->ip_summed = CHECKSUM_NONE;
+ }
+
+ skb->dev = dev;
+ skb_put(skb, len);
+ skb->protocol = eth_type_trans(skb, dev);
+
+#ifdef CONFIG_S2IO_NAPI
+ netif_receive_skb(skb);
+#else
+ netif_rx(skb);
+#endif
+
+ dev->last_rx = jiffies;
+#if DEBUG_ON
+ sp->rxpkt_cnt++;
+#endif
+ sp->rx_pkt_count++;
+ sp->stats.rx_packets++;
+ sp->stats.rx_bytes += len;
+ sp->rxpkt_bytes += len;
+
+ atomic_dec(&sp->rx_bufs_left[ring_no]);
+ rxdp->Host_Control = 0;
+ return SUCCESS;
+}
+
+int check_for_txSpace(nic_t * sp)
+{
+ u32 put_off, get_off, queue_len;
+ int ret = TRUE, i;
+
+ for (i = 0; i < sp->config.TxFIFONum; i++) {
+ queue_len = sp->mac_control.tx_curr_put_info[i].fifo_len
+ + 1;
+ put_off = sp->mac_control.tx_curr_put_info[i].offset;
+ get_off = sp->mac_control.tx_curr_get_info[i].offset;
+ if (((put_off + 1) % queue_len) == get_off) {
+ ret = FALSE;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/*
+* Input Argument/s:
+* sp - private member of the device structure, which is a pointer to the
+* s2io_nic structure.
+* link - inidicates whether link is UP/DOWN.
+* Return value:
+* void.
+* Description:
+* This function stops/starts the Tx queue depending on whether the link
+* status of the NIC is is down or up. This is called by the Alarm interrupt
+* handler whenever a link change interrupt comes up.
+*/
+void s2io_link(nic_t * sp, int link)
+{
+ struct net_device *dev = (struct net_device *) sp->dev;
+
+ if (link != sp->last_link_state) {
+ if (link == LINK_DOWN) {
+ DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
+ netif_carrier_off(dev);
+ netif_stop_queue(dev);
+ } else {
+ DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
+ netif_carrier_on(dev);
+ if (check_for_txSpace(sp) == TRUE) {
+ /* Don't wake the queue, if we know there
+ * are no free TxDs available.
+ */
+ netif_wake_queue(dev);
+ }
+ }
+ }
+ sp->last_link_state = link;
+}
+
+/*
+* Input Argument/s:
+* pdev - structure containing the PCI related information of the device.
+* Return value:
+* returns the revision ID of the device.
+* Description:
+* Function to identify the Revision ID of xena.
+*/
+int get_xena_rev_id(struct pci_dev *pdev)
+{
+ u8 id = 0;
+ int ret;
+ ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
+ return id;
+}
+
+/*
+* Input Argument/s:
+* sp - private member of the device structure, which is a pointer to the
+* s2io_nic structure.
+* Return value:
+* void
+* Description:
+* This function initializes a few of the PCI and PCI-X configuration registers
+* with recommended values.
+*/
+static void s2io_init_pci(nic_t * sp)
+{
+ u16 pci_cmd = 0;
+
+/* Enable Data Parity Error Recovery in PCI-X command register. */
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ &(sp->pcix_cmd));
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ (sp->pcix_cmd | 1));
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ &(sp->pcix_cmd));
+
+/* Set the PErr Response bit in PCI command register. */
+ pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_word(sp->pdev, PCI_COMMAND,
+ (pci_cmd | PCI_COMMAND_PARITY));
+ pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
+
+/* Set user specified value in Latency Timer */
+ if (latency_timer) {
+ pci_write_config_byte(sp->pdev, PCI_LATENCY_TIMER,
+ latency_timer);
+ pci_read_config_byte(sp->pdev, PCI_LATENCY_TIMER,
+ &latency_timer);
+ }
+
+/* Set MMRB count to 4096 in PCI-X Command register. */
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ (sp->pcix_cmd | 0x0C));
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ &(sp->pcix_cmd));
+
+/* Setting Maximum outstanding splits to two for now. */
+ sp->pcix_cmd &= 0xFF1F;
+
+ sp->pcix_cmd |=
+ XENA_MAX_OUTSTANDING_SPLITS(XENA_TWO_SPLIT_TRANSACTION);
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ sp->pcix_cmd);
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ &(sp->pcix_cmd));
+
+}
+
+MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
+MODULE_LICENSE("GPL");
+MODULE_PARM(ring_num, "1-" __MODULE_STRING(1) "i");
+MODULE_PARM(frame_len, "1-" __MODULE_STRING(8) "i");
+MODULE_PARM(ring_len, "1-" __MODULE_STRING(8) "i");
+MODULE_PARM(fifo_num, "1-" __MODULE_STRING(1) "i");
+MODULE_PARM(fifo_len, "1-" __MODULE_STRING(8) "i");
+MODULE_PARM(rx_prio, "1-" __MODULE_STRING(1) "i");
+MODULE_PARM(tx_prio, "1-" __MODULE_STRING(1) "i");
+MODULE_PARM(latency_timer, "1-" __MODULE_STRING(1) "i");
+
+/*
+* Input Argument/s:
+* pdev - structure containing the PCI related information of the device.
+* pre - the List of PCI devices supported by the driver listed in s2io_tbl.
+* Return value:
+* returns '0' on success and negative on failure.
+* Description:
+* The function initializes an adapter identified by the pci_dec structure.
+* All OS related initialization including memory and device structure and
+* initlaization of the device private variable is done. Also the swapper
+* control register is initialized to enable read and write into the I/O
+* registers of the device.
+*
+*/
+static int __devinit
+s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
+{
+ nic_t *sp;
+ struct net_device *dev;
+ char *dev_name = "S2IO 10GE NIC";
+ int i, j, ret;
+ int dma_flag = FALSE;
+ u32 mac_up, mac_down;
+ u64 val64 = 0, tmp64 = 0;
+ XENA_dev_config_t *bar0 = NULL;
+ u16 subid;
+ mac_info_t *mac_control;
+ struct config_param *config;
+
+
+ if ((ret = pci_enable_device(pdev))) {
+ DBG_PRINT(ERR_DBG,
+ "s2io_init_nic: pci_enable_device failed\n");
+ return ret;
+ }
+
+ if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
+ DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
+ dma_flag = TRUE;
+ if (pci_set_consistent_dma_mask
+ (pdev, 0xffffffffffffffffULL)) {
+ DBG_PRINT(ERR_DBG,
+ "Unable to obtain 64bit DMA for \
+ consistent allocations\n");
+ pci_disable_device(pdev);
+ return -ENOMEM;
+ }
+ } else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) {
+ DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
+ } else {
+ pci_disable_device(pdev);
+ return -ENOMEM;
+ }
+
+ if (pci_request_regions(pdev, s2io_driver_name)) {
+ DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
+ pci_disable_device(pdev);
+ return -ENODEV;
+ }
+
+ dev = alloc_etherdev(sizeof(nic_t));
+ if (dev == NULL) {
+ DBG_PRINT(ERR_DBG, "Device allocation failed\n");
+ pci_disable_device(pdev);
+ pci_release_regions(pdev);
+ return -ENODEV;
+ }
+
+ pci_set_master(pdev);
+ pci_set_drvdata(pdev, dev);
+ SET_MODULE_OWNER(dev);
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ /* Private member variable initialized to s2io NIC structure */
+ sp = dev->priv;
+ memset(sp, 0, sizeof(nic_t));
+ sp->dev = dev;
+ sp->pdev = pdev;
+ sp->vendor_id = pdev->vendor;
+ sp->device_id = pdev->device;
+ sp->high_dma_flag = dma_flag;
+ sp->irq = pdev->irq;
+ sp->device_enabled_once = FALSE;
+ strcpy(sp->name, dev_name);
+
+ /* Initialize some PCI/PCI-X fields of the NIC. */
+ s2io_init_pci(sp);
+
+ /* Setting the device configuration parameters.
+ * Most of these parameters can be specified by the user during
+ * module insertion as they are module loadable parameters. If
+ * these parameters are not not specified during load time, they
+ * are initialized with default values.
+ */
+ mac_control = &sp->mac_control;
+ config = &sp->config;
+
+ /* Tx side parameters. */
+ config->TxFIFONum = fifo_num ? fifo_num : 1;
+
+ if (!fifo_len[0] && (fifo_num > 1)) {
+ printk(KERN_ERR "Fifo Lens not specified for all FIFOs\n");
+ goto init_failed;
+ }
+
+ if (fifo_len[0]) {
+ int cnt;
+
+ for (cnt = 0; fifo_len[cnt]; cnt++);
+ if (fifo_num) {
+ if (cnt < fifo_num) {
+ printk(KERN_ERR
+ "Fifo Lens not specified for ");
+ printk(KERN_ERR "all FIFOs\n");
+ goto init_failed;
+ }
+ }
+ for (cnt = 0; cnt < config->TxFIFONum; cnt++) {
+ config->TxCfg[cnt].FifoLen = fifo_len[cnt];
+ config->TxCfg[cnt].FifoPriority = cnt;
+ }
+ } else {
+ config->TxCfg[0].FifoLen = DEFAULT_FIFO_LEN;
+ config->TxCfg[0].FifoPriority = 0;
+ }
+
+ config->TxIntrType = TXD_INT_TYPE_UTILZ;
+ for (i = 0; i < config->TxFIFONum; i++) {
+ if (config->TxCfg[i].FifoLen < 65) {
+ config->TxIntrType = TXD_INT_TYPE_PER_LIST;
+ break;
+ }
+ }
+
+ config->TxCfg[0].fNoSnoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
+ config->MaxTxDs = MAX_SKB_FRAGS;
+ config->TxFlow = TRUE;
+
+ /* Rx side parameters. */
+ config->RxRingNum = ring_num ? ring_num : 1;
+
+ if (ring_len[0]) {
+ int cnt;
+ for (cnt = 0; cnt < config->RxRingNum; cnt++) {
+ config->RxCfg[cnt].NumRxd = ring_len[cnt];
+ config->RxCfg[cnt].RingPriority = cnt;
+ }
+ } else {
+ int id;
+ if ((id = get_xena_rev_id(pdev)) == 1) {
+ config->RxCfg[0].NumRxd = LARGE_RXD_CNT;
+
+ } else {
+ config->RxCfg[0].NumRxd = SMALL_RXD_CNT;
+ }
+ config->RxCfg[0].RingPriority = 0;
+ }
+ config->RxCfg[0].RingOrg = RING_ORG_BUFF1;
+ config->RxCfg[0].RxdThresh = DEFAULT_RXD_THRESHOLD;
+ config->RxCfg[0].fNoSnoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
+ config->RxCfg[0].RxD_BackOff_Interval = TBD;
+ config->RxFlow = TRUE;
+
+ /* Miscellaneous parameters. */
+ config->RxVLANEnable = TRUE;
+ config->MTU = MAX_MTU_VLAN;
+ config->JumboEnable = FALSE;
+
+ /* Setting Mac Control parameters */
+ mac_control->txdl_len = MAX_SKB_FRAGS;
+ mac_control->rmac_pause_time = 0;
+
+ /* Initialize Ring buffer parameters. */
+ for (i = 0; i < config->RxRingNum; i++)
+ atomic_set(&sp->rx_bufs_left[i], 0);
+
+ /* initialize the shared memory used by the NIC and the host */
+ if (initSharedMem(sp)) {
+ DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
+ dev->name);
+ goto mem_alloc_failed;
+ }
+
+ sp->bar0 = (caddr_t) ioremap(pci_resource_start(pdev, 0),
+ pci_resource_len(pdev, 0));
+ if (!sp->bar0) {
+ DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
+ dev->name);
+ goto bar0_remap_failed;
+ }
+
+ sp->bar1 = (caddr_t) ioremap(pci_resource_start(pdev, 2),
+ pci_resource_len(pdev, 2));
+ if (!sp->bar1) {
+ DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
+ dev->name);
+ goto bar1_remap_failed;
+ }
+
+ dev->irq = pdev->irq;
+ dev->base_addr = (unsigned long) sp->bar0;
+
+ /* Initializing the BAR1 address as the start of the FIFO pointer. */
+ for (j = 0; j < MAX_TX_FIFOS; j++) {
+ mac_control->tx_FIFO_start[j] = (TxFIFO_element_t *)
+ (sp->bar1 + (j * 0x00020000));
+ }
+
+ /* Driver entry points */
+ dev->open = &s2io_open;
+ dev->stop = &s2io_close;
+ dev->hard_start_xmit = &s2io_xmit;
+ dev->get_stats = &s2io_get_stats;
+ dev->set_multicast_list = &s2io_set_multicast;
+ dev->do_ioctl = &s2io_ioctl;
+ dev->change_mtu = &s2io_change_mtu;
+ SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
+
+ /*
+ * will use eth_mac_addr() for dev->set_mac_address
+ * mac address will be set every time dev->open() is called
+ */
+#ifdef CONFIG_S2IO_NAPI
+ dev->poll = s2io_poll;
+ dev->weight = 128; /* For now. */
+#endif
+
+ dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
+ if (sp->high_dma_flag == TRUE)
+ dev->features |= NETIF_F_HIGHDMA;
+#ifdef NETIF_F_TSO
+ dev->features |= NETIF_F_TSO;
+#endif
+
+ dev->tx_timeout = &s2io_tx_watchdog;
+ dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
+ INIT_WORK(&sp->rst_timer_task,
+ (void (*)(void *)) s2io_restart_nic, dev);
+ INIT_WORK(&sp->set_link_task,
+ (void (*)(void *)) s2io_set_link, sp);
+
+ if (register_netdev(dev)) {
+ DBG_PRINT(ERR_DBG, "Device registration failed\n");
+ goto register_failed;
+ }
+
+ pci_save_state(sp->pdev, sp->config_space);
+
+ /* Setting swapper control on the NIC, for proper reset operation */
+ if (s2io_set_swapper(sp)) {
+ DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
+ dev->name);
+ goto set_swap_failed;
+ }
+
+ /* Fix for all "FFs" MAC address problems observed on Alpha platforms */
+ FixMacAddress(sp);
+ s2io_reset(sp);
+
+ /* Setting swapper control on the NIC, so the MAC address can be read.
+ */
+ if (s2io_set_swapper(sp)) {
+ DBG_PRINT(ERR_DBG,
+ "%s: S2IO: swapper settings are wrong\n",
+ dev->name);
+ goto set_swap_failed;
+ }
+
+ /* MAC address initialization.
+ * For now only one mac address will be read and used.
+ */
+ bar0 = (XENA_dev_config_t *) sp->bar0;
+ val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
+ RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
+ writeq(val64, &bar0->rmac_addr_cmd_mem);
+ waitForCmdComplete(sp);
+
+ tmp64 = readq(&bar0->rmac_addr_data0_mem);
+ mac_down = (u32) tmp64;
+ mac_up = (u32) (tmp64 >> 32);
+
+ memset(sp->defMacAddr[0].mac_addr, 0, sizeof(ETH_ALEN));
+
+ sp->defMacAddr[0].mac_addr[3] = (u8) (mac_up);
+ sp->defMacAddr[0].mac_addr[2] = (u8) (mac_up >> 8);
+ sp->defMacAddr[0].mac_addr[1] = (u8) (mac_up >> 16);
+ sp->defMacAddr[0].mac_addr[0] = (u8) (mac_up >> 24);
+ sp->defMacAddr[0].mac_addr[5] = (u8) (mac_down >> 16);
+ sp->defMacAddr[0].mac_addr[4] = (u8) (mac_down >> 24);
+
+ DBG_PRINT(INIT_DBG,
+ "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
+ sp->defMacAddr[0].mac_addr[0],
+ sp->defMacAddr[0].mac_addr[1],
+ sp->defMacAddr[0].mac_addr[2],
+ sp->defMacAddr[0].mac_addr[3],
+ sp->defMacAddr[0].mac_addr[4],
+ sp->defMacAddr[0].mac_addr[5]);
+
+ /* Set the factory defined MAC address initially */
+ dev->addr_len = ETH_ALEN;
+ memcpy(dev->dev_addr, sp->defMacAddr, ETH_ALEN);
+
+ /* Initialize the tasklet status flag */
+ atomic_set(&(sp->tasklet_status), 0);
+
+
+ /* Initialize spinlocks */
+ spin_lock_init(&sp->isr_lock);
+ spin_lock_init(&sp->tx_lock);
+
+ /* SXE-002: Configure link and activity LED to init state
+ * on driver load.
+ */
+ subid = sp->pdev->subsystem_device;
+ if ((subid & 0xFF) >= 0x07) {
+ val64 = readq(&bar0->gpio_control);
+ val64 |= 0x0000800000000000ULL;
+ writeq(val64, &bar0->gpio_control);
+ val64 = 0x0411040400000000ULL;
+ writeq(val64, (u64 *) ((u8 *) bar0 + 0x2700));
+ val64 = readq(&bar0->gpio_control);
+ }
+
+ /* Make Link state as off at this point, when the Link change
+ * interrupt comes the state will be automatically changed to
+ * the right state.
+ */
+ netif_carrier_off(dev);
+ sp->last_link_state = LINK_DOWN;
+
+ sp->rx_csum = 1; /* Rx chksum verify enabled by default */
+
+ return 0;
+
+ set_swap_failed:
+ unregister_netdev(dev);
+ register_failed:
+ iounmap(sp->bar1);
+ bar1_remap_failed:
+ iounmap(sp->bar0);
+ bar0_remap_failed:
+ mem_alloc_failed:
+ freeSharedMem(sp);
+ init_failed:
+ pci_disable_device(pdev);
+ pci_release_regions(pdev);
+ pci_set_drvdata(pdev, NULL);
+ free_netdev(dev);
+
+ return -ENODEV;
+}
+
+/*
+* Input Argument/s:
+* pdev - structure containing the PCI related information of the device.
+* Return value:
+* void
+* Description:
+* This function is called by the Pci subsystem to release a PCI device
+* and free up all resource held up by the device. This could be in response
+* to a Hot plug event or when the driver is to be removed from memory.
+*/
+static void __exit s2io_rem_nic(struct pci_dev *pdev)
+{
+ struct net_device *dev =
+ (struct net_device *) pci_get_drvdata(pdev);
+ nic_t *sp;
+
+ if (dev == NULL) {
+ DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
+ return;
+ }
+ sp = dev->priv;
+ freeSharedMem(sp);
+ iounmap(sp->bar0);
+ iounmap(sp->bar1);
+ pci_disable_device(pdev);
+ pci_release_regions(pdev);
+ pci_set_drvdata(pdev, NULL);
+
+ unregister_netdev(dev);
+
+ free_netdev(dev);
+}
+
+int __init s2io_starter(void)
+{
+ return pci_module_init(&s2io_driver);
+}
+
+void s2io_closer(void)
+{
+ pci_unregister_driver(&s2io_driver);
+ DBG_PRINT(INIT_DBG, "cleanup done\n");
+}
+
+module_init(s2io_starter);
+module_exit(s2io_closer);
diff -Nru a/drivers/net/s2io.h b/drivers/net/s2io.h
--- /dev/null Wed Dec 31 16:00:00 1969
+++ b/drivers/net/s2io.h Sun Apr 4 18:58:15 2004
@@ -0,0 +1,855 @@
+/************************************************************************
+ * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
+ * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
+
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ * Drivers based on or derived from this code fall under the GPL and must
+ * retain the authorship, copyright and license notice. This file is not
+ * a complete program and may only be used when the entire operating
+ * system is licensed under the GPL.
+ * See the file COPYING in this distribution for more information.
+ ************************************************************************/
+#ifndef _S2IO_H
+#define _S2IO_H
+
+#define TBD 0
+#define BIT(loc) (0x8000000000000000ULL >> (loc))
+#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
+
+#ifndef BOOL
+#define BOOL int
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#define FALSE 0
+#endif
+
+#undef SUCCESS
+#define SUCCESS 0
+#define FAILURE -1
+
+/* Maximum outstanding splits to be configured into xena. */
+typedef enum xena_max_outstanding_splits {
+ XENA_ONE_SPLIT_TRANSACTION = 0,
+ XENA_TWO_SPLIT_TRANSACTION = 1,
+ XENA_THREE_SPLIT_TRANSACTION = 2,
+ XENA_FOUR_SPLIT_TRANSACTION = 3,
+ XENA_EIGHT_SPLIT_TRANSACTION = 4,
+ XENA_TWELVE_SPLIT_TRANSACTION = 5,
+ XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
+ XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
+} xena_max_outstanding_splits;
+#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
+
+/* OS concerned variables and constants */
+#define WATCH_DOG_TIMEOUT 5*HZ
+#define EFILL 0x1234
+#define ALIGN_SIZE 127
+#define PCIX_COMMAND_REGISTER 0x62
+
+/*
+ * Debug related variables.
+ */
+#define DEBUG_ON TRUE
+
+/* different debug levels. */
+#define ERR_DBG 0
+#define INIT_DBG 1
+#define INFO_DBG 2
+#define TX_DBG 3
+#define INTR_DBG 4
+
+/* Global variable that defines the present debug level of the driver. */
+int debug_level = ERR_DBG; /* Default level. */
+
+/* DEBUG message print. */
+#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
+
+/* Protocol assist features of the NIC */
+#define L3_CKSUM_OK 0xFFFF
+#define L4_CKSUM_OK 0xFFFF
+#define S2IO_JUMBO_SIZE 9600
+
+/* The statistics block of Xena */
+typedef struct stat_block {
+#ifdef __BIG_ENDIAN
+/* Tx MAC statistics counters. */
+ u32 tmac_frms;
+ u32 tmac_data_octets;
+ u64 tmac_drop_frms;
+ u32 tmac_mcst_frms;
+ u32 tmac_bcst_frms;
+ u64 tmac_pause_ctrl_frms;
+ u32 tmac_ttl_octets;
+ u32 tmac_ucst_frms;
+ u32 tmac_nucst_frms;
+ u32 tmac_any_err_frms;
+ u64 tmac_ttl_less_fb_octets;
+ u64 tmac_vld_ip_octets;
+ u32 tmac_vld_ip;
+ u32 tmac_drop_ip;
+ u32 tmac_icmp;
+ u32 tmac_rst_tcp;
+ u64 tmac_tcp;
+ u32 tmac_udp;
+ u32 reserved_0;
+
+/* Rx MAC Statistics counters. */
+ u32 rmac_vld_frms;
+ u32 rmac_data_octets;
+ u64 rmac_fcs_err_frms;
+ u64 rmac_drop_frms;
+ u32 rmac_vld_mcst_frms;
+ u32 rmac_vld_bcst_frms;
+ u32 rmac_in_rng_len_err_frms;
+ u32 rmac_out_rng_len_err_frms;
+ u64 rmac_long_frms;
+ u64 rmac_pause_ctrl_frms;
+ u64 rmac_unsup_ctrl_frms;
+ u32 rmac_ttl_octets;
+ u32 rmac_accepted_ucst_frms;
+ u32 rmac_accepted_nucst_frms;
+ u32 rmac_discarded_frms;
+ u32 rmac_drop_events;
+ u32 reserved_1;
+ u64 rmac_ttl_less_fb_octets;
+ u64 rmac_ttl_frms;
+ u64 reserved_2;
+ u32 reserved_3;
+ u32 rmac_usized_frms;
+ u32 rmac_osized_frms;
+ u32 rmac_frag_frms;
+ u32 rmac_jabber_frms;
+ u32 reserved_4;
+ u64 rmac_ttl_64_frms;
+ u64 rmac_ttl_65_127_frms;
+ u64 reserved_5;
+ u64 rmac_ttl_128_255_frms;
+ u64 rmac_ttl_256_511_frms;
+ u64 reserved_6;
+ u64 rmac_ttl_512_1023_frms;
+ u64 rmac_ttl_1024_1518_frms;
+ u32 reserved_7;
+ u32 rmac_ip;
+ u64 rmac_ip_octets;
+ u32 rmac_hdr_err_ip;
+ u32 rmac_drop_ip;
+ u32 rmac_icmp;
+ u32 reserved_8;
+ u64 rmac_tcp;
+ u32 rmac_udp;
+ u32 rmac_err_drp_udp;
+ u64 rmac_xgmii_err_sym;
+ u64 rmac_frms_q0;
+ u64 rmac_frms_q1;
+ u64 rmac_frms_q2;
+ u64 rmac_frms_q3;
+ u64 rmac_frms_q4;
+ u64 rmac_frms_q5;
+ u64 rmac_frms_q6;
+ u64 rmac_frms_q7;
+ u16 rmac_full_q0;
+ u16 rmac_full_q1;
+ u16 rmac_full_q2;
+ u16 rmac_full_q3;
+ u16 rmac_full_q4;
+ u16 rmac_full_q5;
+ u16 rmac_full_q6;
+ u16 rmac_full_q7;
+ u32 rmac_pause_cnt;
+ u32 reserved_9;
+ u64 rmac_xgmii_data_err_cnt;
+ u64 rmac_xgmii_ctrl_err_cnt;
+ u32 rmac_accepted_ip;
+ u32 rmac_err_tcp;
+
+/* PCI/PCI-X Read transaction statistics. */
+ u32 rd_req_cnt;
+ u32 new_rd_req_cnt;
+ u32 new_rd_req_rtry_cnt;
+ u32 rd_rtry_cnt;
+ u32 wr_rtry_rd_ack_cnt;
+
+/* PCI/PCI-X write transaction statistics. */
+ u32 wr_req_cnt;
+ u32 new_wr_req_cnt;
+ u32 new_wr_req_rtry_cnt;
+ u32 wr_rtry_cnt;
+ u32 wr_disc_cnt;
+ u32 rd_rtry_wr_ack_cnt;
+
+/* DMA Transaction statistics. */
+ u32 txp_wr_cnt;
+ u32 txd_rd_cnt;
+ u32 txd_wr_cnt;
+ u32 rxd_rd_cnt;
+ u32 rxd_wr_cnt;
+ u32 txf_rd_cnt;
+ u32 rxf_wr_cnt;
+#else
+/* Tx MAC statistics counters. */
+ u32 tmac_data_octets;
+ u32 tmac_frms;
+ u64 tmac_drop_frms;
+ u32 tmac_bcst_frms;
+ u32 tmac_mcst_frms;
+ u64 tmac_pause_ctrl_frms;
+ u32 tmac_ucst_frms;
+ u32 tmac_ttl_octets;
+ u32 tmac_any_err_frms;
+ u32 tmac_nucst_frms;
+ u64 tmac_ttl_less_fb_octets;
+ u64 tmac_vld_ip_octets;
+ u32 tmac_drop_ip;
+ u32 tmac_vld_ip;
+ u32 tmac_rst_tcp;
+ u32 tmac_icmp;
+ u64 tmac_tcp;
+ u32 reserved_0;
+ u32 tmac_udp;
+
+/* Rx MAC Statistics counters. */
+ u32 rmac_data_octets;
+ u32 rmac_vld_frms;
+ u64 rmac_fcs_err_frms;
+ u64 rmac_drop_frms;
+ u32 rmac_vld_bcst_frms;
+ u32 rmac_vld_mcst_frms;
+ u32 rmac_out_rng_len_err_frms;
+ u32 rmac_in_rng_len_err_frms;
+ u64 rmac_long_frms;
+ u64 rmac_pause_ctrl_frms;
+ u64 rmac_unsup_ctrl_frms;
+ u32 rmac_accepted_ucst_frms;
+ u32 rmac_ttl_octets;
+ u32 rmac_discarded_frms;
+ u32 rmac_accepted_nucst_frms;
+ u32 reserved_1;
+ u32 rmac_drop_events;
+ u64 rmac_ttl_less_fb_octets;
+ u64 rmac_ttl_frms;
+ u64 reserved_2;
+ u32 rmac_usized_frms;
+ u32 reserved_3;
+ u32 rmac_frag_frms;
+ u32 rmac_osized_frms;
+ u32 reserved_4;
+ u32 rmac_jabber_frms;
+ u64 rmac_ttl_64_frms;
+ u64 rmac_ttl_65_127_frms;
+ u64 reserved_5;
+ u64 rmac_ttl_128_255_frms;
+ u64 rmac_ttl_256_511_frms;
+ u64 reserved_6;
+ u64 rmac_ttl_512_1023_frms;
+ u64 rmac_ttl_1024_1518_frms;
+ u32 rmac_ip;
+ u32 reserved_7;
+ u64 rmac_ip_octets;
+ u32 rmac_drop_ip;
+ u32 rmac_hdr_err_ip;
+ u32 reserved_8;
+ u32 rmac_icmp;
+ u64 rmac_tcp;
+ u32 rmac_err_drp_udp;
+ u32 rmac_udp;
+ u64 rmac_xgmii_err_sym;
+ u64 rmac_frms_q0;
+ u64 rmac_frms_q1;
+ u64 rmac_frms_q2;
+ u64 rmac_frms_q3;
+ u64 rmac_frms_q4;
+ u64 rmac_frms_q5;
+ u64 rmac_frms_q6;
+ u64 rmac_frms_q7;
+ u16 rmac_full_q3;
+ u16 rmac_full_q2;
+ u16 rmac_full_q1;
+ u16 rmac_full_q0;
+ u16 rmac_full_q7;
+ u16 rmac_full_q6;
+ u16 rmac_full_q5;
+ u16 rmac_full_q4;
+ u32 reserved_9;
+ u32 rmac_pause_cnt;
+ u64 rmac_xgmii_data_err_cnt;
+ u64 rmac_xgmii_ctrl_err_cnt;
+ u32 rmac_err_tcp;
+ u32 rmac_accepted_ip;
+
+/* PCI/PCI-X Read transaction statistics. */
+ u32 new_rd_req_cnt;
+ u32 rd_req_cnt;
+ u32 rd_rtry_cnt;
+ u32 new_rd_req_rtry_cnt;
+
+/* PCI/PCI-X Write/Read transaction statistics. */
+ u32 wr_req_cnt;
+ u32 wr_rtry_rd_ack_cnt;
+ u32 new_wr_req_rtry_cnt;
+ u32 new_wr_req_cnt;
+ u32 wr_disc_cnt;
+ u32 wr_rtry_cnt;
+
+/* PCI/PCI-X Write / DMA Transaction statistics. */
+ u32 txp_wr_cnt;
+ u32 rd_rtry_wr_ack_cnt;
+ u32 txd_wr_cnt;
+ u32 txd_rd_cnt;
+ u32 rxd_wr_cnt;
+ u32 rxd_rd_cnt;
+ u32 rxf_wr_cnt;
+ u32 txf_rd_cnt;
+#endif
+} StatInfo_t;
+
+/* Structures representing different init time configuration
+ * parameters of the NIC.
+ */
+
+/* Maintains Per FIFO related information. */
+typedef struct tx_fifo_config {
+#define MAX_AVAILABLE_TXDS 8192
+ u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */
+/* Priority definition */
+#define TX_FIFO_PRI_0 0 /*Highest */
+#define TX_FIFO_PRI_1 1
+#define TX_FIFO_PRI_2 2
+#define TX_FIFO_PRI_3 3
+#define TX_FIFO_PRI_4 4
+#define TX_FIFO_PRI_5 5
+#define TX_FIFO_PRI_6 6
+#define TX_FIFO_PRI_7 7 /*lowest */
+ u8 FifoPriority; /* specifies pointer level for FIFO */
+ /* user should not set twos fifos with same pri */
+ u8 fNoSnoop;
+#define NO_SNOOP_TXD 0x01
+#define NO_SNOOP_TXD_BUFFER 0x02
+} tx_fifo_config_t;
+
+
+/* Maintains per Ring related information */
+typedef struct rx_ring_config {
+ u32 NumRxd; /*No of RxDs per Rx Ring */
+#define RX_RING_PRI_0 0 /* highest */
+#define RX_RING_PRI_1 1
+#define RX_RING_PRI_2 2
+#define RX_RING_PRI_3 3
+#define RX_RING_PRI_4 4
+#define RX_RING_PRI_5 5
+#define RX_RING_PRI_6 6
+#define RX_RING_PRI_7 7 /* lowest */
+
+ u8 RingPriority; /*Specifies service priority of ring */
+ /* OSM should not set any two rings with same priority */
+ u8 RingOrg; /*Organization of ring */
+#define RING_ORG_BUFF1 0x01
+#define RX_RING_ORG_BUFF3 0x03
+#define RX_RING_ORG_BUFF5 0x05
+
+/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
+#define BUFF_SZ_1 22 /* ethernet header */
+#define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
+#define BUFF_SZ_3 (1500-20-20) /* TCP payload */
+#define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
+
+ u32 RxdThresh; /*No of used Rxds NIC can store before transfer to host */
+#define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
+ u8 fNoSnoop;
+#define NO_SNOOP_RXD 0x01
+#define NO_SNOOP_RXD_BUFFER 0x02
+ u32 RxD_BackOff_Interval;
+#define RXD_BACKOFF_INTERVAL_DEF 0x0
+#define RXD_BACKOFF_INTERVAL_MIN 0x0
+#define RXD_BACKOFF_INTERVAL_MAX 0x0
+} rx_ring_config_t;
+
+/* This structure provides contains values of the tunable parameters
+ * of the H/W
+ */
+struct config_param {
+
+/* Tx Side */
+ u32 TxFIFONum; /*Number of Tx FIFOs */
+#define MAX_TX_FIFOS 8
+
+ tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
+ u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
+ BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
+#define TX_REQ_TIMEOUT_DEFAULT 0x0
+#define TX_REQ_TIMEOUT_MIN 0x0
+#define TX_REQ_TIMEOUT_MAX 0x0
+ u32 TxReqTimeOut;
+ BOOL TxFlow; /*Tx flow control enable */
+ BOOL RxFlow;
+ BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
+ Use the new priority information
+ of service state. It is not recommended
+ to change but OSM can opt to do so */
+#define MAX_SERVICE_STATES 36
+ u8 TxServiceState[MAX_SERVICE_STATES];
+ /* Array element represent 'priority'
+ * and array index represents
+ * 'Service state' e.g.
+ * TxServiceState[3]=7; it means
+ * Service state 3 is associated
+ * with priority 7 of a Tx FIFO */
+ u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
+
+/* Rx Side */
+ u32 RxRingNum; /*Number of receive rings */
+#define MAX_RX_RINGS 8
+#define MAX_RX_BLOCKS_PER_RING 150
+
+ rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
+ BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
+ FALSE: Don't strip off VLAN tag */
+
+#define HEADER_ETHERNET_II_802_3_SIZE 14
+#define HEADER_802_2_SIZE 3
+#define HEADER_SNAP_SIZE 5
+#define HEADER_VLAN_SIZE 4
+#define HEADER_ALIGN_LAYER_3 2
+
+#define MIN_MTU 46
+#define MAX_PYLD 1500
+#define MAX_MTU (MAX_PYLD+18)
+#define MAX_MTU_VLAN (MAX_PYLD+22)
+#define MAX_PYLD_JUMBO 9600
+#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
+#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
+ u32 MTU; /*Maximum Payload */
+ BOOL JumboEnable; /*Enable Jumbo frames recv/send */
+ BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
+ Use the new priority information
+ of service state. It is not recommended
+ to change but OSM can opt to do so */
+#define MAX_SERVICE_STATES 36
+ u8 RxServiceState[MAX_SERVICE_STATES];
+ /* Array element represent 'priority'
+ * and array index represents
+ * 'Service state'e.g.
+ * RxServiceState[3]=7; it means
+ * Service state 3 is associated
+ * with priority 7 of a Rx FIFO */
+ BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
+ u32 StatRefreshTime; /*Time for refreshing statistics */
+#define STAT_TRSF_PER_1_SECOND 0x208D5
+};
+
+/* Structure representing MAC Addrs */
+typedef struct mac_addr {
+ u8 mac_addr[ETH_ALEN];
+} macaddr_t;
+
+/* Structure that represent every FIFO element in the BAR1
+ * Address location.
+ */
+typedef struct _TxFIFO_element {
+ u64 TxDL_Pointer;
+
+ u64 List_Control;
+#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
+#define TX_FIFO_FIRST_LIST BIT(14)
+#define TX_FIFO_LAST_LIST BIT(15)
+#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
+#define TX_FIFO_SPECIAL_FUNC BIT(23)
+#define TX_FIFO_DS_NO_SNOOP BIT(31)
+#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
+} TxFIFO_element_t;
+
+/* Tx descriptor structure */
+typedef struct _TxD {
+ u64 Control_1;
+/* bit mask */
+#define TXD_LIST_OWN_XENA BIT(7)
+#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
+#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
+#define TXD_GATHER_CODE (BIT(22) | BIT(23))
+#define TXD_GATHER_CODE_FIRST BIT(22)
+#define TXD_GATHER_CODE_LAST BIT(23)
+#define TXD_TCP_LSO_EN BIT(30)
+#define TXD_UDP_COF_EN BIT(31)
+#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
+#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
+
+ u64 Control_2;
+#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
+#define TXD_TX_CKO_IPV4_EN BIT(5)
+#define TXD_TX_CKO_TCP_EN BIT(6)
+#define TXD_TX_CKO_UDP_EN BIT(7)
+#define TXD_VLAN_ENABLE BIT(15)
+#define TXD_VLAN_TAG(val) vBIT(val,16,16)
+#define TXD_INT_NUMBER(val) vBIT(val,34,6)
+#define TXD_INT_TYPE_PER_LIST BIT(47)
+#define TXD_INT_TYPE_UTILZ BIT(46)
+#define TXD_SET_MARKER vBIT(0x6,0,4)
+
+ u64 Buffer_Pointer;
+ u64 Host_Control; /* reserved for host */
+} TxD_t;
+
+/* Rx descriptor structure */
+typedef struct _RxD_t {
+ u64 Host_Control; /* reserved for host */
+ u64 Control_1;
+#define RXD_OWN_XENA BIT(7)
+#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
+#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
+#define RXD_FRAME_PROTO_IPV4 BIT(27)
+#define RXD_FRAME_PROTO_IPV6 BIT(28)
+#define RXD_FRAME_PROTO_TCP BIT(30)
+#define RXD_FRAME_PROTO_UDP BIT(31)
+#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
+#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
+#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
+
+ u64 Control_2;
+#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
+#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
+#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
+#define SET_VLAN_TAG(val) vBIT(val,48,16)
+#define SET_NUM_TAG(val) vBIT(val,16,32)
+
+#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
+/*
+#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
+#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
+*/
+ u64 Buffer0_ptr;
+} RxD_t;
+
+
+/* Structure that represents the Rx descriptor block which contains
+ * 128 Rx descriptors.
+ */
+typedef struct _RxD_block {
+#define MAX_RXDS_PER_BLOCK 127
+ RxD_t rxd[MAX_RXDS_PER_BLOCK];
+
+ u64 reserved_0;
+#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
+ u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
+ u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
+ u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
+ In a 32 bit arch the upper 32 bits
+ should be 0 */
+} RxD_block_t;
+
+/* Structure which stores all the MAC control parameters */
+
+/* This structure stores the offset of the RxD in the ring
+ * from which the Rx Interrupt processor can start picking
+ * up the RxDs for processing.
+ */
+typedef struct _rx_curr_get_info_t {
+ u32 block_index;
+ u32 offset;
+ u32 ring_len;
+} rx_curr_get_info_t;
+
+typedef rx_curr_get_info_t rx_curr_put_info_t;
+
+/* This structure stores the offset of the TxDl in the FIFO
+ * from which the Tx Interrupt processor can start picking
+ * up the TxDLs for send complete interrupt processing.
+ */
+typedef struct {
+ u32 offset;
+ u32 fifo_len;
+} tx_curr_get_info_t;
+
+typedef tx_curr_get_info_t tx_curr_put_info_t;
+
+/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
+ * is maintained in this structure.
+ */
+typedef struct mac_info {
+/* rx side stuff */
+ u32 rxd_ring_mem_sz;
+ RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
+ dma_addr_t RxRing_Phy[MAX_RX_RINGS];
+
+ /* Put pointer info which indictes which RxD has to be replenished
+ * with a new buffer.
+ */
+ rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
+
+ /* Get pointer info which indictes which is the last RxD that was
+ * processed by the driver.
+ */
+ rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
+
+ u16 rmac_pause_time;
+
+ /* this will be used in receive function, this decides which ring would
+ be processed first. eg: ring with priority value 0 (highest) should
+ be processed first.
+ first 3 LSB bits represent ring number which should be processed
+ first, similarly next 3 bits represent next ring to be processed.
+ eg: value of _rx_ring_pri_map = 0x0000 003A means
+ ring #2 would be processed first and #7 would be processed next
+ */
+ u32 _rx_ring_pri_map;
+
+/* tx side stuff */
+ void *txd_list_mem; /* orignal pointer to allocated mem */
+ dma_addr_t txd_list_mem_phy;
+ u32 txd_list_mem_sz;
+
+ /* logical pointer of start of each Tx FIFO */
+ TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
+
+ /* logical pointer of start of TxDL which corresponds to each Tx FIFO */
+ TxD_t *txdl_start[MAX_TX_FIFOS];
+
+ /* Same as txdl_start but phy addr */
+ dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
+
+/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
+ tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
+ tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
+
+ u16 txdl_len; /* length of a TxDL, same for all */
+
+ void *stats_mem; /* orignal pointer to allocated mem */
+ dma_addr_t stats_mem_phy; /* Physical address of the stat block */
+ u32 stats_mem_sz;
+ StatInfo_t *StatsInfo; /* Logical address of the stat block */
+} mac_info_t;
+
+/* structure representing the user defined MAC addresses */
+typedef struct {
+ char addr[ETH_ALEN];
+ int usage_cnt;
+} usr_addr_t;
+
+/* Structure that holds the Phy and virt addresses of the Blocks */
+typedef struct rx_block_info {
+ RxD_t *block_virt_addr;
+ dma_addr_t block_dma_addr;
+} rx_block_info_t;
+
+/* Structure representing one instance of the NIC */
+typedef struct s2io_nic {
+#define MAX_MAC_SUPPORTED 16
+#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
+
+ macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
+ macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
+
+ struct net_device_stats stats;
+ caddr_t bar0;
+ caddr_t bar1;
+ struct config_param config;
+ mac_info_t mac_control;
+ int high_dma_flag;
+ int device_close_flag;
+ int device_enabled_once;
+
+ char name[32];
+ struct tasklet_struct task;
+ atomic_t tasklet_status;
+ struct timer_list timer;
+ struct net_device *dev;
+ struct pci_dev *pdev;
+
+ u16 vendor_id;
+ u16 device_id;
+ u16 ccmd;
+ u32 cbar0_1;
+ u32 cbar0_2;
+ u32 cbar1_1;
+ u32 cbar1_2;
+ u32 cirq;
+ u8 cache_line;
+ u32 rom_expansion;
+ u16 pcix_cmd;
+ u32 config_space[256 / sizeof(u32)];
+ u32 irq;
+ atomic_t rx_bufs_left[MAX_RX_RINGS];
+
+ spinlock_t isr_lock;
+ spinlock_t tx_lock;
+
+#define PROMISC 1
+#define ALL_MULTI 2
+
+#define MAX_ADDRS_SUPPORTED 64
+ u16 usr_addr_count;
+ u16 mc_addr_count;
+ usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
+
+ u16 m_cast_flg;
+ u16 all_multi_pos;
+ u16 promisc_flg;
+
+ u16 tx_pkt_count;
+ u16 rx_pkt_count;
+ u16 tx_err_count;
+ u16 rx_err_count;
+
+#if DEBUG_ON
+ u64 rxpkt_bytes;
+ u64 txpkt_bytes;
+ int int_cnt;
+ int rxint_cnt;
+ int txint_cnt;
+ u64 rxpkt_cnt;
+#endif
+
+ /* Place holders for the virtual and physical addresses of
+ * all the Rx Blocks
+ */
+ struct rx_block_info
+ rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
+ int block_count[MAX_RX_RINGS];
+ int pkt_cnt[MAX_RX_RINGS];
+
+ /* Id timer, used to blink NIC to physically identify NIC. */
+ struct timer_list id_timer;
+
+ /* Restart timer, used to restart NIC if the device is stuck and
+ * a schedule task that will set the correct Link state once the
+ * NIC's PHY has stabilized after a state change.
+ */
+#ifdef INIT_TQUEUE
+ struct tq_struct rst_timer_task;
+ struct tq_struct set_link_task;
+#else
+ struct work_struct rst_timer_task;
+ struct work_struct set_link_task;
+#endif
+
+ /* Flag that can be used to turn on or turn off the Rx checksum
+ * offload feature.
+ */
+ int rx_csum;
+
+ /* after blink, the adapter must be restored with original
+ * values.
+ */
+ u64 adapt_ctrl_org;
+
+ /* Last known link state. */
+ u16 last_link_state;
+#define LINK_DOWN 1
+#define LINK_UP 2
+} nic_t;
+
+#define RESET_ERROR 1;
+#define CMD_ERROR 2;
+
+/* Default Tunable parameters of the NIC. */
+#define DEFAULT_FIFO_LEN 4096
+#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
+#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
+
+/* OS related system calls */
+#ifndef readq
+static inline u64 readq(void *addr)
+{
+ u64 ret = 0;
+ ret = readl(addr + 4);
+ (u64) ret <<= 32;
+ (u64) ret |= readl(addr);
+
+ return ret;
+}
+#endif
+
+#ifndef writeq
+static inline void writeq(u64 val, void *addr)
+{
+ writel((u32) (val), addr);
+ writel((u32) (val >> 32), (addr + 4));
+}
+#endif
+
+/* Interrupt related values of Xena */
+
+#define ENABLE_INTRS 1
+#define DISABLE_INTRS 2
+
+/* Highest level interrupt blocks */
+#define TX_PIC_INTR (0x0001<<0)
+#define TX_DMA_INTR (0x0001<<1)
+#define TX_MAC_INTR (0x0001<<2)
+#define TX_XGXS_INTR (0x0001<<3)
+#define TX_TRAFFIC_INTR (0x0001<<4)
+#define RX_PIC_INTR (0x0001<<5)
+#define RX_DMA_INTR (0x0001<<6)
+#define RX_MAC_INTR (0x0001<<7)
+#define RX_XGXS_INTR (0x0001<<8)
+#define RX_TRAFFIC_INTR (0x0001<<9)
+#define MC_INTR (0x0001<<10)
+#define ENA_ALL_INTRS ( TX_PIC_INTR | \
+ TX_DMA_INTR | \
+ TX_MAC_INTR | \
+ TX_XGXS_INTR | \
+ TX_TRAFFIC_INTR | \
+ RX_PIC_INTR | \
+ RX_DMA_INTR | \
+ RX_MAC_INTR | \
+ RX_XGXS_INTR | \
+ RX_TRAFFIC_INTR | \
+ MC_INTR )
+
+/* Interrupt masks for the general interrupt mask register */
+#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
+
+#define TXPIC_INT_M BIT(0)
+#define TXDMA_INT_M BIT(1)
+#define TXMAC_INT_M BIT(2)
+#define TXXGXS_INT_M BIT(3)
+#define TXTRAFFIC_INT_M BIT(8)
+#define PIC_RX_INT_M BIT(32)
+#define RXDMA_INT_M BIT(33)
+#define RXMAC_INT_M BIT(34)
+#define MC_INT_M BIT(35)
+#define RXXGXS_INT_M BIT(36)
+#define RXTRAFFIC_INT_M BIT(40)
+
+/* PIC level Interrupts TODO*/
+
+/* DMA level Inressupts */
+#define TXDMA_PFC_INT_M BIT(0)
+ /* PFC block interrupts */
+#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
+
+/*
+ * Prototype declaration.
+ */
+static int __devinit s2io_init_nic(struct pci_dev *pdev,
+ const struct pci_device_id *pre);
+static void __exit s2io_rem_nic(struct pci_dev *pdev);
+static int initSharedMem(struct s2io_nic *sp);
+static void freeSharedMem(struct s2io_nic *sp);
+static int initNic(struct s2io_nic *nic);
+#ifndef CONFIG_S2IO_NAPI
+static void rxIntrHandler(struct s2io_nic *sp);
+#endif
+static void txIntrHandler(struct s2io_nic *sp);
+static void alarmIntrHandler(struct s2io_nic *sp);
+
+static int s2io_starter(void);
+void s2io_closer(void);
+static void s2io_tx_watchdog(struct net_device *dev);
+static void s2io_tasklet(unsigned long dev_addr);
+static void s2io_set_multicast(struct net_device *dev);
+static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
+void s2io_link(nic_t * sp, int link);
+void s2io_reset(nic_t * sp);
+#ifdef CONFIG_S2IO_NAPI
+static int s2io_poll(struct net_device *dev, int *budget);
+#endif
+static void s2io_init_pci(nic_t * sp);
+int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
+static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
+static int verify_xena_quiescence(u64 val64, int flag);
+static struct ethtool_ops netdev_ethtool_ops;
+
+#endif /* _S2IO_H */
diff -Nru a/drivers/net/tc35815.c b/drivers/net/tc35815.c
--- a/drivers/net/tc35815.c Sun Apr 4 18:58:15 2004
+++ b/drivers/net/tc35815.c Sun Apr 4 18:58:15 2004
@@ -1724,12 +1724,7 @@
static int __init tc35815_init_module(void)
{
- int err;
-
- if ((err = pci_module_init(&tc35815_driver)) < 0 )
- return err;
- else
- return 0;
+ return pci_module_init(&tc35815_driver);
}
static void __exit tc35815_cleanup_module(void)
diff -Nru a/include/linux/netdevice.h b/include/linux/netdevice.h
--- a/include/linux/netdevice.h Sun Apr 4 18:58:15 2004
+++ b/include/linux/netdevice.h Sun Apr 4 18:58:15 2004
@@ -42,13 +42,14 @@
struct vlan_group;
struct ethtool_ops;
- /* source back-compat hook */
+ /* source back-compat hooks */
#define SET_ETHTOOL_OPS(netdev,ops) \
( (netdev)->ethtool_ops = (ops) )
#define HAVE_ALLOC_NETDEV /* feature macro: alloc_xxxdev
functions are available. */
-#define HAVE_FREE_NETDEV
+#define HAVE_FREE_NETDEV /* free_netdev() */
+#define HAVE_NETDEV_PRIV /* netdev_priv() */
#define NET_XMIT_SUCCESS 0
#define NET_XMIT_DROP 1 /* skb dropped */
diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h
--- a/include/linux/pci_ids.h Sun Apr 4 18:58:15 2004
+++ b/include/linux/pci_ids.h Sun Apr 4 18:58:15 2004
@@ -1871,6 +1871,10 @@
#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea
#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb
+#define PCI_VENDOR_ID_S2IO 0x17d5
+#define PCI_DEVICE_ID_S2IO_WIN 0x5731
+#define PCI_DEVICE_ID_S2IO_UNI 0x5831
+
#define PCI_VENDOR_ID_SYMPHONY 0x1c1c
#define PCI_DEVICE_ID_SYMPHONY_101 0x0001