From: Jeff Garzik I've been slowly brewing support for the on-CPU crypto stuff in VIA's new CPUs. In addition to the on-chip RNG, they have on-chip AES, and will soon have on-chip SHA1. (this is public info) The attached patch is the first step, the basic CPU setup support. Next step is crypto/ support for AES. After that, Joseph says new chips have two RNGs (?), which I need to look into. * Enable ACE (crypto) and RNG units on bootup. * Do not disable RNG unit when unloading hw_random module. * New bits listed in /proc/cpuinfo: rng_en, ace, ace_en * Add ACE-associated constants to cpufeature.h --- 25-akpm/arch/i386/kernel/cpu/centaur.c | 28 +++++++++++++++++++++++++++- 25-akpm/arch/i386/kernel/cpu/proc.c | 2 +- 25-akpm/drivers/char/hw_random.c | 6 +----- 25-akpm/include/asm-i386/cpufeature.h | 4 ++++ 4 files changed, 33 insertions(+), 7 deletions(-) diff -puN arch/i386/kernel/cpu/centaur.c~centaur-crypto-core-support arch/i386/kernel/cpu/centaur.c --- 25/arch/i386/kernel/cpu/centaur.c~centaur-crypto-core-support Tue Feb 3 13:21:05 2004 +++ 25-akpm/arch/i386/kernel/cpu/centaur.c Tue Feb 3 13:21:05 2004 @@ -246,7 +246,15 @@ static void __init winchip2_protect_mcr( lo&=~0x1C0; /* blank bits 8-6 */ wrmsr(MSR_IDT_MCR_CTRL, lo, hi); } -#endif +#endif /* CONFIG_X86_OOSTORE */ + +#define ACE_PRESENT (1 << 6) +#define ACE_ENABLED (1 << 7) +#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ + +#define RNG_PRESENT (1 << 2) +#define RNG_ENABLED (1 << 3) +#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ static void __init init_c3(struct cpuinfo_x86 *c) { @@ -254,6 +262,24 @@ static void __init init_c3(struct cpuinf /* Test for Centaur Extended Feature Flags presence */ if (cpuid_eax(0xC0000000) >= 0xC0000001) { + u32 tmp = cpuid_edx(0xC0000001); + + /* enable ACE unit, if present and disabled */ + if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) { + rdmsr (MSR_VIA_FCR, lo, hi); + lo |= ACE_FCR; /* enable ACE unit */ + wrmsr (MSR_VIA_FCR, lo, hi); + printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n"); + } + + /* enable RNG unit, if present and disabled */ + if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) { + rdmsr (MSR_VIA_RNG, lo, hi); + lo |= RNG_ENABLE; /* enable RNG unit */ + wrmsr (MSR_VIA_RNG, lo, hi); + printk(KERN_INFO "CPU: Enabled h/w RNG\n"); + } + /* store Centaur Extended Feature Flags as * word 5 of the CPU capability bit array */ diff -puN arch/i386/kernel/cpu/proc.c~centaur-crypto-core-support arch/i386/kernel/cpu/proc.c --- 25/arch/i386/kernel/cpu/proc.c~centaur-crypto-core-support Tue Feb 3 13:21:05 2004 +++ 25-akpm/arch/i386/kernel/cpu/proc.c Tue Feb 3 13:21:05 2004 @@ -50,7 +50,7 @@ static int show_cpuinfo(struct seq_file NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* VIA/Cyrix/Centaur-defined */ - NULL, NULL, "xstore", NULL, NULL, NULL, NULL, NULL, + NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff -puN drivers/char/hw_random.c~centaur-crypto-core-support drivers/char/hw_random.c --- 25/drivers/char/hw_random.c~centaur-crypto-core-support Tue Feb 3 13:21:05 2004 +++ 25-akpm/drivers/char/hw_random.c Tue Feb 3 13:21:05 2004 @@ -454,11 +454,7 @@ static int __init via_init(struct pci_de static void via_cleanup(void) { - u32 lo, hi; - - rdmsr(MSR_VIA_RNG, lo, hi); - lo &= ~VIA_RNG_ENABLE; - wrmsr(MSR_VIA_RNG, lo, hi); + /* do nothing */ } diff -puN include/asm-i386/cpufeature.h~centaur-crypto-core-support include/asm-i386/cpufeature.h --- 25/include/asm-i386/cpufeature.h~centaur-crypto-core-support Tue Feb 3 13:21:05 2004 +++ 25-akpm/include/asm-i386/cpufeature.h Tue Feb 3 13:21:05 2004 @@ -76,6 +76,9 @@ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ +#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ +#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ +#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) @@ -101,6 +104,7 @@ #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) +#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) #endif /* __ASM_I386_CPUFEATURE_H */ _