From: Adam Kropelin PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin Cc: Cc: Greg KH Signed-off-by: Andrew Morton --- drivers/pci/hotplug/pciehp_ctrl.c | 4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) diff -puN drivers/pci/hotplug/pciehp_ctrl.c~pciehp-use-dword-accessors-for-pci_rom_address drivers/pci/hotplug/pciehp_ctrl.c --- devel/drivers/pci/hotplug/pciehp_ctrl.c~pciehp-use-dword-accessors-for-pci_rom_address 2005-09-14 01:20:45.000000000 -0700 +++ devel-akpm/drivers/pci/hotplug/pciehp_ctrl.c 2005-09-14 01:20:45.000000000 -0700 @@ -2526,7 +2526,6 @@ configure_new_function(struct controller int cloop; u8 temp_byte; u8 class_code; - u16 temp_word; u32 rc; u32 temp_register; u32 base; @@ -2682,8 +2681,7 @@ configure_new_function(struct controller } /* End of base register loop */ /* disable ROM base Address */ - temp_word = 0x00L; - rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word); + rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00); /* Set HP parameters (Cache Line Size, Latency Timer) */ rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL); _