From: Eric Dumazet This is a multi-part message in MIME format. If the cpu lacks 3DNOW feature, we can use a normal prefetcht0 instruction instead of NOP5. "prefetchw (%rxx)" and "prefetcht0 (%rxx)" have the same length, ranging from 3 to 5 bytes depending on the register. So this patch even helps AMD64, shortening the length of the code. Signed-off-by: Eric Dumazet Cc: Andi Kleen Signed-off-by: Andrew Morton --- include/asm-x86_64/processor.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) diff -puN include/asm-x86_64/processor.h~x86_64-prefetchw-can-fall-back-to-prefetch-if-3dnow include/asm-x86_64/processor.h --- devel/include/asm-x86_64/processor.h~x86_64-prefetchw-can-fall-back-to-prefetch-if-3dnow 2005-07-30 00:44:02.000000000 -0700 +++ devel-akpm/include/asm-x86_64/processor.h 2005-07-30 00:44:02.000000000 -0700 @@ -398,7 +398,7 @@ static inline void prefetch(void *x) #define ARCH_HAS_PREFETCHW 1 static inline void prefetchw(void *x) { - alternative_input(ASM_NOP5, + alternative_input("prefetcht0 (%1)", "prefetchw (%1)", X86_FEATURE_3DNOW, "r" (x)); _