From: Matt Porter <mporter@kernel.crashing.org>

Adds the appropriate cputable entry for PPC440SP so cache line sizes are
configured correctly.

Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---

 arch/ppc/kernel/cputable.c |   10 ++++++++++
 1 files changed, 10 insertions(+)

diff -puN arch/ppc/kernel/cputable.c~ppc32-add-cputable-entry-for-440sp-rev-a arch/ppc/kernel/cputable.c
--- devel/arch/ppc/kernel/cputable.c~ppc32-add-cputable-entry-for-440sp-rev-a	2005-08-17 21:30:39.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/cputable.c	2005-08-17 21:30:39.000000000 -0700
@@ -922,6 +922,16 @@ struct cpu_spec	cpu_specs[] = {
 		.icache_bsize		= 32,
 		.dcache_bsize		= 32,
 	},
+	{ /* 440SP Rev. A */
+		.pvr_mask		= 0xff000fff,
+		.pvr_value		= 0x53000891,
+		.cpu_name		= "440SP Rev. A",
+		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |
+			CPU_FTR_USE_TB,
+		.cpu_user_features	= PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+	},
 #endif /* CONFIG_44x */
 #ifdef CONFIG_FSL_BOOKE
 	{ 	/* e200z5 */
_