From: Jeff Garzik Silicon Image contributed a patch which should help some of the situations that users were seeing. If you are having problems with sata_sil, please do try out this patch. I'm concerned that the sata_sil blacklist has been growing beyond the older Seagate drives which definitely had buggy firmware; concerned that the Mod15Write fix was simply "fixing" the problem addressed by this patch, simply by hiding the problem behind slow performance. [note: the only way to really know for sure is with ATA bus traces] On platforms where the SiI BIOS isn't executed (non-x86), this patch is probably more critical. On x86, it is purported to only be needed on a single motherboard. Test results (to linux-ide@vger.kernel.org) would be appreciated, particularly from users with newer Seagate drives. Finally, there are also a few reports of problems of "screaming interrupts" on configurations with SiI 311x + Seagate NCQ drives. This is a separate problem, and I haven't looked into it yet. Signed-off-by: Silicon Image Corporation Signed-off-by: Jeff Garzik Signed-off-by: Andrew Morton --- 25-akpm/drivers/scsi/sata_sil.c | 28 +++++++++++++++++++++++++++- 1 files changed, 27 insertions(+), 1 deletion(-) diff -puN drivers/scsi/sata_sil.c~sata_sil-corruption--lockup-fix drivers/scsi/sata_sil.c --- 25/drivers/scsi/sata_sil.c~sata_sil-corruption--lockup-fix 2005-03-24 23:27:49.000000000 -0800 +++ 25-akpm/drivers/scsi/sata_sil.c 2005-03-24 23:27:49.000000000 -0800 @@ -38,12 +38,21 @@ #include #define DRV_NAME "sata_sil" -#define DRV_VERSION "0.8" +#define DRV_VERSION "0.9" enum { sil_3112 = 0, sil_3114 = 1, + SIL_FIFO_R0 = 0x40, + SIL_FIFO_W0 = 0x41, + SIL_FIFO_R1 = 0x44, + SIL_FIFO_W1 = 0x45, + SIL_FIFO_R2 = 0x240, + SIL_FIFO_W2 = 0x241, + SIL_FIFO_R3 = 0x244, + SIL_FIFO_W3 = 0x245, + SIL_SYSCFG = 0x48, SIL_MASK_IDE0_INT = (1 << 22), SIL_MASK_IDE1_INT = (1 << 23), @@ -199,6 +208,13 @@ MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, sil_pci_tbl); MODULE_VERSION(DRV_VERSION); +static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) +{ + u8 cache_line = 0; + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); + return cache_line; +} + static void sil_post_set_mode (struct ata_port *ap) { struct ata_host_set *host_set = ap->host_set; @@ -341,6 +357,7 @@ static int sil_init_one (struct pci_dev unsigned int i; int pci_dev_busy = 0; u32 tmp, irq_mask; + u8 cls; if (!printed_version++) printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); @@ -405,6 +422,15 @@ static int sil_init_one (struct pci_dev ata_std_ports(&probe_ent->port[i]); } + /* Initialize FIFO PCI bus arbitration */ + cls = sil_get_device_cache_line(pdev); + cls >>= 3; + cls++; /* cls = (line_size/8)+1 */ + writeb(cls, mmio_base + SIL_FIFO_R0); + writeb(cls, mmio_base + SIL_FIFO_W0); + writeb(cls, mmio_base + SIL_FIFO_R1); + writeb(cls, mmio_base + SIL_FIFO_W2); + if (ent->driver_data == sil_3114) { irq_mask = SIL_MASK_4PORT; _