From: "Mark A. Greer" The 8241/8245 have an erratum where PCI reads from local memory may return stale data. One of the two workarounds is to set PICR2[0]. This patch does that. Signed-off-by: Mark A. Greer Signed-off-by: Andrew Morton --- 25-akpm/arch/ppc/syslib/mpc10x_common.c | 18 ++++++++++++++++++ 25-akpm/include/asm-ppc/mpc10x.h | 3 +++ 2 files changed, 21 insertions(+) diff -puN arch/ppc/syslib/mpc10x_common.c~ppc32-mpc8245-erratum-28-workaround arch/ppc/syslib/mpc10x_common.c --- 25/arch/ppc/syslib/mpc10x_common.c~ppc32-mpc8245-erratum-28-workaround 2005-01-28 14:34:20.228648536 -0800 +++ 25-akpm/arch/ppc/syslib/mpc10x_common.c 2005-01-28 14:34:20.234647624 -0800 @@ -323,6 +323,24 @@ mpc10x_bridge_init(struct pci_controller MPC10X_CFG_PICR1_REG, picr1); } + /* + * 8241/8245 erratum 28: PCI reads from local memory may return + * stale data. Workaround by setting PICR2[0] to disable copyback + * optimization. Oddly, the latest available user manual for the + * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd. + */ + if (host_bridge == MPC10X_BRIDGE_8245) { + ulong picr2; + + early_read_config_dword(hose, 0, PCI_DEVFN(0,0), + MPC10X_CFG_PICR2_REG, &picr2); + + picr2 |= MPC10X_CFG_PICR2_COPYBACK_OPT; + + early_write_config_dword(hose, 0, PCI_DEVFN(0,0), + MPC10X_CFG_PICR2_REG, picr2); + } + if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100); return 0; } diff -puN include/asm-ppc/mpc10x.h~ppc32-mpc8245-erratum-28-workaround include/asm-ppc/mpc10x.h --- 25/include/asm-ppc/mpc10x.h~ppc32-mpc8245-erratum-28-workaround 2005-01-28 14:34:20.229648384 -0800 +++ 25-akpm/include/asm-ppc/mpc10x.h 2005-01-28 14:34:20.234647624 -0800 @@ -108,6 +108,9 @@ #define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 +#define MPC10X_CFG_PICR2_REG 0xac +#define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 + #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ _