From: Ralf Baechle o Updates for the Sibyte Swarm aka BCM91250 eval board. Mostly trivial changes except the sound driver. o Add the PCI IDS for the HT interface and the HT-to-PCI bridge used on the Swarm and relatives. Signed-off-by: Andrew Morton --- 25-akpm/arch/mips/Kconfig | 5 25-akpm/arch/mips/configs/sb1250-swarm_defconfig | 56 ++ 25-akpm/arch/mips/pci/Makefile | 2 25-akpm/arch/mips/pci/fixup-sb1250.c | 24 + 25-akpm/arch/mips/pci/pci-sb1250.c | 14 25-akpm/arch/mips/sibyte/sb1250/bcm1250_tbprof.c | 112 ++--- 25-akpm/arch/mips/sibyte/sb1250/bus_watcher.c | 3 25-akpm/arch/mips/sibyte/sb1250/irq.c | 79 ++- 25-akpm/arch/mips/sibyte/sb1250/irq_handler.S | 2 25-akpm/arch/mips/sibyte/sb1250/setup.c | 4 25-akpm/arch/mips/sibyte/sb1250/smp.c | 6 25-akpm/arch/mips/sibyte/sb1250/time.c | 23 - 25-akpm/arch/mips/sibyte/swarm/rtc_m41t81.c | 44 +- 25-akpm/arch/mips/sibyte/swarm/rtc_xicor1241.c | 40 - 25-akpm/arch/mips/sibyte/swarm/time.c | 42 + 25-akpm/drivers/i2c/algos/i2c-algo-sibyte.c | 6 25-akpm/include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 1 25-akpm/include/asm-mips/sibyte/sb1250.h | 2 25-akpm/include/linux/pci_ids.h | 6 25-akpm/sound/oss/Kconfig | 10 25-akpm/sound/oss/Makefile | 1 25-akpm/sound/oss/swarm_cs4297a.c | 235 +++++------ 22 files changed, 421 insertions(+), 296 deletions(-) diff -puN arch/mips/configs/sb1250-swarm_defconfig~mips-sibyte-updates arch/mips/configs/sb1250-swarm_defconfig --- 25/arch/mips/configs/sb1250-swarm_defconfig~mips-sibyte-updates 2005-01-29 11:25:54.124641112 -0800 +++ 25-akpm/arch/mips/configs/sb1250-swarm_defconfig 2005-01-29 11:25:54.158635944 -0800 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.10-rc2 -# Sun Nov 21 14:12:06 2004 +# Linux kernel version: 2.6.11-rc2 +# Wed Jan 26 02:49:10 2005 # CONFIG_MIPS=y # CONFIG_MIPS64 is not set @@ -110,13 +110,13 @@ CONFIG_SIBYTE_CFE=y # CONFIG_SNI_RM200_PCI is not set # CONFIG_TOSHIBA_RBTX4927 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_COHERENT=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_FB is not set # # CPU selection @@ -143,8 +143,7 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_SIBYTE_DMA_PAGEOPS is not set -# CONFIG_CPU_HAS_PREFETCH is not set -CONFIG_VTAG_ICACHE=y +CONFIG_CPU_HAS_PREFETCH=y CONFIG_SB1_PASS_1_WORKAROUNDS=y # CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set @@ -166,6 +165,20 @@ CONFIG_PCI_NAMES=y CONFIG_MMU=y # +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PC-card bridges +# + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# # Executable file formats # CONFIG_BINFMT_ELF=y @@ -181,6 +194,7 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set # # Memory Technology Devices (MTD) @@ -204,10 +218,12 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=9220 CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" @@ -223,6 +239,7 @@ CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y +CONFIG_ATA_OVER_ETH=m # # ATA/ATAPI/MFM/RLL support @@ -441,6 +458,7 @@ CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_LIBPS2 is not set CONFIG_SERIO_RAW=m # @@ -454,6 +472,8 @@ CONFIG_SERIO_RAW=m CONFIG_SERIAL_NONSTANDARD=y # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set # CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set @@ -491,7 +511,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_AGP is not set # CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set @@ -522,6 +541,8 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Graphics support # +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -536,11 +557,25 @@ CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information +# + +# # USB Gadget Support # # CONFIG_USB_GADGET is not set # +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# # File systems # CONFIG_EXT2_FS=y @@ -636,6 +671,11 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_NLS is not set # +# Profiling support +# +# CONFIG_PROFILING is not set + +# # Kernel hacking # # CONFIG_DEBUG_KERNEL is not set @@ -679,6 +719,10 @@ CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_TEST is not set # +# Hardware crypto devices +# + +# # Library routines # # CONFIG_CRC_CCITT is not set diff -puN arch/mips/Kconfig~mips-sibyte-updates arch/mips/Kconfig --- 25/arch/mips/Kconfig~mips-sibyte-updates 2005-01-29 11:25:54.126640808 -0800 +++ 25-akpm/arch/mips/Kconfig 2005-01-29 11:25:54.179632752 -0800 @@ -614,6 +614,7 @@ endchoice config SIBYTE_SB1xxx_SOC bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)" depends on EXPERIMENTAL + select BOOT_ELF32 select DMA_COHERENT select SWAP_IO_SPACE @@ -724,6 +725,7 @@ choice config CPU_SB1_PASS_1 bool "1250 Pass1" depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH config CPU_SB1_PASS_2_1250 bool "1250 An" @@ -735,12 +737,14 @@ config CPU_SB1_PASS_2_1250 config CPU_SB1_PASS_2_2 bool "1250 Bn" depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH help Also called BCM1250 Pass 2.2 config CPU_SB1_PASS_4 bool "1250 Cn" depends on SIBYTE_SB1250 + select CPU_HAS_PREFETCH help Also called BCM1250 Pass 3 @@ -752,6 +756,7 @@ config CPU_SB1_PASS_2_112x config CPU_SB1_PASS_3 bool "112x An" depends on SIBYTE_BCM112X + select CPU_HAS_PREFETCH endchoice diff -puN /dev/null arch/mips/pci/fixup-sb1250.c --- /dev/null 2003-09-15 06:40:47.000000000 -0700 +++ 25-akpm/arch/mips/pci/fixup-sb1250.c 2005-01-29 11:25:54.176633208 -0800 @@ -0,0 +1,24 @@ +/* + * arch/mips/pci/fixup-sb1250.c + * + * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +/* + * The BCM1250, etc. PCI/HT bridge reports as a host bridge. + */ +static void __init quirk_sb1250_ht(struct pci_dev *dev) +{ + dev->class = PCI_CLASS_BRIDGE_PCI << 8; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT, + quirk_sb1250_ht); diff -puN arch/mips/pci/Makefile~mips-sibyte-updates arch/mips/pci/Makefile --- 25/arch/mips/pci/Makefile~mips-sibyte-updates 2005-01-29 11:25:54.127640656 -0800 +++ 25-akpm/arch/mips/pci/Makefile 2005-01-29 11:25:54.177633056 -0800 @@ -43,7 +43,7 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yose pci-yosemite.o obj-$(CONFIG_SGI_IP27) += pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o -obj-$(CONFIG_SIBYTE_SB1250) += pci-sb1250.o +obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff -puN arch/mips/pci/pci-sb1250.c~mips-sibyte-updates arch/mips/pci/pci-sb1250.c --- 25/arch/mips/pci/pci-sb1250.c~mips-sibyte-updates 2005-01-29 11:25:54.129640352 -0800 +++ 25-akpm/arch/mips/pci/pci-sb1250.c 2005-01-29 11:25:54.177633056 -0800 @@ -182,8 +182,8 @@ static int sb1250_pcibios_write(struct p } struct pci_ops sb1250_pci_ops = { - .read = sb1250_pcibios_read, - .write = sb1250_pcibios_write + .read = sb1250_pcibios_read, + .write = sb1250_pcibios_write, }; static struct resource sb1250_mem_resource = { @@ -192,7 +192,7 @@ static struct resource sb1250_mem_resour .end = 0x5fffffffUL, .flags = IORESOURCE_MEM, }; - + static struct resource sb1250_io_resource = { .name = "SB1250 PCI I/O", .start = 0x00000000UL, @@ -215,9 +215,13 @@ static int __init sb1250_pcibios_init(vo /* CFE will assign PCI resources */ pci_probe_only = 1; + /* Avoid ISA compat ranges. */ + PCIBIOS_MIN_IO = 0x00008000UL; + PCIBIOS_MIN_MEM = 0x01000000UL; + /* Set I/O resource limits. */ - ioport_resource.end = 0x01ffffff; /* 32MB accessible by sb1250 */ - iomem_resource.end = 0xffffffff; /* no HT support yet */ + ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */ + iomem_resource.end = 0xffffffffUL; /* no HT support yet */ cfg_space = ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024); diff -puN arch/mips/sibyte/sb1250/bcm1250_tbprof.c~mips-sibyte-updates arch/mips/sibyte/sb1250/bcm1250_tbprof.c --- 25/arch/mips/sibyte/sb1250/bcm1250_tbprof.c~mips-sibyte-updates 2005-01-29 11:25:54.130640200 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/bcm1250_tbprof.c 2005-01-29 11:25:54.160635640 -0800 @@ -64,24 +64,24 @@ static void arm_tb(void) u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger start of trace. XXX vary sampling period */ - __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); - scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); + scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Unfortunately, in Pass 2 we must clear all counters to knock down a previous interrupt request. This means that bus profiling requires ALL of the SCD perf counters. */ - __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is + bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is M_SPC_CFG_ENABLE | // enable counting M_SPC_CFG_CLEAR | // clear all counters V_SPC_CFG_SRC1(1), // counter 1 counts cycles - IOADDR(A_SCD_PERF_CNT_CFG)); - __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); + IOADDR(A_SCD_PERF_CNT_CFG)); + bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); /* Reset the trace buffer */ - __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) /* XXXKW may want to expose control to the data-collector */ tb_options |= M_SCD_TRACE_CFG_FORCECNT; #endif - __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); + bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 1; } @@ -93,22 +93,23 @@ static irqreturn_t sbprof_tb_intr(int ir /* XXX should use XKPHYS to make writes bypass L2 */ u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; /* Read out trace */ - __raw_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); + bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); __asm__ __volatile__ ("sync" : : : "memory"); /* Loop runs backwards because bundles are read out in reverse order */ for (i = 256 * 6; i > 0; i -= 6) { // Subscripts decrease to put bundle in the order // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi - p[i-1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi - p[i-2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo - p[i-3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi - p[i-4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo - p[i-5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi - p[i-6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo + p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi + p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo + p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi + p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo + p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi + p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo } if (!sbp.tb_enable) { DBG(printk(DEVNAME ": tb_intr shutdown\n")); - __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + bus_writeq(M_SCD_TRACE_CFG_RESET, + IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; wake_up(&sbp.tb_sync); } else { @@ -117,7 +118,7 @@ static irqreturn_t sbprof_tb_intr(int ir } else { /* No more trace buffer samples */ DBG(printk(DEVNAME ": tb_intr full\n")); - __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); + bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); sbp.tb_armed = 0; if (!sbp.tb_enable) { wake_up(&sbp.tb_sync); @@ -151,13 +152,13 @@ int sbprof_zbprof_start(struct file *fil return -EBUSY; } /* Make sure there isn't a perf-cnt interrupt waiting */ - scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); + scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); /* Disable and clear counters, override SRC_1 */ - __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | + bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), - IOADDR(A_SCD_PERF_CNT_CFG)); + IOADDR(A_SCD_PERF_CNT_CFG)); /* We grab this interrupt to prevent others from trying to use it, even though we don't want to service the interrupts @@ -171,52 +172,55 @@ int sbprof_zbprof_start(struct file *fil /* I need the core to mask these, but the interrupt mapper to pass them through. I am exploiting my knowledge that cp0_status masks out IP[5]. krw */ - __raw_writeq(K_INT_MAP_I3, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_PERF_CNT<<3))); + bus_writeq(K_INT_MAP_I3, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_PERF_CNT << 3))); /* Initialize address traps */ - __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); - - __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); - - __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); - __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); + + bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); + + bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); + bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); /* Initialize Trace Event 0-7 */ // when interrupt - __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); + bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); + bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); /* Initialize Trace Sequence 0-7 */ // Start on event 0 (interrupt) - __raw_writeq(V_SCD_TRSEQ_FUNC_START|0x0fff, - IOADDR(A_SCD_TRACE_SEQUENCE_0)); + bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, + IOADDR(A_SCD_TRACE_SEQUENCE_0)); // dsamp when d used | asamp when a used - __raw_writeq(M_SCD_TRSEQ_ASAMPLE|M_SCD_TRSEQ_DSAMPLE|K_SCD_TRSEQ_TRIGGER_ALL, - IOADDR(A_SCD_TRACE_SEQUENCE_1)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); - __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); + bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | + K_SCD_TRSEQ_TRIGGER_ALL, + IOADDR(A_SCD_TRACE_SEQUENCE_1)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); + bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ - __raw_writeq((1ULL << K_INT_PERF_CNT), IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); + bus_writeq((1ULL << K_INT_PERF_CNT), + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); arm_tb(); diff -puN arch/mips/sibyte/sb1250/bus_watcher.c~mips-sibyte-updates arch/mips/sibyte/sb1250/bus_watcher.c --- 25/arch/mips/sibyte/sb1250/bus_watcher.c~mips-sibyte-updates 2005-01-29 11:25:54.132639896 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/bus_watcher.c 2005-01-29 11:25:54.161635488 -0800 @@ -188,7 +188,8 @@ static irqreturn_t sibyte_bw_int(int irq csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); for (i=0; i<256*6; i++) - printk("%016llx\n", (unsigned long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); + printk("%016llx\n", + (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ))); csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); diff -puN arch/mips/sibyte/sb1250/irq.c~mips-sibyte-updates arch/mips/sibyte/sb1250/irq.c --- 25/arch/mips/sibyte/sb1250/irq.c~mips-sibyte-updates 2005-01-29 11:25:54.133639744 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/irq.c 2005-01-29 11:25:54.162635336 -0800 @@ -88,7 +88,7 @@ static struct hw_interrupt_type sb1250_i /* Store the CPU id (not the logical number) */ int sb1250_irq_owner[SB1250_NR_IRQS]; -spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED; +DEFINE_SPINLOCK(sb1250_imr_lock); void sb1250_mask_irq(int cpu, int irq) { @@ -96,9 +96,11 @@ void sb1250_mask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints |= (((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -108,9 +110,11 @@ void sb1250_unmask_irq(int cpu, int irq) u64 cur_ints; spin_lock_irqsave(&sb1250_imr_lock, flags); - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); spin_unlock_irqrestore(&sb1250_imr_lock, flags); } @@ -145,19 +149,23 @@ static void sb1250_set_affinity(unsigned /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); int_on = !(cur_ints & (((u64) 1) << irq)); if (int_on) { /* If it was on, mask it */ cur_ints |= (((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK)); + __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + + R_IMR_INTERRUPT_MASK)); } sb1250_irq_owner[irq] = cpu; if (int_on) { /* unmask for the new CPU */ - cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); - ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); + __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + + R_IMR_INTERRUPT_MASK)); } spin_unlock(&sb1250_imr_lock); spin_unlock_irqrestore(&desc->lock, flags); @@ -200,8 +208,8 @@ static void ack_sb1250_irq(unsigned int * deliver the interrupts to all CPUs (which makes affinity * changing easier for us) */ - pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], - R_IMR_LDT_INTERRUPT))); + pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], + R_IMR_LDT_INTERRUPT))); pending &= ((u64)1 << (irq)); if (pending) { int i; @@ -216,8 +224,9 @@ static void ack_sb1250_irq(unsigned int * Clear for all CPUs so an affinity switch * doesn't find an old status */ - __raw_writeq(pending, - IOADDR(A_IMR_REGISTER(cpu, R_IMR_LDT_INTERRUPT_CLR))); + bus_writeq(pending, + IOADDR(A_IMR_REGISTER(cpu, + R_IMR_LDT_INTERRUPT_CLR))); } /* @@ -331,14 +340,12 @@ void __init arch_init_irq(void) /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ - __raw_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(0, - R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); - __raw_writeq(IMR_IP2_VAL, - IOADDR(A_IMR_REGISTER(1, - R_IMR_INTERRUPT_MAP_BASE) + - (i << 3))); + bus_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); + bus_writeq(IMR_IP2_VAL, + IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (i << 3))); } init_sb1250_irqs(); @@ -348,21 +355,23 @@ void __init arch_init_irq(void) * inter-cpu messages */ /* Was I1 */ - __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); - __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + - (K_INT_MBOX_0 << 3))); + bus_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); + bus_writeq(IMR_IP3_VAL, + IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ - __raw_writeq(0xffffffffffffffff, - IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); - __raw_writeq(0xffffffffffffffff, - IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); + bus_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); + bus_writeq(0xffffffffffffffffULL, + IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); - __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); - __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); + bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); + bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); sb1250_steal_irq(K_INT_MBOX_0); @@ -387,12 +396,12 @@ void __init arch_init_irq(void) sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ - __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); + bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); sb1250_steal_irq(kgdb_irq); - __raw_writeq(IMR_IP6_VAL, - IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + - (kgdb_irq<<3))); + bus_writeq(IMR_IP6_VAL, + IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (kgdb_irq<<3))); sb1250_unmask_irq(0, kgdb_irq); } #endif diff -puN arch/mips/sibyte/sb1250/irq_handler.S~mips-sibyte-updates arch/mips/sibyte/sb1250/irq_handler.S --- 25/arch/mips/sibyte/sb1250/irq_handler.S~mips-sibyte-updates 2005-01-29 11:25:54.135639440 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/irq_handler.S 2005-01-29 11:25:54.162635336 -0800 @@ -123,7 +123,7 @@ * check the 1250 interrupt registers to figure out what to do * Need to detect which CPU we're on, now that smp_affinity is supported. */ - PTR_LA v0, KSEG1 + A_IMR_CPU0_BASE + PTR_LA v0, CKSEG1 + A_IMR_CPU0_BASE #ifdef CONFIG_SMP lw t1, TI_CPU($28) sll t1, IMR_REGISTER_SPACING_SHIFT diff -puN arch/mips/sibyte/sb1250/setup.c~mips-sibyte-updates arch/mips/sibyte/sb1250/setup.c --- 25/arch/mips/sibyte/sb1250/setup.c~mips-sibyte-updates 2005-01-29 11:25:54.136639288 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/setup.c 2005-01-29 11:25:54.163635184 -0800 @@ -153,7 +153,7 @@ void sb1250_setup(void) int bad_config = 0; sb1_pass = read_c0_prid() & 0xff; - sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); + sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION)); soc_type = SYS_SOC_TYPE(sys_rev); soc_pass = G_SYS_REVISION(sys_rev); @@ -162,7 +162,7 @@ void sb1250_setup(void) machine_restart(NULL); } - plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); + plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG))); zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", diff -puN arch/mips/sibyte/sb1250/smp.c~mips-sibyte-updates arch/mips/sibyte/sb1250/smp.c --- 25/arch/mips/sibyte/sb1250/smp.c~mips-sibyte-updates 2005-01-29 11:25:54.138638984 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/smp.c 2005-01-29 11:25:54.163635184 -0800 @@ -73,7 +73,7 @@ void sb1250_smp_finish(void) */ void core_send_ipi(int cpu, unsigned int action) { - __raw_writeq((((u64)action)<< 48), mailbox_set_regs[cpu]); + bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); } void sb1250_mailbox_interrupt(struct pt_regs *regs) @@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_ kstat_this_cpu.irqs[K_INT_MBOX_0]++; /* Load the mailbox register to figure out what we're supposed to do */ - action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; + action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff; /* Clear the mailbox to clear the interrupt */ - ____raw_writeq(((u64)action)<<48, mailbox_clear_regs[cpu]); + __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); /* * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the diff -puN arch/mips/sibyte/sb1250/time.c~mips-sibyte-updates arch/mips/sibyte/sb1250/time.c --- 25/arch/mips/sibyte/sb1250/time.c~mips-sibyte-updates 2005-01-29 11:25:54.139638832 -0800 +++ 25-akpm/arch/mips/sibyte/sb1250/time.c 2005-01-29 11:25:54.164635032 -0800 @@ -67,21 +67,24 @@ void sb1250_time_init(void) sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ - __raw_writeq(IMR_IP4_VAL, IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + - (irq << 3))); + bus_writeq(IMR_IP4_VAL, + IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + + (irq << 3))); /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ /* Disable the timer and set up the count */ - __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - __raw_writeq(50000 / HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + bus_writeq(50000 / HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - __raw_writeq(1000000/HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); + bus_writeq(1000000/HZ, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif /* Set the timer running */ - __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); @@ -102,8 +105,8 @@ void sb1250_timer_interrupt(struct pt_re int irq = K_INT_TIMER_0 + cpu; /* Reset the timer */ - ____raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, - IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); + __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); /* * CPU 0 handles the global timer interrupt job @@ -127,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_re unsigned long sb1250_gettimeoffset(void) { unsigned long count = - __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); return 1000000/HZ - count; } diff -puN arch/mips/sibyte/swarm/rtc_m41t81.c~mips-sibyte-updates arch/mips/sibyte/swarm/rtc_m41t81.c --- 25/arch/mips/sibyte/swarm/rtc_m41t81.c~mips-sibyte-updates 2005-01-29 11:25:54.140638680 -0800 +++ 25-akpm/arch/mips/sibyte/swarm/rtc_m41t81.c 2005-01-29 11:25:54.165634880 -0800 @@ -82,57 +82,59 @@ #define M41T81REG_SQW 0x13 /* square wave register */ #define M41T81_CCR_ADDRESS 0x68 -#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg))) +#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) static int m41t81_read(uint8_t addr) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); - __raw_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), SMB_CSR(R_SMB_START)); + bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); + bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int m41t81_write(uint8_t addr, int b) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); - __raw_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, - SMB_CSR(R_SMB_START)); + bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); + bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } /* read the same byte again to make sure it is written */ - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, - SMB_CSR(R_SMB_START)); + bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; return 0; diff -puN arch/mips/sibyte/swarm/rtc_xicor1241.c~mips-sibyte-updates arch/mips/sibyte/swarm/rtc_xicor1241.c --- 25/arch/mips/sibyte/swarm/rtc_xicor1241.c~mips-sibyte-updates 2005-01-29 11:25:54.142638376 -0800 +++ 25-akpm/arch/mips/sibyte/swarm/rtc_xicor1241.c 2005-01-29 11:25:54.166634728 -0800 @@ -57,50 +57,52 @@ #define X1241_CCR_ADDRESS 0x6F -#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg))) +#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) static int xicor_read(uint8_t addr) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - __raw_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - __raw_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), SMB_CSR(R_SMB_START)); + bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); - __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + bus_writeq(addr, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; diff -puN arch/mips/sibyte/swarm/time.c~mips-sibyte-updates arch/mips/sibyte/swarm/time.c --- 25/arch/mips/sibyte/swarm/time.c~mips-sibyte-updates 2005-01-29 11:25:54.143638224 -0800 +++ 25-akpm/arch/mips/sibyte/swarm/time.c 2005-01-29 11:25:54.167634576 -0800 @@ -79,46 +79,48 @@ static unsigned int usec_bias = 0; static int xicor_read(uint8_t addr) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); - __raw_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); - __raw_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), SMB_CSR(R_SMB_START)); + bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); + return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); } static int xicor_write(uint8_t addr, int b) { - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); - __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, - SMB_CSR(R_SMB_START)); + bus_writeq(addr, SMB_CSR(R_SMB_CMD)); + bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; @@ -226,8 +228,8 @@ void __init swarm_time_init(void) /* Establish communication with the Xicor 1241 RTC */ /* XXXKW how do I share the SMBus with the I2C subsystem? */ - __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); - __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); + bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); + bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { printk("x1241: couldn't detect on SWARM SMBus 1\n"); diff -puN drivers/i2c/algos/i2c-algo-sibyte.c~mips-sibyte-updates drivers/i2c/algos/i2c-algo-sibyte.c --- 25/drivers/i2c/algos/i2c-algo-sibyte.c~mips-sibyte-updates 2005-01-29 11:25:54.144638072 -0800 +++ 25-akpm/drivers/i2c/algos/i2c-algo-sibyte.c 2005-01-29 11:25:54.168634424 -0800 @@ -181,9 +181,6 @@ int i2c_sibyte_add_bus(struct i2c_adapte printk("\n"); } -#ifdef MODULE - MOD_INC_USE_COUNT; -#endif i2c_add_adapter(i2c_adap); return 0; @@ -197,9 +194,6 @@ int i2c_sibyte_del_bus(struct i2c_adapte if ((res = i2c_del_adapter(adap)) < 0) return res; -#ifdef MODULE - MOD_DEC_USE_COUNT; -#endif return 0; } diff -puN include/asm-mips/mach-sibyte/cpu-feature-overrides.h~mips-sibyte-updates include/asm-mips/mach-sibyte/cpu-feature-overrides.h --- 25/include/asm-mips/mach-sibyte/cpu-feature-overrides.h~mips-sibyte-updates 2005-01-29 11:25:54.146637768 -0800 +++ 25-akpm/include/asm-mips/mach-sibyte/cpu-feature-overrides.h 2005-01-29 11:25:54.179632752 -0800 @@ -25,6 +25,7 @@ #define cpu_has_vtag_icache 1 #define cpu_has_dc_aliases 0 #define cpu_has_ic_fills_f_dc 0 +#define cpu_icache_snoops_remote_store 0 #define cpu_has_nofpuex 0 #define cpu_has_64bits 1 diff -puN include/asm-mips/sibyte/sb1250.h~mips-sibyte-updates include/asm-mips/sibyte/sb1250.h --- 25/include/asm-mips/sibyte/sb1250.h~mips-sibyte-updates 2005-01-29 11:25:54.147637616 -0800 +++ 25-akpm/include/asm-mips/sibyte/sb1250.h 2005-01-29 11:25:54.167634576 -0800 @@ -58,6 +58,6 @@ extern void prom_printf(char *fmt, ...); #endif -#define IOADDR(a) (UNCAC_BASE + (a)) +#define IOADDR(a) (IO_BASE + (a)) #endif diff -puN include/linux/pci_ids.h~mips-sibyte-updates include/linux/pci_ids.h --- 25/include/linux/pci_ids.h~mips-sibyte-updates 2005-01-29 11:25:54.149637312 -0800 +++ 25-akpm/include/linux/pci_ids.h 2005-01-29 11:25:54.182632296 -0800 @@ -1933,6 +1933,9 @@ #define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 #define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 +#define PCI_VENDOR_ID_SIPACKETS 0x14d9 +#define PCI_DEVICE_ID_SP_HT 0x0010 + #define PCI_VENDOR_ID_AFAVLAB 0x14db #define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182 @@ -2016,6 +2019,9 @@ #define PCI_DEVICE_ID_FARSITE_TE1 0x1610 #define PCI_DEVICE_ID_FARSITE_TE1C 0x1612 +#define PCI_VENDOR_ID_SIBYTE 0x166d +#define PCI_DEVICE_ID_BCM1250_HT 0x0002 + #define PCI_VENDOR_ID_LINKSYS 0x1737 #define PCI_DEVICE_ID_LINKSYS_EG1032 0x1032 #define PCI_DEVICE_ID_LINKSYS_EG1064 0x1064 diff -puN sound/oss/Kconfig~mips-sibyte-updates sound/oss/Kconfig --- 25/sound/oss/Kconfig~mips-sibyte-updates 2005-01-29 11:25:54.150637160 -0800 +++ 25-akpm/sound/oss/Kconfig 2005-01-29 11:25:54.176633208 -0800 @@ -100,6 +100,16 @@ config SOUND_CS4281 Picture and feature list at . +config SOUND_BCM_CS4297A + tristate "Crystal Sound CS4297a (for Swarm)" + depends on SOUND_PRIME!=n && SIBYTE_SWARM && SOUND + help + The BCM91250A has a Crystal CS4297a on synchronous serial + port B (in addition to the DB-9 serial port). Say Y or M + here to enable the sound chip instead of the UART. Also + note that CONFIG_KGDB should not be enabled at the same + time, since it also attempts to use this UART port. + config SOUND_ES1370 tristate "Ensoniq AudioPCI (ES1370)" depends on SOUND_PRIME!=n && SOUND && PCI && SOUND_GAMEPORT diff -puN sound/oss/Makefile~mips-sibyte-updates sound/oss/Makefile --- 25/sound/oss/Makefile~mips-sibyte-updates 2005-01-29 11:25:54.152636856 -0800 +++ 25-akpm/sound/oss/Makefile 2005-01-29 11:25:54.175633360 -0800 @@ -71,6 +71,7 @@ obj-$(CONFIG_SOUND_MAESTRO3) += maestro3 obj-$(CONFIG_SOUND_TRIDENT) += trident.o ac97_codec.o obj-$(CONFIG_SOUND_HARMONY) += harmony.o obj-$(CONFIG_SOUND_EMU10K1) += ac97_codec.o +obj-$(CONFIG_SOUND_BCM_CS4297A) += swarm_cs4297a.o obj-$(CONFIG_SOUND_RME96XX) += rme96xx.o obj-$(CONFIG_SOUND_BT878) += btaudio.o obj-$(CONFIG_SOUND_ALI5455) += ali5455.o ac97_codec.o diff -puN sound/oss/swarm_cs4297a.c~mips-sibyte-updates sound/oss/swarm_cs4297a.c --- 25/sound/oss/swarm_cs4297a.c~mips-sibyte-updates 2005-01-29 11:25:54.153636704 -0800 +++ 25-akpm/sound/oss/swarm_cs4297a.c 2005-01-29 11:25:54.174633512 -0800 @@ -10,7 +10,9 @@ * (audio@crystal.cirrus.com). * -- adapted from cs4281 PCI driver for cs4297a on * BCM1250 Synchronous Serial interface -* (kwalker@broadcom.com) +* (Kip Walker, Broadcom Corp.) +* Copyright (C) 2004 Maciej W. Rozycki +* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -71,12 +73,13 @@ #include #include #include -#include -#include #include #include #include -#include + +#include +#include +#include #include #include @@ -86,7 +89,6 @@ #include #include #include -#include struct cs4297a_state; @@ -561,44 +563,44 @@ static int ser_init(struct cs4297a_state CS_DBGOUT(CS_INIT, 2, printk(KERN_INFO "cs4297a: Setting up serial parameters\n")); - out64(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); + __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); - out64(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); - out64(32, SS_CSR(R_SER_MINFRM_SZ)); - out64(32, SS_CSR(R_SER_MAXFRM_SZ)); - - out64(1, SS_CSR(R_SER_TX_RD_THRSH)); - out64(4, SS_CSR(R_SER_TX_WR_THRSH)); - out64(8, SS_CSR(R_SER_RX_RD_THRSH)); + __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); + __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ)); + __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ)); + + __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH)); + __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH)); + __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH)); /* This looks good from experimentation */ - out64((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT | + __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT | M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE), SS_CSR(R_SER_LINE_MODE)); /* This looks good from experimentation */ - out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, SS_TXTBL(0)); - out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, SS_TXTBL(1)); - out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, SS_TXTBL(2)); - out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | + __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3)); - out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, SS_RXTBL(0)); - out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, SS_RXTBL(1)); - out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, + __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, SS_RXTBL(2)); - out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | + __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_RXTBL(3)); for (i=4; i<16; i++) { /* Just in case... */ - out64(M_SYNCSER_SEQ_LAST, SS_TXTBL(i)); - out64(M_SYNCSER_SEQ_LAST, SS_RXTBL(i)); + __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i)); + __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i)); } return 0; @@ -620,7 +622,7 @@ static int init_serdma(serdma_t *dma) memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t)); dma->descrtab_end = dma->descrtab + dma->ringsz; /* XXX bloddy mess, use proper DMA API here ... */ - dma->descrtab_phys = PHYSADDR((int)dma->descrtab); + dma->descrtab_phys = CPHYSADDR((long)dma->descrtab); dma->descr_add = dma->descr_rem = dma->descrtab; /* Frame buffer area */ @@ -631,7 +633,7 @@ static int init_serdma(serdma_t *dma) return -1; } memset(dma->dma_buf, 0, DMA_BUF_SIZE); - dma->dma_buf_phys = PHYSADDR((int)dma->dma_buf); + dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf); /* Samples buffer area */ dma->sbufsz = SAMPLE_BUF_SIZE; @@ -665,8 +667,8 @@ static int dma_init(struct cs4297a_state init_serdma(&s->dma_dac)) return -1; - if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| - in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { + if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| + __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { panic("DMA state corrupted?!"); } @@ -681,38 +683,38 @@ static int dma_init(struct cs4297a_state s->dma_adc.descrtab[i].descr_b = 0; } - out64((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) | + __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) | V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN), SS_CSR(R_SER_DMA_CONFIG0_RX)); - out64(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); - out64(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); + __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); + __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); - out64(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); - out64(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); - out64(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); + __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); + __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); + __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); /* Prep the receive DMA descriptor ring */ - out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); + __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); - out64(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); + __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); - out64((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT), + __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT), SS_CSR(R_SER_INT_MASK)); /* Enable the rx/tx; let the codec warm up to the sync and start sending good frames before the receive FIFO is enabled */ - out64(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); + __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); udelay(1000); - out64(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); + __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); /* XXXKW is this magic? (the "1" part) */ - while ((in64(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) + while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) ; CS_DBGOUT(CS_INIT, 4, printk(KERN_INFO "cs4297a: status: %08x\n", - (unsigned int)(in64(SS_CSR(R_SER_STATUS)) & 0xffffffff))); + (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff))); return 0; } @@ -752,8 +754,8 @@ static int serdma_reg_access(struct cs42 descr = &d->descrtab[swptr]; data_p = &d->dma_buf[swptr * 4]; - *data_p = data; - out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); + *data_p = cpu_to_be64(data); + __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); CS_DBGOUT(CS_DESCR, 4, printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n", data_p, swptr, d->hwptr)); @@ -807,7 +809,7 @@ static void stop_dac(struct cs4297a_stat /* XXXKW what do I really want here? My theory for now is that I just flip the "ena" bit, and the interrupt handler will stop processing the xmit channel */ - out64((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0, + __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0, SS_CSR(R_SER_DMA_ENABLE)); #endif @@ -926,11 +928,11 @@ static void cs4297a_update_ptr(struct cs serdma_descr_t *descr; // update ADC pointer - status = intflag ? in64(SS_CSR(R_SER_STATUS)) : 0; + status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0; if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) { d = &s->dma_adc; - hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - + hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - d->descrtab_phys) / sizeof(serdma_descr_t)); if (s->ena & FMODE_READ) { @@ -944,12 +946,12 @@ static void cs4297a_update_ptr(struct cs s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]); descr = &d->descrtab[d->swptr]; while (diff2--) { - u64 data = *(u64 *)s_ptr; + u64 data = be64_to_cpu(*(u64 *)s_ptr); u64 descr_a; u16 left, right; descr_a = descr->descr_a; descr->descr_a &= ~M_DMA_SERRX_SOP; - if ((descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((int)s_ptr)) { + if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) { printk(KERN_ERR "cs4297a: RX Bad address (read)\n"); } if (((data & 0x9800000000000000) != 0x9800000000000000) || @@ -971,10 +973,11 @@ static void cs4297a_update_ptr(struct cs continue; } good_diff++; - left = ((s_ptr[1] & 0xff) << 8) | ((s_ptr[2] >> 24) & 0xff); - right = (s_ptr[2] >> 4) & 0xffff; - *d->sb_hwptr++ = left; - *d->sb_hwptr++ = right; + left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) | + ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff); + right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff; + *d->sb_hwptr++ = cpu_to_be16(left); + *d->sb_hwptr++ = cpu_to_be16(right); if (d->sb_hwptr == d->sb_end) d->sb_hwptr = d->sample_buf; descr++; @@ -991,7 +994,7 @@ static void cs4297a_update_ptr(struct cs printk(KERN_ERR "cs4297a: bogus receive overflow!!\n"); } d->swptr = (d->swptr + diff) % d->ringsz; - out64(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); + __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); if (d->mapped) { if (d->count >= (signed) d->fragsize) wake_up(&d->wait); @@ -1019,11 +1022,11 @@ static void cs4297a_update_ptr(struct cs here because of an interrupt, so there must be a buffer to process. */ do { - data = *data_p; - if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((int)data_p)) { - printk(KERN_ERR "cs4297a: RX Bad address %d (%x %x)\n", d->swptr, - (int)(descr->descr_a & M_DMA_DSCRA_A_ADDR), - (int)PHYSADDR((int)data_p)); + data = be64_to_cpu(*data_p); + if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) { + printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr, + (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR), + (long)CPHYSADDR((long)data_p)); } if (!(data & (1LL << 63)) || !(descr->descr_a & M_DMA_SERRX_SOP) || @@ -1047,7 +1050,7 @@ static void cs4297a_update_ptr(struct cs d->swptr = 0; data_p = d->dma_buf; } - out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); + __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); } while (--diff); d->hwptr = hwptr; @@ -1072,7 +1075,7 @@ static void cs4297a_update_ptr(struct cs // if (s->ena & FMODE_WRITE) { serdma_t *d = &s->dma_dac; - hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - + hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - d->descrtab_phys) / sizeof(serdma_descr_t)); diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO @@ -1611,7 +1614,7 @@ static int drain_dac(struct cs4297a_stat if (nonblock) return -EBUSY; add_wait_queue(&s->dma_dac.wait, &wait); - while ((count = in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || + while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || (s->dma_dac.count > 0)) { if (!signal_pending(current)) { set_current_state(TASK_INTERRUPTIBLE); @@ -1624,7 +1627,7 @@ static int drain_dac(struct cs4297a_stat } spin_lock_irqsave(&s->lock, flags); /* Reset the bookkeeping */ - hwptr = (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - + hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); s->dma_dac.hwptr = s->dma_dac.swptr = hwptr; spin_unlock_irqrestore(&s->lock, flags); @@ -1787,7 +1790,6 @@ static ssize_t cs4297a_write(struct file u32 *s_tmpl; u32 *t_tmpl; u32 left, right; - /* XXXKW check system endian here ... */ int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE); /* XXXXXX this is broken for BLOAT_FACTOR */ @@ -1798,7 +1800,7 @@ static ssize_t cs4297a_write(struct file } if (d->underrun) { d->underrun = 0; - hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - + hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - d->descrtab_phys) / sizeof(serdma_descr_t)); d->swptr = d->hwptr = hwptr; } @@ -1828,21 +1830,21 @@ static ssize_t cs4297a_write(struct file /* XXXKW assuming 16-bit stereo! */ do { - t_tmpl[0] = 0x98000000; - left = s_tmpl[0] >> 16; - if (left & 0x8000) - left |= 0xf0000; - right = s_tmpl[0] & 0xffff; - if (right & 0x8000) - right |= 0xf0000; - if (swap) { - t_tmpl[1] = left & 0xff; - t_tmpl[2] = ((left & 0xff00) << 16) | ((right & 0xff) << 12) | - ((right & 0xff00) >> 4); - } else { - t_tmpl[1] = left >> 8; - t_tmpl[2] = ((left & 0xff) << 24) | (right << 4); - } + u32 tmp; + + t_tmpl[0] = cpu_to_be32(0x98000000); + + tmp = be32_to_cpu(s_tmpl[0]); + left = tmp & 0xffff; + right = tmp >> 16; + if (swap) { + left = swab16(left); + right = swab16(right); + } + t_tmpl[1] = cpu_to_be32(left >> 8); + t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) | + (right << 4)); + s_tmpl++; t_tmpl += 8; copy_cnt -= 4; @@ -1850,7 +1852,8 @@ static ssize_t cs4297a_write(struct file /* Mux in any pending read/write accesses */ if (s->reg_request) { - *(u64 *)(d->dma_buf + (swptr * 4)) |= s->reg_request; + *(u64 *)(d->dma_buf + (swptr * 4)) |= + cpu_to_be64(s->reg_request); s->reg_request = 0; wake_up(&s->dma_dac.reg_wait); } @@ -1860,7 +1863,7 @@ static ssize_t cs4297a_write(struct file "cs4297a: copy in %d to swptr %x\n", cnt, swptr)); swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz; - out64(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); + __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); spin_lock_irqsave(&s->lock, flags); d->swptr = swptr; d->count += cnt; @@ -1993,20 +1996,20 @@ static int cs4297a_ioctl(struct inode *i "cs4297a: cs4297a_ioctl(): DSP_RESET\n")); if (file->f_mode & FMODE_WRITE) { stop_dac(s); - synchronize_irq(); + synchronize_irq(s->irq); s->dma_dac.count = s->dma_dac.total_bytes = s->dma_dac.blocks = s->dma_dac.wakeup = 0; s->dma_dac.swptr = s->dma_dac.hwptr = - (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - + (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); } if (file->f_mode & FMODE_READ) { stop_adc(s); - synchronize_irq(); + synchronize_irq(s->irq); s->dma_adc.count = s->dma_adc.total_bytes = s->dma_adc.blocks = s->dma_dac.wakeup = 0; s->dma_adc.swptr = s->dma_adc.hwptr = - (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - + (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); } return 0; @@ -2378,7 +2381,7 @@ static int cs4297a_open(struct inode *in "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", (unsigned) inode, (unsigned) file, file->f_mode)); CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO - "cs4297a: status = %08x\n", (int)in64(SS_CSR(R_SER_STATUS_DEBUG)))); + "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG)))); list_for_each(entry, &cs4297a_devs) { @@ -2404,9 +2407,9 @@ static int cs4297a_open(struct inode *in return -ENODEV; } if (file->f_mode & FMODE_WRITE) { - if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { + if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { printk(KERN_ERR "cs4297a: TX pipe needs to drain\n"); - while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) + while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ; } @@ -2501,12 +2504,12 @@ static /*const */ struct file_operations .release = cs4297a_release, }; -static irqreturn_t cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs) +static void cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs) { struct cs4297a_state *s = (struct cs4297a_state *) dev_id; u32 status; - status = in64(SS_CSR(R_SER_STATUS_DEBUG)); + status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG)); CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status)); @@ -2514,16 +2517,16 @@ static irqreturn_t cs4297a_interrupt(int #if 0 /* XXXKW what check *should* be done here? */ if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) { - status = in64(SS_CSR(R_SER_STATUS)); + status = __raw_readq(SS_CSR(R_SER_STATUS)); printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status); - return IRQ_HANDLED; + return; } #endif if (status & M_SYNCSER_RX_SYNC_ERR) { - status = in64(SS_CSR(R_SER_STATUS)); + status = __raw_readq(SS_CSR(R_SER_STATUS)); printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status); - return IRQ_HANDLED; + return; } if (status & M_SYNCSER_RX_OVERRUN) { @@ -2533,9 +2536,9 @@ static irqreturn_t cs4297a_interrupt(int /* Fix things up: get the receive descriptor pool clean and give them back to the hardware */ - while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) + while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) ; - newptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - + newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); for (i=0; idma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP; @@ -2543,7 +2546,7 @@ static irqreturn_t cs4297a_interrupt(int s->dma_adc.swptr = s->dma_adc.hwptr = newptr; s->dma_adc.count = 0; s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf; - out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); + __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); } spin_lock(&s->lock); @@ -2552,9 +2555,9 @@ static irqreturn_t cs4297a_interrupt(int CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO "cs4297a: cs4297a_interrupt()-\n")); - return IRQ_HANDLED; } +#if 0 static struct initvol { int mixch; int vol; @@ -2570,26 +2573,31 @@ static struct initvol { {SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {SOUND_MIXER_WRITE_MIC, 0x0000} }; +#endif static int __init cs4297a_init(void) { struct cs4297a_state *s; - u64 cfg; - u32 pwr, id; + u32 pwr, id; mm_segment_t fs; - int rval, mdio_val; + int rval; +#ifndef CONFIG_BCM_CS4297A_CSWARM + u64 cfg; + int mdio_val; +#endif CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO "cs4297a: cs4297a_init_module()+ \n")); - mdio_val = in64(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) & +#ifndef CONFIG_BCM_CS4297A_CSWARM + mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) & (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT); /* Check syscfg for synchronous serial on port 1 */ - cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG); + cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); if (!(cfg & M_SYS_SER1_ENABLE)) { - out64(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG); - cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG); + __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG); + cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); if (!(cfg & M_SYS_SER1_ENABLE)) { printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n"); return -1; @@ -2599,14 +2607,15 @@ static int __init cs4297a_init(void) /* Force the codec (on SWARM) to reset by clearing GENO, preserving MDIO (no effect on CSWARM) */ - out64(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); + __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); udelay(10); } /* Now set GENO */ - out64(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); + __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); /* Give the codec some time to finish resetting (start the bit clock) */ udelay(100); +#endif if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) { CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR @@ -2659,6 +2668,8 @@ static int __init cs4297a_init(void) } while (!rval && (pwr != 0xf)); if (!rval) { + char *sb1250_duart_present; + fs = get_fs(); set_fs(KERNEL_DS); #if 0 @@ -2679,7 +2690,11 @@ static int __init cs4297a_init(void) list_add(&s->list, &cs4297a_devs); cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id); - + + sb1250_duart_present = symbol_get(sb1250_duart_present); + if (sb1250_duart_present) + sb1250_duart_present[1] = 0; + printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id); CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, @@ -2718,9 +2733,7 @@ static void __exit cs4297a_cleanup(void) // --------------------------------------------------------------------- -EXPORT_NO_SYMBOLS; - -MODULE_AUTHOR("Kip Walker, kwalker@broadcom.com"); +MODULE_AUTHOR("Kip Walker, Broadcom Corp."); MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board"); // --------------------------------------------------------------------- _