From: Karsten Keil Add a new driver for new ISDN hardware. Signed-off-by: Karsten Keil Signed-off-by: Andrew Morton --- 25-akpm/drivers/isdn/hisax/Kconfig | 6 25-akpm/drivers/isdn/hisax/Makefile | 1 25-akpm/drivers/isdn/hisax/hfc48scu.h | 4192 ++++++++++++++++++++++++++++++++ 25-akpm/drivers/isdn/hisax/hfc4s8s_l1.c | 1293 +++++++++ 4 files changed, 5492 insertions(+) diff -puN /dev/null drivers/isdn/hisax/hfc48scu.h --- /dev/null 2003-09-15 06:40:47.000000000 -0700 +++ 25-akpm/drivers/isdn/hisax/hfc48scu.h 2005-01-22 18:38:31.738128456 -0800 @@ -0,0 +1,4192 @@ +// $Id: hfc48scu.h,v 1.1 2004/03/11 16:11:51 martinb1 Exp $ +// $Revision: 1.1 $ +//___________________________________________________________________________________// +// // +// (C) Copyright Cologne Chip AG, 2003 // +//___________________________________________________________________________________// +// // +// File name: HFC48Scu.h // +// File content: This file contains the HFC-4S and HFC-8S register definitions. // +// Creation date: 03rd of February 2003 // +// Creator: GENERO V1.3 // +// Data base: HFC-XML V1.4 // +// File Revision: 1.1 // +// // +// The information presented can not be considered as assured characteristics. // +// Data can change without notice. Please check version numbers in case of doubt. // +// // +// For further information or questions please contact // +// support@CologneChip.com // +// // +// See below for examples how to use this file. // +// // +// // +// // +// _____________________________________________________________ // +// // +// This file has beta status. It is still under investigation. // +// We have tried to fulfil common user requirements. // +// // +// We'd be pleased about feedback for any suggestions to // +// improve this header file for our customer's use. // +// _____________________________________________________________ // +// // +// // +// // +//___________________________________________________________________________________// +// // +// WARNING: This file has been generated automatically and should not be // +// changed to maintain compatibility with later versions. // +//___________________________________________________________________________________// +// // + +#ifndef HFC_4S_8S_cu +#define HFC_4S_8S_cu + + +typedef unsigned char BYTE; +typedef BYTE REGWORD; // chip dependend maximum register length +typedef unsigned short REGWORD16; // chip dependend maximum register length +typedef unsigned int REGWORD32; // chip dependend maximum register length + + + + +//___________________________________________________________________________________// +// // +// HFC48Scu.h usage: // +//___________________________________________________________________________________// +// // +// How can this header file be used? The main idea is, to have names not only for // +// registers but also for every bitmap. The concept allows Bitmap access without // +// shifting the values to their real position. // +// // +// Every bitmap V_.. has a mask named M_.. where all mask bits are set. // +// If a bitmap has a length of more than 1 bit but less than the register width, // +// there are supplementary mask-values for every valid value, i.e. M1_.., M2_.., // +// .., M_.. // +// // +// In the following examples a procedure // +// writereg(BYTE port, REGWORD val) // writes val into port // +// // +// is used. This must be implemented by the user. // +// // +// For all examples the register A_CONF has been choosen. // +// // +// 1. Approach: access without variable // +// ------------------------------------ // +// // +// writereg(A_CONF, M3_CONF_NUM | M_CONF_EN); // initialisation: selected PCM // +// // time slot added to conference // +// // #3 without noise suppr. and // +// // 0 dB atten. level // +// // +// // ... // +// // +// a_conf.reg = M3_CONF_NUM | M_CONF_EN | M1_ATT_LEV | M3_NOISE_SUPPR; // +// // changing the settings: -3 dB // +// // atten. level and strong noise // +// // suppression // +// // +// When calculating bitmap values, please note, that incrementation / decrementation // +// must be done with m1_.. value! One must take care that a bitmap value is always // +// in the range 0 <= v_.. <= M_.. // +// // +// This 1st approach has the advantage that it needs no variable. But if read-back // +// functionality is required the next technique should be used. // +// // +// 2. Approach: access with read-back functionallity // +// ------------------------------------------------- // +// // +// reg_a_conf a_conf; // declaration of chip variable // +// // +// a_conf.bit.v_conf_num = 3; // initialization, // +// a_conf.bit.v_noise_suppr = 0; // same values as above // +// a_conf.bit.v_att_lev = 0; // // +// a_conf.bit.v_conf_en = 1; // // +// // +// writereg(A_CONF, a_conf.reg); // value transfer into the register // +// // +// Now it is possible to change one or more bitmaps: // +// // +// a_conf.bit.v_noise_suppr = m_att_lev; // strongest noise suppr. (same as // +// // m3_att_lev) // +// a_conf.bit.v_att_lev = m1_att_lev; // -3 dB atten. level // +// // +// a_conf.reg = a_conf.reg; // value transfer into the register // +// // +//___________________________________________________________________________________// + + + +/////////////////////////////////////////////////////////////////////////////////////// +// common data definition +/////////////////////////////////////////////////////////////////////////////////////// + + // chip information: + #define CHIP_NAME_4S "HFC-4S" + #define CHIP_NAME_8S "HFC-8S" + #define CHIP_TITLE_4S "ISDN HDLC FIFO controller with 4 S/T interfaces" + #define CHIP_TITLE_8S "ISDN HDLC FIFO controller with 8 S/T interfaces" + #define CHIP_MANUFACTURER "CologneChip" + #define CHIP_ID_4S 0x0C + #define CHIP_ID_8S 0x08 + #define CHIP_ID_SHIFT 4 + #define CHIP_REGISTER_COUNT 124 + #define CHIP_DATABASE "" + + // PCI configuration: + #define PCI_VENDOR_ID_CCD 0x1397 + #define PCI_DEVICE_ID_4S 0x08B4 + #define PCI_DEVICE_ID_8S 0x16B8 + #define PCI_REVISION_ID_4S 0x01 + #define PCI_REVISION_ID_8S 0x01 + + +/////////////////////////////////////////////////////////////////////////////////////// +// begin of register list +/////////////////////////////////////////////////////////////////////////////////////// + + +#define R_IRQ_STATECH 0x12 + +#define M_STATECH_ST0 0x01 +#define M_STATECH_ST1 0x02 +#define M_STATECH_ST2 0x04 +#define M_STATECH_ST3 0x08 +#define M_STATECH_ST4 0x10 +#define M_STATECH_ST5 0x20 +#define M_STATECH_ST6 0x40 +#define M_STATECH_ST7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_statech_st0:1; + REGWORD v_statech_st1:1; + REGWORD v_statech_st2:1; + REGWORD v_statech_st3:1; + REGWORD v_statech_st4:1; + REGWORD v_statech_st5:1; + REGWORD v_statech_st6:1; + REGWORD v_statech_st7:1; + } bit_r_irq_statech; + + typedef union {REGWORD reg; bit_r_irq_statech bit;} reg_r_irq_statech; // register and bitmap access + +#define R_IRQMSK_STATCHG 0x12 + +#define M_IRQMSK_STACHG_ST0 0x01 +#define M_IRQMSK_STACHG_ST1 0x02 +#define M_IRQMSK_STACHG_ST2 0x04 +#define M_IRQMSK_STACHG_ST3 0x08 +#define M_IRQMSK_STACHG_ST4 0x10 +#define M_IRQMSK_STACHG_ST5 0x20 +#define M_IRQMSK_STACHG_ST6 0x40 +#define M_IRQMSK_STACHG_ST7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irqmsk_stachg_st0:1; + REGWORD v_irqmsk_stachg_st1:1; + REGWORD v_irqmsk_stachg_st2:1; + REGWORD v_irqmsk_stachg_st3:1; + REGWORD v_irqmsk_stachg_st4:1; + REGWORD v_irqmsk_stachg_st5:1; + REGWORD v_irqmsk_stachg_st6:1; + REGWORD v_irqmsk_stachg_st7:1; + } bit_r_irqmsk_statchg; + + typedef union {REGWORD reg; bit_r_irqmsk_statchg bit;} reg_r_irqmsk_statchg; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_ST_SEL 0x16 + +#define M_ST_SEL 0x07 + #define M1_ST_SEL 0x01 + #define M2_ST_SEL 0x02 + #define M3_ST_SEL 0x03 + #define M4_ST_SEL 0x04 + #define M5_ST_SEL 0x05 + #define M6_ST_SEL 0x06 + #define M7_ST_SEL 0x07 +#define M_MULT_ST 0x08 + + typedef struct // bitmap construction + { + REGWORD v_st_sel:3; + REGWORD v_mult_st:1; + REGWORD reserved_0:4; + } bit_r_st_sel; + + typedef union {REGWORD reg; bit_r_st_sel bit;} reg_r_st_sel; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_ST_SYNC 0x17 + +#define M_SYNC_SEL 0x07 + #define M1_SYNC_SEL 0x01 + #define M2_SYNC_SEL 0x02 + #define M3_SYNC_SEL 0x03 + #define M4_SYNC_SEL 0x04 + #define M5_SYNC_SEL 0x05 + #define M6_SYNC_SEL 0x06 + #define M7_SYNC_SEL 0x07 +#define M_AUTO_SYNC 0x08 + + typedef struct // bitmap construction + { + REGWORD v_sync_sel:3; + REGWORD v_auto_sync:1; + REGWORD reserved_1:4; + } bit_r_st_sync; + + typedef union {REGWORD reg; bit_r_st_sync bit;} reg_r_st_sync; // register and bitmap access + +#define A_ST_RD_STA 0x30 + +#define M_ST_STA 0x0F + #define M1_ST_STA 0x01 + #define M2_ST_STA 0x02 + #define M3_ST_STA 0x03 + #define M4_ST_STA 0x04 + #define M5_ST_STA 0x05 + #define M6_ST_STA 0x06 + #define M7_ST_STA 0x07 + #define M8_ST_STA 0x08 + #define M9_ST_STA 0x09 + #define M10_ST_STA 0x0A + #define M11_ST_STA 0x0B + #define M12_ST_STA 0x0C + #define M13_ST_STA 0x0D + #define M14_ST_STA 0x0E + #define M15_ST_STA 0x0F +#define M_FR_SYNC 0x10 +#define M_TI2_EXP 0x20 +#define M_INFO0 0x40 +#define M_G2_G3 0x80 + + typedef struct // bitmap construction + { + REGWORD v_st_sta:4; + REGWORD v_fr_sync:1; + REGWORD v_ti2_exp:1; + REGWORD v_info0:1; + REGWORD v_g2_g3:1; + } bit_a_st_rd_sta; + + typedef union {REGWORD reg; bit_a_st_rd_sta bit;} reg_a_st_rd_sta; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_SQ_RD 0x34 + +#define M_ST_SQ 0x0F + #define M1_ST_SQ 0x01 + #define M2_ST_SQ 0x02 + #define M3_ST_SQ 0x03 + #define M4_ST_SQ 0x04 + #define M5_ST_SQ 0x05 + #define M6_ST_SQ 0x06 + #define M7_ST_SQ 0x07 + #define M8_ST_SQ 0x08 + #define M9_ST_SQ 0x09 + #define M10_ST_SQ 0x0A + #define M11_ST_SQ 0x0B + #define M12_ST_SQ 0x0C + #define M13_ST_SQ 0x0D + #define M14_ST_SQ 0x0E + #define M15_ST_SQ 0x0F +#define M_MF_RX_RDY 0x10 +#define M_MF_TX_RDY 0x80 + + typedef struct // bitmap construction + { + REGWORD v_st_sq:4; + REGWORD v_mf_rx_rdy:1; + REGWORD reserved_2:2; + REGWORD v_mf_tx_rdy:1; + } bit_a_st_sq_rd; + + typedef union {REGWORD reg; bit_a_st_sq_rd bit;} reg_a_st_sq_rd; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_B1_RX 0x3C + +#define M_ST_B1_RX 0xFF + + typedef struct // bitmap construction + { + REGWORD v_st_b1_rx:8; + } bit_a_st_b1_rx; + + typedef union {REGWORD reg; bit_a_st_b1_rx bit;} reg_a_st_b1_rx; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_B2_RX 0x3D + +#define M_ST_B2_RX 0xFF + + typedef struct // bitmap construction + { + REGWORD v_st_b2_rx:8; + } bit_a_st_b2_rx; + + typedef union {REGWORD reg; bit_a_st_b2_rx bit;} reg_a_st_b2_rx; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_D_RX 0x3E + +#define M_ST_D_RX 0xC0 + #define M1_ST_D_RX 0x40 + #define M2_ST_D_RX 0x80 + #define M3_ST_D_RX 0xC0 + + typedef struct // bitmap construction + { + REGWORD reserved_3:6; + REGWORD v_st_d_rx:2; + } bit_a_st_d_rx; + + typedef union {REGWORD reg; bit_a_st_d_rx bit;} reg_a_st_d_rx; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_E_RX 0x3F + +#define M_ST_E_RX 0xC0 + #define M1_ST_E_RX 0x40 + #define M2_ST_E_RX 0x80 + #define M3_ST_E_RX 0xC0 + + typedef struct // bitmap construction + { + REGWORD reserved_4:6; + REGWORD v_st_e_rx:2; + } bit_a_st_e_rx; + + typedef union {REGWORD reg; bit_a_st_e_rx bit;} reg_a_st_e_rx; // register and bitmap access + +#define A_ST_WR_STA 0x30 + +#define M_ST_SET_STA 0x0F + #define M1_ST_SET_STA 0x01 + #define M2_ST_SET_STA 0x02 + #define M3_ST_SET_STA 0x03 + #define M4_ST_SET_STA 0x04 + #define M5_ST_SET_STA 0x05 + #define M6_ST_SET_STA 0x06 + #define M7_ST_SET_STA 0x07 + #define M8_ST_SET_STA 0x08 + #define M9_ST_SET_STA 0x09 + #define M10_ST_SET_STA 0x0A + #define M11_ST_SET_STA 0x0B + #define M12_ST_SET_STA 0x0C + #define M13_ST_SET_STA 0x0D + #define M14_ST_SET_STA 0x0E + #define M15_ST_SET_STA 0x0F +#define M_ST_LD_STA 0x10 +#define M_ST_ACT 0x60 + #define M1_ST_ACT 0x20 + #define M2_ST_ACT 0x40 + #define M3_ST_ACT 0x60 +#define M_SET_G2_G3 0x80 + + typedef struct // bitmap construction + { + REGWORD v_st_set_sta:4; + REGWORD v_st_ld_sta:1; + REGWORD v_st_act:2; + REGWORD v_set_g2_g3:1; + } bit_a_st_wr_sta; + + typedef union {REGWORD reg; bit_a_st_wr_sta bit;} reg_a_st_wr_sta; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_CTRL0 0x31 + +#define M_B1_EN 0x01 +#define M_B2_EN 0x02 +#define M_ST_MD 0x04 +#define M_D_PRIO 0x08 +#define M_SQ_EN 0x10 +#define M_96KHZ 0x20 +#define M_TX_LI 0x40 +#define M_ST_STOP 0x80 + + typedef struct // bitmap construction + { + REGWORD v_b1_en:1; + REGWORD v_b2_en:1; + REGWORD v_st_md:1; + REGWORD v_d_prio:1; + REGWORD v_sq_en:1; + REGWORD v_96khz:1; + REGWORD v_tx_li:1; + REGWORD v_st_stop:1; + } bit_a_st_ctrl0; + + typedef union {REGWORD reg; bit_a_st_ctrl0 bit;} reg_a_st_ctrl0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_CTRL1 0x32 + +#define M_G2_G3_EN 0x01 +#define M_D_HI 0x04 +#define M_E_IGNO 0x08 +#define M_E_LO 0x10 +#define M_B12_SWAP 0x80 + + typedef struct // bitmap construction + { + REGWORD v_g2_g3_en:1; + REGWORD reserved_5:1; + REGWORD v_d_hi:1; + REGWORD v_e_igno:1; + REGWORD v_e_lo:1; + REGWORD reserved_6:2; + REGWORD v_b12_swap:1; + } bit_a_st_ctrl1; + + typedef union {REGWORD reg; bit_a_st_ctrl1 bit;} reg_a_st_ctrl1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_CTRL2 0x33 + +#define M_B1_RX_EN 0x01 +#define M_B2_RX_EN 0x02 +#define M_ST_TRIS 0x40 + + typedef struct // bitmap construction + { + REGWORD v_b1_rx_en:1; + REGWORD v_b2_rx_en:1; + REGWORD reserved_7:4; + REGWORD v_st_tris:1; + REGWORD reserved_8:1; + } bit_a_st_ctrl2; + + typedef union {REGWORD reg; bit_a_st_ctrl2 bit;} reg_a_st_ctrl2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_SQ_WR 0x34 + +#define M_ST_SQ 0x0F + #define M1_ST_SQ 0x01 + #define M2_ST_SQ 0x02 + #define M3_ST_SQ 0x03 + #define M4_ST_SQ 0x04 + #define M5_ST_SQ 0x05 + #define M6_ST_SQ 0x06 + #define M7_ST_SQ 0x07 + #define M8_ST_SQ 0x08 + #define M9_ST_SQ 0x09 + #define M10_ST_SQ 0x0A + #define M11_ST_SQ 0x0B + #define M12_ST_SQ 0x0C + #define M13_ST_SQ 0x0D + #define M14_ST_SQ 0x0E + #define M15_ST_SQ 0x0F + + typedef struct // bitmap construction + { + REGWORD v_st_sq:4; + REGWORD reserved_9:4; + } bit_a_st_sq_wr; + + typedef union {REGWORD reg; bit_a_st_sq_wr bit;} reg_a_st_sq_wr; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_CLK_DLY 0x37 + +#define M_ST_CLK_DLY 0x0F + #define M1_ST_CLK_DLY 0x01 + #define M2_ST_CLK_DLY 0x02 + #define M3_ST_CLK_DLY 0x03 + #define M4_ST_CLK_DLY 0x04 + #define M5_ST_CLK_DLY 0x05 + #define M6_ST_CLK_DLY 0x06 + #define M7_ST_CLK_DLY 0x07 + #define M8_ST_CLK_DLY 0x08 + #define M9_ST_CLK_DLY 0x09 + #define M10_ST_CLK_DLY 0x0A + #define M11_ST_CLK_DLY 0x0B + #define M12_ST_CLK_DLY 0x0C + #define M13_ST_CLK_DLY 0x0D + #define M14_ST_CLK_DLY 0x0E + #define M15_ST_CLK_DLY 0x0F +#define M_ST_SMPL 0x70 + #define M1_ST_SMPL 0x10 + #define M2_ST_SMPL 0x20 + #define M3_ST_SMPL 0x30 + #define M4_ST_SMPL 0x40 + #define M5_ST_SMPL 0x50 + #define M6_ST_SMPL 0x60 + #define M7_ST_SMPL 0x70 + + typedef struct // bitmap construction + { + REGWORD v_st_clk_dly:4; + REGWORD v_st_smpl:3; + REGWORD reserved_10:1; + } bit_a_st_clk_dly; + + typedef union {REGWORD reg; bit_a_st_clk_dly bit;} reg_a_st_clk_dly; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_B1_TX 0x3C + +#define M_ST_B1_TX 0xFF + + typedef struct // bitmap construction + { + REGWORD v_st_b1_tx:8; + } bit_a_st_b1_tx; + + typedef union {REGWORD reg; bit_a_st_b1_tx bit;} reg_a_st_b1_tx; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_B2_TX 0x3D + +#define M_ST_B2_TX 0xFF + + typedef struct // bitmap construction + { + REGWORD v_st_b2_tx:8; + } bit_a_st_b2_tx; + + typedef union {REGWORD reg; bit_a_st_b2_tx bit;} reg_a_st_b2_tx; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_ST_D_TX 0x3E + +#define M_ST_D_TX 0xC0 + #define M1_ST_D_TX 0x40 + #define M2_ST_D_TX 0x80 + #define M3_ST_D_TX 0xC0 + + typedef struct // bitmap construction + { + REGWORD reserved_11:6; + REGWORD v_st_d_tx:2; + } bit_a_st_d_tx; + + typedef union {REGWORD reg; bit_a_st_d_tx bit;} reg_a_st_d_tx; // register and bitmap access + +#define A_CHANNEL 0xFC + +#define M_CH_DIR 0x01 +#define M_CH0_SEL 0x3E + #define M1_CH0_SEL 0x02 + #define M2_CH0_SEL 0x04 + #define M3_CH0_SEL 0x06 + #define M4_CH0_SEL 0x08 + #define M5_CH0_SEL 0x0A + #define M6_CH0_SEL 0x0C + #define M7_CH0_SEL 0x0E + #define M8_CH0_SEL 0x10 + #define M9_CH0_SEL 0x12 + #define M10_CH0_SEL 0x14 + #define M11_CH0_SEL 0x16 + #define M12_CH0_SEL 0x18 + #define M13_CH0_SEL 0x1A + #define M14_CH0_SEL 0x1C + #define M15_CH0_SEL 0x1E + #define M16_CH0_SEL 0x20 + #define M17_CH0_SEL 0x22 + #define M18_CH0_SEL 0x24 + #define M19_CH0_SEL 0x26 + #define M20_CH0_SEL 0x28 + #define M21_CH0_SEL 0x2A + #define M22_CH0_SEL 0x2C + #define M23_CH0_SEL 0x2E + #define M24_CH0_SEL 0x30 + #define M25_CH0_SEL 0x32 + #define M26_CH0_SEL 0x34 + #define M27_CH0_SEL 0x36 + #define M28_CH0_SEL 0x38 + #define M29_CH0_SEL 0x3A + #define M30_CH0_SEL 0x3C + #define M31_CH0_SEL 0x3E + + typedef struct // bitmap construction + { + REGWORD v_ch_dir:1; + REGWORD v_ch0_sel:5; + REGWORD reserved_12:2; + } bit_a_channel; + + typedef union {REGWORD reg; bit_a_channel bit;} reg_a_channel; // register and bitmap access + +#define A_Z1L 0x04 + +#define M_Z1L 0xFF + + typedef struct // bitmap construction + { + REGWORD v_z1l:8; + } bit_a_z1l; + + typedef union {REGWORD reg; bit_a_z1l bit;} reg_a_z1l; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z1H 0x05 + +#define M_Z1H 0xFF + + typedef struct // bitmap construction + { + REGWORD v_z1h:8; + } bit_a_z1h; + + typedef union {REGWORD reg; bit_a_z1h bit;} reg_a_z1h; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z1 0x04 + +#define M_Z1 0xFFFF + + typedef struct // bitmap construction + { + REGWORD16 v_z1:16; + } bit_a_z1; + + typedef union {REGWORD reg; bit_a_z1 bit;} reg_a_z1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z2L 0x06 + +#define M_Z2L 0xFF + + typedef struct // bitmap construction + { + REGWORD v_z2l:8; + } bit_a_z2l; + + typedef union {REGWORD reg; bit_a_z2l bit;} reg_a_z2l; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z2H 0x07 + +#define M_Z2H 0xFF + + typedef struct // bitmap construction + { + REGWORD v_z2h:8; + } bit_a_z2h; + + typedef union {REGWORD reg; bit_a_z2h bit;} reg_a_z2h; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z2 0x06 + +#define M_Z2 0xFFFF + + typedef struct // bitmap construction + { + REGWORD16 v_z2:16; + } bit_a_z2; + + typedef union {REGWORD reg; bit_a_z2 bit;} reg_a_z2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_Z12 0x04 + +#define M_Z12 0xFFFFFFFF + + #ifdef COMPILER_32BIT // can be defined by user to allow 32 bit compiler mode + typedef struct // bitmap construction + { + REGWORD32 v_z12:32; + } bit_a_z12; + + typedef union {REGWORD reg; bit_a_z12 bit;} reg_a_z12; // register and bitmap access + #endif + +//___________________________________________________________________________________// +// // +#define A_F1 0x0C + +#define M_F1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_f1:8; + } bit_a_f1; + + typedef union {REGWORD reg; bit_a_f1 bit;} reg_a_f1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_F2 0x0D + +#define M_F2 0xFF + + typedef struct // bitmap construction + { + REGWORD v_f2:8; + } bit_a_f2; + + typedef union {REGWORD reg; bit_a_f2 bit;} reg_a_f2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_F12 0x0C + +#define M_F12 0xFFFF + + typedef struct // bitmap construction + { + REGWORD16 v_f12:16; + } bit_a_f12; + + typedef union {REGWORD reg; bit_a_f12 bit;} reg_a_f12; // register and bitmap access + +#define R_CIRM 0x00 + +#define M_IRQ_SEL 0x07 + #define M1_IRQ_SEL 0x01 + #define M2_IRQ_SEL 0x02 + #define M3_IRQ_SEL 0x03 + #define M4_IRQ_SEL 0x04 + #define M5_IRQ_SEL 0x05 + #define M6_IRQ_SEL 0x06 + #define M7_IRQ_SEL 0x07 +#define M_SRES 0x08 +#define M_HFCRES 0x10 +#define M_PCMRES 0x20 +#define M_STRES 0x40 +#define M_RLD_EPR 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_sel:3; + REGWORD v_sres:1; + REGWORD v_hfcres:1; + REGWORD v_pcmres:1; + REGWORD v_stres:1; + REGWORD v_rld_epr:1; + } bit_r_cirm; + + typedef union {REGWORD reg; bit_r_cirm bit;} reg_r_cirm; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_CTRL 0x01 + +#define M_FIFO_LPRIO 0x02 +#define M_SLOW_RD 0x04 +#define M_EXT_RAM 0x08 +#define M_CLK_OFF 0x20 + + typedef struct // bitmap construction + { + REGWORD reserved_13:1; + REGWORD v_fifo_lprio:1; + REGWORD v_slow_rd:1; + REGWORD v_ext_ram:1; + REGWORD reserved_14:1; + REGWORD v_clk_off:1; + REGWORD reserved_15v_st_clk:2; + } bit_r_ctrl; + + typedef union {REGWORD reg; bit_r_ctrl bit;} reg_r_ctrl; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_PCM_CFG 0x02 + +#define M_BRG_EN 0x01 +#define M_BRG_MD 0x02 +#define M_PCM_CLK 0x20 + + typedef struct // bitmap construction + { + REGWORD v_brg_en:1; + REGWORD v_brg_md:1; + REGWORD reserved_16:3; + REGWORD v_pcm_clk:1; + REGWORD reserved_17v_addr_wrdly:2; + } bit_r_brg_pcm_cfg; + + typedef union {REGWORD reg; bit_r_brg_pcm_cfg bit;} reg_r_brg_pcm_cfg; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_RAM_ADDR0 0x08 + +#define M_RAM_ADDR0 0xFF + + typedef struct // bitmap construction + { + REGWORD v_ram_addr0:8; + } bit_r_ram_addr0; + + typedef union {REGWORD reg; bit_r_ram_addr0 bit;} reg_r_ram_addr0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_RAM_ADDR1 0x09 + +#define M_RAM_ADDR1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_ram_addr1:8; + } bit_r_ram_addr1; + + typedef union {REGWORD reg; bit_r_ram_addr1 bit;} reg_r_ram_addr1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_RAM_ADDR2 0x0A + +#define M_RAM_ADDR2 0x0F + #define M1_RAM_ADDR2 0x01 + #define M2_RAM_ADDR2 0x02 + #define M3_RAM_ADDR2 0x03 + #define M4_RAM_ADDR2 0x04 + #define M5_RAM_ADDR2 0x05 + #define M6_RAM_ADDR2 0x06 + #define M7_RAM_ADDR2 0x07 + #define M8_RAM_ADDR2 0x08 + #define M9_RAM_ADDR2 0x09 + #define M10_RAM_ADDR2 0x0A + #define M11_RAM_ADDR2 0x0B + #define M12_RAM_ADDR2 0x0C + #define M13_RAM_ADDR2 0x0D + #define M14_RAM_ADDR2 0x0E + #define M15_RAM_ADDR2 0x0F +#define M_ADDR_RES 0x40 +#define M_ADDR_INC 0x80 + + typedef struct // bitmap construction + { + REGWORD v_ram_addr2:4; + REGWORD reserved_18:2; + REGWORD v_addr_res:1; + REGWORD v_addr_inc:1; + } bit_r_ram_addr2; + + typedef union {REGWORD reg; bit_r_ram_addr2 bit;} reg_r_ram_addr2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_FIRST_FIFO 0x0B + +#define M_FIRST_FIFO_DIR 0x01 +#define M_FIRST_FIFO_NUM 0x3E + #define M1_FIRST_FIFO_NUM 0x02 + #define M2_FIRST_FIFO_NUM 0x04 + #define M3_FIRST_FIFO_NUM 0x06 + #define M4_FIRST_FIFO_NUM 0x08 + #define M5_FIRST_FIFO_NUM 0x0A + #define M6_FIRST_FIFO_NUM 0x0C + #define M7_FIRST_FIFO_NUM 0x0E + #define M8_FIRST_FIFO_NUM 0x10 + #define M9_FIRST_FIFO_NUM 0x12 + #define M10_FIRST_FIFO_NUM 0x14 + #define M11_FIRST_FIFO_NUM 0x16 + #define M12_FIRST_FIFO_NUM 0x18 + #define M13_FIRST_FIFO_NUM 0x1A + #define M14_FIRST_FIFO_NUM 0x1C + #define M15_FIRST_FIFO_NUM 0x1E + #define M16_FIRST_FIFO_NUM 0x20 + #define M17_FIRST_FIFO_NUM 0x22 + #define M18_FIRST_FIFO_NUM 0x24 + #define M19_FIRST_FIFO_NUM 0x26 + #define M20_FIRST_FIFO_NUM 0x28 + #define M21_FIRST_FIFO_NUM 0x2A + #define M22_FIRST_FIFO_NUM 0x2C + #define M23_FIRST_FIFO_NUM 0x2E + #define M24_FIRST_FIFO_NUM 0x30 + #define M25_FIRST_FIFO_NUM 0x32 + #define M26_FIRST_FIFO_NUM 0x34 + #define M27_FIRST_FIFO_NUM 0x36 + #define M28_FIRST_FIFO_NUM 0x38 + #define M29_FIRST_FIFO_NUM 0x3A + #define M30_FIRST_FIFO_NUM 0x3C + #define M31_FIRST_FIFO_NUM 0x3E + + typedef struct // bitmap construction + { + REGWORD v_first_fifo_dir:1; + REGWORD v_first_fifo_num:5; + REGWORD reserved_19:2; + } bit_r_first_fifo; + + typedef union {REGWORD reg; bit_r_first_fifo bit;} reg_r_first_fifo; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_RAM_SZ 0x0C + +#define M_RAM_SZ 0x03 + #define M1_RAM_SZ 0x01 + #define M2_RAM_SZ 0x02 + #define M3_RAM_SZ 0x03 + #define V_FZ_MD 0x80 + + typedef struct // bitmap construction + { + REGWORD v_ram_sz:2; + REGWORD reserved_20:6; + } bit_r_ram_sz; + + typedef union {REGWORD reg; bit_r_ram_sz bit;} reg_r_ram_sz; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_FIFO_MD 0x0D + +#define M_FIFO_MD 0x03 + #define M1_FIFO_MD 0x01 + #define M2_FIFO_MD 0x02 + #define M3_FIFO_MD 0x03 +#define M_CSM_MD 0x04 +#define M_FSM_MD 0x08 +#define M_FIFO_SZ 0x30 + #define M1_FIFO_SZ 0x10 + #define M2_FIFO_SZ 0x20 + #define M3_FIFO_SZ 0x30 + + typedef struct // bitmap construction + { + REGWORD v_fifo_md:2; + REGWORD v_csm_md:1; + REGWORD v_fsm_md:1; + REGWORD v_fifo_sz:2; + REGWORD reserved_21:2; + } bit_r_fifo_md; + + typedef union {REGWORD reg; bit_r_fifo_md bit;} reg_r_fifo_md; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_INC_RES_FIFO 0x0E + +#define M_INC_F 0x01 +#define M_RES_F 0x02 +#define M_RES_LOST 0x04 + + typedef struct // bitmap construction + { + REGWORD v_inc_f:1; + REGWORD v_res_f:1; + REGWORD v_res_lost:1; + REGWORD reserved_22:5; + } bit_r_inc_res_fifo; + + typedef union {REGWORD reg; bit_r_inc_res_fifo bit;} reg_r_inc_res_fifo; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_FIFO 0x0F + +#define M_FIFO_DIR 0x01 +#define M_FIFO_NUM 0x3E + #define M1_FIFO_NUM 0x02 + #define M2_FIFO_NUM 0x04 + #define M3_FIFO_NUM 0x06 + #define M4_FIFO_NUM 0x08 + #define M5_FIFO_NUM 0x0A + #define M6_FIFO_NUM 0x0C + #define M7_FIFO_NUM 0x0E + #define M8_FIFO_NUM 0x10 + #define M9_FIFO_NUM 0x12 + #define M10_FIFO_NUM 0x14 + #define M11_FIFO_NUM 0x16 + #define M12_FIFO_NUM 0x18 + #define M13_FIFO_NUM 0x1A + #define M14_FIFO_NUM 0x1C + #define M15_FIFO_NUM 0x1E + #define M16_FIFO_NUM 0x20 + #define M17_FIFO_NUM 0x22 + #define M18_FIFO_NUM 0x24 + #define M19_FIFO_NUM 0x26 + #define M20_FIFO_NUM 0x28 + #define M21_FIFO_NUM 0x2A + #define M22_FIFO_NUM 0x2C + #define M23_FIFO_NUM 0x2E + #define M24_FIFO_NUM 0x30 + #define M25_FIFO_NUM 0x32 + #define M26_FIFO_NUM 0x34 + #define M27_FIFO_NUM 0x36 + #define M28_FIFO_NUM 0x38 + #define M29_FIFO_NUM 0x3A + #define M30_FIFO_NUM 0x3C + #define M31_FIFO_NUM 0x3E +#define M_REV 0x80 + + typedef struct // bitmap construction + { + REGWORD v_fifo_dir:1; + REGWORD v_fifo_num:5; + REGWORD reserved_23:1; + REGWORD v_rev:1; + } bit_r_fifo; + + typedef union {REGWORD reg; bit_r_fifo bit;} reg_r_fifo; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_FSM_IDX 0x0F + +#define M_IDX 0x3F + #define M1_IDX 0x01 + #define M2_IDX 0x02 + #define M3_IDX 0x03 + #define M4_IDX 0x04 + #define M5_IDX 0x05 + #define M6_IDX 0x06 + #define M7_IDX 0x07 + #define M8_IDX 0x08 + #define M9_IDX 0x09 + #define M10_IDX 0x0A + #define M11_IDX 0x0B + #define M12_IDX 0x0C + #define M13_IDX 0x0D + #define M14_IDX 0x0E + #define M15_IDX 0x0F + #define M16_IDX 0x10 + #define M17_IDX 0x11 + #define M18_IDX 0x12 + #define M19_IDX 0x13 + #define M20_IDX 0x14 + #define M21_IDX 0x15 + #define M22_IDX 0x16 + #define M23_IDX 0x17 + #define M24_IDX 0x18 + #define M25_IDX 0x19 + #define M26_IDX 0x1A + #define M27_IDX 0x1B + #define M28_IDX 0x1C + #define M29_IDX 0x1D + #define M30_IDX 0x1E + #define M31_IDX 0x1F + #define M32_IDX 0x20 + #define M33_IDX 0x21 + #define M34_IDX 0x22 + #define M35_IDX 0x23 + #define M36_IDX 0x24 + #define M37_IDX 0x25 + #define M38_IDX 0x26 + #define M39_IDX 0x27 + #define M40_IDX 0x28 + #define M41_IDX 0x29 + #define M42_IDX 0x2A + #define M43_IDX 0x2B + #define M44_IDX 0x2C + #define M45_IDX 0x2D + #define M46_IDX 0x2E + #define M47_IDX 0x2F + #define M48_IDX 0x30 + #define M49_IDX 0x31 + #define M50_IDX 0x32 + #define M51_IDX 0x33 + #define M52_IDX 0x34 + #define M53_IDX 0x35 + #define M54_IDX 0x36 + #define M55_IDX 0x37 + #define M56_IDX 0x38 + #define M57_IDX 0x39 + #define M58_IDX 0x3A + #define M59_IDX 0x3B + #define M60_IDX 0x3C + #define M61_IDX 0x3D + #define M62_IDX 0x3E + #define M63_IDX 0x3F + + typedef struct // bitmap construction + { + REGWORD v_idx:6; + REGWORD reserved_24:2; + } bit_r_fsm_idx; + + typedef union {REGWORD reg; bit_r_fsm_idx bit;} reg_r_fsm_idx; // register and bitmap access + +#define R_SRAM_USE 0x15 + +#define M_SRAM_USE 0xFF + + typedef struct // bitmap construction + { + REGWORD v_sram_use:8; + } bit_r_sram_use; + + typedef union {REGWORD reg; bit_r_sram_use bit;} reg_r_sram_use; // register and bitmap access + +#define R_SL_SEL0 0x15 + +#define M_SL_SEL0 0x7F + #define M1_SL_SEL0 0x01 + #define M2_SL_SEL0 0x02 + #define M3_SL_SEL0 0x03 + #define M4_SL_SEL0 0x04 + #define M5_SL_SEL0 0x05 + #define M6_SL_SEL0 0x06 + #define M7_SL_SEL0 0x07 + #define M8_SL_SEL0 0x08 + #define M9_SL_SEL0 0x09 + #define M10_SL_SEL0 0x0A + #define M11_SL_SEL0 0x0B + #define M12_SL_SEL0 0x0C + #define M13_SL_SEL0 0x0D + #define M14_SL_SEL0 0x0E + #define M15_SL_SEL0 0x0F + #define M16_SL_SEL0 0x10 + #define M17_SL_SEL0 0x11 + #define M18_SL_SEL0 0x12 + #define M19_SL_SEL0 0x13 + #define M20_SL_SEL0 0x14 + #define M21_SL_SEL0 0x15 + #define M22_SL_SEL0 0x16 + #define M23_SL_SEL0 0x17 + #define M24_SL_SEL0 0x18 + #define M25_SL_SEL0 0x19 + #define M26_SL_SEL0 0x1A + #define M27_SL_SEL0 0x1B + #define M28_SL_SEL0 0x1C + #define M29_SL_SEL0 0x1D + #define M30_SL_SEL0 0x1E + #define M31_SL_SEL0 0x1F + #define M32_SL_SEL0 0x20 + #define M33_SL_SEL0 0x21 + #define M34_SL_SEL0 0x22 + #define M35_SL_SEL0 0x23 + #define M36_SL_SEL0 0x24 + #define M37_SL_SEL0 0x25 + #define M38_SL_SEL0 0x26 + #define M39_SL_SEL0 0x27 + #define M40_SL_SEL0 0x28 + #define M41_SL_SEL0 0x29 + #define M42_SL_SEL0 0x2A + #define M43_SL_SEL0 0x2B + #define M44_SL_SEL0 0x2C + #define M45_SL_SEL0 0x2D + #define M46_SL_SEL0 0x2E + #define M47_SL_SEL0 0x2F + #define M48_SL_SEL0 0x30 + #define M49_SL_SEL0 0x31 + #define M50_SL_SEL0 0x32 + #define M51_SL_SEL0 0x33 + #define M52_SL_SEL0 0x34 + #define M53_SL_SEL0 0x35 + #define M54_SL_SEL0 0x36 + #define M55_SL_SEL0 0x37 + #define M56_SL_SEL0 0x38 + #define M57_SL_SEL0 0x39 + #define M58_SL_SEL0 0x3A + #define M59_SL_SEL0 0x3B + #define M60_SL_SEL0 0x3C + #define M61_SL_SEL0 0x3D + #define M62_SL_SEL0 0x3E + #define M63_SL_SEL0 0x3F + #define M64_SL_SEL0 0x40 + #define M65_SL_SEL0 0x41 + #define M66_SL_SEL0 0x42 + #define M67_SL_SEL0 0x43 + #define M68_SL_SEL0 0x44 + #define M69_SL_SEL0 0x45 + #define M70_SL_SEL0 0x46 + #define M71_SL_SEL0 0x47 + #define M72_SL_SEL0 0x48 + #define M73_SL_SEL0 0x49 + #define M74_SL_SEL0 0x4A + #define M75_SL_SEL0 0x4B + #define M76_SL_SEL0 0x4C + #define M77_SL_SEL0 0x4D + #define M78_SL_SEL0 0x4E + #define M79_SL_SEL0 0x4F + #define M80_SL_SEL0 0x50 + #define M81_SL_SEL0 0x51 + #define M82_SL_SEL0 0x52 + #define M83_SL_SEL0 0x53 + #define M84_SL_SEL0 0x54 + #define M85_SL_SEL0 0x55 + #define M86_SL_SEL0 0x56 + #define M87_SL_SEL0 0x57 + #define M88_SL_SEL0 0x58 + #define M89_SL_SEL0 0x59 + #define M90_SL_SEL0 0x5A + #define M91_SL_SEL0 0x5B + #define M92_SL_SEL0 0x5C + #define M93_SL_SEL0 0x5D + #define M94_SL_SEL0 0x5E + #define M95_SL_SEL0 0x5F + #define M96_SL_SEL0 0x60 + #define M97_SL_SEL0 0x61 + #define M98_SL_SEL0 0x62 + #define M99_SL_SEL0 0x63 + #define M100_SL_SEL0 0x64 + #define M101_SL_SEL0 0x65 + #define M102_SL_SEL0 0x66 + #define M103_SL_SEL0 0x67 + #define M104_SL_SEL0 0x68 + #define M105_SL_SEL0 0x69 + #define M106_SL_SEL0 0x6A + #define M107_SL_SEL0 0x6B + #define M108_SL_SEL0 0x6C + #define M109_SL_SEL0 0x6D + #define M110_SL_SEL0 0x6E + #define M111_SL_SEL0 0x6F + #define M112_SL_SEL0 0x70 + #define M113_SL_SEL0 0x71 + #define M114_SL_SEL0 0x72 + #define M115_SL_SEL0 0x73 + #define M116_SL_SEL0 0x74 + #define M117_SL_SEL0 0x75 + #define M118_SL_SEL0 0x76 + #define M119_SL_SEL0 0x77 + #define M120_SL_SEL0 0x78 + #define M121_SL_SEL0 0x79 + #define M122_SL_SEL0 0x7A + #define M123_SL_SEL0 0x7B + #define M124_SL_SEL0 0x7C + #define M125_SL_SEL0 0x7D + #define M126_SL_SEL0 0x7E + #define M127_SL_SEL0 0x7F +#define M_SH_SEL0 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel0:7; + REGWORD v_sh_sel0:1; + } bit_r_sl_sel0; + + typedef union {REGWORD reg; bit_r_sl_sel0 bit;} reg_r_sl_sel0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL1 0x15 + +#define M_SL_SEL1 0x7F + #define M1_SL_SEL1 0x01 + #define M2_SL_SEL1 0x02 + #define M3_SL_SEL1 0x03 + #define M4_SL_SEL1 0x04 + #define M5_SL_SEL1 0x05 + #define M6_SL_SEL1 0x06 + #define M7_SL_SEL1 0x07 + #define M8_SL_SEL1 0x08 + #define M9_SL_SEL1 0x09 + #define M10_SL_SEL1 0x0A + #define M11_SL_SEL1 0x0B + #define M12_SL_SEL1 0x0C + #define M13_SL_SEL1 0x0D + #define M14_SL_SEL1 0x0E + #define M15_SL_SEL1 0x0F + #define M16_SL_SEL1 0x10 + #define M17_SL_SEL1 0x11 + #define M18_SL_SEL1 0x12 + #define M19_SL_SEL1 0x13 + #define M20_SL_SEL1 0x14 + #define M21_SL_SEL1 0x15 + #define M22_SL_SEL1 0x16 + #define M23_SL_SEL1 0x17 + #define M24_SL_SEL1 0x18 + #define M25_SL_SEL1 0x19 + #define M26_SL_SEL1 0x1A + #define M27_SL_SEL1 0x1B + #define M28_SL_SEL1 0x1C + #define M29_SL_SEL1 0x1D + #define M30_SL_SEL1 0x1E + #define M31_SL_SEL1 0x1F + #define M32_SL_SEL1 0x20 + #define M33_SL_SEL1 0x21 + #define M34_SL_SEL1 0x22 + #define M35_SL_SEL1 0x23 + #define M36_SL_SEL1 0x24 + #define M37_SL_SEL1 0x25 + #define M38_SL_SEL1 0x26 + #define M39_SL_SEL1 0x27 + #define M40_SL_SEL1 0x28 + #define M41_SL_SEL1 0x29 + #define M42_SL_SEL1 0x2A + #define M43_SL_SEL1 0x2B + #define M44_SL_SEL1 0x2C + #define M45_SL_SEL1 0x2D + #define M46_SL_SEL1 0x2E + #define M47_SL_SEL1 0x2F + #define M48_SL_SEL1 0x30 + #define M49_SL_SEL1 0x31 + #define M50_SL_SEL1 0x32 + #define M51_SL_SEL1 0x33 + #define M52_SL_SEL1 0x34 + #define M53_SL_SEL1 0x35 + #define M54_SL_SEL1 0x36 + #define M55_SL_SEL1 0x37 + #define M56_SL_SEL1 0x38 + #define M57_SL_SEL1 0x39 + #define M58_SL_SEL1 0x3A + #define M59_SL_SEL1 0x3B + #define M60_SL_SEL1 0x3C + #define M61_SL_SEL1 0x3D + #define M62_SL_SEL1 0x3E + #define M63_SL_SEL1 0x3F + #define M64_SL_SEL1 0x40 + #define M65_SL_SEL1 0x41 + #define M66_SL_SEL1 0x42 + #define M67_SL_SEL1 0x43 + #define M68_SL_SEL1 0x44 + #define M69_SL_SEL1 0x45 + #define M70_SL_SEL1 0x46 + #define M71_SL_SEL1 0x47 + #define M72_SL_SEL1 0x48 + #define M73_SL_SEL1 0x49 + #define M74_SL_SEL1 0x4A + #define M75_SL_SEL1 0x4B + #define M76_SL_SEL1 0x4C + #define M77_SL_SEL1 0x4D + #define M78_SL_SEL1 0x4E + #define M79_SL_SEL1 0x4F + #define M80_SL_SEL1 0x50 + #define M81_SL_SEL1 0x51 + #define M82_SL_SEL1 0x52 + #define M83_SL_SEL1 0x53 + #define M84_SL_SEL1 0x54 + #define M85_SL_SEL1 0x55 + #define M86_SL_SEL1 0x56 + #define M87_SL_SEL1 0x57 + #define M88_SL_SEL1 0x58 + #define M89_SL_SEL1 0x59 + #define M90_SL_SEL1 0x5A + #define M91_SL_SEL1 0x5B + #define M92_SL_SEL1 0x5C + #define M93_SL_SEL1 0x5D + #define M94_SL_SEL1 0x5E + #define M95_SL_SEL1 0x5F + #define M96_SL_SEL1 0x60 + #define M97_SL_SEL1 0x61 + #define M98_SL_SEL1 0x62 + #define M99_SL_SEL1 0x63 + #define M100_SL_SEL1 0x64 + #define M101_SL_SEL1 0x65 + #define M102_SL_SEL1 0x66 + #define M103_SL_SEL1 0x67 + #define M104_SL_SEL1 0x68 + #define M105_SL_SEL1 0x69 + #define M106_SL_SEL1 0x6A + #define M107_SL_SEL1 0x6B + #define M108_SL_SEL1 0x6C + #define M109_SL_SEL1 0x6D + #define M110_SL_SEL1 0x6E + #define M111_SL_SEL1 0x6F + #define M112_SL_SEL1 0x70 + #define M113_SL_SEL1 0x71 + #define M114_SL_SEL1 0x72 + #define M115_SL_SEL1 0x73 + #define M116_SL_SEL1 0x74 + #define M117_SL_SEL1 0x75 + #define M118_SL_SEL1 0x76 + #define M119_SL_SEL1 0x77 + #define M120_SL_SEL1 0x78 + #define M121_SL_SEL1 0x79 + #define M122_SL_SEL1 0x7A + #define M123_SL_SEL1 0x7B + #define M124_SL_SEL1 0x7C + #define M125_SL_SEL1 0x7D + #define M126_SL_SEL1 0x7E + #define M127_SL_SEL1 0x7F +#define M_SH_SEL1 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel1:7; + REGWORD v_sh_sel1:1; + } bit_r_sl_sel1; + + typedef union {REGWORD reg; bit_r_sl_sel1 bit;} reg_r_sl_sel1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL2 0x15 + +#define M_SL_SEL2 0x7F + #define M1_SL_SEL2 0x01 + #define M2_SL_SEL2 0x02 + #define M3_SL_SEL2 0x03 + #define M4_SL_SEL2 0x04 + #define M5_SL_SEL2 0x05 + #define M6_SL_SEL2 0x06 + #define M7_SL_SEL2 0x07 + #define M8_SL_SEL2 0x08 + #define M9_SL_SEL2 0x09 + #define M10_SL_SEL2 0x0A + #define M11_SL_SEL2 0x0B + #define M12_SL_SEL2 0x0C + #define M13_SL_SEL2 0x0D + #define M14_SL_SEL2 0x0E + #define M15_SL_SEL2 0x0F + #define M16_SL_SEL2 0x10 + #define M17_SL_SEL2 0x11 + #define M18_SL_SEL2 0x12 + #define M19_SL_SEL2 0x13 + #define M20_SL_SEL2 0x14 + #define M21_SL_SEL2 0x15 + #define M22_SL_SEL2 0x16 + #define M23_SL_SEL2 0x17 + #define M24_SL_SEL2 0x18 + #define M25_SL_SEL2 0x19 + #define M26_SL_SEL2 0x1A + #define M27_SL_SEL2 0x1B + #define M28_SL_SEL2 0x1C + #define M29_SL_SEL2 0x1D + #define M30_SL_SEL2 0x1E + #define M31_SL_SEL2 0x1F + #define M32_SL_SEL2 0x20 + #define M33_SL_SEL2 0x21 + #define M34_SL_SEL2 0x22 + #define M35_SL_SEL2 0x23 + #define M36_SL_SEL2 0x24 + #define M37_SL_SEL2 0x25 + #define M38_SL_SEL2 0x26 + #define M39_SL_SEL2 0x27 + #define M40_SL_SEL2 0x28 + #define M41_SL_SEL2 0x29 + #define M42_SL_SEL2 0x2A + #define M43_SL_SEL2 0x2B + #define M44_SL_SEL2 0x2C + #define M45_SL_SEL2 0x2D + #define M46_SL_SEL2 0x2E + #define M47_SL_SEL2 0x2F + #define M48_SL_SEL2 0x30 + #define M49_SL_SEL2 0x31 + #define M50_SL_SEL2 0x32 + #define M51_SL_SEL2 0x33 + #define M52_SL_SEL2 0x34 + #define M53_SL_SEL2 0x35 + #define M54_SL_SEL2 0x36 + #define M55_SL_SEL2 0x37 + #define M56_SL_SEL2 0x38 + #define M57_SL_SEL2 0x39 + #define M58_SL_SEL2 0x3A + #define M59_SL_SEL2 0x3B + #define M60_SL_SEL2 0x3C + #define M61_SL_SEL2 0x3D + #define M62_SL_SEL2 0x3E + #define M63_SL_SEL2 0x3F + #define M64_SL_SEL2 0x40 + #define M65_SL_SEL2 0x41 + #define M66_SL_SEL2 0x42 + #define M67_SL_SEL2 0x43 + #define M68_SL_SEL2 0x44 + #define M69_SL_SEL2 0x45 + #define M70_SL_SEL2 0x46 + #define M71_SL_SEL2 0x47 + #define M72_SL_SEL2 0x48 + #define M73_SL_SEL2 0x49 + #define M74_SL_SEL2 0x4A + #define M75_SL_SEL2 0x4B + #define M76_SL_SEL2 0x4C + #define M77_SL_SEL2 0x4D + #define M78_SL_SEL2 0x4E + #define M79_SL_SEL2 0x4F + #define M80_SL_SEL2 0x50 + #define M81_SL_SEL2 0x51 + #define M82_SL_SEL2 0x52 + #define M83_SL_SEL2 0x53 + #define M84_SL_SEL2 0x54 + #define M85_SL_SEL2 0x55 + #define M86_SL_SEL2 0x56 + #define M87_SL_SEL2 0x57 + #define M88_SL_SEL2 0x58 + #define M89_SL_SEL2 0x59 + #define M90_SL_SEL2 0x5A + #define M91_SL_SEL2 0x5B + #define M92_SL_SEL2 0x5C + #define M93_SL_SEL2 0x5D + #define M94_SL_SEL2 0x5E + #define M95_SL_SEL2 0x5F + #define M96_SL_SEL2 0x60 + #define M97_SL_SEL2 0x61 + #define M98_SL_SEL2 0x62 + #define M99_SL_SEL2 0x63 + #define M100_SL_SEL2 0x64 + #define M101_SL_SEL2 0x65 + #define M102_SL_SEL2 0x66 + #define M103_SL_SEL2 0x67 + #define M104_SL_SEL2 0x68 + #define M105_SL_SEL2 0x69 + #define M106_SL_SEL2 0x6A + #define M107_SL_SEL2 0x6B + #define M108_SL_SEL2 0x6C + #define M109_SL_SEL2 0x6D + #define M110_SL_SEL2 0x6E + #define M111_SL_SEL2 0x6F + #define M112_SL_SEL2 0x70 + #define M113_SL_SEL2 0x71 + #define M114_SL_SEL2 0x72 + #define M115_SL_SEL2 0x73 + #define M116_SL_SEL2 0x74 + #define M117_SL_SEL2 0x75 + #define M118_SL_SEL2 0x76 + #define M119_SL_SEL2 0x77 + #define M120_SL_SEL2 0x78 + #define M121_SL_SEL2 0x79 + #define M122_SL_SEL2 0x7A + #define M123_SL_SEL2 0x7B + #define M124_SL_SEL2 0x7C + #define M125_SL_SEL2 0x7D + #define M126_SL_SEL2 0x7E + #define M127_SL_SEL2 0x7F +#define M_SH_SEL2 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel2:7; + REGWORD v_sh_sel2:1; + } bit_r_sl_sel2; + + typedef union {REGWORD reg; bit_r_sl_sel2 bit;} reg_r_sl_sel2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL3 0x15 + +#define M_SL_SEL3 0x7F + #define M1_SL_SEL3 0x01 + #define M2_SL_SEL3 0x02 + #define M3_SL_SEL3 0x03 + #define M4_SL_SEL3 0x04 + #define M5_SL_SEL3 0x05 + #define M6_SL_SEL3 0x06 + #define M7_SL_SEL3 0x07 + #define M8_SL_SEL3 0x08 + #define M9_SL_SEL3 0x09 + #define M10_SL_SEL3 0x0A + #define M11_SL_SEL3 0x0B + #define M12_SL_SEL3 0x0C + #define M13_SL_SEL3 0x0D + #define M14_SL_SEL3 0x0E + #define M15_SL_SEL3 0x0F + #define M16_SL_SEL3 0x10 + #define M17_SL_SEL3 0x11 + #define M18_SL_SEL3 0x12 + #define M19_SL_SEL3 0x13 + #define M20_SL_SEL3 0x14 + #define M21_SL_SEL3 0x15 + #define M22_SL_SEL3 0x16 + #define M23_SL_SEL3 0x17 + #define M24_SL_SEL3 0x18 + #define M25_SL_SEL3 0x19 + #define M26_SL_SEL3 0x1A + #define M27_SL_SEL3 0x1B + #define M28_SL_SEL3 0x1C + #define M29_SL_SEL3 0x1D + #define M30_SL_SEL3 0x1E + #define M31_SL_SEL3 0x1F + #define M32_SL_SEL3 0x20 + #define M33_SL_SEL3 0x21 + #define M34_SL_SEL3 0x22 + #define M35_SL_SEL3 0x23 + #define M36_SL_SEL3 0x24 + #define M37_SL_SEL3 0x25 + #define M38_SL_SEL3 0x26 + #define M39_SL_SEL3 0x27 + #define M40_SL_SEL3 0x28 + #define M41_SL_SEL3 0x29 + #define M42_SL_SEL3 0x2A + #define M43_SL_SEL3 0x2B + #define M44_SL_SEL3 0x2C + #define M45_SL_SEL3 0x2D + #define M46_SL_SEL3 0x2E + #define M47_SL_SEL3 0x2F + #define M48_SL_SEL3 0x30 + #define M49_SL_SEL3 0x31 + #define M50_SL_SEL3 0x32 + #define M51_SL_SEL3 0x33 + #define M52_SL_SEL3 0x34 + #define M53_SL_SEL3 0x35 + #define M54_SL_SEL3 0x36 + #define M55_SL_SEL3 0x37 + #define M56_SL_SEL3 0x38 + #define M57_SL_SEL3 0x39 + #define M58_SL_SEL3 0x3A + #define M59_SL_SEL3 0x3B + #define M60_SL_SEL3 0x3C + #define M61_SL_SEL3 0x3D + #define M62_SL_SEL3 0x3E + #define M63_SL_SEL3 0x3F + #define M64_SL_SEL3 0x40 + #define M65_SL_SEL3 0x41 + #define M66_SL_SEL3 0x42 + #define M67_SL_SEL3 0x43 + #define M68_SL_SEL3 0x44 + #define M69_SL_SEL3 0x45 + #define M70_SL_SEL3 0x46 + #define M71_SL_SEL3 0x47 + #define M72_SL_SEL3 0x48 + #define M73_SL_SEL3 0x49 + #define M74_SL_SEL3 0x4A + #define M75_SL_SEL3 0x4B + #define M76_SL_SEL3 0x4C + #define M77_SL_SEL3 0x4D + #define M78_SL_SEL3 0x4E + #define M79_SL_SEL3 0x4F + #define M80_SL_SEL3 0x50 + #define M81_SL_SEL3 0x51 + #define M82_SL_SEL3 0x52 + #define M83_SL_SEL3 0x53 + #define M84_SL_SEL3 0x54 + #define M85_SL_SEL3 0x55 + #define M86_SL_SEL3 0x56 + #define M87_SL_SEL3 0x57 + #define M88_SL_SEL3 0x58 + #define M89_SL_SEL3 0x59 + #define M90_SL_SEL3 0x5A + #define M91_SL_SEL3 0x5B + #define M92_SL_SEL3 0x5C + #define M93_SL_SEL3 0x5D + #define M94_SL_SEL3 0x5E + #define M95_SL_SEL3 0x5F + #define M96_SL_SEL3 0x60 + #define M97_SL_SEL3 0x61 + #define M98_SL_SEL3 0x62 + #define M99_SL_SEL3 0x63 + #define M100_SL_SEL3 0x64 + #define M101_SL_SEL3 0x65 + #define M102_SL_SEL3 0x66 + #define M103_SL_SEL3 0x67 + #define M104_SL_SEL3 0x68 + #define M105_SL_SEL3 0x69 + #define M106_SL_SEL3 0x6A + #define M107_SL_SEL3 0x6B + #define M108_SL_SEL3 0x6C + #define M109_SL_SEL3 0x6D + #define M110_SL_SEL3 0x6E + #define M111_SL_SEL3 0x6F + #define M112_SL_SEL3 0x70 + #define M113_SL_SEL3 0x71 + #define M114_SL_SEL3 0x72 + #define M115_SL_SEL3 0x73 + #define M116_SL_SEL3 0x74 + #define M117_SL_SEL3 0x75 + #define M118_SL_SEL3 0x76 + #define M119_SL_SEL3 0x77 + #define M120_SL_SEL3 0x78 + #define M121_SL_SEL3 0x79 + #define M122_SL_SEL3 0x7A + #define M123_SL_SEL3 0x7B + #define M124_SL_SEL3 0x7C + #define M125_SL_SEL3 0x7D + #define M126_SL_SEL3 0x7E + #define M127_SL_SEL3 0x7F +#define M_SH_SEL3 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel3:7; + REGWORD v_sh_sel3:1; + } bit_r_sl_sel3; + + typedef union {REGWORD reg; bit_r_sl_sel3 bit;} reg_r_sl_sel3; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL4 0x15 + +#define M_SL_SEL4 0x7F + #define M1_SL_SEL4 0x01 + #define M2_SL_SEL4 0x02 + #define M3_SL_SEL4 0x03 + #define M4_SL_SEL4 0x04 + #define M5_SL_SEL4 0x05 + #define M6_SL_SEL4 0x06 + #define M7_SL_SEL4 0x07 + #define M8_SL_SEL4 0x08 + #define M9_SL_SEL4 0x09 + #define M10_SL_SEL4 0x0A + #define M11_SL_SEL4 0x0B + #define M12_SL_SEL4 0x0C + #define M13_SL_SEL4 0x0D + #define M14_SL_SEL4 0x0E + #define M15_SL_SEL4 0x0F + #define M16_SL_SEL4 0x10 + #define M17_SL_SEL4 0x11 + #define M18_SL_SEL4 0x12 + #define M19_SL_SEL4 0x13 + #define M20_SL_SEL4 0x14 + #define M21_SL_SEL4 0x15 + #define M22_SL_SEL4 0x16 + #define M23_SL_SEL4 0x17 + #define M24_SL_SEL4 0x18 + #define M25_SL_SEL4 0x19 + #define M26_SL_SEL4 0x1A + #define M27_SL_SEL4 0x1B + #define M28_SL_SEL4 0x1C + #define M29_SL_SEL4 0x1D + #define M30_SL_SEL4 0x1E + #define M31_SL_SEL4 0x1F + #define M32_SL_SEL4 0x20 + #define M33_SL_SEL4 0x21 + #define M34_SL_SEL4 0x22 + #define M35_SL_SEL4 0x23 + #define M36_SL_SEL4 0x24 + #define M37_SL_SEL4 0x25 + #define M38_SL_SEL4 0x26 + #define M39_SL_SEL4 0x27 + #define M40_SL_SEL4 0x28 + #define M41_SL_SEL4 0x29 + #define M42_SL_SEL4 0x2A + #define M43_SL_SEL4 0x2B + #define M44_SL_SEL4 0x2C + #define M45_SL_SEL4 0x2D + #define M46_SL_SEL4 0x2E + #define M47_SL_SEL4 0x2F + #define M48_SL_SEL4 0x30 + #define M49_SL_SEL4 0x31 + #define M50_SL_SEL4 0x32 + #define M51_SL_SEL4 0x33 + #define M52_SL_SEL4 0x34 + #define M53_SL_SEL4 0x35 + #define M54_SL_SEL4 0x36 + #define M55_SL_SEL4 0x37 + #define M56_SL_SEL4 0x38 + #define M57_SL_SEL4 0x39 + #define M58_SL_SEL4 0x3A + #define M59_SL_SEL4 0x3B + #define M60_SL_SEL4 0x3C + #define M61_SL_SEL4 0x3D + #define M62_SL_SEL4 0x3E + #define M63_SL_SEL4 0x3F + #define M64_SL_SEL4 0x40 + #define M65_SL_SEL4 0x41 + #define M66_SL_SEL4 0x42 + #define M67_SL_SEL4 0x43 + #define M68_SL_SEL4 0x44 + #define M69_SL_SEL4 0x45 + #define M70_SL_SEL4 0x46 + #define M71_SL_SEL4 0x47 + #define M72_SL_SEL4 0x48 + #define M73_SL_SEL4 0x49 + #define M74_SL_SEL4 0x4A + #define M75_SL_SEL4 0x4B + #define M76_SL_SEL4 0x4C + #define M77_SL_SEL4 0x4D + #define M78_SL_SEL4 0x4E + #define M79_SL_SEL4 0x4F + #define M80_SL_SEL4 0x50 + #define M81_SL_SEL4 0x51 + #define M82_SL_SEL4 0x52 + #define M83_SL_SEL4 0x53 + #define M84_SL_SEL4 0x54 + #define M85_SL_SEL4 0x55 + #define M86_SL_SEL4 0x56 + #define M87_SL_SEL4 0x57 + #define M88_SL_SEL4 0x58 + #define M89_SL_SEL4 0x59 + #define M90_SL_SEL4 0x5A + #define M91_SL_SEL4 0x5B + #define M92_SL_SEL4 0x5C + #define M93_SL_SEL4 0x5D + #define M94_SL_SEL4 0x5E + #define M95_SL_SEL4 0x5F + #define M96_SL_SEL4 0x60 + #define M97_SL_SEL4 0x61 + #define M98_SL_SEL4 0x62 + #define M99_SL_SEL4 0x63 + #define M100_SL_SEL4 0x64 + #define M101_SL_SEL4 0x65 + #define M102_SL_SEL4 0x66 + #define M103_SL_SEL4 0x67 + #define M104_SL_SEL4 0x68 + #define M105_SL_SEL4 0x69 + #define M106_SL_SEL4 0x6A + #define M107_SL_SEL4 0x6B + #define M108_SL_SEL4 0x6C + #define M109_SL_SEL4 0x6D + #define M110_SL_SEL4 0x6E + #define M111_SL_SEL4 0x6F + #define M112_SL_SEL4 0x70 + #define M113_SL_SEL4 0x71 + #define M114_SL_SEL4 0x72 + #define M115_SL_SEL4 0x73 + #define M116_SL_SEL4 0x74 + #define M117_SL_SEL4 0x75 + #define M118_SL_SEL4 0x76 + #define M119_SL_SEL4 0x77 + #define M120_SL_SEL4 0x78 + #define M121_SL_SEL4 0x79 + #define M122_SL_SEL4 0x7A + #define M123_SL_SEL4 0x7B + #define M124_SL_SEL4 0x7C + #define M125_SL_SEL4 0x7D + #define M126_SL_SEL4 0x7E + #define M127_SL_SEL4 0x7F +#define M_SH_SEL4 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel4:7; + REGWORD v_sh_sel4:1; + } bit_r_sl_sel4; + + typedef union {REGWORD reg; bit_r_sl_sel4 bit;} reg_r_sl_sel4; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL5 0x15 + +#define M_SL_SEL5 0x7F + #define M1_SL_SEL5 0x01 + #define M2_SL_SEL5 0x02 + #define M3_SL_SEL5 0x03 + #define M4_SL_SEL5 0x04 + #define M5_SL_SEL5 0x05 + #define M6_SL_SEL5 0x06 + #define M7_SL_SEL5 0x07 + #define M8_SL_SEL5 0x08 + #define M9_SL_SEL5 0x09 + #define M10_SL_SEL5 0x0A + #define M11_SL_SEL5 0x0B + #define M12_SL_SEL5 0x0C + #define M13_SL_SEL5 0x0D + #define M14_SL_SEL5 0x0E + #define M15_SL_SEL5 0x0F + #define M16_SL_SEL5 0x10 + #define M17_SL_SEL5 0x11 + #define M18_SL_SEL5 0x12 + #define M19_SL_SEL5 0x13 + #define M20_SL_SEL5 0x14 + #define M21_SL_SEL5 0x15 + #define M22_SL_SEL5 0x16 + #define M23_SL_SEL5 0x17 + #define M24_SL_SEL5 0x18 + #define M25_SL_SEL5 0x19 + #define M26_SL_SEL5 0x1A + #define M27_SL_SEL5 0x1B + #define M28_SL_SEL5 0x1C + #define M29_SL_SEL5 0x1D + #define M30_SL_SEL5 0x1E + #define M31_SL_SEL5 0x1F + #define M32_SL_SEL5 0x20 + #define M33_SL_SEL5 0x21 + #define M34_SL_SEL5 0x22 + #define M35_SL_SEL5 0x23 + #define M36_SL_SEL5 0x24 + #define M37_SL_SEL5 0x25 + #define M38_SL_SEL5 0x26 + #define M39_SL_SEL5 0x27 + #define M40_SL_SEL5 0x28 + #define M41_SL_SEL5 0x29 + #define M42_SL_SEL5 0x2A + #define M43_SL_SEL5 0x2B + #define M44_SL_SEL5 0x2C + #define M45_SL_SEL5 0x2D + #define M46_SL_SEL5 0x2E + #define M47_SL_SEL5 0x2F + #define M48_SL_SEL5 0x30 + #define M49_SL_SEL5 0x31 + #define M50_SL_SEL5 0x32 + #define M51_SL_SEL5 0x33 + #define M52_SL_SEL5 0x34 + #define M53_SL_SEL5 0x35 + #define M54_SL_SEL5 0x36 + #define M55_SL_SEL5 0x37 + #define M56_SL_SEL5 0x38 + #define M57_SL_SEL5 0x39 + #define M58_SL_SEL5 0x3A + #define M59_SL_SEL5 0x3B + #define M60_SL_SEL5 0x3C + #define M61_SL_SEL5 0x3D + #define M62_SL_SEL5 0x3E + #define M63_SL_SEL5 0x3F + #define M64_SL_SEL5 0x40 + #define M65_SL_SEL5 0x41 + #define M66_SL_SEL5 0x42 + #define M67_SL_SEL5 0x43 + #define M68_SL_SEL5 0x44 + #define M69_SL_SEL5 0x45 + #define M70_SL_SEL5 0x46 + #define M71_SL_SEL5 0x47 + #define M72_SL_SEL5 0x48 + #define M73_SL_SEL5 0x49 + #define M74_SL_SEL5 0x4A + #define M75_SL_SEL5 0x4B + #define M76_SL_SEL5 0x4C + #define M77_SL_SEL5 0x4D + #define M78_SL_SEL5 0x4E + #define M79_SL_SEL5 0x4F + #define M80_SL_SEL5 0x50 + #define M81_SL_SEL5 0x51 + #define M82_SL_SEL5 0x52 + #define M83_SL_SEL5 0x53 + #define M84_SL_SEL5 0x54 + #define M85_SL_SEL5 0x55 + #define M86_SL_SEL5 0x56 + #define M87_SL_SEL5 0x57 + #define M88_SL_SEL5 0x58 + #define M89_SL_SEL5 0x59 + #define M90_SL_SEL5 0x5A + #define M91_SL_SEL5 0x5B + #define M92_SL_SEL5 0x5C + #define M93_SL_SEL5 0x5D + #define M94_SL_SEL5 0x5E + #define M95_SL_SEL5 0x5F + #define M96_SL_SEL5 0x60 + #define M97_SL_SEL5 0x61 + #define M98_SL_SEL5 0x62 + #define M99_SL_SEL5 0x63 + #define M100_SL_SEL5 0x64 + #define M101_SL_SEL5 0x65 + #define M102_SL_SEL5 0x66 + #define M103_SL_SEL5 0x67 + #define M104_SL_SEL5 0x68 + #define M105_SL_SEL5 0x69 + #define M106_SL_SEL5 0x6A + #define M107_SL_SEL5 0x6B + #define M108_SL_SEL5 0x6C + #define M109_SL_SEL5 0x6D + #define M110_SL_SEL5 0x6E + #define M111_SL_SEL5 0x6F + #define M112_SL_SEL5 0x70 + #define M113_SL_SEL5 0x71 + #define M114_SL_SEL5 0x72 + #define M115_SL_SEL5 0x73 + #define M116_SL_SEL5 0x74 + #define M117_SL_SEL5 0x75 + #define M118_SL_SEL5 0x76 + #define M119_SL_SEL5 0x77 + #define M120_SL_SEL5 0x78 + #define M121_SL_SEL5 0x79 + #define M122_SL_SEL5 0x7A + #define M123_SL_SEL5 0x7B + #define M124_SL_SEL5 0x7C + #define M125_SL_SEL5 0x7D + #define M126_SL_SEL5 0x7E + #define M127_SL_SEL5 0x7F +#define M_SH_SEL5 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel5:7; + REGWORD v_sh_sel5:1; + } bit_r_sl_sel5; + + typedef union {REGWORD reg; bit_r_sl_sel5 bit;} reg_r_sl_sel5; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL6 0x15 + +#define M_SL_SEL6 0x7F + #define M1_SL_SEL6 0x01 + #define M2_SL_SEL6 0x02 + #define M3_SL_SEL6 0x03 + #define M4_SL_SEL6 0x04 + #define M5_SL_SEL6 0x05 + #define M6_SL_SEL6 0x06 + #define M7_SL_SEL6 0x07 + #define M8_SL_SEL6 0x08 + #define M9_SL_SEL6 0x09 + #define M10_SL_SEL6 0x0A + #define M11_SL_SEL6 0x0B + #define M12_SL_SEL6 0x0C + #define M13_SL_SEL6 0x0D + #define M14_SL_SEL6 0x0E + #define M15_SL_SEL6 0x0F + #define M16_SL_SEL6 0x10 + #define M17_SL_SEL6 0x11 + #define M18_SL_SEL6 0x12 + #define M19_SL_SEL6 0x13 + #define M20_SL_SEL6 0x14 + #define M21_SL_SEL6 0x15 + #define M22_SL_SEL6 0x16 + #define M23_SL_SEL6 0x17 + #define M24_SL_SEL6 0x18 + #define M25_SL_SEL6 0x19 + #define M26_SL_SEL6 0x1A + #define M27_SL_SEL6 0x1B + #define M28_SL_SEL6 0x1C + #define M29_SL_SEL6 0x1D + #define M30_SL_SEL6 0x1E + #define M31_SL_SEL6 0x1F + #define M32_SL_SEL6 0x20 + #define M33_SL_SEL6 0x21 + #define M34_SL_SEL6 0x22 + #define M35_SL_SEL6 0x23 + #define M36_SL_SEL6 0x24 + #define M37_SL_SEL6 0x25 + #define M38_SL_SEL6 0x26 + #define M39_SL_SEL6 0x27 + #define M40_SL_SEL6 0x28 + #define M41_SL_SEL6 0x29 + #define M42_SL_SEL6 0x2A + #define M43_SL_SEL6 0x2B + #define M44_SL_SEL6 0x2C + #define M45_SL_SEL6 0x2D + #define M46_SL_SEL6 0x2E + #define M47_SL_SEL6 0x2F + #define M48_SL_SEL6 0x30 + #define M49_SL_SEL6 0x31 + #define M50_SL_SEL6 0x32 + #define M51_SL_SEL6 0x33 + #define M52_SL_SEL6 0x34 + #define M53_SL_SEL6 0x35 + #define M54_SL_SEL6 0x36 + #define M55_SL_SEL6 0x37 + #define M56_SL_SEL6 0x38 + #define M57_SL_SEL6 0x39 + #define M58_SL_SEL6 0x3A + #define M59_SL_SEL6 0x3B + #define M60_SL_SEL6 0x3C + #define M61_SL_SEL6 0x3D + #define M62_SL_SEL6 0x3E + #define M63_SL_SEL6 0x3F + #define M64_SL_SEL6 0x40 + #define M65_SL_SEL6 0x41 + #define M66_SL_SEL6 0x42 + #define M67_SL_SEL6 0x43 + #define M68_SL_SEL6 0x44 + #define M69_SL_SEL6 0x45 + #define M70_SL_SEL6 0x46 + #define M71_SL_SEL6 0x47 + #define M72_SL_SEL6 0x48 + #define M73_SL_SEL6 0x49 + #define M74_SL_SEL6 0x4A + #define M75_SL_SEL6 0x4B + #define M76_SL_SEL6 0x4C + #define M77_SL_SEL6 0x4D + #define M78_SL_SEL6 0x4E + #define M79_SL_SEL6 0x4F + #define M80_SL_SEL6 0x50 + #define M81_SL_SEL6 0x51 + #define M82_SL_SEL6 0x52 + #define M83_SL_SEL6 0x53 + #define M84_SL_SEL6 0x54 + #define M85_SL_SEL6 0x55 + #define M86_SL_SEL6 0x56 + #define M87_SL_SEL6 0x57 + #define M88_SL_SEL6 0x58 + #define M89_SL_SEL6 0x59 + #define M90_SL_SEL6 0x5A + #define M91_SL_SEL6 0x5B + #define M92_SL_SEL6 0x5C + #define M93_SL_SEL6 0x5D + #define M94_SL_SEL6 0x5E + #define M95_SL_SEL6 0x5F + #define M96_SL_SEL6 0x60 + #define M97_SL_SEL6 0x61 + #define M98_SL_SEL6 0x62 + #define M99_SL_SEL6 0x63 + #define M100_SL_SEL6 0x64 + #define M101_SL_SEL6 0x65 + #define M102_SL_SEL6 0x66 + #define M103_SL_SEL6 0x67 + #define M104_SL_SEL6 0x68 + #define M105_SL_SEL6 0x69 + #define M106_SL_SEL6 0x6A + #define M107_SL_SEL6 0x6B + #define M108_SL_SEL6 0x6C + #define M109_SL_SEL6 0x6D + #define M110_SL_SEL6 0x6E + #define M111_SL_SEL6 0x6F + #define M112_SL_SEL6 0x70 + #define M113_SL_SEL6 0x71 + #define M114_SL_SEL6 0x72 + #define M115_SL_SEL6 0x73 + #define M116_SL_SEL6 0x74 + #define M117_SL_SEL6 0x75 + #define M118_SL_SEL6 0x76 + #define M119_SL_SEL6 0x77 + #define M120_SL_SEL6 0x78 + #define M121_SL_SEL6 0x79 + #define M122_SL_SEL6 0x7A + #define M123_SL_SEL6 0x7B + #define M124_SL_SEL6 0x7C + #define M125_SL_SEL6 0x7D + #define M126_SL_SEL6 0x7E + #define M127_SL_SEL6 0x7F +#define M_SH_SEL6 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel6:7; + REGWORD v_sh_sel6:1; + } bit_r_sl_sel6; + + typedef union {REGWORD reg; bit_r_sl_sel6 bit;} reg_r_sl_sel6; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SL_SEL7 0x15 + +#define M_SL_SEL7 0x7F + #define M1_SL_SEL7 0x01 + #define M2_SL_SEL7 0x02 + #define M3_SL_SEL7 0x03 + #define M4_SL_SEL7 0x04 + #define M5_SL_SEL7 0x05 + #define M6_SL_SEL7 0x06 + #define M7_SL_SEL7 0x07 + #define M8_SL_SEL7 0x08 + #define M9_SL_SEL7 0x09 + #define M10_SL_SEL7 0x0A + #define M11_SL_SEL7 0x0B + #define M12_SL_SEL7 0x0C + #define M13_SL_SEL7 0x0D + #define M14_SL_SEL7 0x0E + #define M15_SL_SEL7 0x0F + #define M16_SL_SEL7 0x10 + #define M17_SL_SEL7 0x11 + #define M18_SL_SEL7 0x12 + #define M19_SL_SEL7 0x13 + #define M20_SL_SEL7 0x14 + #define M21_SL_SEL7 0x15 + #define M22_SL_SEL7 0x16 + #define M23_SL_SEL7 0x17 + #define M24_SL_SEL7 0x18 + #define M25_SL_SEL7 0x19 + #define M26_SL_SEL7 0x1A + #define M27_SL_SEL7 0x1B + #define M28_SL_SEL7 0x1C + #define M29_SL_SEL7 0x1D + #define M30_SL_SEL7 0x1E + #define M31_SL_SEL7 0x1F + #define M32_SL_SEL7 0x20 + #define M33_SL_SEL7 0x21 + #define M34_SL_SEL7 0x22 + #define M35_SL_SEL7 0x23 + #define M36_SL_SEL7 0x24 + #define M37_SL_SEL7 0x25 + #define M38_SL_SEL7 0x26 + #define M39_SL_SEL7 0x27 + #define M40_SL_SEL7 0x28 + #define M41_SL_SEL7 0x29 + #define M42_SL_SEL7 0x2A + #define M43_SL_SEL7 0x2B + #define M44_SL_SEL7 0x2C + #define M45_SL_SEL7 0x2D + #define M46_SL_SEL7 0x2E + #define M47_SL_SEL7 0x2F + #define M48_SL_SEL7 0x30 + #define M49_SL_SEL7 0x31 + #define M50_SL_SEL7 0x32 + #define M51_SL_SEL7 0x33 + #define M52_SL_SEL7 0x34 + #define M53_SL_SEL7 0x35 + #define M54_SL_SEL7 0x36 + #define M55_SL_SEL7 0x37 + #define M56_SL_SEL7 0x38 + #define M57_SL_SEL7 0x39 + #define M58_SL_SEL7 0x3A + #define M59_SL_SEL7 0x3B + #define M60_SL_SEL7 0x3C + #define M61_SL_SEL7 0x3D + #define M62_SL_SEL7 0x3E + #define M63_SL_SEL7 0x3F + #define M64_SL_SEL7 0x40 + #define M65_SL_SEL7 0x41 + #define M66_SL_SEL7 0x42 + #define M67_SL_SEL7 0x43 + #define M68_SL_SEL7 0x44 + #define M69_SL_SEL7 0x45 + #define M70_SL_SEL7 0x46 + #define M71_SL_SEL7 0x47 + #define M72_SL_SEL7 0x48 + #define M73_SL_SEL7 0x49 + #define M74_SL_SEL7 0x4A + #define M75_SL_SEL7 0x4B + #define M76_SL_SEL7 0x4C + #define M77_SL_SEL7 0x4D + #define M78_SL_SEL7 0x4E + #define M79_SL_SEL7 0x4F + #define M80_SL_SEL7 0x50 + #define M81_SL_SEL7 0x51 + #define M82_SL_SEL7 0x52 + #define M83_SL_SEL7 0x53 + #define M84_SL_SEL7 0x54 + #define M85_SL_SEL7 0x55 + #define M86_SL_SEL7 0x56 + #define M87_SL_SEL7 0x57 + #define M88_SL_SEL7 0x58 + #define M89_SL_SEL7 0x59 + #define M90_SL_SEL7 0x5A + #define M91_SL_SEL7 0x5B + #define M92_SL_SEL7 0x5C + #define M93_SL_SEL7 0x5D + #define M94_SL_SEL7 0x5E + #define M95_SL_SEL7 0x5F + #define M96_SL_SEL7 0x60 + #define M97_SL_SEL7 0x61 + #define M98_SL_SEL7 0x62 + #define M99_SL_SEL7 0x63 + #define M100_SL_SEL7 0x64 + #define M101_SL_SEL7 0x65 + #define M102_SL_SEL7 0x66 + #define M103_SL_SEL7 0x67 + #define M104_SL_SEL7 0x68 + #define M105_SL_SEL7 0x69 + #define M106_SL_SEL7 0x6A + #define M107_SL_SEL7 0x6B + #define M108_SL_SEL7 0x6C + #define M109_SL_SEL7 0x6D + #define M110_SL_SEL7 0x6E + #define M111_SL_SEL7 0x6F + #define M112_SL_SEL7 0x70 + #define M113_SL_SEL7 0x71 + #define M114_SL_SEL7 0x72 + #define M115_SL_SEL7 0x73 + #define M116_SL_SEL7 0x74 + #define M117_SL_SEL7 0x75 + #define M118_SL_SEL7 0x76 + #define M119_SL_SEL7 0x77 + #define M120_SL_SEL7 0x78 + #define M121_SL_SEL7 0x79 + #define M122_SL_SEL7 0x7A + #define M123_SL_SEL7 0x7B + #define M124_SL_SEL7 0x7C + #define M125_SL_SEL7 0x7D + #define M126_SL_SEL7 0x7E + #define M127_SL_SEL7 0x7F +#define M_SH_SEL7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_sl_sel7:7; + REGWORD v_sh_sel7:1; + } bit_r_sl_sel7; + + typedef union {REGWORD reg; bit_r_sl_sel7 bit;} reg_r_sl_sel7; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_PCM_MD1 0x15 + +#define M_DEC_CNT 0x01 +#define M_PLL_ADJ_SPEED 0x0C + #define M1_PLL_ADJ_SPEED 0x04 + #define M2_PLL_ADJ_SPEED 0x08 + #define M3_PLL_ADJ_SPEED 0x0C +#define M_PCM_DR 0x30 + #define M1_PCM_DR 0x10 + #define M2_PCM_DR 0x20 + #define M3_PCM_DR 0x30 +#define M_PCM_LOOP 0x40 + + typedef struct // bitmap construction + { + REGWORD v_dec_cnt:1; + REGWORD reserved_25:1; + REGWORD v_pll_adj_speed:2; + REGWORD v_pcm_dr:2; + REGWORD v_pcm_loop:1; + REGWORD reserved_26:1; + } bit_r_pcm_md1; + + typedef union {REGWORD reg; bit_r_pcm_md1 bit;} reg_r_pcm_md1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_PCM_MD2 0x15 + +#define M_SYNC_SRC 0x04 +#define M_SYNC_OUT 0x08 +#define M_ICR_FR_TIME 0x40 +#define M_EN_PLL 0x80 + + typedef struct // bitmap construction + { + REGWORD reserved_27:2; + REGWORD v_sync_src:1; + REGWORD v_sync_out:1; + REGWORD reserved_28:2; + REGWORD v_icr_fr_time:1; + REGWORD v_en_pll:1; + } bit_r_pcm_md2; + + typedef union {REGWORD reg; bit_r_pcm_md2 bit;} reg_r_pcm_md2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SH0L 0x15 + +#define M_SH0L 0xFF + + typedef struct // bitmap construction + { + REGWORD v_sh0l:8; + } bit_r_sh0l; + + typedef union {REGWORD reg; bit_r_sh0l bit;} reg_r_sh0l; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SH0H 0x15 + +#define M_SH0H 0xFF + + typedef struct // bitmap construction + { + REGWORD v_sh0h:8; + } bit_r_sh0h; + + typedef union {REGWORD reg; bit_r_sh0h bit;} reg_r_sh0h; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SH1L 0x15 + +#define M_SH1L 0xFF + + typedef struct // bitmap construction + { + REGWORD v_sh1l:8; + } bit_r_sh1l; + + typedef union {REGWORD reg; bit_r_sh1l bit;} reg_r_sh1l; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_SH1H 0x15 + +#define M_SH1H 0xFF + + typedef struct // bitmap construction + { + REGWORD v_sh1h:8; + } bit_r_sh1h; + + typedef union {REGWORD reg; bit_r_sh1h bit;} reg_r_sh1h; // register and bitmap access + +#define R_IRQ_OVIEW 0x10 + +#define M_IRQ_FIFO_BL0 0x01 +#define M_IRQ_FIFO_BL1 0x02 +#define M_IRQ_FIFO_BL2 0x04 +#define M_IRQ_FIFO_BL3 0x08 +#define M_IRQ_FIFO_BL4 0x10 +#define M_IRQ_FIFO_BL5 0x20 +#define M_IRQ_FIFO_BL6 0x40 +#define M_IRQ_FIFO_BL7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo_bl0:1; + REGWORD v_irq_fifo_bl1:1; + REGWORD v_irq_fifo_bl2:1; + REGWORD v_irq_fifo_bl3:1; + REGWORD v_irq_fifo_bl4:1; + REGWORD v_irq_fifo_bl5:1; + REGWORD v_irq_fifo_bl6:1; + REGWORD v_irq_fifo_bl7:1; + } bit_r_irq_oview; + + typedef union {REGWORD reg; bit_r_irq_oview bit;} reg_r_irq_oview; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_MISC 0x11 + +#define M_TI_IRQ 0x02 +#define M_IRQ_PROC 0x04 +#define M_DTMF_IRQ 0x08 + + typedef struct // bitmap construction + { + REGWORD reserved_30:1; + REGWORD v_ti_irq:1; + REGWORD v_irq_proc:1; + REGWORD v_dtmf_irq:1; + REGWORD reserved_32:1; + REGWORD reserved_34:1; + REGWORD reserved_36:1; + REGWORD reserved_38:1; + } bit_r_irq_misc; + + typedef union {REGWORD reg; bit_r_irq_misc bit;} reg_r_irq_misc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_CONF_OFLOW 0x14 + +#define M_CONF_OFLOW0 0x01 +#define M_CONF_OFLOW1 0x02 +#define M_CONF_OFLOW2 0x04 +#define M_CONF_OFLOW3 0x08 +#define M_CONF_OFLOW4 0x10 +#define M_CONF_OFLOW5 0x20 +#define M_CONF_OFLOW6 0x40 +#define M_CONF_OFLOW7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_conf_oflow0:1; + REGWORD v_conf_oflow1:1; + REGWORD v_conf_oflow2:1; + REGWORD v_conf_oflow3:1; + REGWORD v_conf_oflow4:1; + REGWORD v_conf_oflow5:1; + REGWORD v_conf_oflow6:1; + REGWORD v_conf_oflow7:1; + } bit_r_conf_oflow; + + typedef union {REGWORD reg; bit_r_conf_oflow bit;} reg_r_conf_oflow; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_CHIP_ID 0x16 +#define R_CHIP_RV 0x1F + +#define M_PNP_IRQ 0x0F + #define M1_PNP_IRQ 0x01 + #define M2_PNP_IRQ 0x02 + #define M3_PNP_IRQ 0x03 + #define M4_PNP_IRQ 0x04 + #define M5_PNP_IRQ 0x05 + #define M6_PNP_IRQ 0x06 + #define M7_PNP_IRQ 0x07 + #define M8_PNP_IRQ 0x08 + #define M9_PNP_IRQ 0x09 + #define M10_PNP_IRQ 0x0A + #define M11_PNP_IRQ 0x0B + #define M12_PNP_IRQ 0x0C + #define M13_PNP_IRQ 0x0D + #define M14_PNP_IRQ 0x0E + #define M15_PNP_IRQ 0x0F +#define M_CHIP_ID 0xF0 + #define M1_CHIP_ID 0x10 + #define M2_CHIP_ID 0x20 + #define M3_CHIP_ID 0x30 + #define M4_CHIP_ID 0x40 + #define M5_CHIP_ID 0x50 + #define M6_CHIP_ID 0x60 + #define M7_CHIP_ID 0x70 + #define M8_CHIP_ID 0x80 + #define M9_CHIP_ID 0x90 + #define M10_CHIP_ID 0xA0 + #define M11_CHIP_ID 0xB0 + #define M12_CHIP_ID 0xC0 + #define M13_CHIP_ID 0xD0 + #define M14_CHIP_ID 0xE0 + #define M15_CHIP_ID 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_pnp_irq:4; + REGWORD v_chip_id:4; + } bit_r_chip_id; + + typedef union {REGWORD reg; bit_r_chip_id bit;} reg_r_chip_id; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BERT_STA 0x17 + +#define M_BERT_SYNC 0x10 +#define M_BERT_INV_DATA 0x20 + + typedef struct // bitmap construction + { + REGWORD reserved_39v_bert_sync_src:4; + REGWORD v_bert_sync:1; + REGWORD v_bert_inv_data:1; + REGWORD reserved_40:2; + } bit_r_bert_sta; + + typedef union {REGWORD reg; bit_r_bert_sta bit;} reg_r_bert_sta; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_F0_CNTL 0x18 + +#define M_F0_CNTL 0xFF + + typedef struct // bitmap construction + { + REGWORD v_f0_cntl:8; + } bit_r_f0_cntl; + + typedef union {REGWORD reg; bit_r_f0_cntl bit;} reg_r_f0_cntl; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_F0_CNTH 0x19 + +#define M_F0_CNTH 0xFF + + typedef struct // bitmap construction + { + REGWORD v_f0_cnth:8; + } bit_r_f0_cnth; + + typedef union {REGWORD reg; bit_r_f0_cnth bit;} reg_r_f0_cnth; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BERT_ECL 0x1A + +#define M_BERT_ECL 0xFF + + typedef struct // bitmap construction + { + REGWORD v_bert_ecl:8; + } bit_r_bert_ecl; + + typedef union {REGWORD reg; bit_r_bert_ecl bit;} reg_r_bert_ecl; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BERT_ECH 0x1B + +#define M_BERT_ECH 0xFF + + typedef struct // bitmap construction + { + REGWORD v_bert_ech:8; + } bit_r_bert_ech; + + typedef union {REGWORD reg; bit_r_bert_ech bit;} reg_r_bert_ech; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_STATUS 0x1C + +#define M_BUSY 0x01 +#define M_PROC 0x02 +#define M_DTMF_IRQSTA 0x04 +#define M_LOST_STA 0x08 +#define M_SYNC_IN 0x10 +#define M_EXT_IRQSTA 0x20 +#define M_MISC_IRQSTA 0x40 +#define M_FR_IRQSTA 0x80 + + typedef struct // bitmap construction + { + REGWORD v_busy:1; + REGWORD v_proc:1; + REGWORD v_dtmf_irqsta:1; + REGWORD v_lost_sta:1; + REGWORD v_sync_in:1; + REGWORD v_ext_irqsta:1; + REGWORD v_misc_irqsta:1; + REGWORD v_fr_irqsta:1; + } bit_r_status; + + typedef union {REGWORD reg; bit_r_status bit;} reg_r_status; // register and bitmap access + +#define R_SLOT 0x10 + +#define M_SL_DIR 0x01 +#define M_SL_NUM 0xFE + #define M1_SL_NUM 0x02 + #define M2_SL_NUM 0x04 + #define M3_SL_NUM 0x06 + #define M4_SL_NUM 0x08 + #define M5_SL_NUM 0x0A + #define M6_SL_NUM 0x0C + #define M7_SL_NUM 0x0E + #define M8_SL_NUM 0x10 + #define M9_SL_NUM 0x12 + #define M10_SL_NUM 0x14 + #define M11_SL_NUM 0x16 + #define M12_SL_NUM 0x18 + #define M13_SL_NUM 0x1A + #define M14_SL_NUM 0x1C + #define M15_SL_NUM 0x1E + #define M16_SL_NUM 0x20 + #define M17_SL_NUM 0x22 + #define M18_SL_NUM 0x24 + #define M19_SL_NUM 0x26 + #define M20_SL_NUM 0x28 + #define M21_SL_NUM 0x2A + #define M22_SL_NUM 0x2C + #define M23_SL_NUM 0x2E + #define M24_SL_NUM 0x30 + #define M25_SL_NUM 0x32 + #define M26_SL_NUM 0x34 + #define M27_SL_NUM 0x36 + #define M28_SL_NUM 0x38 + #define M29_SL_NUM 0x3A + #define M30_SL_NUM 0x3C + #define M31_SL_NUM 0x3E + #define M32_SL_NUM 0x40 + #define M33_SL_NUM 0x42 + #define M34_SL_NUM 0x44 + #define M35_SL_NUM 0x46 + #define M36_SL_NUM 0x48 + #define M37_SL_NUM 0x4A + #define M38_SL_NUM 0x4C + #define M39_SL_NUM 0x4E + #define M40_SL_NUM 0x50 + #define M41_SL_NUM 0x52 + #define M42_SL_NUM 0x54 + #define M43_SL_NUM 0x56 + #define M44_SL_NUM 0x58 + #define M45_SL_NUM 0x5A + #define M46_SL_NUM 0x5C + #define M47_SL_NUM 0x5E + #define M48_SL_NUM 0x60 + #define M49_SL_NUM 0x62 + #define M50_SL_NUM 0x64 + #define M51_SL_NUM 0x66 + #define M52_SL_NUM 0x68 + #define M53_SL_NUM 0x6A + #define M54_SL_NUM 0x6C + #define M55_SL_NUM 0x6E + #define M56_SL_NUM 0x70 + #define M57_SL_NUM 0x72 + #define M58_SL_NUM 0x74 + #define M59_SL_NUM 0x76 + #define M60_SL_NUM 0x78 + #define M61_SL_NUM 0x7A + #define M62_SL_NUM 0x7C + #define M63_SL_NUM 0x7E + #define M64_SL_NUM 0x80 + #define M65_SL_NUM 0x82 + #define M66_SL_NUM 0x84 + #define M67_SL_NUM 0x86 + #define M68_SL_NUM 0x88 + #define M69_SL_NUM 0x8A + #define M70_SL_NUM 0x8C + #define M71_SL_NUM 0x8E + #define M72_SL_NUM 0x90 + #define M73_SL_NUM 0x92 + #define M74_SL_NUM 0x94 + #define M75_SL_NUM 0x96 + #define M76_SL_NUM 0x98 + #define M77_SL_NUM 0x9A + #define M78_SL_NUM 0x9C + #define M79_SL_NUM 0x9E + #define M80_SL_NUM 0xA0 + #define M81_SL_NUM 0xA2 + #define M82_SL_NUM 0xA4 + #define M83_SL_NUM 0xA6 + #define M84_SL_NUM 0xA8 + #define M85_SL_NUM 0xAA + #define M86_SL_NUM 0xAC + #define M87_SL_NUM 0xAE + #define M88_SL_NUM 0xB0 + #define M89_SL_NUM 0xB2 + #define M90_SL_NUM 0xB4 + #define M91_SL_NUM 0xB6 + #define M92_SL_NUM 0xB8 + #define M93_SL_NUM 0xBA + #define M94_SL_NUM 0xBC + #define M95_SL_NUM 0xBE + #define M96_SL_NUM 0xC0 + #define M97_SL_NUM 0xC2 + #define M98_SL_NUM 0xC4 + #define M99_SL_NUM 0xC6 + #define M100_SL_NUM 0xC8 + #define M101_SL_NUM 0xCA + #define M102_SL_NUM 0xCC + #define M103_SL_NUM 0xCE + #define M104_SL_NUM 0xD0 + #define M105_SL_NUM 0xD2 + #define M106_SL_NUM 0xD4 + #define M107_SL_NUM 0xD6 + #define M108_SL_NUM 0xD8 + #define M109_SL_NUM 0xDA + #define M110_SL_NUM 0xDC + #define M111_SL_NUM 0xDE + #define M112_SL_NUM 0xE0 + #define M113_SL_NUM 0xE2 + #define M114_SL_NUM 0xE4 + #define M115_SL_NUM 0xE6 + #define M116_SL_NUM 0xE8 + #define M117_SL_NUM 0xEA + #define M118_SL_NUM 0xEC + #define M119_SL_NUM 0xEE + #define M120_SL_NUM 0xF0 + #define M121_SL_NUM 0xF2 + #define M122_SL_NUM 0xF4 + #define M123_SL_NUM 0xF6 + #define M124_SL_NUM 0xF8 + #define M125_SL_NUM 0xFA + #define M126_SL_NUM 0xFC + #define M127_SL_NUM 0xFE + + typedef struct // bitmap construction + { + REGWORD v_sl_dir:1; + REGWORD v_sl_num:7; + } bit_r_slot; + + typedef union {REGWORD reg; bit_r_slot bit;} reg_r_slot; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQMSK_MISC 0x11 + +#define M_TI_IRQMSK 0x02 +#define M_PROC_IRQMSK 0x04 +#define M_DTMF_IRQMSK 0x08 + + typedef struct // bitmap construction + { + REGWORD reserved_42:1; + REGWORD v_ti_irqmsk:1; + REGWORD v_proc_irqmsk:1; + REGWORD v_dtmf_irqmsk:1; + REGWORD reserved_44:1; + REGWORD reserved_46:1; + REGWORD reserved_48:1; + REGWORD reserved_50:1; + } bit_r_irqmsk_misc; + + typedef union {REGWORD reg; bit_r_irqmsk_misc bit;} reg_r_irqmsk_misc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_CTRL 0x13 + +#define M_FIFO_IRQ 0x01 +#define M_GLOB_IRQ_EN 0x08 +#define M_IRQ_POL 0x10 + + typedef struct // bitmap construction + { + REGWORD v_fifo_irq:1; + REGWORD reserved_51:2; + REGWORD v_glob_irq_en:1; + REGWORD v_irq_pol:1; + REGWORD reserved_52:3; + } bit_r_irq_ctrl; + + typedef union {REGWORD reg; bit_r_irq_ctrl bit;} reg_r_irq_ctrl; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_PCM_MD0 0x14 + +#define M_PCM_MD 0x01 +#define M_C4_POL 0x02 +#define M_F0_NEG 0x04 +#define M_F0_LEN 0x08 +#define M_PCM_ADDR 0xF0 + #define M1_PCM_ADDR 0x10 + #define M2_PCM_ADDR 0x20 + #define M3_PCM_ADDR 0x30 + #define M4_PCM_ADDR 0x40 + #define M5_PCM_ADDR 0x50 + #define M6_PCM_ADDR 0x60 + #define M7_PCM_ADDR 0x70 + #define M8_PCM_ADDR 0x80 + #define M9_PCM_ADDR 0x90 + #define M10_PCM_ADDR 0xA0 + #define M11_PCM_ADDR 0xB0 + #define M12_PCM_ADDR 0xC0 + #define M13_PCM_ADDR 0xD0 + #define M14_PCM_ADDR 0xE0 + #define M15_PCM_ADDR 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_pcm_md:1; + REGWORD v_c4_pol:1; + REGWORD v_f0_neg:1; + REGWORD v_f0_len:1; + REGWORD v_pcm_addr:4; + } bit_r_pcm_md0; + + typedef union {REGWORD reg; bit_r_pcm_md0 bit;} reg_r_pcm_md0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_CONF_EN 0x18 + +#define M_CONF_EN 0x01 +#define M_ULAW 0x80 + + typedef struct // bitmap construction + { + REGWORD v_conf_en:1; + REGWORD reserved_53:6; + REGWORD v_ulaw:1; + } bit_r_conf_en; + + typedef union {REGWORD reg; bit_r_conf_en bit;} reg_r_conf_en; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_TI_WD 0x1A + +#define M_EV_TS 0x0F + #define M1_EV_TS 0x01 + #define M2_EV_TS 0x02 + #define M3_EV_TS 0x03 + #define M4_EV_TS 0x04 + #define M5_EV_TS 0x05 + #define M6_EV_TS 0x06 + #define M7_EV_TS 0x07 + #define M8_EV_TS 0x08 + #define M9_EV_TS 0x09 + #define M10_EV_TS 0x0A + #define M11_EV_TS 0x0B + #define M12_EV_TS 0x0C + #define M13_EV_TS 0x0D + #define M14_EV_TS 0x0E + #define M15_EV_TS 0x0F +#define M_WD_TS 0xF0 + #define M1_WD_TS 0x10 + #define M2_WD_TS 0x20 + #define M3_WD_TS 0x30 + #define M4_WD_TS 0x40 + #define M5_WD_TS 0x50 + #define M6_WD_TS 0x60 + #define M7_WD_TS 0x70 + #define M8_WD_TS 0x80 + #define M9_WD_TS 0x90 + #define M10_WD_TS 0xA0 + #define M11_WD_TS 0xB0 + #define M12_WD_TS 0xC0 + #define M13_WD_TS 0xD0 + #define M14_WD_TS 0xE0 + #define M15_WD_TS 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_ev_ts:4; + REGWORD v_wd_ts:4; + } bit_r_ti_wd; + + typedef union {REGWORD reg; bit_r_ti_wd bit;} reg_r_ti_wd; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BERT_WD_MD 0x1B + +#define M_PAT_SEQ 0x07 + #define M1_PAT_SEQ 0x01 + #define M2_PAT_SEQ 0x02 + #define M3_PAT_SEQ 0x03 + #define M4_PAT_SEQ 0x04 + #define M5_PAT_SEQ 0x05 + #define M6_PAT_SEQ 0x06 + #define M7_PAT_SEQ 0x07 +#define M_BERT_ERR 0x08 +#define M_AUTO_WD_RES 0x20 +#define M_WD_RES 0x80 + + typedef struct // bitmap construction + { + REGWORD v_pat_seq:3; + REGWORD v_bert_err:1; + REGWORD reserved_54:1; + REGWORD v_auto_wd_res:1; + REGWORD reserved_55:1; + REGWORD v_wd_res:1; + } bit_r_bert_wd_md; + + typedef union {REGWORD reg; bit_r_bert_wd_md bit;} reg_r_bert_wd_md; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_DTMF0 0x1C + +#define M_DTMF_EN 0x01 +#define M_HARM_SEL 0x02 +#define M_DTMF_RX_CH 0x04 +#define M_DTMF_STOP 0x08 +#define M_CHBL_SEL 0x10 +#define M_RESTART_DTMF 0x40 +#define M_ULAW_SEL 0x80 + + typedef struct // bitmap construction + { + REGWORD v_dtmf_en:1; + REGWORD v_harm_sel:1; + REGWORD v_dtmf_rx_ch:1; + REGWORD v_dtmf_stop:1; + REGWORD v_chbl_sel:1; + REGWORD reserved_56:1; + REGWORD v_restart_dtmf:1; + REGWORD v_ulaw_sel:1; + } bit_r_dtmf0; + + typedef union {REGWORD reg; bit_r_dtmf0 bit;} reg_r_dtmf0; // register and bitmap access + + +//___________________________________________________________________________________// +// // +#define R_DTMF1 0x1D + +#define M_DTMF1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_dtmf1:8; + } bit_r_dtmf1; + + typedef union {REGWORD reg; bit_r_dtmf1 bit;} reg_r_dtmf1; // register and bitmap access + +#define R_PWM0 0x38 + +#define M_PWM0 0xFF + + typedef struct // bitmap construction + { + REGWORD v_pwm0:8; + } bit_r_pwm0; + + typedef union {REGWORD reg; bit_r_pwm0 bit;} reg_r_pwm0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_PWM1 0x39 + +#define M_PWM1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_pwm1:8; + } bit_r_pwm1; + + typedef union {REGWORD reg; bit_r_pwm1 bit;} reg_r_pwm1; // register and bitmap access + +#define R_GPIO_IN0 0x40 + +#define M_GPIO_IN0 0x01 +#define M_GPIO_IN1 0x02 +#define M_GPIO_IN2 0x04 +#define M_GPIO_IN3 0x08 +#define M_GPIO_IN4 0x10 +#define M_GPIO_IN5 0x20 +#define M_GPIO_IN6 0x40 +#define M_GPIO_IN7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_in0:1; + REGWORD v_gpio_in1:1; + REGWORD v_gpio_in2:1; + REGWORD v_gpio_in3:1; + REGWORD v_gpio_in4:1; + REGWORD v_gpio_in5:1; + REGWORD v_gpio_in6:1; + REGWORD v_gpio_in7:1; + } bit_r_gpio_in0; + + typedef union {REGWORD reg; bit_r_gpio_in0 bit;} reg_r_gpio_in0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPIO_IN1 0x41 + +#define M_GPIO_IN8 0x01 +#define M_GPIO_IN9 0x02 +#define M_GPIO_IN10 0x04 +#define M_GPIO_IN11 0x08 +#define M_GPIO_IN12 0x10 +#define M_GPIO_IN13 0x20 +#define M_GPIO_IN14 0x40 +#define M_GPIO_IN15 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_in8:1; + REGWORD v_gpio_in9:1; + REGWORD v_gpio_in10:1; + REGWORD v_gpio_in11:1; + REGWORD v_gpio_in12:1; + REGWORD v_gpio_in13:1; + REGWORD v_gpio_in14:1; + REGWORD v_gpio_in15:1; + } bit_r_gpio_in1; + + typedef union {REGWORD reg; bit_r_gpio_in1 bit;} reg_r_gpio_in1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPI_IN0 0x44 + +#define M_GPI_IN0 0x01 +#define M_GPI_IN1 0x02 +#define M_GPI_IN2 0x04 +#define M_GPI_IN3 0x08 +#define M_GPI_IN4 0x10 +#define M_GPI_IN5 0x20 +#define M_GPI_IN6 0x40 +#define M_GPI_IN7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpi_in0:1; + REGWORD v_gpi_in1:1; + REGWORD v_gpi_in2:1; + REGWORD v_gpi_in3:1; + REGWORD v_gpi_in4:1; + REGWORD v_gpi_in5:1; + REGWORD v_gpi_in6:1; + REGWORD v_gpi_in7:1; + } bit_r_gpi_in0; + + typedef union {REGWORD reg; bit_r_gpi_in0 bit;} reg_r_gpi_in0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPI_IN1 0x45 + +#define M_GPI_IN8 0x01 +#define M_GPI_IN9 0x02 +#define M_GPI_IN10 0x04 +#define M_GPI_IN11 0x08 +#define M_GPI_IN12 0x10 +#define M_GPI_IN13 0x20 +#define M_GPI_IN14 0x40 +#define M_GPI_IN15 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpi_in8:1; + REGWORD v_gpi_in9:1; + REGWORD v_gpi_in10:1; + REGWORD v_gpi_in11:1; + REGWORD v_gpi_in12:1; + REGWORD v_gpi_in13:1; + REGWORD v_gpi_in14:1; + REGWORD v_gpi_in15:1; + } bit_r_gpi_in1; + + typedef union {REGWORD reg; bit_r_gpi_in1 bit;} reg_r_gpi_in1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPI_IN2 0x46 + +#define M_GPI_IN16 0x01 +#define M_GPI_IN17 0x02 +#define M_GPI_IN18 0x04 +#define M_GPI_IN19 0x08 +#define M_GPI_IN20 0x10 +#define M_GPI_IN21 0x20 +#define M_GPI_IN22 0x40 +#define M_GPI_IN23 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpi_in16:1; + REGWORD v_gpi_in17:1; + REGWORD v_gpi_in18:1; + REGWORD v_gpi_in19:1; + REGWORD v_gpi_in20:1; + REGWORD v_gpi_in21:1; + REGWORD v_gpi_in22:1; + REGWORD v_gpi_in23:1; + } bit_r_gpi_in2; + + typedef union {REGWORD reg; bit_r_gpi_in2 bit;} reg_r_gpi_in2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPI_IN3 0x47 + +#define M_GPI_IN24 0x01 +#define M_GPI_IN25 0x02 +#define M_GPI_IN26 0x04 +#define M_GPI_IN27 0x08 +#define M_GPI_IN28 0x10 +#define M_GPI_IN29 0x20 +#define M_GPI_IN30 0x40 +#define M_GPI_IN31 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpi_in24:1; + REGWORD v_gpi_in25:1; + REGWORD v_gpi_in26:1; + REGWORD v_gpi_in27:1; + REGWORD v_gpi_in28:1; + REGWORD v_gpi_in29:1; + REGWORD v_gpi_in30:1; + REGWORD v_gpi_in31:1; + } bit_r_gpi_in3; + + typedef union {REGWORD reg; bit_r_gpi_in3 bit;} reg_r_gpi_in3; // register and bitmap access + +#define R_GPIO_OUT0 0x40 + +#define M_GPIO_OUT0 0x01 +#define M_GPIO_OUT1 0x02 +#define M_GPIO_OUT2 0x04 +#define M_GPIO_OUT3 0x08 +#define M_GPIO_OUT4 0x10 +#define M_GPIO_OUT5 0x20 +#define M_GPIO_OUT6 0x40 +#define M_GPIO_OUT7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_out0:1; + REGWORD v_gpio_out1:1; + REGWORD v_gpio_out2:1; + REGWORD v_gpio_out3:1; + REGWORD v_gpio_out4:1; + REGWORD v_gpio_out5:1; + REGWORD v_gpio_out6:1; + REGWORD v_gpio_out7:1; + } bit_r_gpio_out0; + + typedef union {REGWORD reg; bit_r_gpio_out0 bit;} reg_r_gpio_out0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPIO_OUT1 0x41 + +#define M_GPIO_OUT8 0x01 +#define M_GPIO_OUT9 0x02 +#define M_GPIO_OUT10 0x04 +#define M_GPIO_OUT11 0x08 +#define M_GPIO_OUT12 0x10 +#define M_GPIO_OUT13 0x20 +#define M_GPIO_OUT14 0x40 +#define M_GPIO_OUT15 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_out8:1; + REGWORD v_gpio_out9:1; + REGWORD v_gpio_out10:1; + REGWORD v_gpio_out11:1; + REGWORD v_gpio_out12:1; + REGWORD v_gpio_out13:1; + REGWORD v_gpio_out14:1; + REGWORD v_gpio_out15:1; + } bit_r_gpio_out1; + + typedef union {REGWORD reg; bit_r_gpio_out1 bit;} reg_r_gpio_out1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPIO_EN0 0x42 + +#define M_GPIO_EN0 0x01 +#define M_GPIO_EN1 0x02 +#define M_GPIO_EN2 0x04 +#define M_GPIO_EN3 0x08 +#define M_GPIO_EN4 0x10 +#define M_GPIO_EN5 0x20 +#define M_GPIO_EN6 0x40 +#define M_GPIO_EN7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_en0:1; + REGWORD v_gpio_en1:1; + REGWORD v_gpio_en2:1; + REGWORD v_gpio_en3:1; + REGWORD v_gpio_en4:1; + REGWORD v_gpio_en5:1; + REGWORD v_gpio_en6:1; + REGWORD v_gpio_en7:1; + } bit_r_gpio_en0; + + typedef union {REGWORD reg; bit_r_gpio_en0 bit;} reg_r_gpio_en0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPIO_EN1 0x43 + +#define M_GPIO_EN8 0x01 +#define M_GPIO_EN9 0x02 +#define M_GPIO_EN10 0x04 +#define M_GPIO_EN11 0x08 +#define M_GPIO_EN12 0x10 +#define M_GPIO_EN13 0x20 +#define M_GPIO_EN14 0x40 +#define M_GPIO_EN15 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_en8:1; + REGWORD v_gpio_en9:1; + REGWORD v_gpio_en10:1; + REGWORD v_gpio_en11:1; + REGWORD v_gpio_en12:1; + REGWORD v_gpio_en13:1; + REGWORD v_gpio_en14:1; + REGWORD v_gpio_en15:1; + } bit_r_gpio_en1; + + typedef union {REGWORD reg; bit_r_gpio_en1 bit;} reg_r_gpio_en1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_GPIO_SEL 0x44 + +#define M_GPIO_SEL0 0x01 +#define M_GPIO_SEL1 0x02 +#define M_GPIO_SEL2 0x04 +#define M_GPIO_SEL3 0x08 +#define M_GPIO_SEL4 0x10 +#define M_GPIO_SEL5 0x20 +#define M_GPIO_SEL6 0x40 +#define M_GPIO_SEL7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_gpio_sel0:1; + REGWORD v_gpio_sel1:1; + REGWORD v_gpio_sel2:1; + REGWORD v_gpio_sel3:1; + REGWORD v_gpio_sel4:1; + REGWORD v_gpio_sel5:1; + REGWORD v_gpio_sel6:1; + REGWORD v_gpio_sel7:1; + } bit_r_gpio_sel; + + typedef union {REGWORD reg; bit_r_gpio_sel bit;} reg_r_gpio_sel; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_CTRL 0x45 + +#define M_BRG_CS 0x07 + #define M1_BRG_CS 0x01 + #define M2_BRG_CS 0x02 + #define M3_BRG_CS 0x03 + #define M4_BRG_CS 0x04 + #define M5_BRG_CS 0x05 + #define M6_BRG_CS 0x06 + #define M7_BRG_CS 0x07 +#define M_BRG_ADDR 0x18 + #define M1_BRG_ADDR 0x08 + #define M2_BRG_ADDR 0x10 + #define M3_BRG_ADDR 0x18 +#define M_BRG_CS_SRC 0x80 + + typedef struct // bitmap construction + { + REGWORD v_brg_cs:3; + REGWORD v_brg_addr:2; + REGWORD reserved_57:2; + REGWORD v_brg_cs_src:1; + } bit_r_brg_ctrl; + + typedef union {REGWORD reg; bit_r_brg_ctrl bit;} reg_r_brg_ctrl; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_PWM_MD 0x46 + +#define M_EXT_IRQ_EN 0x08 +#define M_PWM0_MD 0x30 + #define M1_PWM0_MD 0x10 + #define M2_PWM0_MD 0x20 + #define M3_PWM0_MD 0x30 +#define M_PWM1_MD 0xC0 + #define M1_PWM1_MD 0x40 + #define M2_PWM1_MD 0x80 + #define M3_PWM1_MD 0xC0 + + typedef struct // bitmap construction + { + REGWORD reserved_58:3; + REGWORD v_ext_irq_en:1; + REGWORD v_pwm0_md:2; + REGWORD v_pwm1_md:2; + } bit_r_pwm_md; + + typedef union {REGWORD reg; bit_r_pwm_md bit;} reg_r_pwm_md; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_MD 0x47 + +#define M_BRG_MD0 0x01 +#define M_BRG_MD1 0x02 +#define M_BRG_MD2 0x04 +#define M_BRG_MD3 0x08 +#define M_BRG_MD4 0x10 +#define M_BRG_MD5 0x20 +#define M_BRG_MD6 0x40 +#define M_BRG_MD7 0x80 + + typedef struct // bitmap construction + { + REGWORD v_brg_md0:1; + REGWORD v_brg_md1:1; + REGWORD v_brg_md2:1; + REGWORD v_brg_md3:1; + REGWORD v_brg_md4:1; + REGWORD v_brg_md5:1; + REGWORD v_brg_md6:1; + REGWORD v_brg_md7:1; + } bit_r_brg_md; + + typedef union {REGWORD reg; bit_r_brg_md bit;} reg_r_brg_md; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM0 0x48 + +#define M_BRG_TIM0_IDLE 0x0F + #define M1_BRG_TIM0_IDLE 0x01 + #define M2_BRG_TIM0_IDLE 0x02 + #define M3_BRG_TIM0_IDLE 0x03 + #define M4_BRG_TIM0_IDLE 0x04 + #define M5_BRG_TIM0_IDLE 0x05 + #define M6_BRG_TIM0_IDLE 0x06 + #define M7_BRG_TIM0_IDLE 0x07 + #define M8_BRG_TIM0_IDLE 0x08 + #define M9_BRG_TIM0_IDLE 0x09 + #define M10_BRG_TIM0_IDLE 0x0A + #define M11_BRG_TIM0_IDLE 0x0B + #define M12_BRG_TIM0_IDLE 0x0C + #define M13_BRG_TIM0_IDLE 0x0D + #define M14_BRG_TIM0_IDLE 0x0E + #define M15_BRG_TIM0_IDLE 0x0F +#define M_BRG_TIM0_CLK 0xF0 + #define M1_BRG_TIM0_CLK 0x10 + #define M2_BRG_TIM0_CLK 0x20 + #define M3_BRG_TIM0_CLK 0x30 + #define M4_BRG_TIM0_CLK 0x40 + #define M5_BRG_TIM0_CLK 0x50 + #define M6_BRG_TIM0_CLK 0x60 + #define M7_BRG_TIM0_CLK 0x70 + #define M8_BRG_TIM0_CLK 0x80 + #define M9_BRG_TIM0_CLK 0x90 + #define M10_BRG_TIM0_CLK 0xA0 + #define M11_BRG_TIM0_CLK 0xB0 + #define M12_BRG_TIM0_CLK 0xC0 + #define M13_BRG_TIM0_CLK 0xD0 + #define M14_BRG_TIM0_CLK 0xE0 + #define M15_BRG_TIM0_CLK 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_brg_tim0_idle:4; + REGWORD v_brg_tim0_clk:4; + } bit_r_brg_tim0; + + typedef union {REGWORD reg; bit_r_brg_tim0 bit;} reg_r_brg_tim0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM1 0x49 + +#define M_BRG_TIM1_IDLE 0x0F + #define M1_BRG_TIM1_IDLE 0x01 + #define M2_BRG_TIM1_IDLE 0x02 + #define M3_BRG_TIM1_IDLE 0x03 + #define M4_BRG_TIM1_IDLE 0x04 + #define M5_BRG_TIM1_IDLE 0x05 + #define M6_BRG_TIM1_IDLE 0x06 + #define M7_BRG_TIM1_IDLE 0x07 + #define M8_BRG_TIM1_IDLE 0x08 + #define M9_BRG_TIM1_IDLE 0x09 + #define M10_BRG_TIM1_IDLE 0x0A + #define M11_BRG_TIM1_IDLE 0x0B + #define M12_BRG_TIM1_IDLE 0x0C + #define M13_BRG_TIM1_IDLE 0x0D + #define M14_BRG_TIM1_IDLE 0x0E + #define M15_BRG_TIM1_IDLE 0x0F +#define M_BRG_TIM1_CLK 0xF0 + #define M1_BRG_TIM1_CLK 0x10 + #define M2_BRG_TIM1_CLK 0x20 + #define M3_BRG_TIM1_CLK 0x30 + #define M4_BRG_TIM1_CLK 0x40 + #define M5_BRG_TIM1_CLK 0x50 + #define M6_BRG_TIM1_CLK 0x60 + #define M7_BRG_TIM1_CLK 0x70 + #define M8_BRG_TIM1_CLK 0x80 + #define M9_BRG_TIM1_CLK 0x90 + #define M10_BRG_TIM1_CLK 0xA0 + #define M11_BRG_TIM1_CLK 0xB0 + #define M12_BRG_TIM1_CLK 0xC0 + #define M13_BRG_TIM1_CLK 0xD0 + #define M14_BRG_TIM1_CLK 0xE0 + #define M15_BRG_TIM1_CLK 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_brg_tim1_idle:4; + REGWORD v_brg_tim1_clk:4; + } bit_r_brg_tim1; + + typedef union {REGWORD reg; bit_r_brg_tim1 bit;} reg_r_brg_tim1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM2 0x4A + +#define M_BRG_TIM2_IDLE 0x0F + #define M1_BRG_TIM2_IDLE 0x01 + #define M2_BRG_TIM2_IDLE 0x02 + #define M3_BRG_TIM2_IDLE 0x03 + #define M4_BRG_TIM2_IDLE 0x04 + #define M5_BRG_TIM2_IDLE 0x05 + #define M6_BRG_TIM2_IDLE 0x06 + #define M7_BRG_TIM2_IDLE 0x07 + #define M8_BRG_TIM2_IDLE 0x08 + #define M9_BRG_TIM2_IDLE 0x09 + #define M10_BRG_TIM2_IDLE 0x0A + #define M11_BRG_TIM2_IDLE 0x0B + #define M12_BRG_TIM2_IDLE 0x0C + #define M13_BRG_TIM2_IDLE 0x0D + #define M14_BRG_TIM2_IDLE 0x0E + #define M15_BRG_TIM2_IDLE 0x0F +#define M_BRG_TIM2_CLK 0xF0 + #define M1_BRG_TIM2_CLK 0x10 + #define M2_BRG_TIM2_CLK 0x20 + #define M3_BRG_TIM2_CLK 0x30 + #define M4_BRG_TIM2_CLK 0x40 + #define M5_BRG_TIM2_CLK 0x50 + #define M6_BRG_TIM2_CLK 0x60 + #define M7_BRG_TIM2_CLK 0x70 + #define M8_BRG_TIM2_CLK 0x80 + #define M9_BRG_TIM2_CLK 0x90 + #define M10_BRG_TIM2_CLK 0xA0 + #define M11_BRG_TIM2_CLK 0xB0 + #define M12_BRG_TIM2_CLK 0xC0 + #define M13_BRG_TIM2_CLK 0xD0 + #define M14_BRG_TIM2_CLK 0xE0 + #define M15_BRG_TIM2_CLK 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_brg_tim2_idle:4; + REGWORD v_brg_tim2_clk:4; + } bit_r_brg_tim2; + + typedef union {REGWORD reg; bit_r_brg_tim2 bit;} reg_r_brg_tim2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM3 0x4B + +#define M_BRG_TIM3_IDLE 0x0F + #define M1_BRG_TIM3_IDLE 0x01 + #define M2_BRG_TIM3_IDLE 0x02 + #define M3_BRG_TIM3_IDLE 0x03 + #define M4_BRG_TIM3_IDLE 0x04 + #define M5_BRG_TIM3_IDLE 0x05 + #define M6_BRG_TIM3_IDLE 0x06 + #define M7_BRG_TIM3_IDLE 0x07 + #define M8_BRG_TIM3_IDLE 0x08 + #define M9_BRG_TIM3_IDLE 0x09 + #define M10_BRG_TIM3_IDLE 0x0A + #define M11_BRG_TIM3_IDLE 0x0B + #define M12_BRG_TIM3_IDLE 0x0C + #define M13_BRG_TIM3_IDLE 0x0D + #define M14_BRG_TIM3_IDLE 0x0E + #define M15_BRG_TIM3_IDLE 0x0F +#define M_BRG_TIM3_CLK 0xF0 + #define M1_BRG_TIM3_CLK 0x10 + #define M2_BRG_TIM3_CLK 0x20 + #define M3_BRG_TIM3_CLK 0x30 + #define M4_BRG_TIM3_CLK 0x40 + #define M5_BRG_TIM3_CLK 0x50 + #define M6_BRG_TIM3_CLK 0x60 + #define M7_BRG_TIM3_CLK 0x70 + #define M8_BRG_TIM3_CLK 0x80 + #define M9_BRG_TIM3_CLK 0x90 + #define M10_BRG_TIM3_CLK 0xA0 + #define M11_BRG_TIM3_CLK 0xB0 + #define M12_BRG_TIM3_CLK 0xC0 + #define M13_BRG_TIM3_CLK 0xD0 + #define M14_BRG_TIM3_CLK 0xE0 + #define M15_BRG_TIM3_CLK 0xF0 + + typedef struct // bitmap construction + { + REGWORD v_brg_tim3_idle:4; + REGWORD v_brg_tim3_clk:4; + } bit_r_brg_tim3; + + typedef union {REGWORD reg; bit_r_brg_tim3 bit;} reg_r_brg_tim3; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM_SEL01 0x4C + +#define M_BRG_WR_SEL0 0x03 + #define M1_BRG_WR_SEL0 0x01 + #define M2_BRG_WR_SEL0 0x02 + #define M3_BRG_WR_SEL0 0x03 +#define M_BRG_RD_SEL0 0x0C + #define M1_BRG_RD_SEL0 0x04 + #define M2_BRG_RD_SEL0 0x08 + #define M3_BRG_RD_SEL0 0x0C +#define M_BRG_WR_SEL1 0x30 + #define M1_BRG_WR_SEL1 0x10 + #define M2_BRG_WR_SEL1 0x20 + #define M3_BRG_WR_SEL1 0x30 +#define M_BRG_RD_SEL1 0xC0 + #define M1_BRG_RD_SEL1 0x40 + #define M2_BRG_RD_SEL1 0x80 + #define M3_BRG_RD_SEL1 0xC0 + + typedef struct // bitmap construction + { + REGWORD v_brg_wr_sel0:2; + REGWORD v_brg_rd_sel0:2; + REGWORD v_brg_wr_sel1:2; + REGWORD v_brg_rd_sel1:2; + } bit_r_brg_tim_sel01; + + typedef union {REGWORD reg; bit_r_brg_tim_sel01 bit;} reg_r_brg_tim_sel01; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM_SEL23 0x4D + +#define M_BRG_WR_SEL2 0x03 + #define M1_BRG_WR_SEL2 0x01 + #define M2_BRG_WR_SEL2 0x02 + #define M3_BRG_WR_SEL2 0x03 +#define M_BRG_RD_SEL2 0x0C + #define M1_BRG_RD_SEL2 0x04 + #define M2_BRG_RD_SEL2 0x08 + #define M3_BRG_RD_SEL2 0x0C +#define M_BRG_WR_SEL3 0x30 + #define M1_BRG_WR_SEL3 0x10 + #define M2_BRG_WR_SEL3 0x20 + #define M3_BRG_WR_SEL3 0x30 +#define M_BRG_RD_SEL3 0xC0 + #define M1_BRG_RD_SEL3 0x40 + #define M2_BRG_RD_SEL3 0x80 + #define M3_BRG_RD_SEL3 0xC0 + + typedef struct // bitmap construction + { + REGWORD v_brg_wr_sel2:2; + REGWORD v_brg_rd_sel2:2; + REGWORD v_brg_wr_sel3:2; + REGWORD v_brg_rd_sel3:2; + } bit_r_brg_tim_sel23; + + typedef union {REGWORD reg; bit_r_brg_tim_sel23 bit;} reg_r_brg_tim_sel23; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM_SEL45 0x4E + +#define M_BRG_WR_SEL4 0x03 + #define M1_BRG_WR_SEL4 0x01 + #define M2_BRG_WR_SEL4 0x02 + #define M3_BRG_WR_SEL4 0x03 +#define M_BRG_RD_SEL4 0x0C + #define M1_BRG_RD_SEL4 0x04 + #define M2_BRG_RD_SEL4 0x08 + #define M3_BRG_RD_SEL4 0x0C +#define M_BRG_WR_SEL5 0x30 + #define M1_BRG_WR_SEL5 0x10 + #define M2_BRG_WR_SEL5 0x20 + #define M3_BRG_WR_SEL5 0x30 +#define M_BRG_RD_SEL5 0xC0 + #define M1_BRG_RD_SEL5 0x40 + #define M2_BRG_RD_SEL5 0x80 + #define M3_BRG_RD_SEL5 0xC0 + + typedef struct // bitmap construction + { + REGWORD v_brg_wr_sel4:2; + REGWORD v_brg_rd_sel4:2; + REGWORD v_brg_wr_sel5:2; + REGWORD v_brg_rd_sel5:2; + } bit_r_brg_tim_sel45; + + typedef union {REGWORD reg; bit_r_brg_tim_sel45 bit;} reg_r_brg_tim_sel45; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_BRG_TIM_SEL67 0x4F + +#define M_BRG_WR_SEL6 0x03 + #define M1_BRG_WR_SEL6 0x01 + #define M2_BRG_WR_SEL6 0x02 + #define M3_BRG_WR_SEL6 0x03 +#define M_BRG_RD_SEL6 0x0C + #define M1_BRG_RD_SEL6 0x04 + #define M2_BRG_RD_SEL6 0x08 + #define M3_BRG_RD_SEL6 0x0C +#define M_BRG_WR_SEL7 0x30 + #define M1_BRG_WR_SEL7 0x10 + #define M2_BRG_WR_SEL7 0x20 + #define M3_BRG_WR_SEL7 0x30 +#define M_BRG_RD_SEL7 0xC0 + #define M1_BRG_RD_SEL7 0x40 + #define M2_BRG_RD_SEL7 0x80 + #define M3_BRG_RD_SEL7 0xC0 + + typedef struct // bitmap construction + { + REGWORD v_brg_wr_sel6:2; + REGWORD v_brg_rd_sel6:2; + REGWORD v_brg_wr_sel7:2; + REGWORD v_brg_rd_sel7:2; + } bit_r_brg_tim_sel67; + + typedef union {REGWORD reg; bit_r_brg_tim_sel67 bit;} reg_r_brg_tim_sel67; // register and bitmap access + +#define A_FIFO_DATA0 0x80 + +#define M_FIFO_DATA0 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data0:8; + } bit_a_fifo_data0; + + typedef union {REGWORD reg; bit_a_fifo_data0 bit;} reg_a_fifo_data0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA1 0x81 + +#define M_FIFO_DATA1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data1:8; + } bit_a_fifo_data1; + + typedef union {REGWORD reg; bit_a_fifo_data1 bit;} reg_a_fifo_data1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA2 0x82 + +#define M_FIFO_DATA2 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data2:8; + } bit_a_fifo_data2; + + typedef union {REGWORD reg; bit_a_fifo_data2 bit;} reg_a_fifo_data2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA3 0x83 + +#define M_FIFO_DATA3 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data3:8; + } bit_a_fifo_data3; + + typedef union {REGWORD reg; bit_a_fifo_data3 bit;} reg_a_fifo_data3; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA0_NOINC 0x84 + +#define M_FIFO_DATA0_NOINC 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data0_noinc:8; + } bit_a_fifo_data0_noinc; + + typedef union {REGWORD reg; bit_a_fifo_data0_noinc bit;} reg_a_fifo_data0_noinc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA1_NOINC 0x85 + +#define M_FIFO_DATA_NOINC1 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data_noinc1:8; + } bit_a_fifo_data1_noinc; + + typedef union {REGWORD reg; bit_a_fifo_data1_noinc bit;} reg_a_fifo_data1_noinc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA2_NOINC 0x86 + +#define M_FIFO_DATA2_NOINC 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data2_noinc:8; + } bit_a_fifo_data2_noinc; + + typedef union {REGWORD reg; bit_a_fifo_data2_noinc bit;} reg_a_fifo_data2_noinc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_DATA3_NOINC 0x87 + +#define M_FIFO_DATA3_NOINC 0xFF + + typedef struct // bitmap construction + { + REGWORD v_fifo_data3_noinc:8; + } bit_a_fifo_data3_noinc; + + typedef union {REGWORD reg; bit_a_fifo_data3_noinc bit;} reg_a_fifo_data3_noinc; // register and bitmap access + +#define R_RAM_DATA 0xC0 + +#define M_RAM_DATA 0xFF + + typedef struct // bitmap construction + { + REGWORD v_ram_data:8; + } bit_r_ram_data; + + typedef union {REGWORD reg; bit_r_ram_data bit;} reg_r_ram_data; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL0 0xC8 + +#define M_IRQ_FIFO0_TX 0x01 +#define M_IRQ_FIFO0_RX 0x02 +#define M_IRQ_FIFO1_TX 0x04 +#define M_IRQ_FIFO1_RX 0x08 +#define M_IRQ_FIFO2_TX 0x10 +#define M_IRQ_FIFO2_RX 0x20 +#define M_IRQ_FIFO3_TX 0x40 +#define M_IRQ_FIFO3_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo0_tx:1; + REGWORD v_irq_fifo0_rx:1; + REGWORD v_irq_fifo1_tx:1; + REGWORD v_irq_fifo1_rx:1; + REGWORD v_irq_fifo2_tx:1; + REGWORD v_irq_fifo2_rx:1; + REGWORD v_irq_fifo3_tx:1; + REGWORD v_irq_fifo3_rx:1; + } bit_r_irq_fifo_bl0; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl0 bit;} reg_r_irq_fifo_bl0; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL1 0xC9 + +#define M_IRQ_FIFO4_TX 0x01 +#define M_IRQ_FIFO4_RX 0x02 +#define M_IRQ_FIFO5_TX 0x04 +#define M_IRQ_FIFO5_RX 0x08 +#define M_IRQ_FIFO6_TX 0x10 +#define M_IRQ_FIFO6_RX 0x20 +#define M_IRQ_FIFO7_TX 0x40 +#define M_IRQ_FIFO7_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo4_tx:1; + REGWORD v_irq_fifo4_rx:1; + REGWORD v_irq_fifo5_tx:1; + REGWORD v_irq_fifo5_rx:1; + REGWORD v_irq_fifo6_tx:1; + REGWORD v_irq_fifo6_rx:1; + REGWORD v_irq_fifo7_tx:1; + REGWORD v_irq_fifo7_rx:1; + } bit_r_irq_fifo_bl1; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl1 bit;} reg_r_irq_fifo_bl1; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL2 0xCA + +#define M_IRQ_FIFO8_TX 0x01 +#define M_IRQ_FIFO8_RX 0x02 +#define M_IRQ_FIFO9_TX 0x04 +#define M_IRQ_FIFO9_RX 0x08 +#define M_IRQ_FIFO10_TX 0x10 +#define M_IRQ_FIFO10_RX 0x20 +#define M_IRQ_FIFO11_TX 0x40 +#define M_IRQ_FIFO11_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo8_tx:1; + REGWORD v_irq_fifo8_rx:1; + REGWORD v_irq_fifo9_tx:1; + REGWORD v_irq_fifo9_rx:1; + REGWORD v_irq_fifo10_tx:1; + REGWORD v_irq_fifo10_rx:1; + REGWORD v_irq_fifo11_tx:1; + REGWORD v_irq_fifo11_rx:1; + } bit_r_irq_fifo_bl2; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl2 bit;} reg_r_irq_fifo_bl2; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL3 0xCB + +#define M_IRQ_FIFO12_TX 0x01 +#define M_IRQ_FIFO12_RX 0x02 +#define M_IRQ_FIFO13_TX 0x04 +#define M_IRQ_FIFO13_RX 0x08 +#define M_IRQ_FIFO14_TX 0x10 +#define M_IRQ_FIFO14_RX 0x20 +#define M_IRQ_FIFO15_TX 0x40 +#define M_IRQ_FIFO15_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo12_tx:1; + REGWORD v_irq_fifo12_rx:1; + REGWORD v_irq_fifo13_tx:1; + REGWORD v_irq_fifo13_rx:1; + REGWORD v_irq_fifo14_tx:1; + REGWORD v_irq_fifo14_rx:1; + REGWORD v_irq_fifo15_tx:1; + REGWORD v_irq_fifo15_rx:1; + } bit_r_irq_fifo_bl3; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl3 bit;} reg_r_irq_fifo_bl3; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL4 0xCC + +#define M_IRQ_FIFO16_TX 0x01 +#define M_IRQ_FIFO16_RX 0x02 +#define M_IRQ_FIFO17_TX 0x04 +#define M_IRQ_FIFO17_RX 0x08 +#define M_IRQ_FIFO18_TX 0x10 +#define M_IRQ_FIFO18_RX 0x20 +#define M_IRQ_FIFO19_TX 0x40 +#define M_IRQ_FIFO19_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo16_tx:1; + REGWORD v_irq_fifo16_rx:1; + REGWORD v_irq_fifo17_tx:1; + REGWORD v_irq_fifo17_rx:1; + REGWORD v_irq_fifo18_tx:1; + REGWORD v_irq_fifo18_rx:1; + REGWORD v_irq_fifo19_tx:1; + REGWORD v_irq_fifo19_rx:1; + } bit_r_irq_fifo_bl4; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl4 bit;} reg_r_irq_fifo_bl4; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL5 0xCD + +#define M_IRQ_FIFO20_TX 0x01 +#define M_IRQ_FIFO20_RX 0x02 +#define M_IRQ_FIFO21_TX 0x04 +#define M_IRQ_FIFO21_RX 0x08 +#define M_IRQ_FIFO22_TX 0x10 +#define M_IRQ_FIFO22_RX 0x20 +#define M_IRQ_FIFO23_TX 0x40 +#define M_IRQ_FIFO23_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo20_tx:1; + REGWORD v_irq_fifo20_rx:1; + REGWORD v_irq_fifo21_tx:1; + REGWORD v_irq_fifo21_rx:1; + REGWORD v_irq_fifo22_tx:1; + REGWORD v_irq_fifo22_rx:1; + REGWORD v_irq_fifo23_tx:1; + REGWORD v_irq_fifo23_rx:1; + } bit_r_irq_fifo_bl5; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl5 bit;} reg_r_irq_fifo_bl5; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL6 0xCE + +#define M_IRQ_FIFO24_TX 0x01 +#define M_IRQ_FIFO24_RX 0x02 +#define M_IRQ_FIFO25_TX 0x04 +#define M_IRQ_FIFO25_RX 0x08 +#define M_IRQ_FIFO26_TX 0x10 +#define M_IRQ_FIFO26_RX 0x20 +#define M_IRQ_FIFO27_TX 0x40 +#define M_IRQ_FIFO27_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo24_tx:1; + REGWORD v_irq_fifo24_rx:1; + REGWORD v_irq_fifo25_tx:1; + REGWORD v_irq_fifo25_rx:1; + REGWORD v_irq_fifo26_tx:1; + REGWORD v_irq_fifo26_rx:1; + REGWORD v_irq_fifo27_tx:1; + REGWORD v_irq_fifo27_rx:1; + } bit_r_irq_fifo_bl6; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl6 bit;} reg_r_irq_fifo_bl6; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define R_IRQ_FIFO_BL7 0xCF + +#define M_IRQ_FIFO28_TX 0x01 +#define M_IRQ_FIFO28_RX 0x02 +#define M_IRQ_FIFO29_TX 0x04 +#define M_IRQ_FIFO29_RX 0x08 +#define M_IRQ_FIFO30_TX 0x10 +#define M_IRQ_FIFO30_RX 0x20 +#define M_IRQ_FIFO31_TX 0x40 +#define M_IRQ_FIFO31_RX 0x80 + + typedef struct // bitmap construction + { + REGWORD v_irq_fifo28_tx:1; + REGWORD v_irq_fifo28_rx:1; + REGWORD v_irq_fifo29_tx:1; + REGWORD v_irq_fifo29_rx:1; + REGWORD v_irq_fifo30_tx:1; + REGWORD v_irq_fifo30_rx:1; + REGWORD v_irq_fifo31_tx:1; + REGWORD v_irq_fifo31_rx:1; + } bit_r_irq_fifo_bl7; + + typedef union {REGWORD reg; bit_r_irq_fifo_bl7 bit;} reg_r_irq_fifo_bl7; // register and bitmap access + +#define A_SL_CFG 0xD0 + +#define M_CH_DIR 0x01 +#define M_CH1_SEL 0x3E + #define M1_CH1_SEL 0x02 + #define M2_CH1_SEL 0x04 + #define M3_CH1_SEL 0x06 + #define M4_CH1_SEL 0x08 + #define M5_CH1_SEL 0x0A + #define M6_CH1_SEL 0x0C + #define M7_CH1_SEL 0x0E + #define M8_CH1_SEL 0x10 + #define M9_CH1_SEL 0x12 + #define M10_CH1_SEL 0x14 + #define M11_CH1_SEL 0x16 + #define M12_CH1_SEL 0x18 + #define M13_CH1_SEL 0x1A + #define M14_CH1_SEL 0x1C + #define M15_CH1_SEL 0x1E + #define M16_CH1_SEL 0x20 + #define M17_CH1_SEL 0x22 + #define M18_CH1_SEL 0x24 + #define M19_CH1_SEL 0x26 + #define M20_CH1_SEL 0x28 + #define M21_CH1_SEL 0x2A + #define M22_CH1_SEL 0x2C + #define M23_CH1_SEL 0x2E + #define M24_CH1_SEL 0x30 + #define M25_CH1_SEL 0x32 + #define M26_CH1_SEL 0x34 + #define M27_CH1_SEL 0x36 + #define M28_CH1_SEL 0x38 + #define M29_CH1_SEL 0x3A + #define M30_CH1_SEL 0x3C + #define M31_CH1_SEL 0x3E +#define M_ROUT 0xC0 + #define M1_ROUT 0x40 + #define M2_ROUT 0x80 + #define M3_ROUT 0xC0 + + typedef struct // bitmap construction + { + REGWORD v_ch_dir:1; + REGWORD v_ch1_sel:5; + REGWORD v_rout:2; + } bit_a_sl_cfg; + + typedef union {REGWORD reg; bit_a_sl_cfg bit;} reg_a_sl_cfg; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_CONF 0xD1 + +#define M_CONF_NUM 0x07 + #define M1_CONF_NUM 0x01 + #define M2_CONF_NUM 0x02 + #define M3_CONF_NUM 0x03 + #define M4_CONF_NUM 0x04 + #define M5_CONF_NUM 0x05 + #define M6_CONF_NUM 0x06 + #define M7_CONF_NUM 0x07 +#define M_NOISE_SUPPR 0x18 + #define M1_NOISE_SUPPR 0x08 + #define M2_NOISE_SUPPR 0x10 + #define M3_NOISE_SUPPR 0x18 +#define M_ATT_LEV 0x60 + #define M1_ATT_LEV 0x20 + #define M2_ATT_LEV 0x40 + #define M3_ATT_LEV 0x60 +#define M_CONF_SL 0x80 + + typedef struct // bitmap construction + { + REGWORD v_conf_num:3; + REGWORD v_noise_suppr:2; + REGWORD v_att_lev:2; + REGWORD v_conf_sl:1; + } bit_a_conf; + + typedef union {REGWORD reg; bit_a_conf bit;} reg_a_conf; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_CH_MSK 0xF4 + +#define M_CH_MSK 0xFF + + typedef struct // bitmap construction + { + REGWORD v_ch_msk:8; + } bit_a_ch_msk; + + typedef union {REGWORD reg; bit_a_ch_msk bit;} reg_a_ch_msk; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_CON_HDLC 0xFA + +#define M_IFF 0x01 +#define M_HDLC_TRP 0x02 +#define M_TRP_IRQ 0x1C + #define M1_TRP_IRQ 0x04 + #define M2_TRP_IRQ 0x08 + #define M3_TRP_IRQ 0x0C + #define M4_TRP_IRQ 0x10 + #define M5_TRP_IRQ 0x14 + #define M6_TRP_IRQ 0x18 + #define M7_TRP_IRQ 0x1C +#define M_DATA_FLOW 0xE0 + #define M1_DATA_FLOW 0x20 + #define M2_DATA_FLOW 0x40 + #define M3_DATA_FLOW 0x60 + #define M4_DATA_FLOW 0x80 + #define M5_DATA_FLOW 0xA0 + #define M6_DATA_FLOW 0xC0 + #define M7_DATA_FLOW 0xE0 + + typedef struct // bitmap construction + { + REGWORD v_iff:1; + REGWORD v_hdlc_trp:1; + REGWORD v_trp_irq:3; + REGWORD v_data_flow:3; + } bit_a_con_hdlc; + + typedef union {REGWORD reg; bit_a_con_hdlc bit;} reg_a_con_hdlc; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_SUBCH_CFG 0xFB + +#define M_BIT_CNT 0x07 + #define M1_BIT_CNT 0x01 + #define M2_BIT_CNT 0x02 + #define M3_BIT_CNT 0x03 + #define M4_BIT_CNT 0x04 + #define M5_BIT_CNT 0x05 + #define M6_BIT_CNT 0x06 + #define M7_BIT_CNT 0x07 +#define M_START_BIT 0x38 + #define M1_START_BIT 0x08 + #define M2_START_BIT 0x10 + #define M3_START_BIT 0x18 + #define M4_START_BIT 0x20 + #define M5_START_BIT 0x28 + #define M6_START_BIT 0x30 + #define M7_START_BIT 0x38 +#define M_LOOP_FIFO 0x40 +#define M_INV_DATA 0x80 + + typedef struct // bitmap construction + { + REGWORD v_bit_cnt:3; + REGWORD v_start_bit:3; + REGWORD v_loop_fifo:1; + REGWORD v_inv_data:1; + } bit_a_subch_cfg; + + typedef union {REGWORD reg; bit_a_subch_cfg bit;} reg_a_subch_cfg; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_FIFO_SEQ 0xFD + +#define M_NEXT_FIFO_DIR 0x01 +#define M_NEXT_FIFO_NUM 0x3E + #define M1_NEXT_FIFO_NUM 0x02 + #define M2_NEXT_FIFO_NUM 0x04 + #define M3_NEXT_FIFO_NUM 0x06 + #define M4_NEXT_FIFO_NUM 0x08 + #define M5_NEXT_FIFO_NUM 0x0A + #define M6_NEXT_FIFO_NUM 0x0C + #define M7_NEXT_FIFO_NUM 0x0E + #define M8_NEXT_FIFO_NUM 0x10 + #define M9_NEXT_FIFO_NUM 0x12 + #define M10_NEXT_FIFO_NUM 0x14 + #define M11_NEXT_FIFO_NUM 0x16 + #define M12_NEXT_FIFO_NUM 0x18 + #define M13_NEXT_FIFO_NUM 0x1A + #define M14_NEXT_FIFO_NUM 0x1C + #define M15_NEXT_FIFO_NUM 0x1E + #define M16_NEXT_FIFO_NUM 0x20 + #define M17_NEXT_FIFO_NUM 0x22 + #define M18_NEXT_FIFO_NUM 0x24 + #define M19_NEXT_FIFO_NUM 0x26 + #define M20_NEXT_FIFO_NUM 0x28 + #define M21_NEXT_FIFO_NUM 0x2A + #define M22_NEXT_FIFO_NUM 0x2C + #define M23_NEXT_FIFO_NUM 0x2E + #define M24_NEXT_FIFO_NUM 0x30 + #define M25_NEXT_FIFO_NUM 0x32 + #define M26_NEXT_FIFO_NUM 0x34 + #define M27_NEXT_FIFO_NUM 0x36 + #define M28_NEXT_FIFO_NUM 0x38 + #define M29_NEXT_FIFO_NUM 0x3A + #define M30_NEXT_FIFO_NUM 0x3C + #define M31_NEXT_FIFO_NUM 0x3E +#define M_SEQ_END 0x40 + + typedef struct // bitmap construction + { + REGWORD v_next_fifo_dir:1; + REGWORD v_next_fifo_num:5; + REGWORD v_seq_end:1; + REGWORD reserved_59:1; + } bit_a_fifo_seq; + + typedef union {REGWORD reg; bit_a_fifo_seq bit;} reg_a_fifo_seq; // register and bitmap access + +//___________________________________________________________________________________// +// // +#define A_IRQ_MSK 0xFF + +#define M_IRQ 0x01 +#define M_BERT_EN 0x02 +#define M_MIX_IRQ 0x04 + + typedef struct // bitmap construction + { + REGWORD v_irq:1; + REGWORD v_bert_en:1; + REGWORD v_mix_irq:1; + REGWORD reserved_60:5; + } bit_a_irq_msk; + + typedef union {REGWORD reg; bit_a_irq_msk bit;} reg_a_irq_msk; // register and bitmap access + +#endif + +//______________________________ end of register list _______________________________// +// // diff -puN /dev/null drivers/isdn/hisax/hfc4s8s_l1.c --- /dev/null 2003-09-15 06:40:47.000000000 -0700 +++ 25-akpm/drivers/isdn/hisax/hfc4s8s_l1.c 2005-01-22 18:38:31.745127392 -0800 @@ -0,0 +1,1293 @@ +/*************************************************************************/ +/* $Id: hfc4s8s_l1.c,v 1.8 2004/07/13 14:13:34 martinb1 Exp $ */ +/* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */ +/* The low layer (L1) is implemented as a loadable module for usage with */ +/* the HiSax isdn driver for passive cards. */ +/* */ +/* Author: Werner Cornelius */ +/* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */ +/* */ +/* Driver maintained by Cologne Chip */ +/* - Martin Bachem, support@colognechip.com */ +/* */ +/* This driver only works with chip revisions >= 1, older revision 0 */ +/* engineering samples (only first manufacturer sample cards) will not */ +/* work and are rejected by the driver. */ +/* */ +/* This file distributed under the GNU GPL. */ +/* */ +/* See Version History at the end of this file */ +/* */ +/*************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hisax_if.h" +#include "hfc48scu.h" + +static const char hfc4s8s_rev[] = "$Revision: 1.8 $"; + +/***************************************************************/ +/* adjustable transparent mode fifo threshold */ +/* The value defines the used fifo threshold with the equation */ +/* */ +/* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */ +/* */ +/* The default value is 5 which results in a buffer size of 64 */ +/* and an interrupt rate of 8ms. */ +/* The maximum value is 7 due to fifo size restrictions. */ +/* Values below 3-4 are not recommended due to high interrupt */ +/* load of the processor. For non critical applications the */ +/* value should be raised to 7 to reduce any interrupt overhead*/ +/***************************************************************/ +#define TRANS_FIFO_THRES 5 + +/****************************************/ +/* Enable 32 bit fifo access if defined */ +/* Only usefull on intel pc based arch. */ +/* Default is enabled (PC usage). */ +/****************************************/ +#define FIFO_32BIT_ACCESS + +/*************/ +/* constants */ +/*************/ +#define MAX_HFC8_CARDS 4 +#define HFC_MAX_ST 8 +#define HFC_MAX_CHANNELS 32 +#define MAX_D_FRAME_SIZE 270 +#define MAX_B_FRAME_SIZE 1536 +#define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf) +#define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES) +#define MAX_F_CNT 0x0f + +/******************/ +/* types and vars */ +/******************/ +struct hfc8s_hw; + +/* table entry in the PCI devices list */ +typedef struct { + int vendor_id; + int device_id; + int chip_id; + int sub_vendor_id; + int sub_device_id; + char *vendor_name; + char *card_name; + int max_channels; + int clock_mode; +} PCI_ENTRY; + +/* static list of available card types */ +static const PCI_ENTRY __devinitdata id_list[] = + { + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_4S, CHIP_ID_4S, 0x1397, 0x8b4, "Cologne Chip", "HFC-4S Eval", 4, 0}, + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_8S, CHIP_ID_8S, 0x1397, 0x16b8, "Cologne Chip", "HFC-8S Eval", 8, 0}, + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_4S, CHIP_ID_4S, 0x1397, 0xb520, "Cologne Chip", "IOB4ST", 4, 1}, + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_8S, CHIP_ID_8S, 0x1397, 0xb522, "Cologne Chip", "IOB8ST", 8, 1}, + {0, 0, 0, 0, 0, (char *)NULL, (char *)NULL, 0, 0}, + }; + + +/***********/ +/* layer 1 */ +/***********/ +struct hfc8s_btype { + spinlock_t lock; + struct hisax_b_if b_if; + struct hfc8s_l1 *l1p; + struct sk_buff_head tx_queue; + struct sk_buff *tx_skb; + struct sk_buff *rx_skb; + __u8 *rx_ptr; + int tx_cnt; + int bchan; + int mode; +}; + +struct hfc8s_l1 { + spinlock_t lock; + struct hfc8s_hw *hw; // pointer to hardware area + int l1_state; // actual l1 state + struct timer_list l1_timer; // layer 1 timer structure + int nt_mode; // set to nt mode + int st_num; // own index + int enabled; // interface is enabled + struct sk_buff_head d_tx_queue; // send queue + int tx_cnt; // bytes to send + struct hisax_d_if d_if; // D-channel interface + struct hfc8s_btype b_ch[2]; // B-channel data + struct hisax_b_if *b_table[2]; +}; + +/**********************/ +/* hardware structure */ +/**********************/ +struct hfc8s_hw { + spinlock_t lock; + int ifnum; + int iobase; + int nt_mode; + u_char *membase; + u_char *hw_membase; + struct pci_dev *pci_dev; + int max_st_ports; + int max_fifo; + int clock_mode; + int irq; + int fifo_sched_cnt; + struct work_struct tqueue; + struct hfc8s_l1 l1[HFC_MAX_ST]; + char card_name[60]; + struct { + u_char r_irq_ctrl; + u_char r_ctrl0; + volatile u_char r_irq_statech; // active isdn l1 status + u_char r_irqmsk_statchg; // enabled isdn status ints + u_char r_irq_fifo_blx[8]; // fifo status registers + u_char fifo_rx_trans_enables[8]; // mask for enabled transparent rx fifos + u_char fifo_slow_timer_service[8]; // mask for fifos needing slower timer service + volatile u_char r_irq_oview; // contents of overview register + volatile u_char timer_irq; + int timer_usg_cnt; // number of channels using timer + } mr; +}; + + +/*************/ +/* constants */ +/*************/ +#define CLKDEL_NT 0x6c +#define CLKDEL_TE 0xf +#define CTRL0_NT 4 +#define CTRL0_TE 0 + +#define L1_TIMER_T4 2 // minimum in jiffies +#define L1_TIMER_T3 (7 * HZ) // activation timeout +#define L1_TIMER_T1 ((120 * HZ) / 1000) // NT mode deactivation timeout + +/***************************/ +/* inline function defines */ +/***************************/ +// memory write and dummy IO read to avoid PCI byte merge problems +#define Write_hfc8(a,b,c) {(*((volatile u_char *)(a->membase+b)) = c); inb(a->iobase+4);} +// memory write without dummy IO access for fifo data access +#define fWrite_hfc8(a,b,c) (*((volatile u_char *)(a->membase+b)) = c) +#define Read_hfc8(a,b) (*((volatile u_char *)(a->membase+b))) +#define Write_hfc16(a,b,c) (*((volatile unsigned short *)(a->membase+b)) = c) +#define Read_hfc16(a,b) (*((volatile unsigned short *)(a->membase+b))) +#define Write_hfc32(a,b,c) (*((volatile unsigned long *)(a->membase+b)) = c) +#define Read_hfc32(a,b) (*((volatile unsigned long *)(a->membase+b))) +#define wait_busy(a) {while ((Read_hfc8(a, R_STATUS) & M_BUSY));} +#define PCI_ENA_MEMIO 0x03 + + +/*******************************************************************************************/ +/* function to read critical counter registers that may be udpated by the chip during read */ +/*******************************************************************************************/ + +static volatile u_char Read_hfc8_stable(struct hfc8s_hw *hw, int reg) +{ + u_char ref8; + u_char in8; + ref8=Read_hfc8(hw,reg); + while (((in8=Read_hfc8(hw,reg))!=ref8)) { + ref8=in8; + } + return in8; +} + +static volatile int Read_hfc16_stable(struct hfc8s_hw *hw, int reg) +{ + int ref16; + int in16; + + ref16=Read_hfc16(hw,reg); + while (((in16=Read_hfc16(hw,reg))!=ref16)) { + ref16=in16; + } + return in16; +} + + +/*************/ +/* data area */ +/*************/ +static struct hfc8s_hw hfc8s[MAX_HFC8_CARDS]; +static int card_cnt; + +/*****************************/ +/* D-channel call from HiSax */ +/*****************************/ +static void dch_l2l1(struct hisax_d_if *iface, int pr, void *arg) +{ + struct hfc8s_l1 *l1 = iface->ifc.priv; + struct sk_buff *skb = (struct sk_buff *) arg; + u_long flags; + + switch (pr) { + + case (PH_DATA | REQUEST): + if (!l1->enabled) { + dev_kfree_skb(skb); + break; + } + spin_lock_irqsave(&l1->lock, flags); + skb_queue_tail(&l1->d_tx_queue, skb); + if ((skb_queue_len(&l1->d_tx_queue) == 1) && + (l1->tx_cnt <= 0)) { + l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= 0x10; + spin_unlock_irqrestore(&l1->lock, flags); + schedule_work(&l1->hw->tqueue); + } else + spin_unlock_irqrestore(&l1->lock, flags); + break; + + case (PH_ACTIVATE | REQUEST): + if (!l1->enabled) + break; + if (!l1->nt_mode) { + if (l1->l1_state < 6) { + spin_lock_irqsave(&l1->lock, flags); + + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + Write_hfc8(l1->hw, A_ST_WR_STA, 0x60); + mod_timer(&l1->l1_timer, jiffies + L1_TIMER_T3); + spin_unlock_irqrestore(&l1->lock, flags); + } else + if (l1->l1_state == 7) + l1->d_if.ifc.l1l2(&l1->d_if.ifc, PH_ACTIVATE | INDICATION, NULL); + } else { + if (l1->l1_state != 3) { + spin_lock_irqsave(&l1->lock, flags); + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + Write_hfc8(l1->hw, A_ST_WR_STA, 0x60); + spin_unlock_irqrestore(&l1->lock, flags); + } else + if (l1->l1_state == 3) + l1->d_if.ifc.l1l2(&l1->d_if.ifc, PH_ACTIVATE | INDICATION, NULL); + } + break; + + default: + printk(KERN_INFO "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n", pr); + break; + } + if (!l1->enabled) + l1->d_if.ifc.l1l2(&l1->d_if.ifc, PH_DEACTIVATE | INDICATION, NULL); +} /* dch_l2l1 */ + +/*****************************/ +/* B-channel call from HiSax */ +/*****************************/ +static void bch_l2l1(struct hisax_if *ifc, int pr, void *arg) +{ + struct hfc8s_btype *bch = ifc->priv; + struct hfc8s_l1 *l1 = bch->l1p; + struct sk_buff *skb = (struct sk_buff *) arg; + int mode = (int) arg; + u_long flags; + + switch (pr) { + + case (PH_DATA | REQUEST): + if (!l1->enabled || (bch->mode == L1_MODE_NULL)) { + dev_kfree_skb(skb); + break; + } + spin_lock_irqsave(&l1->lock, flags); + skb_queue_tail(&bch->tx_queue, skb); + if (!bch->tx_skb && (bch->tx_cnt <= 0)) { + l1->hw->mr.r_irq_fifo_blx[l1->st_num] |= ((bch->bchan == 1) ? 1 : 4); + spin_unlock_irqrestore(&l1->lock, flags); + schedule_work(&l1->hw->tqueue); + } else + spin_unlock_irqrestore(&l1->lock, flags); + break; + + case (PH_ACTIVATE | REQUEST): + case (PH_DEACTIVATE | REQUEST): + if (!l1->enabled) + break; + if (pr == (PH_DEACTIVATE | REQUEST)) + mode = L1_MODE_NULL; + + switch (mode) { + case L1_MODE_HDLC: + spin_lock_irqsave(&l1->lock, flags); + l1->hw->mr.timer_usg_cnt++; + l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= ((bch->bchan == 1) ? 0x2 : 0x8); + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_CON_HDLC, 0xc); // HDLC mode, flag fill, connect ST + Write_hfc8(l1->hw, A_SUBCH_CFG, 0); // 8 bits + Write_hfc8(l1->hw, A_IRQ_MSK, 1); // enable TX interrupts for hdlc + Write_hfc8(l1->hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(l1->hw); + + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_CON_HDLC, 0xc); // HDLC mode, flag fill, connect ST + Write_hfc8(l1->hw, A_SUBCH_CFG, 0); // 8 bits + Write_hfc8(l1->hw, A_IRQ_MSK, 1); // enable RX interrupts for hdlc + Write_hfc8(l1->hw, R_INC_RES_FIFO, 2); // reset fifo + + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + l1->hw->mr.r_ctrl0 |= (bch->bchan & 3); + Write_hfc8(l1->hw, A_ST_CTRL0, l1->hw->mr.r_ctrl0); + bch->mode = L1_MODE_HDLC; + spin_unlock_irqrestore(&l1->lock, flags); + + bch->b_if.ifc.l1l2(&bch->b_if.ifc, PH_ACTIVATE | INDICATION, NULL); + break; + + case L1_MODE_TRANS: + spin_lock_irqsave(&l1->lock, flags); + l1->hw->mr.fifo_rx_trans_enables[l1->st_num] |= ((bch->bchan == 1) ? 0x2 : 0x8); + l1->hw->mr.timer_usg_cnt++; + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_CON_HDLC, 0xf); // Transparent mode, 1 fill, connect ST + Write_hfc8(l1->hw, A_SUBCH_CFG, 0); // 8 bits + Write_hfc8(l1->hw, A_IRQ_MSK, 0); // disable TX interrupts + Write_hfc8(l1->hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(l1->hw); + + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_CON_HDLC, 0xf); // Transparent mode, 1 fill, connect ST + Write_hfc8(l1->hw, A_SUBCH_CFG, 0); // 8 bits + Write_hfc8(l1->hw, A_IRQ_MSK, 0); // disable RX interrupts + Write_hfc8(l1->hw, R_INC_RES_FIFO, 2); // reset fifo + + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + l1->hw->mr.r_ctrl0 |= (bch->bchan & 3); + Write_hfc8(l1->hw, A_ST_CTRL0, l1->hw->mr.r_ctrl0); + bch->mode = L1_MODE_TRANS; + spin_unlock_irqrestore(&l1->lock, flags); + + bch->b_if.ifc.l1l2(&bch->b_if.ifc, PH_ACTIVATE | INDICATION, NULL); + break; + + default: + if (bch->mode == L1_MODE_NULL) + break; + spin_lock_irqsave(&l1->lock, flags); + l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= ~((bch->bchan == 1) ? 0x3 : 0xc); + l1->hw->mr.fifo_rx_trans_enables[l1->st_num] &= ~((bch->bchan == 1) ? 0x3 : 0xc); + l1->hw->mr.timer_usg_cnt--; + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_IRQ_MSK, 0); // disable TX interrupts + wait_busy(l1->hw); + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); + wait_busy(l1->hw); + Write_hfc8(l1->hw, A_IRQ_MSK, 0); // disable RX interrupts + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + l1->hw->mr.r_ctrl0 &= ~(bch->bchan & 3); + Write_hfc8(l1->hw, A_ST_CTRL0, l1->hw->mr.r_ctrl0); + spin_unlock_irqrestore(&l1->lock, flags); + + bch->mode = L1_MODE_NULL; + bch->b_if.ifc.l1l2(&bch->b_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + if (bch->tx_skb) { + dev_kfree_skb(bch->tx_skb); + bch->tx_skb = NULL; + } + if (bch->rx_skb) { + dev_kfree_skb(bch->rx_skb); + bch->rx_skb = NULL; + } + skb_queue_purge(&bch->tx_queue); + bch->tx_cnt = 0; + bch->rx_ptr = NULL; + break; + } + + // timer is only used when at least one b channel is set up to transparent mode + if (l1->hw->mr.timer_usg_cnt){ + Write_hfc8(l1->hw, R_IRQMSK_MISC, M_TI_IRQMSK); + } + else { + Write_hfc8(l1->hw, R_IRQMSK_MISC, 0); + } + + break; + + default: + printk(KERN_INFO "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",pr); + break; + } + if (!l1->enabled) + bch->b_if.ifc.l1l2(&bch->b_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + +} /* bch_l2l1 */ + +/**************************/ +/* layer 1 timer function */ +/**************************/ +static void hfc_l1_timer(struct hfc8s_l1 *l1) +{ + u_long flags; + + if (!l1->enabled) + return; + + spin_lock_irqsave(&l1->lock, flags); + if (l1->nt_mode) { + l1->l1_state = 1; + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + Write_hfc8(l1->hw, A_ST_WR_STA, 0x11); + spin_unlock_irqrestore(&l1->lock, flags); + l1->d_if.ifc.l1l2(&l1->d_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + spin_lock_irqsave(&l1->lock, flags); + l1->l1_state = 1; + Write_hfc8(l1->hw, A_ST_WR_STA, 0x1); + spin_unlock_irqrestore(&l1->lock, flags); + } else { + /* activation timed out */ + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + Write_hfc8(l1->hw, A_ST_WR_STA, 0x13); + spin_unlock_irqrestore(&l1->lock, flags); + l1->d_if.ifc.l1l2(&l1->d_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + spin_lock_irqsave(&l1->lock, flags); + Write_hfc8(l1->hw, R_ST_SEL, l1->st_num); + Write_hfc8(l1->hw, A_ST_WR_STA, 0x3); + spin_unlock_irqrestore(&l1->lock, flags); + } +} /* hfc_l1_timer */ + + +/****************************************/ +/* a complete D-frame has been received */ +/****************************************/ + +static void rx_d_frame(struct hfc8s_l1 *l1p, int ech) +{ + int z1, z2; + u_char f1, f2, df; + struct sk_buff *skb; + u_char *cp; + + + if (!l1p->enabled) + return; + do { + Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + ((ech) ? 7 : 5))); // E/D RX fifo + wait_busy(l1p->hw); + + f1=Read_hfc8_stable(l1p->hw, A_F1); + f2=Read_hfc8(l1p->hw, A_F2); + df=f1-f2; + if ((f1-f2)<0) df=f1-f2+MAX_F_CNT+1; + + + if (!df) { + return; // no complete frame in fifo + } + + z1 = Read_hfc16_stable(l1p->hw, A_Z1); + z2 = Read_hfc16(l1p->hw, A_Z2); + + z1 = z1 - z2 + 1; + if (z1 < 0) + z1 += 384; + + + if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) { + printk(KERN_INFO "HFC-4S/8S: Could not allocate D/E channel receive buffer"); + Write_hfc8(l1p->hw, R_INC_RES_FIFO, 2); + wait_busy(l1p->hw); + return; + } + + if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) { + if (skb) dev_kfree_skb(skb); + // remove errornous D frame + if (df==1) { // reset fifo + Write_hfc8(l1p->hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(l1p->hw); + return; + } + else { // read errornous D frame + +#ifdef FIFO_32BIT_ACCESS + while (z1 >=4) { + Read_hfc32(l1p->hw, A_FIFO_DATA0); + z1 -= 4; + } +#endif + while (z1--) + Read_hfc8(l1p->hw, A_FIFO_DATA0); + + Write_hfc8(l1p->hw, R_INC_RES_FIFO, 1); + wait_busy(l1p->hw); + return; + } + } + + cp = skb->data; +#ifdef FIFO_32BIT_ACCESS + while (z1 >=4) { + *((unsigned long *)cp) = Read_hfc32(l1p->hw, A_FIFO_DATA0); + cp += 4; + z1 -= 4; + } +#endif + while (z1--) + *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0); + + Write_hfc8(l1p->hw, R_INC_RES_FIFO, 1); // increment f counter + wait_busy(l1p->hw); + + if (*(--cp)) { + dev_kfree_skb(skb); + } else { + skb->len = (cp - skb->data) - 2; + if (ech) + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA_E | INDICATION, skb); + else + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | INDICATION, skb); + } + + } while (1); +} /* rx_d_frame */ + + +/*************************************************************/ +/* a B-frame has been received (perhaps not fully completed) */ +/*************************************************************/ +static void rx_b_frame(struct hfc8s_btype *bch) +{ + int z1, z2, hdlc_complete; + u_char f1, f2; + struct hfc8s_l1 *l1 = bch->l1p; + struct sk_buff *skb; + + if (!l1->enabled || (bch->mode == L1_MODE_NULL)) + return; + + do { + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3))); // RX fifo + wait_busy(l1->hw); + + if (bch->mode == L1_MODE_HDLC) { + f1=Read_hfc8_stable(l1->hw, A_F1); + f2=Read_hfc8(l1->hw, A_F2); + hdlc_complete = ((f1 ^ f2) & MAX_F_CNT); + } else + hdlc_complete = 0; + z1 = Read_hfc16_stable(l1->hw, A_Z1); + z2 = Read_hfc16(l1->hw, A_Z2); + z1 = (z1 - z2); + if (hdlc_complete) + z1++; + if (z1 < 0) + z1 += 384; + + if (!z1) + break; + + if (!(skb = bch->rx_skb)) { + if (!(skb = dev_alloc_skb((bch->mode == L1_MODE_TRANS) ? z1 : (MAX_B_FRAME_SIZE + 3)))) { + printk(KERN_ERR "HFC-4S/8S: Could not allocate B channel receive buffer"); + return; + } + bch->rx_ptr = skb->data; + bch->rx_skb = skb; + } + + skb->len = (bch->rx_ptr - skb->data) + z1; + + // HDLC length check + if ((bch->mode == L1_MODE_HDLC) && + ((hdlc_complete && (skb->len < 4)) || + (skb->len > (MAX_B_FRAME_SIZE + 3)))) { + + skb->len = 0; + bch->rx_ptr = skb->data; + Write_hfc8(l1->hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(l1->hw); + return; + } + +#ifdef FIFO_32BIT_ACCESS + while (z1 >=4) { + *((unsigned long *)bch->rx_ptr) = Read_hfc32(l1->hw, A_FIFO_DATA0); + bch->rx_ptr += 4; + z1 -= 4; + } +#endif + while (z1--) + *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0); + + if (hdlc_complete) { + Write_hfc8(l1->hw, R_INC_RES_FIFO, 1); // increment f counter + wait_busy(l1->hw); + + // hdlc crc check + bch->rx_ptr--; + if (*bch->rx_ptr) { + skb->len = 0; + bch->rx_ptr = skb->data; + continue; + } + skb->len -= 3; + } + if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) { + bch->rx_skb = NULL; + bch->rx_ptr = NULL; + bch->b_if.ifc.l1l2(&bch->b_if.ifc, PH_DATA | INDICATION, skb); + } + + } while (1); +} /* rx_b_frame */ + + +/********************************************/ +/* a D-frame has been/should be transmitted */ +/********************************************/ +static void tx_d_frame(struct hfc8s_l1 *l1p) +{ + struct sk_buff *skb; + u_char f1, f2; + u_char *cp; + int cnt; + + if (l1p->l1_state != 7) + return; + + Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4)); // TX fifo + wait_busy(l1p->hw); + + f1=Read_hfc8(l1p->hw, A_F1); + f2=Read_hfc8_stable(l1p->hw, A_F2); + + if ((f1 ^ f2) & MAX_F_CNT) + return; // fifo is still filled + + if (l1p->tx_cnt > 0) { + cnt = l1p->tx_cnt; + l1p->tx_cnt = 0; + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM, (void *) cnt); + } + + if ((skb = skb_dequeue(&l1p->d_tx_queue))) { + + cp = skb->data; + cnt = skb->len; +#ifdef FIFO_32BIT_ACCESS + while (cnt >=4) { + Write_hfc32(l1p->hw, A_FIFO_DATA0, *(unsigned long *)cp); + cp += 4; + cnt -= 4; + } +#endif + while (cnt--) + fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++); + l1p->tx_cnt = skb->truesize; + Write_hfc8(l1p->hw, R_INC_RES_FIFO, 1); // increment f counter + wait_busy(l1p->hw); + + dev_kfree_skb(skb); + } +} /* tx_d_frame */ + +/******************************************************/ +/* a B-frame may be transmitted (or is not completed) */ +/******************************************************/ +static void tx_b_frame(struct hfc8s_btype *bch) +{ + struct sk_buff *skb; + struct hfc8s_l1 *l1 = bch->l1p; + u_char *cp; + int cnt, max, hdlc_num, ack_len = 0; + + if (!l1->enabled || (bch->mode == L1_MODE_NULL)) + return; + + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); // TX fifo + wait_busy(l1->hw); + do { + + if (bch->mode == L1_MODE_HDLC) { + hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT; + hdlc_num -= (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT); + if (hdlc_num < 0) + hdlc_num += 16; + if (hdlc_num >= 15) + break; // fifo still filled up with hdlc frames + } else + hdlc_num = 0; + + if (!(skb = bch->tx_skb)) { + if (!(skb = skb_dequeue(&bch->tx_queue))) { + l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= ~((bch->bchan == 1) ? 1 : 4); + break; // list empty + } + bch->tx_skb = skb; + bch->tx_cnt = 0; + } + + if (!hdlc_num) + l1->hw->mr.fifo_slow_timer_service[l1->st_num] |= ((bch->bchan == 1) ? 1 : 4); + else + l1->hw->mr.fifo_slow_timer_service[l1->st_num] &= ~((bch->bchan == 1) ? 1 : 4); + + max = Read_hfc16_stable(l1->hw, A_Z2); + max -= Read_hfc16(l1->hw, A_Z1); + if (max <= 0) + max += 384; + max--; + + if (max < 16) + break; // don't write to small amounts of bytes + + cnt = skb->len - bch->tx_cnt; + if (cnt > max) + cnt = max; + cp = skb->data + bch->tx_cnt; + bch->tx_cnt += cnt; +#ifdef FIFO_32BIT_ACCESS + while (cnt >=4) { + Write_hfc32(l1->hw, A_FIFO_DATA0, *(unsigned long *)cp); + cp += 4; + cnt -= 4; + } +#endif + while (cnt--) + Write_hfc8(l1->hw, A_FIFO_DATA0, *cp++); + + if (bch->tx_cnt >= skb->len) { + if (bch->mode == L1_MODE_HDLC) { + Write_hfc8(l1->hw, R_INC_RES_FIFO, 1); // increment f counter + } + ack_len += skb->truesize; + bch->tx_skb = 0; + bch->tx_cnt = 0; + dev_kfree_skb(skb); + } else + Write_hfc8(l1->hw, R_FIFO, (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2))); // Re-Select + wait_busy(l1->hw); + + } while (1); + + if (ack_len) + bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if, PH_DATA | CONFIRM, (void *) ack_len); +} /* tx_b_frame */ + +/*************************************/ +/* bottom half handler for interrupt */ +/*************************************/ +static void hfc8s_bh(struct hfc8s_hw *hw) +{ + u_char b; + struct hfc8s_l1 *l1p; + volatile u_char *fifo_stat; + int idx; + + // handle layer 1 state changes + b = 1; + l1p = hw->l1; + while (b) { + if ((b & hw->mr.r_irq_statech)) { + hw->mr.r_irq_statech &= ~b; // reset l1 event + if (l1p->enabled) { + if (l1p->nt_mode) { + u_char oldstate = l1p->l1_state; // save old l1 state + + Write_hfc8(l1p->hw, R_ST_SEL, l1p->st_num); + l1p->l1_state = Read_hfc8(l1p->hw, A_ST_RD_STA) & 0xf; // new state + + if ((oldstate == 3) && (l1p->l1_state != 3)) + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + + if (l1p->l1_state != 2) { + del_timer(&l1p->l1_timer); + if (l1p->l1_state == 3) { + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_ACTIVATE | INDICATION, NULL); + } + } else { + Write_hfc8(hw, A_ST_WR_STA, M_SET_G2_G3); // allow transition + mod_timer(&l1p->l1_timer, jiffies + L1_TIMER_T1); + } + printk(KERN_INFO "HFC-4S/8S: NT ch %d l1 state %d -> %d\n", + l1p->st_num, oldstate, l1p->l1_state); + } else { + u_char oldstate = l1p->l1_state; // save old l1 state + + Write_hfc8(l1p->hw, R_ST_SEL, l1p->st_num); + l1p->l1_state = Read_hfc8(l1p->hw, A_ST_RD_STA) & 0xf; // new state + + if (((l1p->l1_state == 3) && + ((oldstate == 7) || + (oldstate == 8))) || + ((timer_pending(&l1p->l1_timer)) && + (l1p->l1_state == 8))) { + mod_timer(&l1p->l1_timer, L1_TIMER_T4 + jiffies); + } else { + if (l1p->l1_state == 7) { + del_timer(&l1p->l1_timer); /* no longer needed */ + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_ACTIVATE | INDICATION, NULL); + tx_d_frame(l1p); + } + if (l1p->l1_state == 3) { + if (oldstate != 3) + l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DEACTIVATE | INDICATION, NULL); + } + } + printk(KERN_INFO "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n", + l1p->hw - hfc8s, l1p->st_num, oldstate, l1p->l1_state); + } + } + } + b <<= 1; + l1p++; + } + + // now handle the fifos + idx = 0; + fifo_stat = hw->mr.r_irq_fifo_blx; + l1p = hw->l1; + while (idx < hw->max_st_ports) { + + if (hw->mr.timer_irq) { + *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx]; + if (hw->fifo_sched_cnt <= 0) { + *fifo_stat |= hw->mr.fifo_slow_timer_service[l1p->st_num]; + } + } + // ignore fifo 6 (TX E fifo) + *fifo_stat &= 0xff-0x40; + + while (*fifo_stat) { + + if (!l1p->nt_mode) { + // RX Fifo has data to read + if ((*fifo_stat & 0x20)) { + *fifo_stat &= ~0x20; + rx_d_frame(l1p, 0); + } + + // E Fifo has data to read + if ((*fifo_stat & 0x80)) { + *fifo_stat &= ~0x80; + rx_d_frame(l1p, 1); + } + + // TX Fifo completed send + if ((*fifo_stat & 0x10)) { + *fifo_stat &= ~0x10; + tx_d_frame(l1p); + } + } + + + // B1 RX Fifo has data to read + if ((*fifo_stat & 0x2)) { + *fifo_stat &= ~0x2; + rx_b_frame(l1p->b_ch); + } + + // B1 TX Fifo has send completed + if ((*fifo_stat & 0x1)) { + *fifo_stat &= ~0x1; + tx_b_frame(l1p->b_ch); + } + + // B2 RX Fifo has data to read + if ((*fifo_stat & 0x8)) { + *fifo_stat &= ~0x8; + rx_b_frame(l1p->b_ch + 1); + } + + // B2 TX Fifo has send completed + if ((*fifo_stat & 0x4)) { + *fifo_stat &= ~0x4; + tx_b_frame(l1p->b_ch + 1); + } + + + } + fifo_stat++; + l1p++; + idx++; + } + + if (hw->fifo_sched_cnt <= 0) + hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE)); + hw->mr.timer_irq = 0; // clear requested timer irq +} /* hfc8s_bh */ + +/*********************/ +/* interrupt handler */ +/*********************/ +static irqreturn_t hfc8s_interrupt(int intno, void *dev_id, struct pt_regs *regs) +{ + struct hfc8s_hw *hw = dev_id; + u_char b, ovr; + volatile u_char *ovp; + int idx; + + if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN)) + return IRQ_NONE;; + + /* Layer 1 State change */ + hw->mr.r_irq_statech |= (Read_hfc8(hw, R_IRQ_STATECH) & hw->mr.r_irqmsk_statchg); + if (!(b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA))) && + !hw->mr.r_irq_statech) + return IRQ_NONE; + + /* timer event */ + if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) { + hw->mr.timer_irq = 1; + hw->fifo_sched_cnt--; + } + + /* FIFO event */ + if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) { + hw->mr.r_irq_oview |= ovr; + idx = R_IRQ_FIFO_BL0; + ovp = hw->mr.r_irq_fifo_blx; + while (ovr) { + if ((ovr & 1)) { + *ovp |= Read_hfc8(hw, idx); + } + ovp++; + idx++; + ovr >>= 1; + } + } + + /* queue the request to allow other cards to interrupt */ + schedule_work(&hw->tqueue); + + return IRQ_HANDLED; +} /* hfc8s_interrupt */ + +/***********************************************************************/ +/* reset the complete chip, don't release the chips irq but disable it */ +/***********************************************************************/ +static void chipreset(struct hfc8s_hw *hw) +{ + u_long flags; + + spin_lock_irqsave(&hw->lock, flags); + Write_hfc8(hw, R_CTRL, 0); // use internal RAM + Write_hfc8(hw, R_RAM_SZ, 0); // 32k*8 RAM + Write_hfc8(hw, R_FIFO_MD, 0); // fifo mode 386 byte/fifo simple mode + Write_hfc8(hw, R_CIRM, M_SRES); // reset chip + hw->mr.r_irq_ctrl = 0; // interrupt is inactive + spin_unlock_irqrestore(&hw->lock, flags); + + udelay(3); + Write_hfc8(hw, R_CIRM, 0); // disable reset + wait_busy(hw); + + Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); // master mode + Write_hfc8(hw, R_RAM_SZ, V_FZ_MD); // transmit fifo option + if (hw->clock_mode == 1) + Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); // PCM clk / 2 + Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); // timer interval + + memset(&hw->mr, 0, sizeof(hw->mr)); + +} /* chipreset */ + +/********************************************/ +/* disable/enable hardware in nt or te mode */ +/********************************************/ +void hfc_hardware_enable(struct hfc8s_hw *hw, int enable, int nt_mode) +{ + u_long flags; + char if_name[40]; + int i; + + if (enable) { + + // save system vars + hw->nt_mode = nt_mode; + + // enable fifo and state irqs, but not global irq enable + hw->mr.r_irq_ctrl = M_FIFO_IRQ; + Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); + hw->mr.r_irqmsk_statchg = 0; + Write_hfc8(hw, R_IRQMSK_STATCHG, hw->mr.r_irqmsk_statchg); + Write_hfc8(hw, R_PWM_MD, 0x80); + Write_hfc8(hw, R_PWM1, 26); + if (!nt_mode) + Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC); + + // enable the line interfaces and fifos + for (i = 0; i < hw->max_st_ports; i++) { + hw->mr.r_irqmsk_statchg |= (1 << i); + Write_hfc8(hw, R_IRQMSK_STATCHG, hw->mr.r_irqmsk_statchg); + Write_hfc8(hw, R_ST_SEL, i); + Write_hfc8(hw, A_ST_CLK_DLY, ((nt_mode) ? CLKDEL_NT : CLKDEL_TE)); + hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE); + Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0); + Write_hfc8(hw, A_ST_CTRL2, 3); + Write_hfc8(hw, A_ST_WR_STA, 0); // enable state machine + + hw->l1[i].enabled = 1; + hw->l1[i].nt_mode = nt_mode; + + if (!nt_mode) { + // setup E-fifo + Write_hfc8(hw, R_FIFO, i * 8 + 7); // E fifo + wait_busy(hw); + Write_hfc8(hw, A_CON_HDLC, 0x11); // HDLC mode, 1 fill, connect ST + Write_hfc8(hw, A_SUBCH_CFG, 2); // only 2 bits + Write_hfc8(hw, A_IRQ_MSK, 1); // enable interrupt + Write_hfc8(hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(hw); + + // setup D RX-fifo + Write_hfc8(hw, R_FIFO, i * 8 + 5); // RX fifo + wait_busy(hw); + Write_hfc8(hw, A_CON_HDLC, 0x11); // HDLC mode, 1 fill, connect ST + Write_hfc8(hw, A_SUBCH_CFG, 2); // only 2 bits + Write_hfc8(hw, A_IRQ_MSK, 1); // enable interrupt + Write_hfc8(hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(hw); + + // setup D TX-fifo + Write_hfc8(hw, R_FIFO, i * 8 + 4); // TX fifo + wait_busy(hw); + Write_hfc8(hw, A_CON_HDLC, 0x11); // HDLC mode, 1 fill, connect ST + Write_hfc8(hw, A_SUBCH_CFG, 2); // only 2 bits + Write_hfc8(hw, A_IRQ_MSK, 1); // enable interrupt + Write_hfc8(hw, R_INC_RES_FIFO, 2); // reset fifo + wait_busy(hw); + } + + + sprintf(if_name, "hfc4s8s_%d%d_", hw - hfc8s, i); + if (hisax_register(&hw->l1[i].d_if, hw->l1[i].b_table, + if_name, ((nt_mode) ? 3 : 2))) { + + hw->l1[i].enabled = 0; + hw->mr.r_irqmsk_statchg &= ~(1 << i); + Write_hfc8(hw, R_IRQMSK_STATCHG, hw->mr.r_irqmsk_statchg); + printk(KERN_INFO "HFC-4S/8S: Unable to register S/T device %s, break\n", if_name); + break; + } + } + + spin_lock_irqsave(&hw->lock, flags); + hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN; + Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); + spin_unlock_irqrestore(&hw->lock, flags); + + } else { + spin_lock_irqsave(&hw->lock, flags); + hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN; + Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl); + spin_unlock_irqrestore(&hw->lock, flags); + + for (i = hw->max_st_ports - 1; i >= 0; i--) { + hw->l1[i].enabled = 0; + hisax_unregister(&hw->l1[i].d_if); + del_timer(&hw->l1[i].l1_timer); + skb_queue_purge(&hw->l1[i].d_tx_queue); + skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue); + skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue); + } + + chipreset(hw); + } +} /* hfc_hardware_enable */ + +/*************************************/ +/* initialise the HFC-4s/8s hardware */ +/* return 0 on success. */ +/*************************************/ +static int __init hfc8s_init_hw(void) +{ + struct pci_dev *tmp_hfc8s = NULL; + PCI_ENTRY *list = (PCI_ENTRY *)id_list; + struct hfc8s_hw *hw = hfc8s; + u_long flags; + int i; + + printk(KERN_INFO "Layer 1 driver module for HFC-4S/8S isdn chips, %s\n", hfc4s8s_rev); + printk(KERN_INFO "(C) 2003 Cornelius Consult, www.cornelius-consult.de\n"); + + do { + + spin_lock_init(&hw->lock); + + tmp_hfc8s = pci_find_device(list->vendor_id, list->device_id, tmp_hfc8s); + if (!tmp_hfc8s) { + list++; // next PCI-ID + if (!list->vendor_id) + break; // end of list + continue; // search PCI base again + } + + if (list->sub_vendor_id && (list->sub_vendor_id != tmp_hfc8s->subsystem_vendor)) + continue; // sub_vendor defined and not matching + + if (list->sub_device_id && (list->sub_device_id != tmp_hfc8s->subsystem_device)) + continue; // sub_device defined and not matching + + // init Layer 1 structure + if (tmp_hfc8s->irq <= 0) { + printk(KERN_INFO "HFC-4S/8S: found PCI card without assigned IRQ, card ignored\n"); + continue; + } + + if (pci_enable_device(tmp_hfc8s)) { + printk(KERN_INFO "HFC-4S/8S: Error enabling PCI card, card ignored\n"); + continue; + } + + hw->irq = tmp_hfc8s->irq; + hw->max_st_ports = list->max_channels; + hw->max_fifo = list->max_channels * 4; + hw->clock_mode = list->clock_mode; + + for (i = 0; i < HFC_MAX_ST; i++) { + struct hfc8s_l1 *l1p; + + l1p = hw->l1 + i; + + spin_lock_init(&l1p->lock); + l1p->hw = hw; + l1p->l1_timer.function = (void *) hfc_l1_timer; + l1p->l1_timer.data = (long) (l1p); + init_timer(&l1p->l1_timer); + l1p->st_num = i; + skb_queue_head_init(&l1p->d_tx_queue); + l1p->d_if.ifc.priv = hw->l1 + i; + l1p->d_if.ifc.l2l1 = (void *) dch_l2l1; + + spin_lock_init(&l1p->b_ch[0].lock); + l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1; + l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0]; + l1p->b_ch[0].l1p = hw->l1 + i; + l1p->b_ch[0].bchan = 1; + l1p->b_table[0] = &l1p->b_ch[0].b_if; + skb_queue_head_init(&l1p->b_ch[0].tx_queue); + + spin_lock_init(&l1p->b_ch[1].lock); + l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1; + l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1]; + l1p->b_ch[1].l1p = hw->l1 + i; + l1p->b_ch[1].bchan = 2; + l1p->b_table[1] = &l1p->b_ch[1].b_if; + skb_queue_head_init(&l1p->b_ch[1].tx_queue); + } + + hw->iobase = tmp_hfc8s->resource[0].start & PCI_BASE_ADDRESS_IO_MASK; + hw->hw_membase = (u_char *)tmp_hfc8s->resource[1].start; + hw->membase = ioremap((ulong) hw->hw_membase, 256); + + hw->pci_dev = tmp_hfc8s; + + /* now enable memory mapped ports */ + pci_write_config_word(hw->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); + chipreset(hw); + i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT; + + if (i != list->chip_id) { + printk(KERN_INFO "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n", i, list->chip_id); + pci_write_config_word(hw->pci_dev, PCI_COMMAND, 0); /* disable memory mapped ports */ + vfree(hw->membase); + continue; + } + + i = Read_hfc8(hw, R_CHIP_RV) & 0xf; + + if (!i) { + printk(KERN_INFO "HFC-4S/8S: chip revision 0 not supported, card ignored\n"); + pci_write_config_word(hw->pci_dev, PCI_COMMAND, 0); /* disable memory mapped ports */ + vfree(hw->membase); + continue; + } + + INIT_WORK(&hw->tqueue, (void *)(void *) hfc8s_bh, hw); + + sprintf(hw->card_name, "hfc4s8s_%d", hw - hfc8s); + spin_lock_irqsave(&hw->lock, flags); + if (request_irq(hw->irq, hfc8s_interrupt, SA_SHIRQ, hw->card_name, hw)) { + vfree(hw->membase); + spin_unlock_irqrestore(&hw->lock, flags); + printk(KERN_INFO "HFC-4S/8S: unable to alloc irq %d, card ignored\n", hw->irq); + hw->irq = 0; + continue; + } + spin_unlock_irqrestore(&hw->lock, flags); + + printk(KERN_INFO "HFC-4S/8S: found PCI card at 0x%p, irq %d\n", hw->hw_membase, hw->irq); + hfc_hardware_enable(hw, 1, 0); + card_cnt++; + hw++; + + } while ((card_cnt < MAX_HFC8_CARDS) && list->vendor_id); + + printk(KERN_INFO "HFC-4S/8S: nominal transparent fifo transfer size is %d bytes\n", TRANS_FIFO_BYTES); + printk(KERN_INFO "HFC-4S/8S: module successfully installed, %d cards found\n", card_cnt); + + return(0); +} /* hfc8s_init_hw */ + +/*************************************/ +/* release the HFC-4s/8s hardware */ +/*************************************/ +static void hfc8s_release_hw(void) +{ + struct hfc8s_hw *hw = hfc8s + card_cnt - 1; + + while (card_cnt) { + hfc_hardware_enable(hw, 0, 0); + if (hw->irq) + free_irq(hw->irq, hw); + hw->irq = 0; + pci_write_config_word(hw->pci_dev, PCI_COMMAND, 0); /* disable memory mapped ports */ + vfree(hw->membase); + hw--; + card_cnt--; + } + + printk(KERN_INFO "HFC-4S/8S: module removed successfully\n"); +} /* hfc8s_release_hw */ + + +MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de"); +MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips"); +MODULE_LICENSE("GPL"); +module_init(hfc8s_init_hw); +module_exit(hfc8s_release_hw); + +/************************************************************************************************************ +* + +$Log: hfc4s8s_l1.c,v $ +Revision 1.8 2004/07/13 14:13:34 martinb1 +unified chip name + +Revision 1.7 2004/07/13 09:19:52 martinb1 +driver ported to 2.6 kernels (info@colognechip.com) + +Revision 1.6 2004/05/03 09:19:42 joergc1 +stable counter read function added +D receive frame handling changed for unexpected frames +changes to source formatting + +Revision 1.5 2004/04/20 14:43:09 martinb1 +memory based 8 bit PCI register access Write_hfc8 changed to avoid PCI byte merging problems +masking of fifo interupt bits changed + +Revision 1.4 2004/03/11 16:12:25 martinb1 +initial version of hfc4s8s_l1.c + +*/ diff -puN drivers/isdn/hisax/Kconfig~i4l-hfc-4s-and-hfc-8s-driver drivers/isdn/hisax/Kconfig --- 25/drivers/isdn/hisax/Kconfig~i4l-hfc-4s-and-hfc-8s-driver 2005-01-22 18:38:31.712132408 -0800 +++ 25-akpm/drivers/isdn/hisax/Kconfig 2005-01-22 18:38:31.746127240 -0800 @@ -411,6 +411,12 @@ config HISAX_HFCUSB help This enables the driver for HFC USB based ISDN modems. +config HISAX_HFC4S8S + tristate "HFC-4S/8S based ISDN cards (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This enables the driver for HFC-4S/8S based ISDN cards. + config HISAX_FRITZ_PCIPNP tristate "AVM Fritz!Card PCI/PCIv2/PnP support (EXPERIMENTAL)" depends on PCI && EXPERIMENTAL diff -puN drivers/isdn/hisax/Makefile~i4l-hfc-4s-and-hfc-8s-driver drivers/isdn/hisax/Makefile --- 25/drivers/isdn/hisax/Makefile~i4l-hfc-4s-and-hfc-8s-driver 2005-01-22 18:38:31.714132104 -0800 +++ 25-akpm/drivers/isdn/hisax/Makefile 2005-01-22 18:38:31.747127088 -0800 @@ -13,6 +13,7 @@ obj-$(CONFIG_HISAX_AVM_A1_CS) += avma1_ obj-$(CONFIG_HISAX_TELES_CS) += teles_cs.o obj-$(CONFIG_HISAX_ST5481) += hisax_st5481.o obj-$(CONFIG_HISAX_HFCUSB) += hfc_usb.o +obj-$(CONFIG_HISAX_HFC4S8S) += hfc4s8s_l1.o obj-$(CONFIG_HISAX_FRITZ_PCIPNP) += hisax_isac.o hisax_fcpcipnp.o ifdef CONFIG_HISAX_HDLC _