From: David Howells The attached patch stops the FRV kernel-instruction-TLB-miss handler from setting the write-protect bit on a mapping entry when punting an entry from the mapping fast cache registers (DAMR1/IAMR1) to the TLB. This patch derives the WP value from the DAMPR1 register (which actually has a WP bit) rather than the IAMPR1 register (which does not). Signed-Off-By: David Howells Signed-off-by: Andrew Morton --- 25-akpm/arch/frv/mm/tlb-miss.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff -puN arch/frv/mm/tlb-miss.S~frv-accidental-tlb-entry-write-protect-fix arch/frv/mm/tlb-miss.S --- 25/arch/frv/mm/tlb-miss.S~frv-accidental-tlb-entry-write-protect-fix Thu Dec 16 14:43:23 2004 +++ 25-akpm/arch/frv/mm/tlb-miss.S Thu Dec 16 14:43:23 2004 @@ -184,8 +184,8 @@ __itlb_k_PTD_mapped: movgs gr31,tplr /* set TPLR.CXN */ tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */ - movsg iampr1,gr31 - ori gr31,#xAMPRx_V|DAMPRx_WP,gr31 /* entry was invalidated by tlbpr #4 */ + movsg dampr1,gr31 + ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */ movgs gr31,tppr movsg iamlr1,gr31 /* set TPLR.CXN */ movgs gr31,tplr _