From: Matt Porter Always disable L2 cache on PPC440GX. All revs/speeds of silicon have parity error problems despite errata claims to the contrary. Signed-off-by: Matt Porter Signed-off-by: Andrew Morton --- 25-akpm/arch/ppc/platforms/4xx/ocotea.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff -puN arch/ppc/platforms/4xx/ocotea.c~ppc32-disable-broken-l2-cache-on-all-440gx-revs arch/ppc/platforms/4xx/ocotea.c --- 25/arch/ppc/platforms/4xx/ocotea.c~ppc32-disable-broken-l2-cache-on-all-440gx-revs 2004-10-26 19:56:17.132677776 -0700 +++ 25-akpm/arch/ppc/platforms/4xx/ocotea.c 2004-10-26 19:56:17.135677320 -0700 @@ -350,8 +350,12 @@ void __init platform_init(unsigned long ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); ocp_sys_info.opb_bus_freq = clocks.opb; - /* Disable L2-Cache on broken hardware, enable it otherwise */ - ibm440gx_l2c_setup(&clocks); + /* + * Always disable L2 cache. All revs/speeds of silicon + * have parity error problems despite errata claims to + * the contrary. + */ + ibm440gx_l2c_disable(); ibm44x_platform_init(); _