From: Pat Gefre <pfg@sgi.com>
Mostly printk clean up and remove some dead code
---
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c | 17 +++----
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c | 6 --
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c | 57 ++++++++----------------
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c | 12 ++---
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c | 10 +---
25-akpm/arch/ia64/sn/io/sn2/pic.c | 9 ++-
25-akpm/include/asm-ia64/sn/xtalk/xtalk.h | 4 -
7 files changed, 46 insertions(+), 69 deletions(-)
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c~sn73 arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c Thu Jan 8 15:25:36 2004
@@ -2085,8 +2085,8 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
#ifdef PCI_LATER
PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pconn_vhdl,
- "pcibr_addr_pci_to_xio: Device(%d): %x\n",
- win, devreg, device_bits));
+ "pcibr_addr_pci_to_xio: Device(%d): 0x%x\n",
+ win, devreg));
#endif
}
pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
@@ -2161,9 +2161,9 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn
} else if (IS_PIC_BUSNUM_SOFT(pcibr_soft, 1)) { /* PIC bus 1 */
base = PICBRIDGE1_PCI_MEM32_BASE;
limit = PICBRIDGE1_PCI_MEM32_LIMIT;
- } else { /* Bridge/Xbridge */
- base = BRIDGE_PCI_MEM32_BASE;
- limit = BRIDGE_PCI_MEM32_LIMIT;
+ } else {
+ printk("pcibr_addr_pci_to_xio(): unknown bridge type");
+ return (iopaddr_t)0;
}
if ((pci_addr + base + req_size - 1) <= limit)
@@ -2177,9 +2177,9 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn
} else if (IS_PIC_BUSNUM_SOFT(pcibr_soft, 1)) { /* PIC bus 1 */
base = PICBRIDGE1_PCI_MEM64_BASE;
limit = PICBRIDGE1_PCI_MEM64_LIMIT;
- } else { /* Bridge/Xbridge */
- base = BRIDGE_PCI_MEM64_BASE;
- limit = BRIDGE_PCI_MEM64_LIMIT;
+ } else {
+ printk("pcibr_addr_pci_to_xio(): unknown bridge type");
+ return (iopaddr_t)0;
}
if ((pci_addr + base + req_size - 1) <= limit)
@@ -2554,6 +2554,7 @@ pcibr_piospace_free(vertex_hdl_t pconn_v
size_t req_size)
{
pcibr_info_t pcibr_info = pcibr_info_get(pconn_vhdl);
+ pcibr_soft_t pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
pciio_piospace_t piosp;
unsigned long s;
char name[1024];
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_error.c~sn73 arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c Thu Jan 8 15:25:36 2004
@@ -254,12 +254,6 @@ print_register(unsigned long long reg, s
printk(">\n");
}
-#define BEM_ADD_STR(s) printk("%s", (s))
-#define BEM_ADD_VAR(v) printk("\t%20s: 0x%llx\n", #v, ((unsigned long long)v))
-#define BEM_ADD_REG(r) printk("\t%20s: ", #r); print_register((r), r ## _desc)
-#define BEM_ADD_NSPC(n,s) printk("\t%20s: ", n); print_register(s, space_desc)
-#define BEM_ADD_SPC(s) BEM_ADD_NSPC(#s, s)
-
/*
* display memory directory state
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c~sn73 arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c Thu Jan 8 15:25:36 2004
@@ -351,19 +351,6 @@ pcibr_intr_alloc(vertex_hdl_t pconn_vhdl
*/
xtalk_intr_free(xtalk_intr);
xtalk_intr = *xtalk_intr_p;
-#if PARANOID
- /* once xtalk_intr is set, we never clear it,
- * so if the CAS fails above, this condition
- * can "never happen" ...
- */
- if (!xtalk_intr) {
- printk(KERN_ALERT
- "pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
- xconn_vhdl);
- /* yes, we leak resources here. */
- return 0;
- }
-#endif
}
}
@@ -648,9 +635,6 @@ pcibr_intr_disconnect(pcibr_intr_t pcibr
if (!pcibr_int_bits)
return;
- /* PIC WAR. PV# 854697
- * On PIC we must write 64-bit MMRs with 64-bit stores
- */
s = pcibr_lock(pcibr_soft);
if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
int_enable = bridge->p_int_enable_64;
@@ -904,26 +888,27 @@ pcibr_intr_func(intr_arg_t arg)
for (list = wrap->iw_list; list != NULL; list = list->il_next) {
if ((intr = list->il_intr) && (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
- /*
- * This device may have initiated write
- * requests since the bridge last saw
- * an edge on this interrupt input; flushing
- * the buffer prior to invoking the handler
- * should help but may not be sufficient if we
- * get more requests after the flush, followed
- * by the card deciding it wants service, before
- * the interrupt handler checks to see if things need
- * to be done.
- *
- * There is a similar race condition if
- * an interrupt handler loops around and
- * notices further service is required.
- * Perhaps we need to have an explicit
- * call that interrupt handlers need to
- * do between noticing that DMA to memory
- * has completed, but before observing the
- * contents of memory?
- */
+
+ /*
+ * This device may have initiated write
+ * requests since the bridge last saw
+ * an edge on this interrupt input; flushing
+ * the buffer prior to invoking the handler
+ * should help but may not be sufficient if we
+ * get more requests after the flush, followed
+ * by the card deciding it wants service, before
+ * the interrupt handler checks to see if things need
+ * to be done.
+ *
+ * There is a similar race condition if
+ * an interrupt handler loops around and
+ * notices further service is requred.
+ * Perhaps we need to have an explicit
+ * call that interrupt handlers need to
+ * do between noticing that DMA to memory
+ * has completed, but before observing the
+ * contents of memory?
+ */
if ((do_nonthreaded) && (!is_threaded)) {
/* Non-threaded - Call the interrupt handler at interrupt level */
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c~sn73 arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c Thu Jan 8 15:25:36 2004
@@ -72,7 +72,7 @@ do_pcibr_rrb_count_valid(bridge_t *bridg
pciio_slot_t slot,
int vchan)
{
- bridgereg_t tmp;
+ uint64_t tmp;
uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
int rrb_index, cnt=0;
@@ -105,7 +105,7 @@ int
do_pcibr_rrb_count_avail(bridge_t *bridge,
pciio_slot_t slot)
{
- bridgereg_t tmp;
+ uint64_t tmp;
uint16_t enable_bit;
int rrb_index, cnt=0;
@@ -141,7 +141,7 @@ do_pcibr_rrb_alloc(bridge_t *bridge,
int vchan,
int more)
{
- bridgereg_t reg, tmp = (bridgereg_t)0;
+ uint64_t reg, tmp = 0;
uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
int rrb_index;
@@ -186,7 +186,7 @@ do_pcibr_rrb_free(bridge_t *bridge,
int vchan,
int less)
{
- bridgereg_t reg, tmp = (bridgereg_t)0, clr = 0;
+ uint64_t reg, tmp = 0, clr = 0;
uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
int rrb_index;
@@ -258,7 +258,7 @@ do_pcibr_rrb_free_all(pcibr_soft_t pcibr
void
do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
{
- bridgereg_t status;
+ uint64_t status;
/* bridge_lock must be held;
* this RRB must be disabled.
@@ -350,7 +350,7 @@ pcibr_rrb_flush(vertex_hdl_t pconn_vhdl)
pciio_slot_t slot = PCIBR_INFO_SLOT_GET_INT(pciio_info);
bridge_t *bridge = pcibr_soft->bs_base;
- bridgereg_t tmp;
+ uint64_t tmp;
uint16_t enable_bit, pdev_bits, rrb_bits, rrb_mask;
int rrb_index;
unsigned long s;
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c~sn73 arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Thu Jan 8 15:25:36 2004
@@ -280,13 +280,9 @@ pcibr_slot_info_init(vertex_hdl_t pcibr
*/
if (!(pcix_cap = pcibr_find_capability(cfgw, PCI_CAP_PCIX))) {
printk(KERN_WARNING
-#if defined(SUPPORT_PRINTING_V_FORMAT)
- "%v: Bus running in PCI-X mode, But card in slot %d, "
- "func %d not PCI-X capable\n", pcibr_vhdl, slot, func);
-#else
- "0x%lx: Bus running in PCI-X mode, But card in slot %d, "
- "func %d not PCI-X capable\n", (unsigned long)pcibr_vhdl, slot, func);
-#endif
+ "%s: Bus running in PCI-X mode, But card in slot %d, "
+ "func %d not PCI-X capable\n",
+ pcibr_soft->bs_name, slot, func);
pcibr_device_info_new(pcibr_soft, slot, PCIIO_FUNC_NONE,
PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
continue;
diff -puN arch/ia64/sn/io/sn2/pic.c~sn73 arch/ia64/sn/io/sn2/pic.c
--- 25/arch/ia64/sn/io/sn2/pic.c~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pic.c Thu Jan 8 15:25:36 2004
@@ -170,13 +170,14 @@ pic_attach(vertex_hdl_t conn_v)
bridge1 = (bridge_t *)((char *)bridge0 + PIC_BUS1_OFFSET);
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, conn_v,
- "pic_attach: bridge0=0x%x, bridge1=0x%x\n",
+ "pic_attach: bridge0=0x%lx, bridge1=0x%lx\n",
bridge0, bridge1));
conn_v0 = conn_v1 = conn_v;
/* If dual-ported then split the two PIC buses across both Cbricks */
- if ((peer_conn_v = (pic_bus1_redist(NASID_GET(bridge0), conn_v))))
+ peer_conn_v = pic_bus1_redist(NASID_GET(bridge0), conn_v);
+ if (peer_conn_v)
conn_v1 = peer_conn_v;
/*
@@ -204,7 +205,7 @@ pic_attach(vertex_hdl_t conn_v)
}
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, conn_v,
- "pic_attach: pcibr_vhdl0=%v, pcibr_vhdl1=%v\n",
+ "pic_attach: pcibr_vhdl0=0x%lx, pcibr_vhdl1=0x%lx\n",
pcibr_vhdl0, pcibr_vhdl1));
/* register pci provider array */
@@ -222,7 +223,7 @@ pic_attach(vertex_hdl_t conn_v)
bus1_soft->bs_peers_soft = bus0_soft;
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, conn_v,
- "pic_attach: bus0_soft=0x%x, bus1_soft=0x%x\n",
+ "pic_attach: bus0_soft=0x%lx, bus1_soft=0x%lx\n",
bus0_soft, bus1_soft));
return 0;
diff -puN include/asm-ia64/sn/xtalk/xtalk.h~sn73 include/asm-ia64/sn/xtalk/xtalk.h
--- 25/include/asm-ia64/sn/xtalk/xtalk.h~sn73 Thu Jan 8 15:25:36 2004
+++ 25-akpm/include/asm-ia64/sn/xtalk/xtalk.h Thu Jan 8 15:25:36 2004
@@ -234,6 +234,8 @@ xtalk_widgetdev_enable_f (vertex_hdl_t,
typedef void
xtalk_widgetdev_shutdown_f (vertex_hdl_t, int);
+/* Error Management */
+
/* Early Action Support */
typedef caddr_t
xtalk_early_piotrans_addr_f (xwidget_part_num_t part_num,
@@ -276,8 +278,6 @@ typedef struct xtalk_provider_s {
/* CONFIGURATION MANAGEMENT */
xtalk_provider_startup_f *provider_startup;
xtalk_provider_shutdown_f *provider_shutdown;
-
- /* Error Management */
} xtalk_provider_t;
/* Crosstalk devices use these standard Crosstalk provider interfaces */
_