# This is a BitKeeper generated patch for the following project: # Project Name: Linux kernel tree # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: # ChangeSet v2.5.60 -> 1.1012 # drivers/net/3c59x.c 1.28 -> 1.29 # kernel/ksyms.c 1.181 -> 1.183 # fs/sysv/inode.c 1.25 -> 1.26 # drivers/net/tulip/de4x5.c 1.21 -> 1.22 # include/linux/jiffies.h 1.5 -> 1.6 # include/linux/buffer_head.h 1.37 -> 1.38 # drivers/net/3c509.c 1.30 -> 1.31 # drivers/char/agp/sis-agp.c 1.13 -> 1.14 # drivers/ide/pci/amd74xx.h 1.5 -> 1.6 # fs/ext2/inode.c 1.61 -> 1.62 # include/linux/ext3_jbd.h 1.8 -> 1.9 # drivers/char/agp/i7x05-agp.c 1.7 -> 1.8 # include/linux/sched.h 1.128 -> 1.129 # kernel/sys.c 1.40 -> 1.41 # drivers/net/Space.c 1.16 -> 1.17 # include/linux/hfs_sysdep.h 1.8 -> 1.9 # drivers/char/agp/frontend.c 1.26 -> 1.28 # drivers/char/agp/generic-3.0.c 1.5 -> 1.7 # fs/jfs/jfs_imap.c 1.19 -> 1.20 # fs/jbd/journal.c 1.25 -> 1.27 # net/bluetooth/af_bluetooth.c 1.11 -> 1.12 # fs/ufs/inode.c 1.18 -> 1.19 # kernel/time.c 1.9 -> 1.10 # lib/radix-tree.c 1.12 -> 1.13 # fs/jfs/jfs_mount.c 1.13 -> 1.14 # fs/sysv/itree.c 1.18 -> 1.19 # kernel/kmod.c 1.20 -> 1.21 # fs/jbd/transaction.c 1.25 -> 1.28 # drivers/char/agp/Makefile 1.15 -> 1.17 # arch/i386/kernel/io_apic.c 1.41 -> 1.42 # fs/reiserfs/resize.c 1.10 -> 1.11 # drivers/char/agp/generic.c 1.15 -> 1.18 # kernel/user.c 1.5 -> 1.6 # fs/ncpfs/sock.c 1.13 -> 1.14 # drivers/char/agp/sworks-agp.c 1.21 -> 1.22 # fs/ext2/balloc.c 1.26 -> 1.27 # arch/i386/mach-voyager/voyager_smp.c 1.5 -> 1.6 # drivers/char/agp/agp.h 1.38 -> 1.41 # arch/i386/kernel/smpboot.c 1.47 -> 1.48 # drivers/char/agp/intel-agp.c 1.21 -> 1.22 # include/linux/hugetlb.h 1.10 -> 1.11 # fs/ufs/truncate.c 1.15 -> 1.16 # fs/ext2/ialloc.c 1.28 -> 1.29 # arch/ia64/mm/hugetlbpage.c 1.7 -> 1.8 # fs/minix/inode.c 1.32 -> 1.33 # arch/x86_64/mm/hugetlbpage.c 1.5 -> 1.6 # drivers/char/rio/rioroute.c 1.3 -> 1.4 # drivers/char/agp/Kconfig 1.8 -> 1.10 # fs/buffer.c 1.182 -> 1.184 # drivers/char/agp/i460-agp.c 1.13 -> 1.14 # MAINTAINERS 1.117 -> 1.118 # fs/reiserfs/journal.c 1.60 -> 1.61 # mm/mmap.c 1.69 -> 1.70 # fs/ext2/xattr.c 1.4 -> 1.5 # fs/ufs/balloc.c 1.15 -> 1.16 # drivers/char/agp/ali-agp.c 1.13 -> 1.14 # fs/ext2/super.c 1.44 -> 1.45 # fs/jfs/resize.c 1.7 -> 1.8 # fs/ext3/inode.c 1.59 -> 1.60 # arch/sparc64/mm/hugetlbpage.c 1.5 -> 1.6 # drivers/char/agp/amd-k8-agp.c 1.21 -> 1.22 # fs/ntfs/super.c 1.122 -> 1.123 # drivers/char/agp/backend.c 1.66 -> 1.71 # drivers/block/DAC960.c 1.51 -> 1.52 # fs/jfs/namei.c 1.24 -> 1.25 # drivers/char/agp/via-kt400.c 1.6 -> (deleted) # include/linux/agp_backend.h 1.23 -> 1.25 # fs/jbd/recovery.c 1.9 -> 1.10 # drivers/char/agp/hp-agp.c 1.13 -> 1.14 # include/linux/jbd.h 1.15 -> 1.16 # fs/ufs/dir.c 1.12 -> 1.13 # drivers/char/agp/via-agp.c 1.20 -> 1.27 # fs/qnx4/inode.c 1.28 -> 1.29 # kernel/exit.c 1.88 -> 1.89 # fs/jbd/commit.c 1.14 -> 1.15 # fs/ufs/ialloc.c 1.10 -> 1.11 # drivers/char/specialix.c 1.8 -> 1.9 # fs/ext3/super.c 1.49 -> 1.51 # arch/i386/mm/hugetlbpage.c 1.29 -> 1.30 # drivers/ide/pci/amd74xx.c 1.11 -> 1.12 # arch/i386/kernel/apic.c 1.30 -> 1.31 # drivers/char/agp/amd-k7-agp.c 1.17 -> 1.18 # net/core/rtnetlink.c 1.8 -> 1.9 # fs/udf/inode.c 1.30 -> 1.31 # (new) -> 1.2 drivers/char/agp/alpha-agp.c # # The following is the BitKeeper ChangeSet Log # -------------------------------------------- # 03/02/10 torvalds@home.transmeta.com 1.992 # Linux v2.5.60 # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.1 # [AGPGART] Fix up lots of 'comparison between signed and unsigned' warnings # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.2 # [AGPGART] Fix same logic bug in KT400 mode determination. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.3 # [AGPGART] Don't oops when deregistering failed to init agp modules. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.4 # [AGPGART] Handle the "KT400 in disguise as a KT266" case. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.5 # [AGPGART] Handle failure during initialisation more gracefully. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.6 # [AGPGART] Add ident for VIA KT400 in disguise as a KT266 # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.7 # [AGPGART] More failure path sanity checking. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.8 # [AGPGART] VIA KT400 Aperture size is 12 bit in AGP3 mode. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.9 # [AGPGART] kt400's enable routine can't be __init # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.10 # [AGPGART] alpha agp infrastructure # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.11 # [AGPGART] First step towards multiple AGP buses. # # The AGP3 spec allows for >1 AGP bus. This is the first of several patches # from Jeff Hartmann towards a context-using agp_bridge, by replacing # agp_bridge.foo accesses with agp_bridge->foo accesses. For now, there # should be no functional differences, as there is still only a single # agp_bridge_data struct defined. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.12 # [AGPGART] Add extra VIA GART IDs. # # Based upon information from VIA, this also adds a bunch of placeholder # entries that will get filled in over time when they have been proven # to work with the code with no extra modification. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.13 # [AGPGART] Additional VIA ids. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.14 # [AGPGART] Fix missed agp_bridge conversion that caused oops. # -------------------------------------------- # 03/02/10 davej@codemonkey.org.uk 1.989.1.15 # [AGPGART] Merge VIA KT400 AGP3 support into main via-agp module. # # This removes lots of annoying problems trying to prevent both modules # from being loaded, and also shares quite a bit of code. # CONFIG_AGP3 will disable AGP3 mode operation of KT400s. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.16 # [AGPGART] Remove pointless enums from VIA GART driver. # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.989.1.17 # [AGPGART] Enable support for VIA PLE133 chipset # -------------------------------------------- # 03/02/10 davej@tetrachloride.(none) 1.993 # Merge tetrachloride.(none):/mnt/stuff/kernel/2.5/bk-linus # into tetrachloride.(none):/mnt/stuff/kernel/2.5/agpgart-respin # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.994 # [PATCH] Fix synchronous writers to wait properly for the result # # Mikulas Patocka points out a bug in # ll_rw_block() usage. # # Typical usage is: # # mark_buffer_dirty(bh); # ll_rw_block(WRITE, 1, &bh); # wait_on_buffer(bh); # # the problem is that if the buffer was locked on entry to this code sequence # (due to in-progress I/O), ll_rw_block() will not wait, and start new I/O. So # this code will wait on the _old_ I/O, and will then continue execution, # leaving the buffer dirty. # # It turns out that all callers were only writing one buffer, and they were all # waiting on that writeout. So I added a new sync_dirty_buffer() function: # # void sync_dirty_buffer(struct buffer_head *bh) # { # lock_buffer(bh); # if (test_clear_buffer_dirty(bh)) { # get_bh(bh); # bh->b_end_io = end_buffer_io_sync; # submit_bh(WRITE, bh); # } else { # unlock_buffer(bh); # } # } # # which allowed a fair amount of code to be removed, while adding the desired # data-integrity guarantees. # # UFS has its own wrappers around ll_rw_block() which got in the way, so this # operation was open-coded in that case. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.995 # [PATCH] ncpfs compile fix # # Patch from Joel Becker # # The task_struct->sig -> task_struct->signal bits. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.996 # [PATCH] de4x5 compile fix # # Move the definition of version[] down to where __initdata has been defined. # -------------------------------------------- # 03/02/10 rddunlap@osdl.org 1.997 # [PATCH] checker bounds/limits fixes # # Part of the bounds checking bugs found by the Stanford checker. # # The 4 fixes below have been acked by their maintainers. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.998 # [PATCH] uninline get_jiffies_64() for 32-bit architectures # # uninline get_jiffies_64() for 32-bit architectures # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.999 # [PATCH] use per-cpu data for ia32 profiler # # Patch from Ravikiran G Thirumalai # # Converts the ia32 kernel profiler to use use the percpu area infrastructure. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1000 # [PATCH] NUMAQ io_apic programming fix # # Patch from William Lee Irwin III # # Don't touch IO-APIC physid's on NUMA-Q. The BIOS pre-programs them. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1001 # [PATCH] ext3: Remove journal_try_start() # # journal_try_start() is a function which nonblockingly attempts to open a JBD # transaction handle. It was added a long time ago when there were concerns # that ext3_writepage() could block kswapd for too long. # # It was never clearly necessary. # # So the patch throws it all away and just calls the blocking journal_start() # from ext3_writepage(). # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1002 # [PATCH] DAC960 Stanford Checker fix # # Patch from Dave Olien # # This was found by the Standford Checker. # The LogicalDeviceNumber bad range test was changed from > to >= # I also replaced a couple of panic() calls with error messages, # since panic-ing seemed a little extreme. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1003 # [PATCH] Add David Olien MAINTAINERs for DAC960 # # (I asked Dave for this...) # # From: Dave Olien # # Add me as maintainer for DAC960 driver. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1004 # [PATCH] nforce2 IDE support for the amd74xx driver # # Patch from James Curbo # # The amd74xx IDE driver in 2.5.59 has support for the nforce IDE controller, # but not explicitly for the nforce2 IDE controller (which has a different PCI # ID, which is in the kernel already). I'm not sure if the nforce and nforce2 # controllers are identical, but I made a small patch that made the amd74xx # driver recognize the nforce2 IDE, and it boots for me, seems to work fine, as # my drives were tuned to their highest transfer rate automatically (udma5). # # I don't know if this patch is proper or correct, but it Works for Me [tm]. # Patch is attached. # # Vojtech has acked this change. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1005 # [PATCH] hugetlbpage MAP_FIXED fix # # We need to validate that the address and length of a MAP_FIXED request are # suitable for hugetlb pages. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1006 # [PATCH] remove unneeded test from radix_tree_extend() # # Patch from: Szabolcs Berecz # # No need to check root->rnode in the loop. In the loop it remains nonzero. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1007 # [PATCH] ext3 commenting cleanup # # Redo the (strange) layout of some of Roger's comments. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1008 # [PATCH] Don't run unlock_super() in ext3_fill_super() # # A very long time ago ext3_fill_super() was beng called under the VFS's # lock_super(), and it had to drop that lock for deadlock avoidance reasons. # # But the VFS was later changed to not take lock_super() across ->fill_super(), # so we're upping a non-downed semaphore. # # Just take it out. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1009 # [PATCH] remove the buffer_head mempool # # mempools have the wrong semantics for use by buffer_heads. The problem # scenario: # # - Process A calls mempool_alloc(), asking for a buffer_head. # # - While process A sleeps, process B frees up a ton of memory. # # That's it. There is no longer any memory pressure, so nobody frees any # buffer_heads, so process A does not get woken up. I managed to trigger this # in some testing recently. # # One approach would be to use a schedule_timeout(2) in mempool_alloc(). # # Anyway, the importance of buffer_head allocation was lessened when swapout # stopped using them, so let's just drop the mempool out of it for now. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1010 # [PATCH] fix current->user->processes leak # # Patch from: Eric Lammerts # # Every time you do a loop mount, a kernel thread is started (those # processes are called "loop0", "loop1", etc.). The problem is that when # it starts, it's counted as one of your processes. Then, it's # changed to be a root-owned process without correcting that count. # # Patch below fixes the problem. It moves the bookkeeping of changing # current->user to a new function switch_uid() (which is now also used # by exec_usermodehelper() in kmod.c). The patch is tested. # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1011 # [PATCH] 3c509 compile fix # # Patch from Marc Zyngier # # Fix compilation of 3c509.c # -------------------------------------------- # 03/02/10 akpm@digeo.com 1.1012 # [PATCH] Get 3c59x to compile on non-PCI systems # # Patch from Marc Zyngier # # My previous round of EISA hacking left the 3c59x driver unable to # compile on non-PCI systems (that is, EISA only...). # # This small patch fixes it. # -------------------------------------------- # diff -Nru a/MAINTAINERS b/MAINTAINERS --- a/MAINTAINERS Tue Feb 11 00:01:27 2003 +++ b/MAINTAINERS Tue Feb 11 00:01:27 2003 @@ -460,6 +460,13 @@ W: http://www.cyclades.com/ S: Supported +DAC960 RAID CONTROLLER DRIVER +P: Dave Olien +M dmo@osdl.org +W: http://www.osdl.org/archive/dmo/DAC960 +L: linux-kernel@vger.kernel.org +S: Maintained + DAMA SLAVE for AX.25 P: Joerg Reuter M: jreuter@yaina.de diff -Nru a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c --- a/arch/i386/kernel/apic.c Tue Feb 11 00:01:27 2003 +++ b/arch/i386/kernel/apic.c Tue Feb 11 00:01:27 2003 @@ -52,7 +52,7 @@ int prof_multiplier[NR_CPUS] = { 1, }; int prof_old_multiplier[NR_CPUS] = { 1, }; -int prof_counter[NR_CPUS] = { 1, }; +DEFINE_PER_CPU(int, prof_counter) = 1; int get_maxlvt(void) { @@ -997,7 +997,7 @@ x86_do_profile(regs); - if (--prof_counter[cpu] <= 0) { + if (--per_cpu(prof_counter, cpu) <= 0) { /* * The multiplier may have changed since the last time we got * to this point as a result of the user writing to @@ -1006,10 +1006,12 @@ * * Interrupts are already masked off at this point. */ - prof_counter[cpu] = prof_multiplier[cpu]; - if (prof_counter[cpu] != prof_old_multiplier[cpu]) { - __setup_APIC_LVTT(calibration_result/prof_counter[cpu]); - prof_old_multiplier[cpu] = prof_counter[cpu]; + per_cpu(prof_counter, cpu) = prof_multiplier[cpu]; + if (per_cpu(prof_counter, cpu) != prof_old_multiplier[cpu]) { + __setup_APIC_LVTT( + calibration_result/ + per_cpu(prof_counter, cpu)); + prof_old_multiplier[cpu] = per_cpu(prof_counter, cpu); } #ifdef CONFIG_SMP diff -Nru a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c --- a/arch/i386/kernel/io_apic.c Tue Feb 11 00:01:27 2003 +++ b/arch/i386/kernel/io_apic.c Tue Feb 11 00:01:27 2003 @@ -1440,7 +1440,8 @@ * by Matt Domsch Tue Dec 21 12:25:05 CST 1999 */ -static void __init setup_ioapic_ids_from_mpc (void) +#ifndef CONFIG_X86_NUMAQ +static void __init setup_ioapic_ids_from_mpc(void) { struct IO_APIC_reg_00 reg_00; unsigned long phys_id_present_map; @@ -1533,6 +1534,9 @@ printk(" ok.\n"); } } +#else +static void __init setup_ioapic_ids_from_mpc(void) { } +#endif /* * There is a nasty bug in some older SMP boards, their mptable lies diff -Nru a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c --- a/arch/i386/kernel/smpboot.c Tue Feb 11 00:01:27 2003 +++ b/arch/i386/kernel/smpboot.c Tue Feb 11 00:01:27 2003 @@ -935,10 +935,6 @@ * Cycle through the processors sending APIC IPIs to boot each. */ -extern int prof_multiplier[NR_CPUS]; -extern int prof_old_multiplier[NR_CPUS]; -extern int prof_counter[NR_CPUS]; - static int boot_cpu_logical_apicid; /* Where the IO area was mapped on multiquad, always 0 otherwise */ void *xquad_portio; @@ -948,17 +944,6 @@ static void __init smp_boot_cpus(unsigned int max_cpus) { int apicid, cpu, bit; - - /* - * Initialize the logical to physical CPU number mapping - * and the per-CPU profiling counter/multiplier - */ - - for (cpu = 0; cpu < NR_CPUS; cpu++) { - prof_counter[cpu] = 1; - prof_old_multiplier[cpu] = 1; - prof_multiplier[cpu] = 1; - } /* * Setup boot CPU information diff -Nru a/arch/i386/mach-voyager/voyager_smp.c b/arch/i386/mach-voyager/voyager_smp.c --- a/arch/i386/mach-voyager/voyager_smp.c Tue Feb 11 00:01:27 2003 +++ b/arch/i386/mach-voyager/voyager_smp.c Tue Feb 11 00:01:27 2003 @@ -236,7 +236,7 @@ /* The per cpu profile stuff - used in smp_local_timer_interrupt */ static unsigned int prof_multiplier[NR_CPUS] __cacheline_aligned = { 1, }; static unsigned int prof_old_multiplier[NR_CPUS] __cacheline_aligned = { 1, }; -static unsigned int prof_counter[NR_CPUS] __cacheline_aligned = { 1, }; +static DEFINE_PER_CPU(unsigned int, prof_counter) = 1; /* the map used to check if a CPU has booted */ static __u32 cpu_booted_map; @@ -393,9 +393,6 @@ /* initialize the CPU structures (moved from smp_boot_cpus) */ for(i=0; iLogicalDeviceNumber; - if (LogicalDeviceNumber > DAC960_MaxLogicalDrives) - panic("DAC960: Logical Drive Number %d not supported\n", - LogicalDeviceNumber); - if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) - panic("DAC960: Logical Drive Block Size %d not supported\n", - NewLogicalDeviceInfo->DeviceBlockSizeInBytes); + if (LogicalDeviceNumber >= DAC960_MaxLogicalDrives) { + DAC960_Error("DAC960: Logical Drive Number %d not supported\n", + Controller, LogicalDeviceNumber); + break; + } + if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) { + DAC960_Error("DAC960: Logical Drive Block Size %d not supported\n", + Controller, NewLogicalDeviceInfo->DeviceBlockSizeInBytes); + LogicalDeviceNumber++; + continue; + } PhysicalDevice.Controller = 0; PhysicalDevice.Channel = NewLogicalDeviceInfo->Channel; PhysicalDevice.TargetID = NewLogicalDeviceInfo->TargetID; diff -Nru a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig --- a/drivers/char/agp/Kconfig Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/Kconfig Tue Feb 11 00:01:27 2003 @@ -61,16 +61,6 @@ You should say Y here if you use XFree86 3.3.6 or 4.x and want to use GLX or DRI. If unsure, say N. -config AGP_VIA_KT400 - tristate "VIA KT400 chipset support" - depends on AGP3 - help - This option gives you AGP support for the GLX component of the - XFree86 4.x on VIA KT400 AGP 3.0 chipsets. - - You should say Y here if you use XFree86 3.3.6 or 4.x and want to - use GLX or DRI. If unsure, say N. - config AGP_AMD tristate "AMD Irongate, 761, and 762 support" depends on AGP @@ -140,6 +130,11 @@ help This option gives you AGP GART support for the HP ZX1 chipset for IA64 processors. + +config AGP_ALPHA_CORE + tristate + depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL) + default AGP # Put AGP 3.0 entries below here. diff -Nru a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile --- a/drivers/char/agp/Makefile Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/Makefile Tue Feb 11 00:01:27 2003 @@ -10,7 +10,6 @@ obj-$(CONFIG_AGP_INTEL) += intel-agp.o obj-$(CONFIG_AGP_VIA) += via-agp.o -obj-$(CONFIG_AGP_VIA_KT400) += via-kt400.o obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o obj-$(CONFIG_AGP_SIS) += sis-agp.o obj-$(CONFIG_AGP_ALI) += ali-agp.o @@ -18,6 +17,7 @@ obj-$(CONFIG_AGP_I460) += i460-agp.o obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o obj-$(CONFIG_AGP_AMD_8151) += amd-k8-agp.o +obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o obj-$(CONFIG_AGP_I7x05) += i7x05-agp.o diff -Nru a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h --- a/drivers/char/agp/agp.h Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/agp.h Tue Feb 11 00:01:27 2003 @@ -30,7 +30,7 @@ #include /* for flush_agp_cache() */ -extern struct agp_bridge_data agp_bridge; +extern struct agp_bridge_data *agp_bridge; #define PFX "agpgart: " @@ -128,6 +128,7 @@ int num_aperture_sizes; int capndx; int cant_use_aperture; + struct vm_operations_struct *vm_ops; /* Links to driver specific functions */ @@ -165,20 +166,20 @@ #define MB(x) (KB (KB (x))) #define GB(x) (MB (KB (x))) -#define CACHE_FLUSH agp_bridge.cache_flush +#define CACHE_FLUSH agp_bridge->cache_flush #define A_SIZE_8(x) ((struct aper_size_info_8 *) x) #define A_SIZE_16(x) ((struct aper_size_info_16 *) x) #define A_SIZE_32(x) ((struct aper_size_info_32 *) x) #define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x) #define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x) -#define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i) -#define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i) -#define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i) -#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i) -#define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i) +#define A_IDX8() (A_SIZE_8(agp_bridge->aperture_sizes) + i) +#define A_IDX16() (A_SIZE_16(agp_bridge->aperture_sizes) + i) +#define A_IDX32() (A_SIZE_32(agp_bridge->aperture_sizes) + i) +#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge->aperture_sizes) + i) +#define A_IDXFIX() (A_SIZE_FIX(agp_bridge->aperture_sizes) + i) #define MAXKEY (4096 * 32) -#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page) +#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge->scratch_page) /* intel register */ #define INTEL_APBASE 0x10 @@ -366,7 +367,7 @@ /* Generic routines. */ void agp_generic_agp_enable(u32 mode); -int agp_generic_agp_3_0_enable(u32 mode); +void agp_generic_agp_3_0_enable(u32 mode); int agp_generic_create_gatt_table(void); int agp_generic_free_gatt_table(void); agp_memory *agp_create_memory(int scratch_pages); diff -Nru a/drivers/char/agp/ali-agp.c b/drivers/char/agp/ali-agp.c --- a/drivers/char/agp/ali-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/ali-agp.c Tue Feb 11 00:01:27 2003 @@ -17,15 +17,15 @@ u32 temp; struct aper_size_info_32 *values; - pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp); + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); temp &= ~(0xfffffff0); - values = A_SIZE_32(agp_bridge.aperture_sizes); + values = A_SIZE_32(agp_bridge->aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -37,9 +37,9 @@ { u32 temp; - pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp); + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); // clear tag - pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL, + pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, ((temp & 0xfffffff0) | 0x00000001|0x00000002)); } @@ -48,15 +48,15 @@ struct aper_size_info_32 *previous_size; u32 temp; - previous_size = A_SIZE_32(agp_bridge.previous_size); + previous_size = A_SIZE_32(agp_bridge->previous_size); - pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp); + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); // clear tag - pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL, + pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, ((temp & 0xffffff00) | 0x00000001|0x00000002)); - pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp); - pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, ((temp & 0x00000ff0) | previous_size->size_value)); } @@ -65,24 +65,24 @@ u32 temp; struct aper_size_info_32 *current_size; - current_size = A_SIZE_32(agp_bridge.current_size); + current_size = A_SIZE_32(agp_bridge->current_size); /* aperture size and gatt addr */ - pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp); - temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000)) + pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); + temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000)) | (current_size->size_value & 0xf)); - pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp); + pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp); /* tlb control */ - pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, ALI_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); #if 0 - if (agp_bridge.type == ALI_M1541) { + if (agp_bridge->type == ALI_M1541) { u32 nlvm_addr = 0; switch (current_size->size_value) { @@ -101,15 +101,15 @@ nlvm_addr--; nlvm_addr&=0xfff00000; - nlvm_addr+= agp_bridge.gart_bus_addr; - nlvm_addr|=(agp_bridge.gart_bus_addr>>12); + nlvm_addr+= agp_bridge->gart_bus_addr; + nlvm_addr|=(agp_bridge->gart_bus_addr>>12); printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr); } #endif - pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp); + pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); temp &= 0xffffff7f; //enable TLB - pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp); + pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp); return 0; } @@ -118,23 +118,23 @@ { /* Memory type is ignored */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } static void ali_cache_flush(void) { global_cache_flush(); - if (agp_bridge.type == ALI_M1541) { + if (agp_bridge->type == ALI_M1541) { int i, page_count; u32 temp; - page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order; + page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order; for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) { - pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp); - pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | - (agp_bridge.gatt_bus_addr + i)) | + (agp_bridge->gatt_bus_addr + i)) | ALI_CACHE_FLUSH_EN)); } } @@ -148,9 +148,9 @@ if (adr == 0) return 0; - if (agp_bridge.type == ALI_M1541) { - pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp); - pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, + if (agp_bridge->type == ALI_M1541) { + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | virt_to_phys(adr)) | ALI_CACHE_FLUSH_EN )); @@ -167,9 +167,9 @@ global_cache_flush(); - if (agp_bridge.type == ALI_M1541) { - pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp); - pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, + if (agp_bridge->type == ALI_M1541) { + pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); + pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | virt_to_phys(addr)) | ALI_CACHE_FLUSH_EN)); @@ -197,30 +197,30 @@ static int __init ali_generic_setup (struct pci_dev *pdev) { - agp_bridge.masks = ali_generic_masks; - agp_bridge.aperture_sizes = (void *) ali_generic_sizes; - agp_bridge.size_type = U32_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = ali_configure; - agp_bridge.fetch_size = ali_fetch_size; - agp_bridge.cleanup = ali_cleanup; - agp_bridge.tlb_flush = ali_tlbflush; - agp_bridge.mask_memory = ali_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = ali_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = ali_alloc_page; - agp_bridge.agp_destroy_page = ali_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = ali_generic_masks; + agp_bridge->aperture_sizes = (void *) ali_generic_sizes; + agp_bridge->size_type = U32_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = ali_configure; + agp_bridge->fetch_size = ali_fetch_size; + agp_bridge->cleanup = ali_cleanup; + agp_bridge->tlb_flush = ali_tlbflush; + agp_bridge->mask_memory = ali_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = ali_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = ali_alloc_page; + agp_bridge->agp_destroy_page = ali_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -313,7 +313,7 @@ printk (KERN_INFO PFX "Detected ALi %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = devs[j].chipset; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -327,7 +327,7 @@ if (agp_try_unsupported) { printk(KERN_WARNING PFX "Trying generic ALi routines" " for device id: %04x\n", pdev->device); - agp_bridge.type = ALI_GENERIC; + agp_bridge->type = ALI_GENERIC; return ali_generic_setup(pdev); } @@ -350,10 +350,10 @@ /* probe for known chipsets */ if (agp_lookup_host_bridge(dev) != -ENODEV) { - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); ali_agp_driver.dev = dev; agp_register_driver(&ali_agp_driver); return 0; @@ -387,7 +387,7 @@ ret_val = pci_module_init(&agp_ali_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/char/agp/alpha-agp.c Tue Feb 11 00:01:27 2003 @@ -0,0 +1,217 @@ +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../../arch/alpha/kernel/pci_impl.h" + +#include "agp.h" + +static struct page *alpha_core_agp_vm_nopage(struct vm_area_struct *vma, + unsigned long address, + int write_access) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + dma_addr_t dma_addr; + unsigned long pa; + struct page *page; + + dma_addr = address - vma->vm_start + agp->aperture.bus_base; + pa = agp->ops->translate(agp, dma_addr); + + if (pa == (unsigned long)-EINVAL) return NULL; /* no translation */ + + /* + * Get the page, inc the use count, and return it + */ + page = virt_to_page(__va(pa)); + get_page(page); + return page; +} + +static struct aper_size_info_fixed alpha_core_agp_sizes[] = +{ + { 0, 0, 0 }, /* filled in by alpha_core_agp_setup */ +}; + +static struct gatt_mask alpha_core_agp_masks[] = { + { .mask = 0, .type = 0 }, +}; + +struct vm_operations_struct alpha_core_agp_vm_ops = { + .nopage = alpha_core_agp_vm_nopage, +}; + + +static int alpha_core_agp_nop(void) +{ + /* just return success */ + return 0; +} + +static int alpha_core_agp_fetch_size(void) +{ + return alpha_core_agp_sizes[0].size; +} + +static int alpha_core_agp_configure(void) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + agp_bridge->gart_bus_addr = agp->aperture.bus_base; + return 0; +} + +static void alpha_core_agp_cleanup(void) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + + agp->ops->cleanup(agp); +} + +static void alpha_core_agp_tlbflush(agp_memory *mem) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + alpha_mv.mv_pci_tbi(agp->hose, 0, -1); +} + +static unsigned long alpha_core_agp_mask_memory(unsigned long addr, int type) +{ + /* Memory type is ignored */ + return addr | agp_bridge->masks[0].mask; +} + +static void alpha_core_agp_enable(u32 mode) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + + agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw); + + agp->mode.bits.enable = 1; + agp->ops->configure(agp); + + agp_device_command(agp->mode.lw, 0); +} + +static int alpha_core_agp_insert_memory(agp_memory *mem, off_t pg_start, + int type) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + int num_entries, status; + void *temp; + + temp = agp_bridge->current_size; + num_entries = A_SIZE_FIX(temp)->num_entries; + if ((pg_start + mem->page_count) > num_entries) return -EINVAL; + + status = agp->ops->bind(agp, pg_start, mem); + mb(); + agp_bridge->tlb_flush(mem); + + return status; +} + +static int alpha_core_agp_remove_memory(agp_memory *mem, off_t pg_start, + int type) +{ + alpha_agp_info *agp = agp_bridge->dev_private_data; + int status; + + status = agp->ops->unbind(agp, pg_start, mem); + agp_bridge->tlb_flush(mem); + return status; +} + + +static struct agp_driver alpha_core_agp_driver = { + .owner = THIS_MODULE, +}; + +int __init +alpha_core_agp_setup(void) +{ + alpha_agp_info *agp = alpha_mv.agp_info(); + struct aper_size_info_fixed *aper_size; + + if (!agp) return -ENODEV; + if (agp->ops->setup(agp)) return -ENODEV; + + /* + * Build the aperture size descriptor + */ + aper_size = alpha_core_agp_sizes; + if (!aper_size) return -ENOMEM; + aper_size->size = agp->aperture.size / (1024 * 1024); + aper_size->num_entries = agp->aperture.size / PAGE_SIZE; + aper_size->page_order = ffs(aper_size->num_entries / 1024) - 1; + + /* + * Build a fake pci_dev struct + */ + if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) { + return -ENOMEM; + } + agp_bridge->dev->vendor = 0xffff; + agp_bridge->dev->device = 0xffff; + agp_bridge->dev->sysdata = agp->hose; + + /* + * Fill in the rest of the agp_bridge struct + */ + agp_bridge->masks = alpha_core_agp_masks; + agp_bridge->aperture_sizes = aper_size; + agp_bridge->current_size = aper_size; /* only one entry */ + agp_bridge->size_type = FIXED_APER_SIZE; + agp_bridge->num_aperture_sizes = 1; + agp_bridge->dev_private_data = agp; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = alpha_core_agp_configure; + agp_bridge->fetch_size = alpha_core_agp_fetch_size; + agp_bridge->cleanup = alpha_core_agp_cleanup; + agp_bridge->tlb_flush = alpha_core_agp_tlbflush; + agp_bridge->mask_memory = alpha_core_agp_mask_memory; + agp_bridge->agp_enable = alpha_core_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = alpha_core_agp_nop; + agp_bridge->free_gatt_table = alpha_core_agp_nop; + agp_bridge->insert_memory = alpha_core_agp_insert_memory; + agp_bridge->remove_memory = alpha_core_agp_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->mode = agp->capability.lw; + agp_bridge->cant_use_aperture = 1; + agp_bridgevm_ops = &alpha_core_agp_vm_ops; + + alpha_core_agp_driver.dev = agp_bridge->dev; + agp_register_driver(&alpha_core_agp_driver); + printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index); + return 0; +} + +static int __init agp_alpha_core_init(void) +{ + int ret_val = -ENODEV; + if (alpha_mv.agp_info) { + agp_bridge->type = ALPHA_CORE_AGP; + ret_val = alpha_core_agp_setup(); + } + + return ret_val; +} + +static void __exit agp_alpha_core_cleanup(void) +{ + agp_unregister_driver(&alpha_core_agp_driver); + /* no pci driver for core */ +} + +module_init(agp_alpha_core_init); +module_exit(agp_alpha_core_cleanup); + +MODULE_AUTHOR("Jeff Wiedemeier "); +MODULE_LICENSE("GPL and additional rights"); diff -Nru a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c --- a/drivers/char/agp/amd-k7-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/amd-k7-agp.c Tue Feb 11 00:01:27 2003 @@ -45,7 +45,7 @@ CACHE_FLUSH(); for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { - page_map->remapped[i] = agp_bridge.scratch_page; + page_map->remapped[i] = agp_bridge->scratch_page; } return 0; @@ -115,7 +115,7 @@ #define GET_PAGE_DIR_OFF(addr) (addr >> 22) #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ - GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr)) + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\ GET_PAGE_DIR_IDX(addr)]->remapped) @@ -129,7 +129,7 @@ u32 temp; int i; - value = A_SIZE_LVL2(agp_bridge.current_size); + value = A_SIZE_LVL2(agp_bridge->current_size); retval = amd_create_page_map(&page_dir); if (retval != 0) { return retval; @@ -141,18 +141,18 @@ return retval; } - agp_bridge.gatt_table_real = (u32 *)page_dir.real; - agp_bridge.gatt_table = (u32 *)page_dir.remapped; - agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real); + agp_bridge->gatt_table_real = (u32 *)page_dir.real; + agp_bridge->gatt_table = (u32 *)page_dir.remapped; + agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); /* Get the address for the gart region. * This is a bus address even on the alpha, b/c its * used to program the agp master not the cpu */ - pci_read_config_dword(agp_bridge.dev, AMD_APBASE, &temp); + pci_read_config_dword(agp_bridge->dev, AMD_APBASE, &temp); addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); - agp_bridge.gart_bus_addr = addr; + agp_bridge->gart_bus_addr = addr; /* Calculate the agp offset */ for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { @@ -168,8 +168,8 @@ { struct amd_page_map page_dir; - page_dir.real = (unsigned long *)agp_bridge.gatt_table_real; - page_dir.remapped = (unsigned long *)agp_bridge.gatt_table; + page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; + page_dir.remapped = (unsigned long *)agp_bridge->gatt_table; amd_free_gatt_pages(); amd_free_page_map(&page_dir); @@ -182,15 +182,15 @@ u32 temp; struct aper_size_info_lvl2 *values; - pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp); + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); temp = (temp & 0x0000000e); - values = A_SIZE_LVL2(agp_bridge.aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + values = A_SIZE_LVL2(agp_bridge->aperture_sizes); + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -204,22 +204,22 @@ u32 temp; u16 enable_reg; - current_size = A_SIZE_LVL2(agp_bridge.current_size); + current_size = A_SIZE_LVL2(agp_bridge->current_size); /* Get the memory mapped registers */ - pci_read_config_dword(agp_bridge.dev, AMD_MMBASE, &temp); + pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp); temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096); /* Write out the address of the gatt table */ OUTREG32(amd_irongate_private.registers, AMD_ATTBASE, - agp_bridge.gatt_bus_addr); + agp_bridge->gatt_bus_addr); /* Write the Sync register */ - pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL, 0x80); + pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80); /* Set indexing mode */ - pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL2, 0x00); + pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00); /* Write the enable register */ enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE); @@ -227,10 +227,10 @@ OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg); /* Write out the size register */ - pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp); + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 0x00000001); - pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp); + pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); /* Flush the tlb */ OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001); @@ -244,16 +244,16 @@ u32 temp; u16 enable_reg; - previous_size = A_SIZE_LVL2(agp_bridge.previous_size); + previous_size = A_SIZE_LVL2(agp_bridge->previous_size); enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE); enable_reg = (enable_reg & ~(0x0004)); OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg); /* Write back the previous size and disable gart translation */ - pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp); + pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); temp = ((temp & ~(0x0000000f)) | previous_size->size_value); - pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp); + pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); iounmap((void *) amd_irongate_private.registers); } @@ -274,7 +274,7 @@ { /* Only type 0 is supported by the irongate */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } static int amd_insert_memory(agp_memory * mem, @@ -284,7 +284,7 @@ unsigned long *cur_gatt; unsigned long addr; - num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries; + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; if (type != 0 || mem->type != 0) { return -EINVAL; @@ -295,7 +295,7 @@ j = pg_start; while (j < (pg_start + mem->page_count)) { - addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = GET_GATT(addr); if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) { return -EBUSY; @@ -309,12 +309,12 @@ } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { - addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = GET_GATT(addr); cur_gatt[GET_GATT_OFF(addr)] = - agp_bridge.mask_memory(mem->memory[i], mem->type); + agp_bridge->mask_memory(mem->memory[i], mem->type); } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -329,13 +329,13 @@ return -EINVAL; } for (i = pg_start; i < (mem->page_count + pg_start); i++) { - addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = GET_GATT(addr); cur_gatt[GET_GATT_OFF(addr)] = - (unsigned long) agp_bridge.scratch_page; + (unsigned long) agp_bridge->scratch_page; } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -357,30 +357,30 @@ static int __init amd_irongate_setup (struct pci_dev *pdev) { - agp_bridge.masks = amd_irongate_masks; - agp_bridge.aperture_sizes = (void *) amd_irongate_sizes; - agp_bridge.size_type = LVL2_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = (void *) &amd_irongate_private; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = amd_irongate_configure; - agp_bridge.fetch_size = amd_irongate_fetch_size; - agp_bridge.cleanup = amd_irongate_cleanup; - agp_bridge.tlb_flush = amd_irongate_tlbflush; - agp_bridge.mask_memory = amd_irongate_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = amd_create_gatt_table; - agp_bridge.free_gatt_table = amd_free_gatt_table; - agp_bridge.insert_memory = amd_insert_memory; - agp_bridge.remove_memory = amd_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = amd_irongate_masks; + agp_bridge->aperture_sizes = (void *) amd_irongate_sizes; + agp_bridge->size_type = LVL2_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = (void *) &amd_irongate_private; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = amd_irongate_configure; + agp_bridge->fetch_size = amd_irongate_fetch_size; + agp_bridge->cleanup = amd_irongate_cleanup; + agp_bridge->tlb_flush = amd_irongate_tlbflush; + agp_bridge->mask_memory = amd_irongate_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = amd_create_gatt_table; + agp_bridge->free_gatt_table = amd_free_gatt_table; + agp_bridge->insert_memory = amd_insert_memory; + agp_bridge->remove_memory = amd_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -416,7 +416,7 @@ while (devs[j].chipset_name != NULL) { if (pdev->device == devs[j].device_id) { printk (KERN_INFO PFX "Detected AMD %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = devs[j].chipset; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -430,7 +430,7 @@ if (agp_try_unsupported) { printk(KERN_WARNING PFX "Trying generic AMD routines" " for device id: %04x\n", pdev->device); - agp_bridge.type = AMD_GENERIC; + agp_bridge->type = AMD_GENERIC; return amd_irongate_setup(pdev); } @@ -455,10 +455,10 @@ return -ENODEV; if (agp_lookup_host_bridge(dev) != -ENODEV) { - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); amd_k7_agp_driver.dev = dev; agp_register_driver(&amd_k7_agp_driver); return 0; @@ -492,7 +492,7 @@ ret_val = pci_module_init(&agp_amdk7_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/amd-k8-agp.c b/drivers/char/agp/amd-k8-agp.c --- a/drivers/char/agp/amd-k8-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/amd-k8-agp.c Tue Feb 11 00:01:27 2003 @@ -70,7 +70,7 @@ /* gatt table should be empty. */ while (j < (pg_start + mem->page_count)) { - if (!PGE_EMPTY(agp_bridge.gatt_table[j])) + if (!PGE_EMPTY(agp_bridge->gatt_table[j])) return -EBUSY; j++; } @@ -81,7 +81,7 @@ } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { - addr = agp_bridge.mask_memory(mem->memory[i], mem->type); + addr = agp_bridge->mask_memory(mem->memory[i], mem->type); tmp = addr; BUG_ON(tmp & 0xffffff0000000ffc); @@ -89,9 +89,9 @@ pte |=(tmp & 0x00000000fffff000); pte |= 1<<1|1<<0; - agp_bridge.gatt_table[j] = pte; + agp_bridge->gatt_table[j] = pte; } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -134,12 +134,12 @@ temp = (temp & 0xe); values = A_SIZE_32(x86_64_aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -225,14 +225,14 @@ int current_size; int tmp, tmp2, i; u64 aperbar; - unsigned long gatt_bus = virt_to_phys(agp_bridge.gatt_table_real); + unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real); /* Configure AGP regs in each x86-64 host bridge. */ pci_for_each_dev(dev) { if (dev->bus->number==0 && PCI_FUNC(dev->devfn)==3 && PCI_SLOT(dev->devfn)>=24 && PCI_SLOT(dev->devfn)<=31) { - agp_bridge.gart_bus_addr = amd_x86_64_configure(dev,gatt_bus); + agp_bridge->gart_bus_addr = amd_x86_64_configure(dev,gatt_bus); hammer = dev; /* @@ -248,7 +248,7 @@ /* Shadow x86-64 registers into 8151 registers. */ - dev = agp_bridge.dev; + dev = agp_bridge->dev; if (!dev) return -ENODEV; @@ -315,7 +315,7 @@ static unsigned long amd_8151_mask_memory(unsigned long addr, int type) { - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } @@ -368,12 +368,12 @@ } - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &command); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command); command = agp_collect_device_status(mode, command); command |= 0x100; - pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_COMMAND, command); + pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command); agp_device_command(command, 1); } @@ -381,30 +381,30 @@ static int __init amd_8151_setup (struct pci_dev *pdev) { - agp_bridge.masks = amd_8151_masks; - agp_bridge.aperture_sizes = (void *) amd_8151_sizes; - agp_bridge.size_type = U32_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = amd_8151_configure; - agp_bridge.fetch_size = amd_x86_64_fetch_size; - agp_bridge.cleanup = amd_8151_cleanup; - agp_bridge.tlb_flush = amd_x86_64_tlbflush; - agp_bridge.mask_memory = amd_8151_mask_memory; - agp_bridge.agp_enable = agp_x86_64_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = x86_64_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = amd_8151_masks; + agp_bridge->aperture_sizes = (void *) amd_8151_sizes; + agp_bridge->size_type = U32_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = amd_8151_configure; + agp_bridge->fetch_size = amd_x86_64_fetch_size; + agp_bridge->cleanup = amd_8151_cleanup; + agp_bridge->tlb_flush = amd_x86_64_tlbflush; + agp_bridge->mask_memory = amd_8151_mask_memory; + agp_bridge->agp_enable = agp_x86_64_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = x86_64_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -420,11 +420,11 @@ if (cap_ptr == 0) return -ENODEV; - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); amd_8151_setup(dev); amd_k8_agp_driver.dev = dev; agp_register_driver(&amd_k8_agp_driver); @@ -458,9 +458,9 @@ ret_val = pci_module_init(&agp_amdk8_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; - agp_bridge.type = AMD_8151; + agp_bridge->type = AMD_8151; return ret_val; } diff -Nru a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c --- a/drivers/char/agp/backend.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/backend.c Tue Feb 11 00:01:27 2003 @@ -44,26 +44,27 @@ #define AGPGART_VERSION_MAJOR 0 #define AGPGART_VERSION_MINOR 100 -struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED }; +struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED }; +struct agp_bridge_data *agp_bridge = &agp_bridge_dummy; int agp_backend_acquire(void) { - if (agp_bridge.type == NOT_SUPPORTED) + if (agp_bridge->type == NOT_SUPPORTED) return -EINVAL; - if (atomic_read(&agp_bridge.agp_in_use) != 0) + if (atomic_read(&agp_bridge->agp_in_use) != 0) return -EBUSY; - atomic_inc(&agp_bridge.agp_in_use); + atomic_inc(&agp_bridge->agp_in_use); return 0; } void agp_backend_release(void) { - if (agp_bridge.type == NOT_SUPPORTED) + if (agp_bridge->type == NOT_SUPPORTED) return; - atomic_dec(&agp_bridge.agp_in_use); + atomic_dec(&agp_bridge->agp_in_use); } struct agp_max_table { @@ -114,38 +115,38 @@ { int size_value, rc, got_gatt=0, got_keylist=0; - agp_bridge.max_memory_agp = agp_find_max(); - agp_bridge.version = &agp_current_version; + agp_bridge->max_memory_agp = agp_find_max(); + agp_bridge->version = &agp_current_version; - if (agp_bridge.needs_scratch_page == TRUE) { + if (agp_bridge->needs_scratch_page == TRUE) { void *addr; - addr = agp_bridge.agp_alloc_page(); + addr = agp_bridge->agp_alloc_page(); if (addr == NULL) { printk(KERN_ERR PFX "unable to get memory for scratch page.\n"); return -ENOMEM; } - agp_bridge.scratch_page_real = virt_to_phys(addr); - agp_bridge.scratch_page = - agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0); + agp_bridge->scratch_page_real = virt_to_phys(addr); + agp_bridge->scratch_page = + agp_bridge->mask_memory(agp_bridge->scratch_page_real, 0); } - size_value = agp_bridge.fetch_size(); + size_value = agp_bridge->fetch_size(); if (size_value == 0) { printk(KERN_ERR PFX "unable to determine aperture size.\n"); rc = -EINVAL; goto err_out; } - if (agp_bridge.create_gatt_table()) { + if (agp_bridge->create_gatt_table()) { printk(KERN_ERR PFX "unable to get memory for graphics translation table.\n"); rc = -ENOMEM; goto err_out; } got_gatt = 1; - agp_bridge.key_list = vmalloc(PAGE_SIZE * 4); - if (agp_bridge.key_list == NULL) { + agp_bridge->key_list = vmalloc(PAGE_SIZE * 4); + if (agp_bridge->key_list == NULL) { printk(KERN_ERR PFX "error allocating memory for key lists.\n"); rc = -ENOMEM; goto err_out; @@ -153,27 +154,27 @@ got_keylist = 1; /* FIXME vmalloc'd memory not guaranteed contiguous */ - memset(agp_bridge.key_list, 0, PAGE_SIZE * 4); + memset(agp_bridge->key_list, 0, PAGE_SIZE * 4); - if (agp_bridge.configure()) { + if (agp_bridge->configure()) { printk(KERN_ERR PFX "error configuring host chipset.\n"); rc = -EINVAL; goto err_out; } printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n", - size_value, agp_bridge.gart_bus_addr); + size_value, agp_bridge->gart_bus_addr); return 0; err_out: - if (agp_bridge.needs_scratch_page == TRUE) { - agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real)); + if (agp_bridge->needs_scratch_page == TRUE) { + agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real)); } if (got_gatt) - agp_bridge.free_gatt_table(); + agp_bridge->free_gatt_table(); if (got_keylist) - vfree(agp_bridge.key_list); + vfree(agp_bridge->key_list); return rc; } @@ -181,13 +182,16 @@ /* cannot be __exit b/c as it could be called from __init code */ static void agp_backend_cleanup(void) { - agp_bridge.cleanup(); - agp_bridge.free_gatt_table(); - vfree(agp_bridge.key_list); - - if (agp_bridge.needs_scratch_page == TRUE) { - agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real)); - } + if (agp_bridge->cleanup != NULL) + agp_bridge->cleanup(); + if (agp_bridge->free_gatt_table != NULL) + agp_bridge->free_gatt_table(); + if (agp_bridge->key_list) + vfree(agp_bridge->key_list); + + if ((agp_bridge->agp_destroy_page!=NULL) && + (agp_bridge->needs_scratch_page == TRUE)) + agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real)); } static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data) @@ -195,9 +199,9 @@ switch(rq) { case PM_SUSPEND: - return agp_bridge.suspend(); + return agp_bridge->suspend(); case PM_RESUME: - agp_bridge.resume(); + agp_bridge->resume(); return 0; } return 0; @@ -248,21 +252,25 @@ /* FIXME: What to do with this? */ inter_module_register("drm_agp", THIS_MODULE, &drm_agp); - pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge.dev), agp_power); + pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge->dev), agp_power); agp_count++; return 0; frontend_err: agp_backend_cleanup(); err_out: - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; module_put(drv->owner); + drv->dev = NULL; return ret_val; } int agp_unregister_driver(struct agp_driver *drv) { - agp_bridge.type = NOT_SUPPORTED; + if (drv->dev==NULL) + return -ENODEV; + + agp_bridge->type = NOT_SUPPORTED; pm_unregister_all(agp_power); agp_frontend_cleanup(); agp_backend_cleanup(); @@ -282,8 +290,8 @@ already_initialised = 1; - memset(&agp_bridge, 0, sizeof(struct agp_bridge_data)); - agp_bridge.type = NOT_SUPPORTED; + memset(agp_bridge, 0, sizeof(struct agp_bridge_data)); + agp_bridge->type = NOT_SUPPORTED; printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n", AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR); diff -Nru a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c --- a/drivers/char/agp/frontend.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/frontend.c Tue Feb 11 00:01:27 2003 @@ -97,7 +97,9 @@ int size, pgprot_t page_prot) { agp_segment_priv *seg; - int num_segments, pg_start, pg_count, i; + int num_segments, i; + off_t pg_start; + size_t pg_count; pg_start = offset / 4096; pg_count = size / 4096; @@ -174,7 +176,7 @@ agp_segment_priv **ret_seg; agp_segment_priv *seg; agp_segment *user_seg; - int i; + size_t i; seg = kmalloc((sizeof(agp_segment_priv) * region->seg_count), GFP_KERNEL); if (seg == NULL) { @@ -578,8 +580,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma) { - int size; - int current_size; + unsigned int size, current_size; unsigned long offset; agp_client *client; agp_file_private *priv = (agp_file_private *) file->private_data; @@ -611,8 +612,11 @@ if (!agp_find_seg_in_client(client, offset, size, vma->vm_page_prot)) goto out_inval; - if (remap_page_range(vma, vma->vm_start, (kerninfo.aper_base + offset), - size, vma->vm_page_prot)) { + if (kerninfo.vm_ops) { + vma->vm_ops = kerninfo.vm_ops; + } else if (remap_page_range(vma, vma->vm_start, + (kerninfo.aper_base + offset), + size, vma->vm_page_prot)) { goto out_again; } AGP_UNLOCK(); @@ -623,8 +627,11 @@ if (size != current_size) goto out_inval; - if (remap_page_range(vma, vma->vm_start, kerninfo.aper_base, - size, vma->vm_page_prot)) { + if (kerninfo.vm_ops) { + vma->vm_ops = kerninfo.vm_ops; + } else if (remap_page_range(vma, vma->vm_start, + kerninfo.aper_base, + size, vma->vm_page_prot)) { goto out_again; } AGP_UNLOCK(); diff -Nru a/drivers/char/agp/generic-3.0.c b/drivers/char/agp/generic-3.0.c --- a/drivers/char/agp/generic-3.0.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/generic-3.0.c Tue Feb 11 00:01:27 2003 @@ -77,7 +77,7 @@ struct agp_3_0_dev *dev; }; - struct pci_dev *td = agp_bridge.dev, *dev; + struct pci_dev *td = agp_bridge->dev, *dev; struct list_head *head = &dev_list->list, *pos; struct agp_3_0_dev *cur; struct isoch_data *master, target; @@ -117,8 +117,8 @@ if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0) goto free_and_exit; - pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat); - pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus); + pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat); + pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus); /* Extract power-on defaults from the target */ target.maxbw = (tnistat >> 16) & 0xff; @@ -170,13 +170,13 @@ * in the target's NISTAT register, so we need to do this now * to get an accurate value for ISOCH_N later. */ - pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd); + pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd); tnicmd &= ~(0x3 << 6); tnicmd |= target.y << 6; - pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd); + pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd); /* Reread the target's ISOCH_N */ - pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat); + pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat); target.n = (tnistat >> 8) & 0xff; /* Calculate the minimum ISOCH_N needed by each master */ @@ -296,7 +296,7 @@ u32 trq, mrq, rem; unsigned int cdev = 0; - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus); trq = (tstatus >> 24) & 0xff; mrq = trq / ndevs; @@ -321,7 +321,7 @@ */ static int agp_3_0_node_enable(u32 mode, u32 minor) { - struct pci_dev *td = agp_bridge.dev, *dev; + struct pci_dev *td = agp_bridge->dev, *dev; u8 bus_num, mcapndx; u32 isoch, arqsz, cal_cycle, tmp, rate; u32 tstatus, tcmd, mcmd, mstatus, ncapid; @@ -364,7 +364,7 @@ } /* Extract some power-on defaults from the target */ - pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus); + pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus); isoch = (tstatus >> 17) & 0x1; arqsz = (tstatus >> 13) & 0x7; cal_cycle = (tstatus >> 10) & 0x7; @@ -470,7 +470,7 @@ * Also set the AGP_ENABLE bit, effectively 'turning on' the * target (this has to be done _before_ turning on the masters). */ - pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd); + pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd); tcmd &= ~(0x7 << 10); tcmd &= ~0x7; @@ -479,7 +479,7 @@ tcmd |= 0x1 << 8; tcmd |= rate; - pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd); + pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd); /* * Set the target's advertised arqsz value, the minimum supported @@ -525,11 +525,11 @@ * (AGP 3.0 devices are required to operate as AGP 2.0 devices * when not using 3.0 electricals. */ -int agp_generic_agp_3_0_enable(u32 mode) +void agp_generic_agp_3_0_enable(u32 mode) { u32 ncapid, major, minor, agp_3_0; - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid); major = (ncapid >> 20) & 0xf; minor = (ncapid >> 16) & 0xf; @@ -537,16 +537,13 @@ printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor); if(major >= 3) { - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0); /* * Check to see if we are operating in 3.0 mode */ - if((agp_3_0 >> 3) & 0x1) { + if((agp_3_0 >> 3) & 0x1) agp_3_0_node_enable(mode, minor); - return TRUE; - } } - return FALSE; } EXPORT_SYMBOL(agp_generic_agp_3_0_enable); diff -Nru a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c --- a/drivers/char/agp/generic.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/generic.c Tue Feb 11 00:01:27 2003 @@ -52,16 +52,16 @@ return; if (key < MAXKEY) - clear_bit(key, agp_bridge.key_list); + clear_bit(key, agp_bridge->key_list); } static int agp_get_key(void) { int bit; - bit = find_first_zero_bit(agp_bridge.key_list, MAXKEY); + bit = find_first_zero_bit(agp_bridge->key_list, MAXKEY); if (bit < MAXKEY) { - set_bit(bit, agp_bridge.key_list); + set_bit(bit, agp_bridge->key_list); return bit; } return -1; @@ -96,21 +96,21 @@ void agp_free_memory(agp_memory * curr) { - int i; + size_t i; - if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL)) + if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL)) return; if (curr->is_bound == TRUE) agp_unbind_memory(curr); if (curr->type != 0) { - agp_bridge.free_by_type(curr); + agp_bridge->free_by_type(curr); return; } if (curr->page_count != 0) { for (i = 0; i < curr->page_count; i++) { - agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[i])); + agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[i])); } } agp_free_key(curr->key); @@ -124,16 +124,16 @@ { int scratch_pages; agp_memory *new; - int i; + size_t i; - if (agp_bridge.type == NOT_SUPPORTED) + if (agp_bridge->type == NOT_SUPPORTED) return NULL; - if ((atomic_read(&agp_bridge.current_memory_agp) + page_count) > agp_bridge.max_memory_agp) + if ((atomic_read(&agp_bridge->current_memory_agp) + page_count) > agp_bridge->max_memory_agp) return NULL; if (type != 0) { - new = agp_bridge.alloc_by_type(page_count, type); + new = agp_bridge->alloc_by_type(page_count, type); return new; } @@ -145,7 +145,7 @@ return NULL; for (i = 0; i < page_count; i++) { - void *addr = agp_bridge.agp_alloc_page(); + void *addr = agp_bridge->agp_alloc_page(); if (addr == NULL) { agp_free_memory(new); @@ -167,9 +167,9 @@ int current_size; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: current_size = A_SIZE_8(temp)->size; break; @@ -201,9 +201,9 @@ int num_entries; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: num_entries = A_SIZE_8(temp)->num_entries; break; @@ -235,20 +235,21 @@ int agp_copy_info(agp_kern_info * info) { memset(info, 0, sizeof(agp_kern_info)); - if (agp_bridge.type == NOT_SUPPORTED) { - info->chipset = agp_bridge.type; + if (agp_bridge->type == NOT_SUPPORTED) { + info->chipset = agp_bridge->type; return -EIO; } - info->version.major = agp_bridge.version->major; - info->version.minor = agp_bridge.version->minor; - info->device = agp_bridge.dev; - info->chipset = agp_bridge.type; - info->mode = agp_bridge.mode; - info->aper_base = agp_bridge.gart_bus_addr; + info->version.major = agp_bridge->version->major; + info->version.minor = agp_bridge->version->minor; + info->device = agp_bridge->dev; + info->chipset = agp_bridge->type; + info->mode = agp_bridge->mode; + info->aper_base = agp_bridge->gart_bus_addr; info->aper_size = agp_return_size(); - info->max_memory = agp_bridge.max_memory_agp; - info->current_memory = atomic_read(&agp_bridge.current_memory_agp); - info->cant_use_aperture = agp_bridge.cant_use_aperture; + info->max_memory = agp_bridge->max_memory_agp; + info->current_memory = atomic_read(&agp_bridge->current_memory_agp); + info->cant_use_aperture = agp_bridge->cant_use_aperture; + info->vm_ops = agp_bridge->vm_ops; info->page_mask = ~0UL; return 0; } @@ -265,7 +266,7 @@ { int ret_val; - if ((agp_bridge.type == NOT_SUPPORTED) || + if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL) || (curr->is_bound == TRUE)) { return -EINVAL; } @@ -273,7 +274,7 @@ CACHE_FLUSH(); curr->is_flushed = TRUE; } - ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type); + ret_val = agp_bridge->insert_memory(curr, pg_start, curr->type); if (ret_val != 0) return ret_val; @@ -287,13 +288,13 @@ { int ret_val; - if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL)) + if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL)) return -EINVAL; if (curr->is_bound != TRUE) return -EINVAL; - ret_val = agp_bridge.remove_memory(curr, curr->pg_start, curr->type); + ret_val = agp_bridge->remove_memory(curr, curr->pg_start, curr->type); if (ret_val != 0) return ret_val; @@ -395,15 +396,15 @@ { u32 command; - pci_read_config_dword(agp_bridge.dev, - agp_bridge.capndx + PCI_AGP_STATUS, + pci_read_config_dword(agp_bridge->dev, + agp_bridge->capndx + PCI_AGP_STATUS, &command); command = agp_collect_device_status(mode, command); command |= 0x100; - pci_write_config_dword(agp_bridge.dev, - agp_bridge.capndx + PCI_AGP_COMMAND, + pci_write_config_dword(agp_bridge->dev, + agp_bridge->capndx + PCI_AGP_COMMAND, command); agp_device_command(command, 0); @@ -421,17 +422,17 @@ struct page *page; /* The generic routines can't handle 2 level gatt's */ - if (agp_bridge.size_type == LVL2_APER_SIZE) + if (agp_bridge->size_type == LVL2_APER_SIZE) return -EINVAL; table = NULL; - i = agp_bridge.aperture_size_idx; - temp = agp_bridge.current_size; + i = agp_bridge->aperture_size_idx; + temp = agp_bridge->current_size; size = page_order = num_entries = 0; - if (agp_bridge.size_type != FIXED_APER_SIZE) { + if (agp_bridge->size_type != FIXED_APER_SIZE) { do { - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: size = A_SIZE_8(temp)->size; page_order = @@ -462,15 +463,15 @@ if (table == NULL) { i++; - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: - agp_bridge.current_size = A_IDX8(); + agp_bridge->current_size = A_IDX8(); break; case U16_APER_SIZE: - agp_bridge.current_size = A_IDX16(); + agp_bridge->current_size = A_IDX16(); break; case U32_APER_SIZE: - agp_bridge.current_size = A_IDX32(); + agp_bridge->current_size = A_IDX32(); break; /* This case will never really * happen. @@ -478,15 +479,15 @@ case FIXED_APER_SIZE: case LVL2_APER_SIZE: default: - agp_bridge.current_size = - agp_bridge.current_size; + agp_bridge->current_size = + agp_bridge->current_size; break; } - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; } else { - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; } - } while ((table == NULL) && (i < agp_bridge.num_aperture_sizes)); + } while ((table == NULL) && (i < agp_bridge->num_aperture_sizes)); } else { size = ((struct aper_size_info_fixed *) temp)->size; page_order = ((struct aper_size_info_fixed *) temp)->page_order; @@ -502,14 +503,14 @@ for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) SetPageReserved(page); - agp_bridge.gatt_table_real = (u32 *) table; + agp_bridge->gatt_table_real = (u32 *) table; agp_gatt_table = (void *)table; CACHE_FLUSH(); - agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), + agp_bridge->gatt_table = ioremap_nocache(virt_to_phys(table), (PAGE_SIZE * (1 << page_order))); CACHE_FLUSH(); - if (agp_bridge.gatt_table == NULL) { + if (agp_bridge->gatt_table == NULL) { for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) ClearPageReserved(page); @@ -517,11 +518,11 @@ return -ENOMEM; } - agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real); + agp_bridge->gatt_bus_addr = virt_to_phys(agp_bridge->gatt_table_real); /* AK: bogus, should encode addresses > 4GB */ for (i = 0; i < num_entries; i++) - agp_bridge.gatt_table[i] = (unsigned long) agp_bridge.scratch_page; + agp_bridge->gatt_table[i] = (unsigned long) agp_bridge->scratch_page; return 0; } @@ -543,9 +544,9 @@ void *temp; struct page *page; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: page_order = A_SIZE_8(temp)->page_order; break; @@ -572,25 +573,27 @@ * from the table. */ - iounmap(agp_bridge.gatt_table); - table = (char *) agp_bridge.gatt_table_real; + iounmap(agp_bridge->gatt_table); + table = (char *) agp_bridge->gatt_table_real; table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) ClearPageReserved(page); - free_pages((unsigned long) agp_bridge.gatt_table_real, page_order); + free_pages((unsigned long) agp_bridge->gatt_table_real, page_order); return 0; } int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type) { - int i, j, num_entries; + int num_entries; + size_t i; + off_t j; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; - switch (agp_bridge.size_type) { + switch (agp_bridge->size_type) { case U8_APER_SIZE: num_entries = A_SIZE_8(temp)->num_entries; break; @@ -627,7 +630,7 @@ j = pg_start; while (j < (pg_start + mem->page_count)) { - if (!PGE_EMPTY(agp_bridge.gatt_table[j])) { + if (!PGE_EMPTY(agp_bridge->gatt_table[j])) { return -EBUSY; } j++; @@ -639,16 +642,16 @@ } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) - agp_bridge.gatt_table[j] = - agp_bridge.mask_memory(mem->memory[i], mem->type); + agp_bridge->gatt_table[j] = + agp_bridge->mask_memory(mem->memory[i], mem->type); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } int agp_generic_remove_memory(agp_memory * mem, off_t pg_start, int type) { - int i; + size_t i; if (type != 0 || mem->type != 0) { /* The generic routines know nothing of memory types */ @@ -657,11 +660,11 @@ /* AK: bogus, should encode addresses > 4GB */ for (i = pg_start; i < (mem->page_count + pg_start); i++) { - agp_bridge.gatt_table[i] = - (unsigned long) agp_bridge.scratch_page; + agp_bridge->gatt_table[i] = + (unsigned long) agp_bridge->scratch_page; } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -700,7 +703,7 @@ get_page(page); SetPageLocked(page); - atomic_inc(&agp_bridge.current_memory_agp); + atomic_inc(&agp_bridge->current_memory_agp); return page_address(page); } @@ -716,16 +719,16 @@ put_page(page); unlock_page(page); free_page((unsigned long)addr); - atomic_dec(&agp_bridge.current_memory_agp); + atomic_dec(&agp_bridge->current_memory_agp); } /* End Basic Page Allocation Routines */ void agp_enable(u32 mode) { - if (agp_bridge.type == NOT_SUPPORTED) + if (agp_bridge->type == NOT_SUPPORTED) return; - agp_bridge.agp_enable(mode); + agp_bridge->agp_enable(mode); } EXPORT_SYMBOL(agp_free_memory); diff -Nru a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c --- a/drivers/char/agp/hp-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/hp-agp.c Tue Feb 11 00:01:27 2003 @@ -176,7 +176,7 @@ size = hp_private.gart_size / MB(1); hp_zx1_sizes[0].size = size; - agp_bridge.current_size = (void *) &hp_zx1_sizes[0]; + agp_bridge->current_size = (void *) &hp_zx1_sizes[0]; return size; } @@ -184,10 +184,10 @@ { struct _hp_private *hp = &hp_private; - agp_bridge.gart_bus_addr = hp->gart_base; - agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP); - pci_read_config_dword(agp_bridge.dev, - agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode); + agp_bridge->gart_bus_addr = hp->gart_base; + agp_bridge->capndx = pci_find_capability(agp_bridge->dev, PCI_CAP_ID_AGP); + pci_read_config_dword(agp_bridge->dev, + agp_bridge->capndx + PCI_AGP_STATUS, &agp_bridge->mode); if (hp->io_pdir_owner) { OUTREG64(hp->registers, HP_ZX1_PDIR_BASE, @@ -241,7 +241,7 @@ } for (i = 0; i < hp->gatt_entries; i++) { - hp->gatt[i] = (unsigned long) agp_bridge.scratch_page; + hp->gatt[i] = (unsigned long) agp_bridge->scratch_page; } return 0; @@ -296,11 +296,11 @@ for (k = 0; k < hp->io_pages_per_kpage; k++, j++, paddr += hp->io_page_size) { - hp->gatt[j] = agp_bridge.mask_memory(paddr, type); + hp->gatt[j] = agp_bridge->mask_memory(paddr, type); } } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -316,10 +316,10 @@ io_pg_start = hp->io_pages_per_kpage * pg_start; io_pg_count = hp->io_pages_per_kpage * mem->page_count; for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { - hp->gatt[i] = agp_bridge.scratch_page; + hp->gatt[i] = agp_bridge->scratch_page; } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -330,39 +330,39 @@ static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused))) { - agp_bridge.masks = hp_zx1_masks; - agp_bridge.dev_private_data = NULL; - agp_bridge.size_type = FIXED_APER_SIZE; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = hp_zx1_configure; - agp_bridge.fetch_size = hp_zx1_fetch_size; - agp_bridge.cleanup = hp_zx1_cleanup; - agp_bridge.tlb_flush = hp_zx1_tlbflush; - agp_bridge.mask_memory = hp_zx1_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = hp_zx1_create_gatt_table; - agp_bridge.free_gatt_table = hp_zx1_free_gatt_table; - agp_bridge.insert_memory = hp_zx1_insert_memory; - agp_bridge.remove_memory = hp_zx1_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.cant_use_aperture = 1; + agp_bridge->masks = hp_zx1_masks; + agp_bridge->dev_private_data = NULL; + agp_bridge->size_type = FIXED_APER_SIZE; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = hp_zx1_configure; + agp_bridge->fetch_size = hp_zx1_fetch_size; + agp_bridge->cleanup = hp_zx1_cleanup; + agp_bridge->tlb_flush = hp_zx1_tlbflush; + agp_bridge->mask_memory = hp_zx1_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = hp_zx1_create_gatt_table; + agp_bridge->free_gatt_table = hp_zx1_free_gatt_table; + agp_bridge->insert_memory = hp_zx1_insert_memory; + agp_bridge->remove_memory = hp_zx1_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->cant_use_aperture = 1; return hp_zx1_ioc_init(); } static int __init agp_find_supported_device(struct pci_dev *dev) { - agp_bridge.dev = dev; + agp_bridge->dev = dev; /* ZX1 LBAs can be either PCI or AGP bridges */ if (pci_find_capability(dev, PCI_CAP_ID_AGP)) { printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n", dev->slot_name); - agp_bridge.type = HP_ZX1; - agp_bridge.dev = dev; + agp_bridge->type = HP_ZX1; + agp_bridge->dev = dev; return hp_zx1_setup(dev); } return -ENODEV; @@ -408,7 +408,7 @@ ret_val = pci_module_init(&agp_hp_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c --- a/drivers/char/agp/i460-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/i460-agp.c Tue Feb 11 00:01:27 2003 @@ -96,7 +96,7 @@ struct aper_size_info_8 *values; /* Determine the GART page size */ - pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp); + pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp); i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12; pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift); @@ -107,9 +107,9 @@ return 0; } - values = A_SIZE_8(agp_bridge.aperture_sizes); + values = A_SIZE_8(agp_bridge->aperture_sizes); - pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); + pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); /* Exit now if the IO drivers for the GART SRAMS are turned off */ if (temp & I460_SRAM_IO_DISABLE) { @@ -130,7 +130,7 @@ else i460.dynamic_apbase = INTEL_I460_APBASE; - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { /* * Dynamically calculate the proper num_entries and page_order values for * the define aperture sizes. Take care not to shift off the end of @@ -140,11 +140,11 @@ values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT); } - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { /* Neglect control bits when matching up size_value */ if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) { - agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -166,8 +166,8 @@ { u8 temp; - pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); - pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, + pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp); + pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, ((temp & ~I460_AGPSIZ_MASK) | size_value)); } @@ -175,7 +175,7 @@ { struct aper_size_info_8 *previous_size; - previous_size = A_SIZE_8(agp_bridge.previous_size); + previous_size = A_SIZE_8(agp_bridge->previous_size); i460_write_agpsiz(previous_size->size_value); if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) @@ -194,7 +194,7 @@ temp.large = 0; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); i460_write_agpsiz(current_size->size_value); /* @@ -202,14 +202,14 @@ * This has to be done since the AGP aperture can be above 4GB on * 460 based systems. */ - pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase, &(temp.small[0])); - pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase + 4, &(temp.small[1])); + pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0])); + pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1])); /* Clear BAR control bits */ - agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1); + agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1); - pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch); - pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, + pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch); + pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); /* @@ -234,16 +234,16 @@ /* * Load up the fixed address of the GART SRAMS which hold our GATT table. */ - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; page_order = A_SIZE_8(temp)->page_order; num_entries = A_SIZE_8(temp)->num_entries; i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order); /* These are no good, the should be removed from the agp_bridge strucure... */ - agp_bridge.gatt_table_real = NULL; - agp_bridge.gatt_table = NULL; - agp_bridge.gatt_bus_addr = 0; + agp_bridge->gatt_table_real = NULL; + agp_bridge->gatt_table = NULL; + agp_bridge->gatt_bus_addr = 0; for (i = 0; i < num_entries; ++i) WR_GATT(i, 0); @@ -256,7 +256,7 @@ int num_entries, i; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_8(temp)->num_entries; @@ -284,7 +284,7 @@ io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_8(temp)->num_entries; if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) { @@ -306,7 +306,7 @@ for (i = 0, j = io_pg_start; i < mem->page_count; i++) { paddr = mem->memory[i]; for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size) - WR_GATT(j, agp_bridge.mask_memory(paddr, mem->type)); + WR_GATT(j, agp_bridge->mask_memory(paddr, mem->type)); } WR_FLUSH_GATT(j - 1); return 0; @@ -364,7 +364,7 @@ lp->paddr = virt_to_phys(lpage); lp->refcount = 0; - atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp); + atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); return 0; } @@ -374,7 +374,7 @@ lp->alloced_map = NULL; free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT); - atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp); + atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp); } static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, int type) @@ -383,7 +383,7 @@ struct lp_desc *start, *end, *lp; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_8(temp)->num_entries; /* Figure out what pg_start means in terms of our large GART pages */ @@ -417,7 +417,7 @@ if (i460_alloc_large_page(lp) < 0) return -ENOMEM; pg = lp - i460.lp_desc; - WR_GATT(pg, agp_bridge.mask_memory(lp->paddr, 0)); + WR_GATT(pg, agp_bridge->mask_memory(lp->paddr, 0)); WR_FLUSH_GATT(pg); } @@ -439,7 +439,7 @@ struct lp_desc *start, *end, *lp; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_8(temp)->num_entries; /* Figure out what pg_start means in terms of our large GART pages */ @@ -519,43 +519,43 @@ static unsigned long i460_mask_memory (unsigned long addr, int type) { /* Make sure the returned address is a valid GATT entry */ - return (agp_bridge.masks[0].mask + return (agp_bridge->masks[0].mask | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12)); } static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused))) { - agp_bridge.masks = i460_masks; - agp_bridge.aperture_sizes = (void *) i460_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 3; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = i460_configure; - agp_bridge.fetch_size = i460_fetch_size; - agp_bridge.cleanup = i460_cleanup; - agp_bridge.tlb_flush = i460_tlb_flush; - agp_bridge.mask_memory = i460_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = i460_create_gatt_table; - agp_bridge.free_gatt_table = i460_free_gatt_table; + agp_bridge->masks = i460_masks; + agp_bridge->aperture_sizes = (void *) i460_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 3; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = i460_configure; + agp_bridge->fetch_size = i460_fetch_size; + agp_bridge->cleanup = i460_cleanup; + agp_bridge->tlb_flush = i460_tlb_flush; + agp_bridge->mask_memory = i460_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = i460_create_gatt_table; + agp_bridge->free_gatt_table = i460_free_gatt_table; #if I460_LARGE_IO_PAGES - agp_bridge.insert_memory = i460_insert_memory; - agp_bridge.remove_memory = i460_remove_memory; - agp_bridge.agp_alloc_page = i460_alloc_page; - agp_bridge.agp_destroy_page = i460_destroy_page; + agp_bridge->insert_memory = i460_insert_memory; + agp_bridge->remove_memory = i460_remove_memory; + agp_bridge->agp_alloc_page = i460_alloc_page; + agp_bridge->agp_destroy_page = i460_destroy_page; #else - agp_bridge.insert_memory = i460_insert_memory_small_io_page; - agp_bridge.remove_memory = i460_remove_memory_small_io_page; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; + agp_bridge->insert_memory = i460_insert_memory_small_io_page; + agp_bridge->remove_memory = i460_remove_memory_small_io_page; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; #endif - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 1; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 1; return 0; } @@ -571,8 +571,8 @@ if (cap_ptr == 0) return -ENODEV; - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; intel_i460_setup(dev); i460_agp_driver.dev = dev; agp_register_driver(&i460_agp_driver); @@ -605,7 +605,7 @@ ret_val = pci_module_init(&agp_intel_i460_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/i7x05-agp.c b/drivers/char/agp/i7x05-agp.c --- a/drivers/char/agp/i7x05-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/i7x05-agp.c Tue Feb 11 00:01:27 2003 @@ -13,16 +13,16 @@ /* * For AGP 3.0 APSIZE is now 16 bits */ - pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp); + pci_read_config_word (agp_bridge->dev, INTEL_I7505_APSIZE, &tmp); tmp = (tmp & 0xfff); - values = A_SIZE_16(agp_bridge.aperture_sizes); + values = A_SIZE_16(agp_bridge->aperture_sizes); - for (i=0; i < agp_bridge.num_aperture_sizes; i++) { + for (i=0; i < agp_bridge->num_aperture_sizes; i++) { if (tmp == values[i].size_value) { - agp_bridge.previous_size = agp_bridge.current_size = + agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -33,18 +33,18 @@ static void intel_7505_tlbflush(agp_memory *mem) { u32 temp; - pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7)); - pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7)); + pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7)); + pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp | (1 << 7)); } static void intel_7505_cleanup(void) { aper_size_info_16 *previous_size; - previous_size = A_SIZE_16(agp_bridge.previous_size); - pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE, + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, INTEL_I7505_APSIZE, previous_size->size_value); } @@ -54,25 +54,25 @@ u32 temp; aper_size_info_16 *current_size; - current_size = A_SIZE_16(agp_bridge.current_size); + current_size = A_SIZE_16(agp_bridge->current_size); /* aperture size */ - pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE, + pci_write_config_word(agp_bridge->dev, INTEL_I7505_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_I7505_NAPBASELO, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase */ - pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE, - agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_I7505_ATTBASE, + agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, 0x0000); /* clear error registers */ - pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff); + pci_write_config_byte(agp_bridge->dev, INTEL_I7505_ERRSTS, 0xff); return 0; } @@ -95,30 +95,30 @@ static int __init intel_7505_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_7505_sizes; - agp_bridge.size_type = U16_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_7505_configure; - agp_bridge.fetch_size = intel_7505_fetch_size; - agp_bridge.cleanup = intel_7505_cleanup; - agp_bridge.tlb_flush = intel_7505_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = i7505_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_7505_sizes; + agp_bridge->size_type = U16_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_7505_configure; + agp_bridge->fetch_size = intel_7505_fetch_size; + agp_bridge->cleanup = intel_7505_cleanup; + agp_bridge->tlb_flush = intel_7505_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = i7505_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -149,7 +149,7 @@ if (pdev->device == devs[j].device_id) { printk (KERN_INFO PFX "Detected Intel %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = devs[j].chipset; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -177,10 +177,10 @@ return -ENODEV; if (agp_lookup_host_bridge(dev) != -ENODEV) { - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode) + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode) i7x05_agp_driver.dev = dev; agp_register_driver(&i7x05_agp_driver); return 0; @@ -215,7 +215,7 @@ ret_val = pci_module_init(&agp_i7x05_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c --- a/drivers/char/agp/intel-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/intel-agp.c Tue Feb 11 00:01:27 2003 @@ -39,22 +39,22 @@ u32 smram_miscc; struct aper_size_info_fixed *values; - pci_read_config_dword(agp_bridge.dev, I810_SMRAM_MISCC, &smram_miscc); - values = A_SIZE_FIX(agp_bridge.aperture_sizes); + pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); + values = A_SIZE_FIX(agp_bridge->aperture_sizes); if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { printk(KERN_WARNING PFX "i810 is disabled\n"); return 0; } if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + 1); - agp_bridge.aperture_size_idx = 1; + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + 1); + agp_bridge->aperture_size_idx = 1; return values[1].size; } else { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values); - agp_bridge.aperture_size_idx = 0; + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values); + agp_bridge->aperture_size_idx = 0; return values[0].size; } @@ -67,7 +67,7 @@ u32 temp; int i; - current_size = A_SIZE_FIX(agp_bridge.current_size); + current_size = A_SIZE_FIX(agp_bridge->current_size); pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); temp &= 0xfff80000; @@ -81,16 +81,16 @@ intel_i810_private.num_dcache_entries = 1024; } pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL, - agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED); + agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED); CACHE_FLUSH(); - if (agp_bridge.needs_scratch_page == TRUE) { + if (agp_bridge->needs_scratch_page == TRUE) { for (i = 0; i < current_size->num_entries; i++) { OUTREG32(intel_i810_private.registers, I810_PTE_BASE + (i * 4), - agp_bridge.scratch_page); + agp_bridge->scratch_page); } } return 0; @@ -118,14 +118,14 @@ int i, j, num_entries; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_FIX(temp)->num_entries; if ((pg_start + mem->page_count) > num_entries) { return -EINVAL; } for (j = pg_start; j < (pg_start + mem->page_count); j++) { - if (!PGE_EMPTY(agp_bridge.gatt_table[j])) { + if (!PGE_EMPTY(agp_bridge->gatt_table[j])) { return -EBUSY; } } @@ -141,7 +141,7 @@ I810_PTE_VALID); } CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY)) @@ -154,11 +154,11 @@ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { OUTREG32(intel_i810_private.registers, I810_PTE_BASE + (j * 4), - agp_bridge.mask_memory(mem->memory[i], mem->type)); + agp_bridge->mask_memory(mem->memory[i], mem->type)); } CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -170,11 +170,11 @@ for (i = pg_start; i < (mem->page_count + pg_start); i++) { OUTREG32(intel_i810_private.registers, I810_PTE_BASE + (i * 4), - agp_bridge.scratch_page); + agp_bridge->scratch_page); } CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -211,7 +211,7 @@ if (new == NULL) return NULL; - addr = agp_bridge.agp_alloc_page(); + addr = agp_bridge->agp_alloc_page(); if (addr == NULL) { /* Free this structure */ @@ -232,7 +232,7 @@ { agp_free_key(curr->key); if(curr->type == AGP_PHYS_MEMORY) { - agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[0])); + agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[0])); vfree(curr->memory); } kfree(curr); @@ -241,37 +241,37 @@ static unsigned long intel_i810_mask_memory(unsigned long addr, int type) { /* Type checking must be done elsewhere */ - return addr | agp_bridge.masks[type].mask; + return addr | agp_bridge->masks[type].mask; } static int __init intel_i810_setup(struct pci_dev *i810_dev) { intel_i810_private.i810_dev = i810_dev; - agp_bridge.masks = intel_i810_masks; - agp_bridge.aperture_sizes = (void *) intel_i810_sizes; - agp_bridge.size_type = FIXED_APER_SIZE; - agp_bridge.num_aperture_sizes = 2; - agp_bridge.dev_private_data = (void *) &intel_i810_private; - agp_bridge.needs_scratch_page = TRUE; - agp_bridge.configure = intel_i810_configure; - agp_bridge.fetch_size = intel_i810_fetch_size; - agp_bridge.cleanup = intel_i810_cleanup; - agp_bridge.tlb_flush = intel_i810_tlbflush; - agp_bridge.mask_memory = intel_i810_mask_memory; - agp_bridge.agp_enable = intel_i810_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = intel_i810_insert_entries; - agp_bridge.remove_memory = intel_i810_remove_entries; - agp_bridge.alloc_by_type = intel_i810_alloc_by_type; - agp_bridge.free_by_type = intel_i810_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_i810_masks; + agp_bridge->aperture_sizes = (void *) intel_i810_sizes; + agp_bridge->size_type = FIXED_APER_SIZE; + agp_bridge->num_aperture_sizes = 2; + agp_bridge->dev_private_data = (void *) &intel_i810_private; + agp_bridge->needs_scratch_page = TRUE; + agp_bridge->configure = intel_i810_configure; + agp_bridge->fetch_size = intel_i810_fetch_size; + agp_bridge->cleanup = intel_i810_cleanup; + agp_bridge->tlb_flush = intel_i810_tlbflush; + agp_bridge->mask_memory = intel_i810_mask_memory; + agp_bridge->agp_enable = intel_i810_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = intel_i810_insert_entries; + agp_bridge->remove_memory = intel_i810_remove_entries; + agp_bridge->alloc_by_type = intel_i810_alloc_by_type; + agp_bridge->free_by_type = intel_i810_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -296,7 +296,7 @@ u8 rdct; static const int ddt[4] = { 0, 16, 32, 64 }; - pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl); + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); switch (gmch_ctrl & I830_GMCH_GMS_MASK) { case I830_GMCH_GMS_STOLEN_512: @@ -337,10 +337,10 @@ int num_entries; u32 temp; - size = agp_bridge.current_size; + size = agp_bridge->current_size; page_order = size->page_order; num_entries = size->num_entries; - agp_bridge.gatt_table_real = 0; + agp_bridge->gatt_table_real = 0; pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); temp &= 0xfff80000; @@ -354,9 +354,9 @@ /* we have to call this as early as possible after the MMIO base address is known */ intel_i830_init_gtt_entries(); - agp_bridge.gatt_table = NULL; + agp_bridge->gatt_table = NULL; - agp_bridge.gatt_bus_addr = temp; + agp_bridge->gatt_bus_addr = temp; return(0); } @@ -374,16 +374,16 @@ u16 gmch_ctrl; struct aper_size_info_fixed *values; - pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl); - values = A_SIZE_FIX(agp_bridge.aperture_sizes); + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); + values = A_SIZE_FIX(agp_bridge->aperture_sizes); if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { - agp_bridge.previous_size = agp_bridge.current_size = (void *) values; - agp_bridge.aperture_size_idx = 0; + agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->aperture_size_idx = 0; return(values[0].size); } else { - agp_bridge.previous_size = agp_bridge.current_size = (void *) values; - agp_bridge.aperture_size_idx = 1; + agp_bridge->previous_size = agp_bridge->current_size = (void *) values; + agp_bridge->aperture_size_idx = 1; return(values[1].size); } @@ -397,21 +397,21 @@ u16 gmch_ctrl; int i; - current_size = A_SIZE_FIX(agp_bridge.current_size); + current_size = A_SIZE_FIX(agp_bridge->current_size); pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); - pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl); + pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); gmch_ctrl |= I830_GMCH_ENABLED; - pci_write_config_word(agp_bridge.dev,I830_GMCH_CTRL,gmch_ctrl); + pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); - OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED); + OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED); CACHE_FLUSH(); - if (agp_bridge.needs_scratch_page == TRUE) + if (agp_bridge->needs_scratch_page == TRUE) for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) - OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page); + OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page); return (0); } @@ -426,7 +426,7 @@ int i,j,num_entries; void *temp; - temp = agp_bridge.current_size; + temp = agp_bridge->current_size; num_entries = A_SIZE_FIX(temp)->num_entries; if (pg_start < intel_i830_private.gtt_entries) { @@ -452,11 +452,11 @@ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4), - agp_bridge.mask_memory(mem->memory[i], mem->type)); + agp_bridge->mask_memory(mem->memory[i], mem->type)); CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return(0); } @@ -473,11 +473,11 @@ } for (i = pg_start; i < (mem->page_count + pg_start); i++) - OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page); + OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page); CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return (0); } @@ -504,7 +504,7 @@ if (nw == NULL) return(NULL); - addr = agp_bridge.agp_alloc_page(); + addr = agp_bridge->agp_alloc_page(); if (addr == NULL) { /* free this structure */ agp_free_memory(nw); @@ -526,35 +526,35 @@ { intel_i830_private.i830_dev = i830_dev; - agp_bridge.masks = intel_i810_masks; - agp_bridge.aperture_sizes = (void *) intel_i830_sizes; - agp_bridge.size_type = FIXED_APER_SIZE; - agp_bridge.num_aperture_sizes = 2; - - agp_bridge.dev_private_data = (void *) &intel_i830_private; - agp_bridge.needs_scratch_page = TRUE; - - agp_bridge.configure = intel_i830_configure; - agp_bridge.fetch_size = intel_i830_fetch_size; - agp_bridge.cleanup = intel_i830_cleanup; - agp_bridge.tlb_flush = intel_i810_tlbflush; - agp_bridge.mask_memory = intel_i810_mask_memory; - agp_bridge.agp_enable = intel_i810_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - - agp_bridge.create_gatt_table = intel_i830_create_gatt_table; - agp_bridge.free_gatt_table = intel_i830_free_gatt_table; - - agp_bridge.insert_memory = intel_i830_insert_entries; - agp_bridge.remove_memory = intel_i830_remove_entries; - agp_bridge.alloc_by_type = intel_i830_alloc_by_type; - agp_bridge.free_by_type = intel_i810_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_i810_masks; + agp_bridge->aperture_sizes = (void *) intel_i830_sizes; + agp_bridge->size_type = FIXED_APER_SIZE; + agp_bridge->num_aperture_sizes = 2; + + agp_bridge->dev_private_data = (void *) &intel_i830_private; + agp_bridge->needs_scratch_page = TRUE; + + agp_bridge->configure = intel_i830_configure; + agp_bridge->fetch_size = intel_i830_fetch_size; + agp_bridge->cleanup = intel_i830_cleanup; + agp_bridge->tlb_flush = intel_i810_tlbflush; + agp_bridge->mask_memory = intel_i810_mask_memory; + agp_bridge->agp_enable = intel_i810_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + + agp_bridge->create_gatt_table = intel_i830_create_gatt_table; + agp_bridge->free_gatt_table = intel_i830_free_gatt_table; + + agp_bridge->insert_memory = intel_i830_insert_entries; + agp_bridge->remove_memory = intel_i830_remove_entries; + agp_bridge->alloc_by_type = intel_i830_alloc_by_type; + agp_bridge->free_by_type = intel_i810_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return(0); } @@ -564,13 +564,13 @@ u16 temp; struct aper_size_info_16 *values; - pci_read_config_word(agp_bridge.dev, INTEL_APSIZE, &temp); - values = A_SIZE_16(agp_bridge.aperture_sizes); + pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); + values = A_SIZE_16(agp_bridge->aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -584,20 +584,20 @@ u8 temp; struct aper_size_info_8 *values; - pci_read_config_byte(agp_bridge.dev, INTEL_APSIZE, &temp); + pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); /* Intel 815 chipsets have a _weird_ APSIZE register with only * one non-reserved bit, so mask the others out ... */ - if (agp_bridge.type == INTEL_I815) + if (agp_bridge->type == INTEL_I815) temp &= (1 << 3); - values = A_SIZE_8(agp_bridge.aperture_sizes); + values = A_SIZE_8(agp_bridge->aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -607,18 +607,18 @@ static void intel_tlbflush(agp_memory * mem) { - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2200); - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); } static void intel_8xx_tlbflush(agp_memory * mem) { u32 temp; - pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7)); - pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7)); + pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); + pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); } @@ -627,10 +627,10 @@ u16 temp; struct aper_size_info_16 *previous_size; - previous_size = A_SIZE_16(agp_bridge.previous_size); - pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp); - pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9)); - pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value); + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); } @@ -639,10 +639,10 @@ u16 temp; struct aper_size_info_8 *previous_size; - previous_size = A_SIZE_8(agp_bridge.previous_size); - pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp); - pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9)); - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value); + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); } @@ -652,27 +652,27 @@ u16 temp2; struct aper_size_info_16 *current_size; - current_size = A_SIZE_16(agp_bridge.current_size); + current_size = A_SIZE_16(agp_bridge->current_size); /* aperture size */ - pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); /* paccfg/nbxcfg */ - pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2); - pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, (temp2 & ~(1 << 10)) | (1 << 9)); /* clear any possible error conditions */ - pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7); + pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); return 0; } @@ -682,32 +682,32 @@ u8 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ /* the Intel 815 chipset spec. says that bits 29-31 in the * ATTBASE register are reserved -> try not to write them */ - if (agp_bridge.gatt_bus_addr & INTEL_815_ATTBASE_MASK) + if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) panic("gatt bus addr too high"); - pci_read_config_dword(agp_bridge.dev, INTEL_ATTBASE, &addr); + pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); addr &= INTEL_815_ATTBASE_MASK; - addr |= agp_bridge.gatt_bus_addr; - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, addr); + addr |= agp_bridge->gatt_bus_addr; + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* apcont */ - pci_read_config_byte(agp_bridge.dev, INTEL_815_APCONT, &temp2); - pci_write_config_byte(agp_bridge.dev, INTEL_815_APCONT, temp2 | (1 << 1)); + pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); /* clear any possible error conditions */ /* Oddness : this chipset seems to have no ERRSTS register ! */ @@ -724,11 +724,11 @@ u8 temp; struct aper_size_info_8 *previous_size; - previous_size = A_SIZE_8(agp_bridge.previous_size); - pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp); - pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); + pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp & ~(1 << 1)); - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); } @@ -739,28 +739,28 @@ u8 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* global enable aperture access */ /* This flag is not accessed through MCHCFG register as in */ /* i850 chipset. */ - pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp2); - pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, temp2 | (1 << 1)); + pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); /* clear any possible AGP-related error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I820_ERRSTS, 0x001c); + pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); return 0; } @@ -770,26 +770,26 @@ u16 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* mcgcfg */ - pci_read_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, &temp2); - pci_write_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); + pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); /* clear any possible error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I840_ERRSTS, 0xc000); + pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); return 0; } @@ -799,26 +799,26 @@ u8 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* agpm */ - pci_read_config_byte(agp_bridge.dev, INTEL_I845_AGPM, &temp2); - pci_write_config_byte(agp_bridge.dev, INTEL_I845_AGPM, temp2 | (1 << 1)); + pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); + pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); /* clear any possible error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I845_ERRSTS, 0x001c); + pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); return 0; } @@ -833,26 +833,26 @@ u16 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* mcgcfg */ - pci_read_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, &temp2); - pci_write_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); + pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); /* clear any possible AGP-related error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I850_ERRSTS, 0x001c); + pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); return 0; } @@ -862,26 +862,26 @@ u16 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* mcgcfg */ - pci_read_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, &temp2); - pci_write_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); + pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); /* clear any possible AGP-related error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I860_ERRSTS, 0xf700); + pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); return 0; } @@ -891,33 +891,33 @@ u16 temp2; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value); + pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); /* address to map to */ - pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* attbase - aperture base */ - pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr); + pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); /* agpctrl */ - pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000); + pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); /* gmch */ - pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2); - pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp2 | (1 << 9)); + pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); + pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); /* clear any possible AGP-related error conditions */ - pci_write_config_word(agp_bridge.dev, INTEL_I830_ERRSTS, 0x1c); + pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); return 0; } static unsigned long intel_mask_memory(unsigned long addr, int type) { /* Memory type is ignored */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } static void intel_resume(void) @@ -969,234 +969,234 @@ static int __init intel_generic_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_generic_sizes; - agp_bridge.size_type = U16_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_configure; - agp_bridge.fetch_size = intel_fetch_size; - agp_bridge.cleanup = intel_cleanup; - agp_bridge.tlb_flush = intel_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = intel_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_generic_sizes; + agp_bridge->size_type = U16_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_configure; + agp_bridge->fetch_size = intel_fetch_size; + agp_bridge->cleanup = intel_cleanup; + agp_bridge->tlb_flush = intel_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = intel_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_815_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_815_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 2; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_815_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_815_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 2; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_815_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_820_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_8xx_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_820_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_820_cleanup; - agp_bridge.tlb_flush = intel_820_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_8xx_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_820_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_820_cleanup; + agp_bridge->tlb_flush = intel_820_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_830mp_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_830mp_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 4; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_830mp_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_830mp_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 4; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_830mp_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_840_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_8xx_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_840_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_8xx_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_840_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_845_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_8xx_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_845_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = intel_845_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_8xx_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_845_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = intel_845_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_850_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_8xx_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_850_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_8xx_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_850_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } static int __init intel_860_setup (struct pci_dev *pdev) { - agp_bridge.masks = intel_generic_masks; - agp_bridge.aperture_sizes = (void *) intel_8xx_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_860_configure; - agp_bridge.fetch_size = intel_8xx_fetch_size; - agp_bridge.cleanup = intel_8xx_cleanup; - agp_bridge.tlb_flush = intel_8xx_tlbflush; - agp_bridge.mask_memory = intel_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = intel_generic_masks; + agp_bridge->aperture_sizes = (void *) intel_8xx_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = intel_860_configure; + agp_bridge->fetch_size = intel_8xx_fetch_size; + agp_bridge->cleanup = intel_8xx_cleanup; + agp_bridge->tlb_flush = intel_8xx_tlbflush; + agp_bridge->mask_memory = intel_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -1287,7 +1287,7 @@ if (pdev->device == devs[j].device_id) { printk (KERN_INFO PFX "Detected Intel %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = devs[j].chipset; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -1302,7 +1302,7 @@ if (agp_try_unsupported) { printk(KERN_WARNING PFX "Trying generic Intel routines" " for device id: %04x\n", pdev->device); - agp_bridge.type = INTEL_GENERIC; + agp_bridge->type = INTEL_GENERIC; return intel_generic_setup(pdev); } @@ -1319,7 +1319,7 @@ struct pci_dev *i810_dev; u8 cap_ptr = 0; - agp_bridge.dev = dev; + agp_bridge->dev = dev; /* This shit needs moving into tables/init-routines. */ switch (dev->device) { @@ -1331,7 +1331,7 @@ return -ENODEV; } printk(KERN_INFO PFX "Detected an Intel i810 Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i810_setup (i810_dev); case PCI_DEVICE_ID_INTEL_82810_MC3: @@ -1342,7 +1342,7 @@ return -ENODEV; } printk(KERN_INFO PFX "Detected an Intel i810 DC100 Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i810_setup(i810_dev); case PCI_DEVICE_ID_INTEL_82810E_MC: @@ -1353,7 +1353,7 @@ return -ENODEV; } printk(KERN_INFO PFX "Detected an Intel i810 E Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i810_setup(i810_dev); case PCI_DEVICE_ID_INTEL_82815_MC: @@ -1371,7 +1371,7 @@ break; } printk(KERN_INFO PFX "agpgart: Detected an Intel i815 Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i810_setup(i810_dev); case PCI_DEVICE_ID_INTEL_82845G_HB: @@ -1387,11 +1387,11 @@ * We probably have a I845MP chipset with an external graphics * card. It will be initialized later */ - agp_bridge.type = INTEL_I845_G; + agp_bridge->type = INTEL_I845_G; break; } printk(KERN_INFO PFX "Detected an Intel 845G Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i830_setup(i810_dev); case PCI_DEVICE_ID_INTEL_82830_HB: @@ -1402,11 +1402,11 @@ if (i810_dev == NULL) { /* Intel 830MP with external graphic card */ /* It will be initialized later */ - agp_bridge.type = INTEL_I830_M; + agp_bridge->type = INTEL_I830_M; break; } printk(KERN_INFO PFX "Detected an Intel 830M Chipset.\n"); - agp_bridge.type = INTEL_I810; + agp_bridge->type = INTEL_I810; return intel_i830_setup(i810_dev); default: @@ -1416,10 +1416,10 @@ cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP); if (cap_ptr == 0) return -ENODEV; - agp_bridge.capndx = cap_ptr; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); /* probe for known chipsets */ return agp_lookup_host_bridge(dev); @@ -1472,7 +1472,7 @@ ret_val = pci_module_init(&agp_intel_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/sis-agp.c b/drivers/char/agp/sis-agp.c --- a/drivers/char/agp/sis-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/sis-agp.c Tue Feb 11 00:01:27 2003 @@ -16,16 +16,16 @@ int i; struct aper_size_info_8 *values; - pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size); - values = A_SIZE_8(agp_bridge.aperture_sizes); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size); + values = A_SIZE_8(agp_bridge->aperture_sizes); + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if ((temp_size == values[i].size_value) || ((temp_size & ~(0x03)) == (values[i].size_value & ~(0x03)))) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -35,7 +35,7 @@ static void sis_tlbflush(agp_memory * mem) { - pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02); + pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02); } static int sis_configure(void) @@ -43,13 +43,13 @@ u32 temp; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); - pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05); - pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); - pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE, - agp_bridge.gatt_bus_addr); - pci_write_config_byte(agp_bridge.dev, SIS_APSIZE, + current_size = A_SIZE_8(agp_bridge->current_size); + pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05); + pci_read_config_dword(agp_bridge->dev, SIS_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE, + agp_bridge->gatt_bus_addr); + pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, current_size->size_value); return 0; } @@ -58,8 +58,8 @@ { struct aper_size_info_8 *previous_size; - previous_size = A_SIZE_8(agp_bridge.previous_size); - pci_write_config_byte(agp_bridge.dev, SIS_APSIZE, + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, (previous_size->size_value & ~(0x03))); } @@ -67,7 +67,7 @@ { /* Memory type is ignored */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } static struct aper_size_info_8 sis_generic_sizes[7] = @@ -88,30 +88,30 @@ static int __init sis_generic_setup (struct pci_dev *pdev) { - agp_bridge.masks = sis_generic_masks; - agp_bridge.aperture_sizes = (void *) sis_generic_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = sis_configure; - agp_bridge.fetch_size = sis_fetch_size; - agp_bridge.cleanup = sis_cleanup; - agp_bridge.tlb_flush = sis_tlbflush; - agp_bridge.mask_memory = sis_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = sis_generic_masks; + agp_bridge->aperture_sizes = (void *) sis_generic_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = sis_configure; + agp_bridge->fetch_size = sis_fetch_size; + agp_bridge->cleanup = sis_cleanup; + agp_bridge->tlb_flush = sis_tlbflush; + agp_bridge->mask_memory = sis_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } @@ -198,7 +198,7 @@ if (pdev->device == devs[j].device_id) { printk (KERN_INFO PFX "Detected SiS %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = devs[j].chipset; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -212,7 +212,7 @@ if (agp_try_unsupported) { printk(KERN_WARNING PFX "Trying generic SiS routines" " for device id: %04x\n", pdev->device); - agp_bridge.type = SIS_GENERIC; + agp_bridge->type = SIS_GENERIC; return sis_generic_setup(pdev); } @@ -235,10 +235,10 @@ /* probe for known chipsets */ if (agp_lookup_host_bridge(dev) != -ENODEV) { - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); sis_agp_driver.dev = dev; agp_register_driver(&sis_agp_driver); return 0; @@ -272,7 +272,7 @@ ret_val = pci_module_init(&agp_sis_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c --- a/drivers/char/agp/sworks-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/sworks-agp.c Tue Feb 11 00:01:27 2003 @@ -47,7 +47,7 @@ CACHE_FLUSH(); for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { - page_map->remapped[i] = agp_bridge.scratch_page; + page_map->remapped[i] = agp_bridge->scratch_page; } return 0; @@ -120,7 +120,7 @@ #ifndef GET_PAGE_DIR_IDX #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ - GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr)) + GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) #endif #ifndef GET_GATT_OFF @@ -135,7 +135,7 @@ u32 temp; int i; - value = A_SIZE_LVL2(agp_bridge.current_size); + value = A_SIZE_LVL2(agp_bridge->current_size); retval = serverworks_create_page_map(&page_dir); if (retval != 0) { return retval; @@ -147,7 +147,7 @@ } /* Create a fake scratch directory */ for(i = 0; i < 1024; i++) { - serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge.scratch_page; + serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page; page_dir.remapped[i] = virt_to_phys(serverworks_private.scratch_dir.real); page_dir.remapped[i] |= 0x00000001; @@ -160,17 +160,17 @@ return retval; } - agp_bridge.gatt_table_real = (u32 *)page_dir.real; - agp_bridge.gatt_table = (u32 *)page_dir.remapped; - agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real); + agp_bridge->gatt_table_real = (u32 *)page_dir.real; + agp_bridge->gatt_table = (u32 *)page_dir.remapped; + agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); /* Get the address for the gart region. * This is a bus address even on the alpha, b/c its * used to program the agp master not the cpu */ - pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* Calculate the agp offset */ @@ -187,8 +187,8 @@ { struct serverworks_page_map page_dir; - page_dir.real = (unsigned long *)agp_bridge.gatt_table_real; - page_dir.remapped = (unsigned long *)agp_bridge.gatt_table; + page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; + page_dir.remapped = (unsigned long *)agp_bridge->gatt_table; serverworks_free_gatt_pages(); serverworks_free_page_map(&page_dir); @@ -203,20 +203,20 @@ u32 temp2; struct aper_size_info_lvl2 *values; - values = A_SIZE_LVL2(agp_bridge.aperture_sizes); - pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp); - pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs, + values = A_SIZE_LVL2(agp_bridge->aperture_sizes); + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); + pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs, SVWRKS_SIZE_MASK); - pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp2); - pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,temp); + pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2); + pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp); temp2 &= SVWRKS_SIZE_MASK; - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp2 == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->aperture_size_idx = i; return values[i].size; } } @@ -231,17 +231,17 @@ u8 enable_reg; u16 cap_reg; - current_size = A_SIZE_LVL2(agp_bridge.current_size); + current_size = A_SIZE_LVL2(agp_bridge->current_size); /* Get the memory mapped registers */ - pci_read_config_dword(agp_bridge.dev, serverworks_private.mm_addr_ofs, &temp); + pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp); temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096); OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a); OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE, - agp_bridge.gatt_bus_addr); + agp_bridge->gatt_bus_addr); cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND); cap_reg &= ~0x0007; @@ -253,21 +253,21 @@ enable_reg |= 0x1; /* Agp Enable bit */ pci_write_config_byte(serverworks_private.svrwrks_dev, SVWRKS_AGP_ENABLE, enable_reg); - agp_bridge.tlb_flush(NULL); + agp_bridge->tlb_flush(NULL); - agp_bridge.capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP); + agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP); /* Fill in the mode register */ pci_read_config_dword(serverworks_private.svrwrks_dev, - agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); - pci_read_config_byte(agp_bridge.dev, SVWRKS_CACHING, &enable_reg); + pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg); enable_reg &= ~0x3; - pci_write_config_byte(agp_bridge.dev, SVWRKS_CACHING, enable_reg); + pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg); - pci_read_config_byte(agp_bridge.dev, SVWRKS_FEATURE, &enable_reg); + pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg); enable_reg |= (1<<6); - pci_write_config_byte(agp_bridge.dev,SVWRKS_FEATURE, enable_reg); + pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg); return 0; } @@ -313,7 +313,7 @@ { /* Only type 0 is supported by the serverworks chipsets */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } static int serverworks_insert_memory(agp_memory * mem, @@ -323,7 +323,7 @@ unsigned long *cur_gatt; unsigned long addr; - num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries; + num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; if (type != 0 || mem->type != 0) { return -EINVAL; @@ -334,7 +334,7 @@ j = pg_start; while (j < (pg_start + mem->page_count)) { - addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = SVRWRKS_GET_GATT(addr); if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) { return -EBUSY; @@ -348,12 +348,12 @@ } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { - addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = SVRWRKS_GET_GATT(addr); cur_gatt[GET_GATT_OFF(addr)] = - agp_bridge.mask_memory(mem->memory[i], mem->type); + agp_bridge->mask_memory(mem->memory[i], mem->type); } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -369,16 +369,16 @@ } CACHE_FLUSH(); - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); for (i = pg_start; i < (mem->page_count + pg_start); i++) { - addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr; + addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; cur_gatt = SVRWRKS_GET_GATT(addr); cur_gatt[GET_GATT_OFF(addr)] = - (unsigned long) agp_bridge.scratch_page; + (unsigned long) agp_bridge->scratch_page; } - agp_bridge.tlb_flush(mem); + agp_bridge->tlb_flush(mem); return 0; } @@ -403,7 +403,7 @@ u32 command; pci_read_config_dword(serverworks_private.svrwrks_dev, - agp_bridge.capndx + PCI_AGP_STATUS, + agp_bridge->capndx + PCI_AGP_STATUS, &command); command = agp_collect_device_status(mode, command); @@ -414,7 +414,7 @@ command |= 0x100; pci_write_config_dword(serverworks_private.svrwrks_dev, - agp_bridge.capndx + PCI_AGP_COMMAND, + agp_bridge->capndx + PCI_AGP_COMMAND, command); agp_device_command(command, 0); @@ -427,39 +427,39 @@ serverworks_private.svrwrks_dev = pdev; - agp_bridge.masks = serverworks_masks; - agp_bridge.aperture_sizes = (void *) serverworks_sizes; - agp_bridge.size_type = LVL2_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = (void *) &serverworks_private; - agp_bridge.needs_scratch_page = TRUE; - agp_bridge.configure = serverworks_configure; - agp_bridge.fetch_size = serverworks_fetch_size; - agp_bridge.cleanup = serverworks_cleanup; - agp_bridge.tlb_flush = serverworks_tlbflush; - agp_bridge.mask_memory = serverworks_mask_memory; - agp_bridge.agp_enable = serverworks_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = serverworks_create_gatt_table; - agp_bridge.free_gatt_table = serverworks_free_gatt_table; - agp_bridge.insert_memory = serverworks_insert_memory; - agp_bridge.remove_memory = serverworks_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; + agp_bridge->masks = serverworks_masks; + agp_bridge->aperture_sizes = (void *) serverworks_sizes; + agp_bridge->size_type = LVL2_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = (void *) &serverworks_private; + agp_bridge->needs_scratch_page = TRUE; + agp_bridge->configure = serverworks_configure; + agp_bridge->fetch_size = serverworks_fetch_size; + agp_bridge->cleanup = serverworks_cleanup; + agp_bridge->tlb_flush = serverworks_tlbflush; + agp_bridge->mask_memory = serverworks_mask_memory; + agp_bridge->agp_enable = serverworks_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = serverworks_create_gatt_table; + agp_bridge->free_gatt_table = serverworks_free_gatt_table; + agp_bridge->insert_memory = serverworks_insert_memory; + agp_bridge->remove_memory = serverworks_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; - pci_read_config_dword(agp_bridge.dev, + pci_read_config_dword(agp_bridge->dev, SVWRKS_APSIZE, &temp); serverworks_private.gart_addr_ofs = 0x10; if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { - pci_read_config_dword(agp_bridge.dev, + pci_read_config_dword(agp_bridge->dev, SVWRKS_APSIZE + 4, &temp2); if(temp2 != 0) { @@ -472,11 +472,11 @@ serverworks_private.mm_addr_ofs = 0x14; } - pci_read_config_dword(agp_bridge.dev, + pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp); if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { - pci_read_config_dword(agp_bridge.dev, + pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs + 4, &temp2); if(temp2 != 0) { @@ -503,21 +503,21 @@ return -ENODEV; } - agp_bridge.dev = dev; + agp_bridge->dev = dev; switch (dev->device) { case PCI_DEVICE_ID_SERVERWORKS_HE: - agp_bridge.type = SVWRKS_HE; + agp_bridge->type = SVWRKS_HE; return serverworks_setup(bridge_dev); case PCI_DEVICE_ID_SERVERWORKS_LE: case 0x0007: - agp_bridge.type = SVWRKS_LE; + agp_bridge->type = SVWRKS_LE; return serverworks_setup(bridge_dev); default: if(agp_try_unsupported) { - agp_bridge.type = SVWRKS_GENERIC; + agp_bridge->type = SVWRKS_GENERIC; return serverworks_setup(bridge_dev); } break; @@ -565,7 +565,7 @@ ret_val = pci_module_init(&agp_serverworks_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } diff -Nru a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c --- a/drivers/char/agp/via-agp.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/agp/via-agp.c Tue Feb 11 00:01:27 2003 @@ -11,73 +11,78 @@ static int agp_try_unsupported __initdata = 0; + static int via_fetch_size(void) { int i; u8 temp; struct aper_size_info_8 *values; - values = A_SIZE_8(agp_bridge.aperture_sizes); - pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + values = A_SIZE_8(agp_bridge->aperture_sizes); + pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp); + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; return values[i].size; } } - return 0; } + static int via_configure(void) { u32 temp; struct aper_size_info_8 *current_size; - current_size = A_SIZE_8(agp_bridge.current_size); + current_size = A_SIZE_8(agp_bridge->current_size); /* aperture size */ - pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, current_size->size_value); /* address to map too */ - pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); /* GART control register */ - pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); /* attbase - aperture GATT base */ - pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE, - (agp_bridge.gatt_bus_addr & 0xfffff000) | 3); + pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE, + (agp_bridge->gatt_bus_addr & 0xfffff000) | 3); return 0; } + static void via_cleanup(void) { struct aper_size_info_8 *previous_size; - previous_size = A_SIZE_8(agp_bridge.previous_size); - pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, + previous_size = A_SIZE_8(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value); /* Do not disable by writing 0 to VIA_ATTBASE, it screws things up * during reinitialization. */ } + static void via_tlbflush(agp_memory * mem) { - pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f); - pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000008f); + pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); } + static unsigned long via_mask_memory(unsigned long addr, int type) { /* Memory type is ignored */ - return addr | agp_bridge.masks[0].mask; + return addr | agp_bridge->masks[0].mask; } + static struct aper_size_info_8 via_generic_sizes[7] = { {256, 65536, 6, 0}, @@ -89,123 +94,327 @@ {4, 1024, 0, 252} }; + static struct gatt_mask via_generic_masks[] = { {.mask = 0x00000000, .type = 0} }; + +#ifdef CONFIG_AGP3 +static int via_fetch_size_agp3(void) +{ + int i; + u16 temp; + struct aper_size_info_16 *values; + + values = A_SIZE_16(agp_bridge->aperture_sizes); + pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp); + temp &= 0xfff; + + for (i = 0; i < agp_bridge->num_aperture_sizes; i++) { + if (temp == values[i].size_value) { + agp_bridge->previous_size = + agp_bridge->current_size = (void *) (values + i); + agp_bridge->aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + + +static int via_configure_agp3(void) +{ + u32 temp; + struct aper_size_info_16 *current_size; + + current_size = A_SIZE_16(agp_bridge->current_size); + + /* address to map too */ + pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp); + agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase - aperture GATT base */ + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE, + agp_bridge->gatt_bus_addr & 0xfffff000); + return 0; +} + + +static void via_cleanup_agp3(void) +{ + struct aper_size_info_16 *previous_size; + + previous_size = A_SIZE_16(agp_bridge->previous_size); + pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value); +} + + +static void via_tlbflush_agp3(agp_memory * mem) +{ + u32 temp; + + pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7)); + pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp); +} + + +static struct aper_size_info_16 via_generic_agp3_sizes[11] = +{ + { 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 }, + { 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1}, + { 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2}, + { 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3}, + { 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4}, + { 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5}, + { 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8}, + { 512, 131072, 7, 1<<11|1<<10|1<<9}, + { 1024, 262144, 8, 1<<11|1<<10}, + { 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */ +}; + + +static int __init via_generic_agp3_setup (struct pci_dev *pdev) +{ + agp_bridge->dev = pdev; + agp_bridge->type = VIA_GENERIC; + agp_bridge->masks = via_generic_masks; + agp_bridge->aperture_sizes = (void *) via_generic_agp3_sizes; + agp_bridge->size_type = U16_APER_SIZE; + agp_bridge->num_aperture_sizes = 10; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->agp_enable = agp_generic_agp_3_0_enable; + agp_bridge->configure = via_configure_agp3; + agp_bridge->fetch_size = via_fetch_size_agp3; + agp_bridge->cleanup = via_cleanup_agp3; + agp_bridge->tlb_flush = via_tlbflush_agp3; + agp_bridge->mask_memory = via_mask_memory; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; + return 0; +} +#else +static int __init via_generic_agp3_setup (struct pci_dev *pdev) +{ + printk (KERN_INFO PFX "Bridge in AGP3 mode, but CONFIG_AGP3=n\n"); + return -ENODEV; +} +#endif /* CONFIG_AGP3 */ + + static int __init via_generic_setup (struct pci_dev *pdev) { - agp_bridge.masks = via_generic_masks; - agp_bridge.aperture_sizes = (void *) via_generic_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = via_configure; - agp_bridge.fetch_size = via_fetch_size; - agp_bridge.cleanup = via_cleanup; - agp_bridge.tlb_flush = via_tlbflush; - agp_bridge.mask_memory = via_mask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; +#ifdef CONFIG_AGP3 + /* Garg, there are KT400s with KT266 IDs. */ + if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) { + + /* Is there a KT400 subsystem ? */ + if (pdev->subsystem_device==PCI_DEVICE_ID_VIA_8377_0) { + u8 reg; + + printk (KERN_INFO PFX "Found KT400 in disguise as a KT266.\n"); + + /* Check AGP compatability mode. */ + pci_read_config_byte(pdev, VIA_AGPSEL, ®); + if ((reg & (1<<1))==0) + return via_generic_agp3_setup(pdev); + + /* Its in 2.0 mode, drop through. */ + } + } +#endif + + agp_bridge->masks = via_generic_masks; + agp_bridge->aperture_sizes = (void *) via_generic_sizes; + agp_bridge->size_type = U8_APER_SIZE; + agp_bridge->num_aperture_sizes = 7; + agp_bridge->dev_private_data = NULL; + agp_bridge->needs_scratch_page = FALSE; + agp_bridge->configure = via_configure; + agp_bridge->fetch_size = via_fetch_size; + agp_bridge->cleanup = via_cleanup; + agp_bridge->tlb_flush = via_tlbflush; + agp_bridge->mask_memory = via_mask_memory; + agp_bridge->agp_enable = agp_generic_agp_enable; + agp_bridge->cache_flush = global_cache_flush; + agp_bridge->create_gatt_table = agp_generic_create_gatt_table; + agp_bridge->free_gatt_table = agp_generic_free_gatt_table; + agp_bridge->insert_memory = agp_generic_insert_memory; + agp_bridge->remove_memory = agp_generic_remove_memory; + agp_bridge->alloc_by_type = agp_generic_alloc_by_type; + agp_bridge->free_by_type = agp_generic_free_by_type; + agp_bridge->agp_alloc_page = agp_generic_alloc_page; + agp_bridge->agp_destroy_page = agp_generic_destroy_page; + agp_bridge->suspend = agp_generic_suspend; + agp_bridge->resume = agp_generic_resume; + agp_bridge->cant_use_aperture = 0; return 0; } -/* - * The KT400 does magick to put the AGP bridge compliant with the same - * standards version as the graphics card. If we haven't fallen into - * 2.0 compatability mode, we abort, as this gets picked up by - * via-agp3.o - */ +/* The KT400 does magick to put the AGP bridge compliant with the same + * standards version as the graphics card. */ static int __init via_kt400_setup(struct pci_dev *pdev) { u8 reg; pci_read_config_byte(pdev, VIA_AGPSEL, ®); /* Check AGP 2.0 compatability mode. */ - if ((reg & (1<<1))==1) { - via_generic_setup(pdev); - return 0; - } - return -ENODEV; + if ((reg & (1<<1))==0) + return via_generic_agp3_setup(pdev); + return via_generic_setup(pdev); } + static struct agp_device_ids via_agp_device_ids[] __initdata = { { .device_id = PCI_DEVICE_ID_VIA_82C597_0, - .chipset = VIA_VP3, .chipset_name = "VP3", }, + { .device_id = PCI_DEVICE_ID_VIA_82C598_0, - .chipset = VIA_MVP3, .chipset_name = "MVP3", }, + { .device_id = PCI_DEVICE_ID_VIA_8501_0, - .chipset = VIA_MVP4, .chipset_name = "MVP4", }, + + /* VT8601 */ + { + .device_id = PCI_DEVICE_ID_VIA_8601_0, + .chipset_name = "PLE133 ProMedia", + }, + + /* VT82C693A / VT28C694T */ { .device_id = PCI_DEVICE_ID_VIA_82C691, - .chipset = VIA_APOLLO_PRO, - .chipset_name = "Apollo Pro", + .chipset_name = "Apollo Pro 133", }, + { .device_id = PCI_DEVICE_ID_VIA_8371_0, - .chipset = VIA_APOLLO_KX133, .chipset_name = "Apollo Pro KX133", }, + + /* VT8633 */ { .device_id = PCI_DEVICE_ID_VIA_8633_0, - .chipset = VIA_APOLLO_PRO_266, .chipset_name = "Apollo Pro 266", }, + + /* VT8361 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_8361, // 0x3112 + .chipset_name = "Apollo KLE133", + }, */ + + /* VT8365 / VT8362 */ { .device_id = PCI_DEVICE_ID_VIA_8363_0, - .chipset = VIA_APOLLO_KT133, - .chipset_name = "Apollo Pro KT133", + .chipset_name = "Apollo Pro KT133/KM133/TwisterK", }, + + /* VT8753A */ +/* { + .device_id = PCI_DEVICE_ID_VIA_8753_0, // 0x3128 + .chipset_name = "P4X266", + }, */ + + /* VT8366 */ { .device_id = PCI_DEVICE_ID_VIA_8367_0, - .chipset = VIA_APOLLO_KT133, - .chipset_name = "Apollo Pro KT266", + .chipset_name = "Apollo Pro KT266/KT333", }, + + /* VT8633 (for CuMine/ Celeron) */ { .device_id = PCI_DEVICE_ID_VIA_8653_0, - .chipset = VIA_APOLLO_PRO, .chipset_name = "Apollo Pro 266T", }, + + /* KM266 / PM266 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_KM266, // 0x3116 + .chipset_name = "KM266/PM266", + }, */ + + /* CLE266 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_CLE266, // 0x3123 + .chipset_name = "CLE266", + }, */ + { .device_id = PCI_DEVICE_ID_VIA_8377_0, - .chipset = VIA_APOLLO_KT400, .chipset_name = "Apollo Pro KT400", .chipset_setup = via_kt400_setup, }, + + /* VT8604 / VT8605 / VT8603 / TwisterT + * (Apollo Pro133A chipset with S3 Savage4) */ { - /* VIA ProSavage PM133 (Apollo Pro133A chipset with S3 Savage4) */ .device_id = PCI_DEVICE_ID_VIA_82C694X_0, - .chipset = VIA_VT8605, - .chipset_name = "Apollo ProSavage PM133" + .chipset_name = "Apollo ProSavage PM133/PL133/PN133/Twister" }, + + /* VT8752*/ +/* { + .device_id = PCI_DEVICE_ID_VIA_8752, // 0x3148 + .chipset_name = "ProSavage DDR P4M266", + }, */ + + /* KN266/PN266 */ +/* { + .device_id = PCI_DEVICE_ID_KN266, // 0x3156 + .chipset_name = "KN266/PN266", + }, */ + + /* VT8754 */ { .device_id = PCI_DEVICE_ID_VIA_8754, - .chipset = VIA_P4X, .chipset_name = "Apollo P4X333/P4X400" }, + + /* P4N333 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_P4N333, // 0x3178 + .chipset_name = "P4N333", + }, */ + + /* P4X600 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_P4X600, // 0x0198 + .chipset_name = "P4X600", + }, */ + + /* KM400 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_KM400, // 0x3205 + .chipset_name = "KM400", + }, */ + + /* P4M400 */ +/* { + .device_id = PCI_DEVICE_ID_VIA_P4M400, // 0x3209 + .chipset_name = "PM400", + }, */ + { }, /* dummy final entry, always present */ }; @@ -221,7 +430,7 @@ while (devs[j].chipset_name != NULL) { if (pdev->device == devs[j].device_id) { printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name); - agp_bridge.type = devs[j].chipset; + agp_bridge->type = VIA_GENERIC; if (devs[j].chipset_setup != NULL) return devs[j].chipset_setup(pdev); @@ -235,7 +444,7 @@ if (agp_try_unsupported) { printk(KERN_WARNING PFX "Trying generic VIA routines" " for device id: %04x\n", pdev->device); - agp_bridge.type = VIA_GENERIC; + agp_bridge->type = VIA_GENERIC; return via_generic_setup(pdev); } @@ -244,10 +453,12 @@ return -ENODEV; } + static struct agp_driver via_agp_driver = { .owner = THIS_MODULE, }; + static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent) { u8 cap_ptr = 0; @@ -258,10 +469,10 @@ /* probe for known chipsets */ if (agp_lookup_host_bridge (dev) != -ENODEV) { - agp_bridge.dev = dev; - agp_bridge.capndx = cap_ptr; + agp_bridge->dev = dev; + agp_bridge->capndx = cap_ptr; /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); + pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); via_agp_driver.dev = dev; agp_register_driver(&via_agp_driver); return 0; @@ -269,6 +480,7 @@ return -ENODEV; } + static struct pci_device_id agp_via_pci_table[] __initdata = { { .class = (PCI_CLASS_BRIDGE_HOST << 8), @@ -283,31 +495,36 @@ MODULE_DEVICE_TABLE(pci, agp_via_pci_table); + static struct __initdata pci_driver agp_via_pci_driver = { .name = "agpgart-via", .id_table = agp_via_pci_table, .probe = agp_via_probe, }; + static int __init agp_via_init(void) { int ret_val; ret_val = pci_module_init(&agp_via_pci_driver); if (ret_val) - agp_bridge.type = NOT_SUPPORTED; + agp_bridge->type = NOT_SUPPORTED; return ret_val; } + static void __exit agp_via_cleanup(void) { agp_unregister_driver(&via_agp_driver); pci_unregister_driver(&agp_via_pci_driver); } + module_init(agp_via_init); module_exit(agp_via_cleanup); MODULE_PARM(agp_try_unsupported, "1i"); MODULE_LICENSE("GPL and additional rights"); +MODULE_AUTHOR("Dave Jones "); diff -Nru a/drivers/char/agp/via-kt400.c b/drivers/char/agp/via-kt400.c --- a/drivers/char/agp/via-kt400.c Tue Feb 11 00:01:27 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,202 +0,0 @@ -/* - * VIA KT400 AGPGART routines. - * - * The KT400 does magick to put the AGP bridge compliant with the same - * standards version as the graphics card. If we haven't fallen into - * 2.0 compatability mode, we run this code. Otherwise, we run the - * code in via-agp.c - */ - -#include -#include -#include -#include -#include -#include "agp.h" - -static int via_fetch_size(void) -{ - int i; - u8 temp; - struct aper_size_info_16 *values; - - values = A_SIZE_16(agp_bridge.aperture_sizes); - pci_read_config_byte(agp_bridge.dev, VIA_AGP3_APSIZE, &temp); - for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { - if (temp == values[i].size_value) { - agp_bridge.previous_size = - agp_bridge.current_size = (void *) (values + i); - agp_bridge.aperture_size_idx = i; - return values[i].size; - } - } - return 0; -} - -static int via_configure(void) -{ - u32 temp; - struct aper_size_info_16 *current_size; - - current_size = A_SIZE_16(agp_bridge.current_size); - - /* address to map too */ - pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp); - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); - - /* attbase - aperture GATT base */ - pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE, - agp_bridge.gatt_bus_addr & 0xfffff000); - return 0; -} - -static void via_cleanup(void) -{ - struct aper_size_info_16 *previous_size; - - previous_size = A_SIZE_16(agp_bridge.previous_size); - pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, previous_size->size_value); -} - -static void via_tlbflush(agp_memory * mem) -{ - u32 temp; - - pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp); - pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7)); - pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp); -} - -static unsigned long via_mask_memory(unsigned long addr, int type) -{ - /* Memory type is ignored */ - - return addr | agp_bridge.masks[0].mask; -} - -static struct aper_size_info_16 via_generic_sizes[11] = -{ - { 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 }, - { 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1}, - { 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2}, - { 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3}, - { 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4}, - { 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5}, - { 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8}, - { 512, 131072, 7, 1<<11|1<<10|1<<9}, - { 1024, 262144, 8, 1<<11|1<<10}, - { 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */ -}; - -static struct gatt_mask via_generic_masks[] = -{ - {.mask = 0x00000000, .type = 0} -}; - - -static void __init via_kt400_enable(u32 mode) -{ - if ((agp_generic_agp_3_0_enable(mode))==FALSE) - printk (KERN_INFO PFX "agp_generic_agp_3_0_enable() failed\n"); -} - -static struct agp_driver via_kt400_agp_driver = { - .owner = THIS_MODULE, -}; - -static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent) -{ - u8 reg; - u8 cap_ptr = 0; - - cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP); - if (cap_ptr == 0) - return -ENODEV; - - pci_read_config_byte(dev, VIA_AGPSEL, ®); - /* Check if we are in AGP 2.0 compatability mode, if so it - * will be picked up by via-agp.o */ - if ((reg & (1<<1))==1) - return -ENODEV; - - printk (KERN_INFO PFX "Detected VIA KT400 AGP3 chipset\n"); - - agp_bridge.dev = dev; - agp_bridge.type = VIA_APOLLO_KT400_3; - agp_bridge.capndx = cap_ptr; - agp_bridge.masks = via_generic_masks; - agp_bridge.aperture_sizes = (void *) via_generic_sizes; - agp_bridge.size_type = U8_APER_SIZE; - agp_bridge.num_aperture_sizes = 7; - agp_bridge.dev_private_data = NULL; - agp_bridge.needs_scratch_page = FALSE; - agp_bridge.agp_enable = via_kt400_enable; - agp_bridge.configure = via_configure; - agp_bridge.fetch_size = via_fetch_size; - agp_bridge.cleanup = via_cleanup; - agp_bridge.tlb_flush = via_tlbflush; - agp_bridge.mask_memory = via_mask_memory; - agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = agp_generic_create_gatt_table; - agp_bridge.free_gatt_table = agp_generic_free_gatt_table; - agp_bridge.insert_memory = agp_generic_insert_memory; - agp_bridge.remove_memory = agp_generic_remove_memory; - agp_bridge.alloc_by_type = agp_generic_alloc_by_type; - agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = agp_generic_alloc_page; - agp_bridge.agp_destroy_page = agp_generic_destroy_page; - agp_bridge.suspend = agp_generic_suspend; - agp_bridge.resume = agp_generic_resume; - agp_bridge.cant_use_aperture = 0; - - /* Fill in the mode register */ - pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode); - - via_kt400_agp_driver.dev = dev; - agp_register_driver(&via_kt400_agp_driver); - return 0; -} - -static struct pci_device_id agp_via_pci_table[] __initdata = { - { - .class = (PCI_CLASS_BRIDGE_HOST << 8), - .class_mask = ~0, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8377_0, - .subvendor = PCI_ANY_ID, - .subdevice = PCI_ANY_ID, - }, - { } -}; - -MODULE_DEVICE_TABLE(pci, agp_via_pci_table); - -static struct __initdata pci_driver agp_via_pci_driver = { - .name = "agpgart-via", - .id_table = agp_via_pci_table, - .probe = agp_via_probe, -}; - -static int __init agp_via_init(void) -{ - int ret_val; - - ret_val = pci_module_init(&agp_via_pci_driver); - if (ret_val) - agp_bridge.type = NOT_SUPPORTED; - - return ret_val; -} - -static void __exit agp_via_cleanup(void) -{ - agp_unregister_driver(&via_kt400_agp_driver); - pci_unregister_driver(&agp_via_pci_driver); -} - -module_init(agp_via_init); -module_exit(agp_via_cleanup); - -MODULE_AUTHOR("Dave Jones "); -MODULE_LICENSE("GPL and additional rights"); - diff -Nru a/drivers/char/rio/rioroute.c b/drivers/char/rio/rioroute.c --- a/drivers/char/rio/rioroute.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/rio/rioroute.c Tue Feb 11 00:01:27 2003 @@ -763,7 +763,7 @@ #endif UnitId--; /* this trick relies on the Unit Id being UNSIGNED! */ - if ( UnitId > MAX_RUP ) /* dontcha just lurv unsigned maths! */ + if ( UnitId >= MAX_RUP ) /* dontcha just lurv unsigned maths! */ return(0); if ( HostP->Mapping[UnitId].Flags & BEEN_HERE ) diff -Nru a/drivers/char/specialix.c b/drivers/char/specialix.c --- a/drivers/char/specialix.c Tue Feb 11 00:01:27 2003 +++ b/drivers/char/specialix.c Tue Feb 11 00:01:27 2003 @@ -1456,7 +1456,7 @@ board = SX_BOARD(minor(tty->device)); - if (board > SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT)) + if (board >= SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT)) return -ENODEV; bp = &sx_board[board]; @@ -2363,7 +2363,7 @@ struct pci_dev *pdev = NULL; i=0; - while (i <= SX_NBOARD) { + while (i < SX_NBOARD) { if (sx_board[i].flags & SX_BOARD_PRESENT) { i++; continue; diff -Nru a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c --- a/drivers/ide/pci/amd74xx.c Tue Feb 11 00:01:27 2003 +++ b/drivers/ide/pci/amd74xx.c Tue Feb 11 00:01:27 2003 @@ -60,7 +60,7 @@ { PCI_DEVICE_ID_AMD_OPUS_7441, 0x00, 0x40, AMD_UDMA_100 }, /* AMD-768 Opus */ { PCI_DEVICE_ID_AMD_8111_IDE, 0x00, 0x40, AMD_UDMA_100 }, /* AMD-8111 */ { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x00, 0x50, AMD_UDMA_100 }, /* nVidia nForce */ - + { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x00, 0x50, AMD_UDMA_100 }, /* nVidia nForce 2 */ { 0 } }; @@ -446,6 +446,7 @@ { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, { 0, }, }; diff -Nru a/drivers/ide/pci/amd74xx.h b/drivers/ide/pci/amd74xx.h --- a/drivers/ide/pci/amd74xx.h Tue Feb 11 00:01:27 2003 +++ b/drivers/ide/pci/amd74xx.h Tue Feb 11 00:01:27 2003 @@ -110,6 +110,20 @@ .bootable = ON_BOARD, .extra = 0, }, + { /* 6 */ + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, + .name = "NFORCE2", + .init_chipset = init_chipset_amd74xx, + .init_iops = NULL, + .init_hwif = init_hwif_amd74xx, + .init_dma = init_dma_amd74xx, + .channels = 2, + .autodma = AUTODMA, + .enablebits = {{0x50,0x01,0x01}, {0x50,0x02,0x02}}, + .bootable = ON_BOARD, + .extra = 0, + }, { .vendor = 0, .device = 0, diff -Nru a/drivers/net/3c509.c b/drivers/net/3c509.c --- a/drivers/net/3c509.c Tue Feb 11 00:01:27 2003 +++ b/drivers/net/3c509.c Tue Feb 11 00:01:27 2003 @@ -338,16 +338,6 @@ dev->watchdog_timeo = TX_TIMEOUT; dev->do_ioctl = netdev_ioctl; -#ifdef CONFIG_PM - /* register power management */ - lp->pmdev = pm_register(PM_ISA_DEV, card_idx, el3_pm_callback); - if (lp->pmdev) { - struct pm_dev *p; - p = lp->pmdev; - p->data = (struct net_device *)dev; - } -#endif - return 0; } @@ -417,6 +407,13 @@ phys_addr[j] = htons(read_eeprom(ioaddr, j)); if_port = read_eeprom(ioaddr, 8) >> 14; + if (!(dev = init_etherdev(NULL, sizeof(struct el3_private)))) { + release_region(ioaddr, EL3_IO_EXTENT); + pnp_device_detach(idev); + return -ENOMEM; + } + + SET_MODULE_OWNER(dev); pnp_cards++; goto found; } @@ -497,24 +494,29 @@ } irq = id_read_eeprom(9) >> 12; -#if 0 /* Huh ? - Can someone explain what is this for ? */ - if (dev) { /* Set passed-in IRQ or I/O Addr. */ - if (dev->irq > 1 && dev->irq < 16) + if (!(dev = init_etherdev(NULL, sizeof(struct el3_private)))) + return -ENOMEM; + + SET_MODULE_OWNER(dev); + + /* Set passed-in IRQ or I/O Addr. */ + if (dev->irq > 1 && dev->irq < 16) irq = dev->irq; - if (dev->base_addr) { + if (dev->base_addr) { if (dev->mem_end == 0x3c509 /* Magic key */ && dev->base_addr >= 0x200 && dev->base_addr <= 0x3e0) - ioaddr = dev->base_addr & 0x3f0; - else if (dev->base_addr != ioaddr) - return -ENODEV; - } + ioaddr = dev->base_addr & 0x3f0; + else if (dev->base_addr != ioaddr) { + unregister_netdev (dev); + return -ENODEV; + } } -#endif - if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509")) - return -EBUSY; + if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509")) { + unregister_netdev (dev); + return -EBUSY; + } /* Set the adaptor tag so that the next card can be found. */ outb(0xd0 + ++current_tag, id_port); @@ -524,6 +526,7 @@ EL3WINDOW(0); if (inw(ioaddr) != 0x6d50) { + unregister_netdev (dev); release_region(ioaddr, EL3_IO_EXTENT); return -ENODEV; } @@ -531,12 +534,9 @@ /* Free the interrupt so that some other card can use it. */ outw(0x0f00, ioaddr + WN0_IRQ); - dev = init_etherdev(NULL, sizeof(struct el3_private)); - if (dev == NULL) { - release_region(ioaddr, EL3_IO_EXTENT); - return -ENOMEM; - } - SET_MODULE_OWNER(dev); +#ifdef __ISAPNP__ + found: /* PNP jumps here... */ +#endif /* __ISAPNP__ */ memcpy(dev->dev_addr, phys_addr, sizeof(phys_addr)); dev->base_addr = ioaddr; @@ -547,6 +547,16 @@ lp->dev = &idev->dev; #endif +#ifdef CONFIG_PM + /* register power management */ + lp->pmdev = pm_register(PM_ISA_DEV, card_idx, el3_pm_callback); + if (lp->pmdev) { + struct pm_dev *p; + p = lp->pmdev; + p->data = (struct net_device *)dev; + } +#endif + return el3_common_init (dev); } @@ -667,6 +677,7 @@ } #endif +#if defined(CONFIG_EISA) || defined(CONFIG_MCA) /* This remove works for all device types. * * The net dev must be stored in the driver_data field */ @@ -679,6 +690,7 @@ el3_common_remove (dev); return 0; } +#endif /* Read a word from the EEPROM using the regular EEPROM access register. Assume that we are in register window zero. diff -Nru a/drivers/net/3c59x.c b/drivers/net/3c59x.c --- a/drivers/net/3c59x.c Tue Feb 11 00:01:26 2003 +++ b/drivers/net/3c59x.c Tue Feb 11 00:01:26 2003 @@ -181,7 +181,7 @@ - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details. - Also see Documentation/networking/vortex.txt - LK1.1.19 10Nov09 Marc Zyngier + LK1.1.19 10Nov02 Marc Zyngier - EISA sysfs integration. */ @@ -817,7 +817,11 @@ u32 power_state[16]; }; +#ifdef CONFIG_PCI #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL) +#else +#define DEVICE_PCI(dev) NULL +#endif #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL) diff -Nru a/drivers/net/Space.c b/drivers/net/Space.c --- a/drivers/net/Space.c Tue Feb 11 00:01:27 2003 +++ b/drivers/net/Space.c Tue Feb 11 00:01:27 2003 @@ -224,9 +224,6 @@ #ifdef CONFIG_EL2 /* 3c503 */ {el2_probe, 0}, #endif -#ifdef CONFIG_EL3 - {el3_probe, 0}, -#endif #ifdef CONFIG_HPLAN {hp_probe, 0}, #endif diff -Nru a/drivers/net/tulip/de4x5.c b/drivers/net/tulip/de4x5.c --- a/drivers/net/tulip/de4x5.c Tue Feb 11 00:01:27 2003 +++ b/drivers/net/tulip/de4x5.c Tue Feb 11 00:01:27 2003 @@ -440,8 +440,6 @@ ========================================================================= */ -static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n"; - #include #include #include @@ -476,6 +474,8 @@ #endif /* CONFIG_PPC */ #include "de4x5.h" + +static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n"; #define c_char const char #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a))) diff -Nru a/fs/buffer.c b/fs/buffer.c --- a/fs/buffer.c Tue Feb 11 00:01:27 2003 +++ b/fs/buffer.c Tue Feb 11 00:01:27 2003 @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -2619,6 +2618,24 @@ } /* + * For a data-integrity writeout, we need to wait upon any in-progress I/O + * and then start new I/O and then wait upon it. + */ +void sync_dirty_buffer(struct buffer_head *bh) +{ + WARN_ON(atomic_read(&bh->b_count) < 1); + lock_buffer(bh); + if (test_clear_buffer_dirty(bh)) { + get_bh(bh); + bh->b_end_io = end_buffer_io_sync; + submit_bh(WRITE, bh); + wait_on_buffer(bh); + } else { + unlock_buffer(bh); + } +} + +/* * Sanity checks for try_to_free_buffers. */ static void check_ttfb_buffer(struct page *page, struct buffer_head *bh) @@ -2773,7 +2790,6 @@ * Buffer-head allocation */ static kmem_cache_t *bh_cachep; -static mempool_t *bh_mempool; /* * Once the number of bh's in the machine exceeds this level, we start @@ -2807,7 +2823,7 @@ struct buffer_head *alloc_buffer_head(void) { - struct buffer_head *ret = mempool_alloc(bh_mempool, GFP_NOFS); + struct buffer_head *ret = kmem_cache_alloc(bh_cachep, GFP_NOFS); if (ret) { preempt_disable(); __get_cpu_var(bh_accounting).nr++; @@ -2821,7 +2837,7 @@ void free_buffer_head(struct buffer_head *bh) { BUG_ON(!list_empty(&bh->b_assoc_buffers)); - mempool_free(bh, bh_mempool); + kmem_cache_free(bh_cachep, bh); preempt_disable(); __get_cpu_var(bh_accounting).nr--; recalc_bh_state(); @@ -2829,7 +2845,8 @@ } EXPORT_SYMBOL(free_buffer_head); -static void init_buffer_head(void *data, kmem_cache_t *cachep, unsigned long flags) +static void +init_buffer_head(void *data, kmem_cache_t *cachep, unsigned long flags) { if ((flags & (SLAB_CTOR_VERIFY|SLAB_CTOR_CONSTRUCTOR)) == SLAB_CTOR_CONSTRUCTOR) { @@ -2840,19 +2857,6 @@ } } -static void *bh_mempool_alloc(int gfp_mask, void *pool_data) -{ - return kmem_cache_alloc(bh_cachep, gfp_mask); -} - -static void bh_mempool_free(void *element, void *pool_data) -{ - return kmem_cache_free(bh_cachep, element); -} - -#define NR_RESERVED (10*MAX_BUF_PER_PAGE) -#define MAX_UNUSED_BUFFERS NR_RESERVED+20 - static void buffer_init_cpu(int cpu) { struct bh_accounting *bha = &per_cpu(bh_accounting, cpu); @@ -2889,8 +2893,6 @@ bh_cachep = kmem_cache_create("buffer_head", sizeof(struct buffer_head), 0, 0, init_buffer_head, NULL); - bh_mempool = mempool_create(MAX_UNUSED_BUFFERS, bh_mempool_alloc, - bh_mempool_free, NULL); for (i = 0; i < ARRAY_SIZE(bh_wait_queue_heads); i++) init_waitqueue_head(&bh_wait_queue_heads[i].wqh); diff -Nru a/fs/ext2/balloc.c b/fs/ext2/balloc.c --- a/fs/ext2/balloc.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext2/balloc.c Tue Feb 11 00:01:27 2003 @@ -233,10 +233,8 @@ } mark_buffer_dirty(bitmap_bh); - if (sb->s_flags & MS_SYNCHRONOUS) { - ll_rw_block(WRITE, 1, &bitmap_bh); - wait_on_buffer(bitmap_bh); - } + if (sb->s_flags & MS_SYNCHRONOUS) + sync_dirty_buffer(bitmap_bh); group_release_blocks(desc, bh2, group_freed); freed += group_freed; @@ -466,10 +464,8 @@ write_unlock(&EXT2_I(inode)->i_meta_lock); mark_buffer_dirty(bitmap_bh); - if (sb->s_flags & MS_SYNCHRONOUS) { - ll_rw_block(WRITE, 1, &bitmap_bh); - wait_on_buffer(bitmap_bh); - } + if (sb->s_flags & MS_SYNCHRONOUS) + sync_dirty_buffer(bitmap_bh); ext2_debug ("allocating block %d. ", block); diff -Nru a/fs/ext2/ialloc.c b/fs/ext2/ialloc.c --- a/fs/ext2/ialloc.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext2/ialloc.c Tue Feb 11 00:01:27 2003 @@ -146,10 +146,8 @@ mark_buffer_dirty(EXT2_SB(sb)->s_sbh); } mark_buffer_dirty(bitmap_bh); - if (sb->s_flags & MS_SYNCHRONOUS) { - ll_rw_block(WRITE, 1, &bitmap_bh); - wait_on_buffer(bitmap_bh); - } + if (sb->s_flags & MS_SYNCHRONOUS) + sync_dirty_buffer(bitmap_bh); sb->s_dirt = 1; error_return: brelse(bitmap_bh); @@ -485,10 +483,8 @@ ext2_set_bit(i, bitmap_bh->b_data); mark_buffer_dirty(bitmap_bh); - if (sb->s_flags & MS_SYNCHRONOUS) { - ll_rw_block(WRITE, 1, &bitmap_bh); - wait_on_buffer(bitmap_bh); - } + if (sb->s_flags & MS_SYNCHRONOUS) + sync_dirty_buffer(bitmap_bh); brelse(bitmap_bh); ino = group * EXT2_INODES_PER_GROUP(sb) + i + 1; diff -Nru a/fs/ext2/inode.c b/fs/ext2/inode.c --- a/fs/ext2/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext2/inode.c Tue Feb 11 00:01:27 2003 @@ -443,10 +443,8 @@ * But we now rely upon generic_osync_inode() * and b_inode_buffers. But not for directories. */ - if (S_ISDIR(inode->i_mode) && IS_DIRSYNC(inode)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); - } + if (S_ISDIR(inode->i_mode) && IS_DIRSYNC(inode)) + sync_dirty_buffer(bh); parent = nr; } if (n == num) @@ -1208,8 +1206,7 @@ raw_inode->i_block[n] = ei->i_data[n]; mark_buffer_dirty(bh); if (do_sync) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); + sync_dirty_buffer(bh); if (buffer_req(bh) && !buffer_uptodate(bh)) { printk ("IO error syncing ext2 inode [%s:%08lx]\n", sb->s_id, (unsigned long) ino); diff -Nru a/fs/ext2/super.c b/fs/ext2/super.c --- a/fs/ext2/super.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext2/super.c Tue Feb 11 00:01:27 2003 @@ -842,8 +842,7 @@ { es->s_wtime = cpu_to_le32(get_seconds()); mark_buffer_dirty(EXT2_SB(sb)->s_sbh); - ll_rw_block(WRITE, 1, &EXT2_SB(sb)->s_sbh); - wait_on_buffer(EXT2_SB(sb)->s_sbh); + sync_dirty_buffer(EXT2_SB(sb)->s_sbh); sb->s_dirt = 0; } diff -Nru a/fs/ext2/xattr.c b/fs/ext2/xattr.c --- a/fs/ext2/xattr.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext2/xattr.c Tue Feb 11 00:01:27 2003 @@ -774,8 +774,7 @@ } mark_buffer_dirty(new_bh); if (IS_SYNC(inode)) { - ll_rw_block(WRITE, 1, &new_bh); - wait_on_buffer(new_bh); + sync_dirty_buffer(new_bh); error = -EIO; if (buffer_req(new_bh) && !buffer_uptodate(new_bh)) goto cleanup; @@ -865,10 +864,8 @@ HDR(bh)->h_refcount = cpu_to_le32( le32_to_cpu(HDR(bh)->h_refcount) - 1); mark_buffer_dirty(bh); - if (IS_SYNC(inode)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); - } + if (IS_SYNC(inode)) + sync_dirty_buffer(bh); DQUOT_FREE_BLOCK(inode, 1); } EXT2_I(inode)->i_file_acl = 0; diff -Nru a/fs/ext3/inode.c b/fs/ext3/inode.c --- a/fs/ext3/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext3/inode.c Tue Feb 11 00:01:27 2003 @@ -1317,10 +1317,7 @@ goto out_fail; needed = ext3_writepage_trans_blocks(inode); - if (wbc->for_reclaim) - handle = ext3_journal_try_start(inode, needed); - else - handle = ext3_journal_start(inode, needed); + handle = ext3_journal_start(inode, needed); if (IS_ERR(handle)) { ret = PTR_ERR(handle); diff -Nru a/fs/ext3/super.c b/fs/ext3/super.c --- a/fs/ext3/super.c Tue Feb 11 00:01:27 2003 +++ b/fs/ext3/super.c Tue Feb 11 00:01:27 2003 @@ -1343,9 +1343,7 @@ * superblock lock. */ EXT3_SB(sb)->s_mount_state |= EXT3_ORPHAN_FS; - unlock_super(sb); /* akpm: sigh */ ext3_orphan_cleanup(sb, es); - lock_super(sb); EXT3_SB(sb)->s_mount_state &= ~EXT3_ORPHAN_FS; if (needs_recovery) printk (KERN_INFO "EXT3-fs: recovery complete.\n"); @@ -1627,10 +1625,8 @@ es->s_wtime = cpu_to_le32(get_seconds()); BUFFER_TRACE(EXT3_SB(sb)->s_sbh, "marking dirty"); mark_buffer_dirty(EXT3_SB(sb)->s_sbh); - if (sync) { - ll_rw_block(WRITE, 1, &EXT3_SB(sb)->s_sbh); - wait_on_buffer(EXT3_SB(sb)->s_sbh); - } + if (sync) + sync_dirty_buffer(EXT3_SB(sb)->s_sbh); } diff -Nru a/fs/jbd/commit.c b/fs/jbd/commit.c --- a/fs/jbd/commit.c Tue Feb 11 00:01:27 2003 +++ b/fs/jbd/commit.c Tue Feb 11 00:01:27 2003 @@ -562,8 +562,7 @@ { struct buffer_head *bh = jh2bh(descriptor); set_buffer_uptodate(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); __brelse(bh); /* One for getblk() */ journal_unlock_journal_head(descriptor); } diff -Nru a/fs/jbd/journal.c b/fs/jbd/journal.c --- a/fs/jbd/journal.c Tue Feb 11 00:01:27 2003 +++ b/fs/jbd/journal.c Tue Feb 11 00:01:27 2003 @@ -38,7 +38,6 @@ #include EXPORT_SYMBOL(journal_start); -EXPORT_SYMBOL(journal_try_start); EXPORT_SYMBOL(journal_restart); EXPORT_SYMBOL(journal_extend); EXPORT_SYMBOL(journal_stop); @@ -960,9 +959,10 @@ BUFFER_TRACE(bh, "marking dirty"); mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); if (wait) - wait_on_buffer(bh); + sync_dirty_buffer(bh); + else + ll_rw_block(WRITE, 1, &bh); /* If we have just flushed the log (by marking s_start==0), then * any future commit will have to be careful to update the @@ -1296,8 +1296,7 @@ bh = journal->j_sb_buffer; BUFFER_TRACE(bh, "marking dirty"); mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); return 0; } diff -Nru a/fs/jbd/recovery.c b/fs/jbd/recovery.c --- a/fs/jbd/recovery.c Tue Feb 11 00:01:27 2003 +++ b/fs/jbd/recovery.c Tue Feb 11 00:01:27 2003 @@ -212,16 +212,14 @@ * * The primary function for recovering the log contents when mounting a * journaled device. - */ -int journal_recover(journal_t *journal) -{ -/* + * * Recovery is done in three passes. In the first pass, we look for the * end of the log. In the second, we assemble the list of revoke * blocks. In the third and final pass, we replay any un-revoked blocks * in the log. */ - +int journal_recover(journal_t *journal) +{ int err; journal_superblock_t * sb; @@ -273,15 +271,13 @@ * journal structures in memory to ignore it (presumably because the * caller has evidence that it is out of date). * This function does'nt appear to be exorted.. - */ -int journal_skip_recovery(journal_t *journal) -{ -/* + * * We perform one pass over the journal to allow us to tell the user how * much recovery information is being erased, and to let us initialise * the journal transaction sequence numbers to the next unused ID. */ - +int journal_skip_recovery(journal_t *journal) +{ int err; journal_superblock_t * sb; diff -Nru a/fs/jbd/transaction.c b/fs/jbd/transaction.c --- a/fs/jbd/transaction.c Tue Feb 11 00:01:27 2003 +++ b/fs/jbd/transaction.c Tue Feb 11 00:01:27 2003 @@ -266,113 +266,6 @@ return handle; } -/* - * Return zero on success - */ -static int try_start_this_handle(journal_t *journal, handle_t *handle) -{ - transaction_t *transaction; - int needed; - int nblocks = handle->h_buffer_credits; - int ret = 0; - - jbd_debug(3, "New handle %p maybe going live.\n", handle); - - lock_journal(journal); - - if (is_journal_aborted(journal) || - (journal->j_errno != 0 && !(journal->j_flags & JFS_ACK_ERR))) { - ret = -EROFS; - goto fail_unlock; - } - - if (journal->j_barrier_count) - goto fail_unlock; - - if (!journal->j_running_transaction && get_transaction(journal, 1) == 0) - goto fail_unlock; - - transaction = journal->j_running_transaction; - if (transaction->t_state == T_LOCKED) - goto fail_unlock; - - needed = transaction->t_outstanding_credits + nblocks; - /* We could run log_start_commit here */ - if (needed > journal->j_max_transaction_buffers) - goto fail_unlock; - - needed = journal->j_max_transaction_buffers; - if (journal->j_committing_transaction) - needed += journal->j_committing_transaction-> - t_outstanding_credits; - - if (log_space_left(journal) < needed) - goto fail_unlock; - - handle->h_transaction = transaction; - transaction->t_outstanding_credits += nblocks; - transaction->t_updates++; - jbd_debug(4, "Handle %p given %d credits (total %d, free %d)\n", - handle, nblocks, transaction->t_outstanding_credits, - log_space_left(journal)); - unlock_journal(journal); - return 0; - -fail_unlock: - unlock_journal(journal); - if (ret >= 0) - ret = -1; - return ret; -} - -/** - * handle_t *journal_try_start() - Don't block, but try and get a handle - * @journal: Journal to start transaction on. - * @nblocks: number of block buffer we might modify - * - * Try to start a handle, but non-blockingly. If we weren't able - * to, return an ERR_PTR value. - */ -handle_t *journal_try_start(journal_t *journal, int nblocks) -{ - handle_t *handle = journal_current_handle(); - int err; - - if (!journal) - return ERR_PTR(-EROFS); - - if (handle) { - jbd_debug(4, "h_ref %d -> %d\n", - handle->h_ref, - handle->h_ref + 1); - J_ASSERT(handle->h_transaction->t_journal == journal); - if (is_handle_aborted(handle)) - return ERR_PTR(-EIO); - handle->h_ref++; - return handle; - } else { - jbd_debug(4, "no current transaction\n"); - } - - if (is_journal_aborted(journal)) - return ERR_PTR(-EIO); - - handle = new_handle(nblocks); - if (!handle) - return ERR_PTR(-ENOMEM); - - current->journal_info = handle; - - err = try_start_this_handle(journal, handle); - if (err < 0) { - kfree(handle); - current->journal_info = NULL; - return ERR_PTR(err); - } - - return handle; -} - /** * int journal_extend() - extend buffer credits. * @handle: handle to 'extend' @@ -969,22 +862,23 @@ } /** - * int journal_dirty_data() - mark a buffer as containing dirty data which needs to be flushed before we can commit the current transaction. + * int journal_dirty_data() - mark a buffer as containing dirty data which + * needs to be flushed before we can commit the + * current transaction. * @handle: transaction * @bh: bufferhead to mark * * The buffer is placed on the transaction's data list and is marked as * belonging to the transaction. * - * Returns error number or 0 on success. - */ -int journal_dirty_data (handle_t *handle, struct buffer_head *bh) -{ -/* + * Returns error number or 0 on success. + * * journal_dirty_data() can be called via page_launder->ext3_writepage * by kswapd. So it cannot block. Happily, there's nothing here * which needs lock_journal if `async' is set. */ +int journal_dirty_data (handle_t *handle, struct buffer_head *bh) +{ journal_t *journal = handle->h_transaction->t_journal; int need_brelse = 0; struct journal_head *jh; @@ -1079,8 +973,7 @@ atomic_inc(&bh->b_count); spin_unlock(&journal_datalist_lock); need_brelse = 1; - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); spin_lock(&journal_datalist_lock); /* The buffer may become locked again at any time if it is redirtied */ @@ -1130,23 +1023,22 @@ * @handle: transaction to add buffer to. * @bh: buffer to mark * - * mark dirty metadata which needs to be journaled as part of the current transaction. + * mark dirty metadata which needs to be journaled as part of the current + * transaction. * * The buffer is placed on the transaction's metadata list and is marked * as belonging to the transaction. * * Returns error number or 0 on success. - */ -int journal_dirty_metadata (handle_t *handle, struct buffer_head *bh) -{ -/* + * * Special care needs to be taken if the buffer already belongs to the * current committing transaction (in which case we should have frozen * data present for that commit). In that case, we don't relink the * buffer: that only gets done when the old transaction finally * completes its commit. - * */ +int journal_dirty_metadata (handle_t *handle, struct buffer_head *bh) +{ transaction_t *transaction = handle->h_transaction; journal_t *journal = transaction->t_journal; struct journal_head *jh = bh2jh(bh); @@ -1361,8 +1253,7 @@ } atomic_inc(&bh->b_count); spin_unlock(&journal_datalist_lock); - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); __brelse(bh); goto out; } @@ -1728,13 +1619,6 @@ * to be called. We do this if the page is releasable by try_to_free_buffers(). * We also do it if the page has locked or dirty buffers and the caller wants * us to perform sync or async writeout. - */ -int journal_try_to_free_buffers(journal_t *journal, - struct page *page, int unused_gfp_mask) -{ -/* - * journal_try_to_free_buffers(). Try to remove all this page's buffers - * from the journal. * * This complicates JBD locking somewhat. We aren't protected by the * BKL here. We wish to remove the buffer from its committing or @@ -1754,6 +1638,9 @@ * cannot happen because we never reallocate freed data as metadata * while the data is part of a transaction. Yes? */ +int journal_try_to_free_buffers(journal_t *journal, + struct page *page, int unused_gfp_mask) +{ struct buffer_head *head; struct buffer_head *bh; int ret = 0; diff -Nru a/fs/jfs/jfs_imap.c b/fs/jfs/jfs_imap.c --- a/fs/jfs/jfs_imap.c Tue Feb 11 00:01:27 2003 +++ b/fs/jfs/jfs_imap.c Tue Feb 11 00:01:27 2003 @@ -2980,8 +2980,7 @@ j_sb->s_flag |= JFS_BAD_SAIT; mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); brelse(bh); return; } diff -Nru a/fs/jfs/jfs_mount.c b/fs/jfs/jfs_mount.c --- a/fs/jfs/jfs_mount.c Tue Feb 11 00:01:27 2003 +++ b/fs/jfs/jfs_mount.c Tue Feb 11 00:01:27 2003 @@ -449,8 +449,7 @@ } mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); brelse(bh); return 0; diff -Nru a/fs/jfs/namei.c b/fs/jfs/namei.c --- a/fs/jfs/namei.c Tue Feb 11 00:01:27 2003 +++ b/fs/jfs/namei.c Tue Feb 11 00:01:27 2003 @@ -972,10 +972,8 @@ #if 0 set_buffer_uptodate(bp); mark_buffer_dirty(bp, 1); - if (IS_SYNC(dip)) { - ll_rw_block(WRITE, 1, &bp); - wait_on_buffer(bp); - } + if (IS_SYNC(dip)) + sync_dirty_buffer(bp); brelse(bp); #endif /* 0 */ ssize -= copy_size; diff -Nru a/fs/jfs/resize.c b/fs/jfs/resize.c --- a/fs/jfs/resize.c Tue Feb 11 00:01:27 2003 +++ b/fs/jfs/resize.c Tue Feb 11 00:01:27 2003 @@ -243,8 +243,7 @@ /* synchronously update superblock */ mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); brelse(bh); /* @@ -512,15 +511,13 @@ memcpy(j_sb2, j_sb, sizeof (struct jfs_superblock)); mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh2); - wait_on_buffer(bh2); + sync_dirty_buffer(bh2); brelse(bh2); } /* write primary superblock */ mark_buffer_dirty(bh); - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); brelse(bh); goto resume; diff -Nru a/fs/minix/inode.c b/fs/minix/inode.c --- a/fs/minix/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/minix/inode.c Tue Feb 11 00:01:27 2003 @@ -517,8 +517,7 @@ bh = minix_update_inode(inode); if (bh && buffer_dirty(bh)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); if (buffer_req(bh) && !buffer_uptodate(bh)) { printk ("IO error syncing minix inode [%s:%08lx]\n", diff -Nru a/fs/ncpfs/sock.c b/fs/ncpfs/sock.c --- a/fs/ncpfs/sock.c Tue Feb 11 00:01:27 2003 +++ b/fs/ncpfs/sock.c Tue Feb 11 00:01:27 2003 @@ -757,9 +757,9 @@ What if we've blocked it ourselves? What about alarms? Why, in fact, are we mucking with the sigmask at all? -- r~ */ - if (current->sig->action[SIGINT - 1].sa.sa_handler == SIG_DFL) + if (current->sighand->action[SIGINT - 1].sa.sa_handler == SIG_DFL) mask |= sigmask(SIGINT); - if (current->sig->action[SIGQUIT - 1].sa.sa_handler == SIG_DFL) + if (current->sighand->action[SIGQUIT - 1].sa.sa_handler == SIG_DFL) mask |= sigmask(SIGQUIT); } siginitsetinv(¤t->blocked, mask); diff -Nru a/fs/ntfs/super.c b/fs/ntfs/super.c --- a/fs/ntfs/super.c Tue Feb 11 00:01:27 2003 +++ b/fs/ntfs/super.c Tue Feb 11 00:01:27 2003 @@ -505,8 +505,7 @@ memcpy(bh_primary->b_data, bh_backup->b_data, sb->s_blocksize); mark_buffer_dirty(bh_primary); - ll_rw_block(WRITE, 1, &bh_primary); - wait_on_buffer(bh_primary); + sync_dirty_buffer(bh_primary); if (buffer_uptodate(bh_primary)) { brelse(bh_backup); return bh_primary; diff -Nru a/fs/qnx4/inode.c b/fs/qnx4/inode.c --- a/fs/qnx4/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/qnx4/inode.c Tue Feb 11 00:01:27 2003 @@ -44,8 +44,7 @@ bh = qnx4_update_inode(inode); if (bh && buffer_dirty(bh)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); if (buffer_req(bh) && !buffer_uptodate(bh)) { printk ("IO error syncing qnx4 inode [%s:%08lx]\n", diff -Nru a/fs/reiserfs/journal.c b/fs/reiserfs/journal.c --- a/fs/reiserfs/journal.c Tue Feb 11 00:01:27 2003 +++ b/fs/reiserfs/journal.c Tue Feb 11 00:01:27 2003 @@ -735,8 +735,7 @@ } mark_buffer_dirty(jl->j_commit_bh) ; - ll_rw_block(WRITE, 1, &(jl->j_commit_bh)) ; - wait_on_buffer(jl->j_commit_bh) ; + sync_dirty_buffer(jl->j_commit_bh) ; if (!buffer_uptodate(jl->j_commit_bh)) { reiserfs_panic(s, "journal-615: buffer write failed\n") ; } @@ -828,8 +827,7 @@ jh->j_first_unflushed_offset = cpu_to_le32(offset) ; jh->j_mount_id = cpu_to_le32(SB_JOURNAL(p_s_sb)->j_mount_id) ; set_buffer_dirty(SB_JOURNAL(p_s_sb)->j_header_bh) ; - ll_rw_block(WRITE, 1, &(SB_JOURNAL(p_s_sb)->j_header_bh)) ; - wait_on_buffer((SB_JOURNAL(p_s_sb)->j_header_bh)) ; + sync_dirty_buffer(SB_JOURNAL(p_s_sb)->j_header_bh) ; if (!buffer_uptodate(SB_JOURNAL(p_s_sb)->j_header_bh)) { printk( "reiserfs: journal-837: IO error during journal replay\n" ); return -EIO ; diff -Nru a/fs/reiserfs/resize.c b/fs/reiserfs/resize.c --- a/fs/reiserfs/resize.c Tue Feb 11 00:01:27 2003 +++ b/fs/reiserfs/resize.c Tue Feb 11 00:01:27 2003 @@ -120,8 +120,7 @@ mark_buffer_dirty(bitmap[i].bh) ; set_buffer_uptodate(bitmap[i].bh); - ll_rw_block(WRITE, 1, &bitmap[i].bh); - wait_on_buffer(bitmap[i].bh); + sync_dirty_buffer(bitmap[i].bh); // update bitmap_info stuff bitmap[i].first_zero_hint=1; bitmap[i].free_count = sb_blocksize(sb) * 8 - 1; diff -Nru a/fs/sysv/inode.c b/fs/sysv/inode.c --- a/fs/sysv/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/sysv/inode.c Tue Feb 11 00:01:27 2003 @@ -265,8 +265,7 @@ bh = sysv_update_inode(inode); if (bh && buffer_dirty(bh)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); if (buffer_req(bh) && !buffer_uptodate(bh)) { printk ("IO error syncing sysv inode [%s:%08lx]\n", inode->i_sb->s_id, inode->i_ino); diff -Nru a/fs/sysv/itree.c b/fs/sysv/itree.c --- a/fs/sysv/itree.c Tue Feb 11 00:01:27 2003 +++ b/fs/sysv/itree.c Tue Feb 11 00:01:27 2003 @@ -15,10 +15,8 @@ static inline void dirty_indirect(struct buffer_head *bh, struct inode *inode) { mark_buffer_dirty_inode(bh, inode); - if (IS_SYNC(inode)) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); - } + if (IS_SYNC(inode)) + sync_dirty_buffer(bh); } static int block_to_path(struct inode *inode, long block, int offsets[DEPTH]) diff -Nru a/fs/udf/inode.c b/fs/udf/inode.c --- a/fs/udf/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/udf/inode.c Tue Feb 11 00:01:27 2003 @@ -1520,8 +1520,7 @@ mark_buffer_dirty(bh); if (do_sync) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); + sync_dirty_buffer(bh); if (buffer_req(bh) && !buffer_uptodate(bh)) { printk("IO error syncing udf inode [%s:%08lx]\n", diff -Nru a/fs/ufs/balloc.c b/fs/ufs/balloc.c --- a/fs/ufs/balloc.c Tue Feb 11 00:01:27 2003 +++ b/fs/ufs/balloc.c Tue Feb 11 00:01:27 2003 @@ -114,6 +114,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **)&ucpi); ubh_wait_on_buffer (UCPI_UBH); } @@ -199,6 +200,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **)&ucpi); ubh_wait_on_buffer (UCPI_UBH); } @@ -228,10 +230,8 @@ memset (bh->b_data, 0, sb->s_blocksize); \ set_buffer_uptodate(bh); \ mark_buffer_dirty (bh); \ - if (IS_SYNC(inode)) { \ - ll_rw_block (WRITE, 1, &bh); \ - wait_on_buffer (bh); \ - } \ + if (IS_SYNC(inode)) \ + sync_dirty_buffer(bh); \ brelse (bh); \ } @@ -364,10 +364,8 @@ clear_buffer_dirty(bh); bh->b_blocknr = result + i; mark_buffer_dirty (bh); - if (IS_SYNC(inode)) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); - } + if (IS_SYNC(inode)) + sync_dirty_buffer(bh); brelse (bh); } else @@ -459,6 +457,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **)&ucpi); ubh_wait_on_buffer (UCPI_UBH); } @@ -584,6 +583,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **)&ucpi); ubh_wait_on_buffer (UCPI_UBH); } diff -Nru a/fs/ufs/dir.c b/fs/ufs/dir.c --- a/fs/ufs/dir.c Tue Feb 11 00:01:27 2003 +++ b/fs/ufs/dir.c Tue Feb 11 00:01:27 2003 @@ -356,10 +356,8 @@ dir->i_version++; de->d_ino = cpu_to_fs32(dir->i_sb, inode->i_ino); mark_buffer_dirty(bh); - if (IS_DIRSYNC(dir)) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer(bh); - } + if (IS_DIRSYNC(dir)) + sync_dirty_buffer(bh); brelse (bh); } @@ -457,10 +455,8 @@ de->d_ino = cpu_to_fs32(sb, inode->i_ino); ufs_set_de_type(sb, de, inode->i_mode); mark_buffer_dirty(bh); - if (IS_DIRSYNC(dir)) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); - } + if (IS_DIRSYNC(dir)) + sync_dirty_buffer(bh); brelse (bh); dir->i_mtime = dir->i_ctime = CURRENT_TIME; dir->i_version++; @@ -508,10 +504,8 @@ inode->i_ctime = inode->i_mtime = CURRENT_TIME; mark_inode_dirty(inode); mark_buffer_dirty(bh); - if (IS_DIRSYNC(inode)) { - ll_rw_block(WRITE, 1, &bh); - wait_on_buffer(bh); - } + if (IS_DIRSYNC(inode)) + sync_dirty_buffer(bh); brelse(bh); UFSD(("EXIT\n")) return 0; diff -Nru a/fs/ufs/ialloc.c b/fs/ufs/ialloc.c --- a/fs/ufs/ialloc.c Tue Feb 11 00:01:27 2003 +++ b/fs/ufs/ialloc.c Tue Feb 11 00:01:27 2003 @@ -124,6 +124,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **) &ucpi); ubh_wait_on_buffer (UCPI_UBH); } @@ -248,6 +249,7 @@ ubh_mark_buffer_dirty (USPI_UBH); ubh_mark_buffer_dirty (UCPI_UBH); if (sb->s_flags & MS_SYNCHRONOUS) { + ubh_wait_on_buffer (UCPI_UBH); ubh_ll_rw_block (WRITE, 1, (struct ufs_buffer_head **) &ucpi); ubh_wait_on_buffer (UCPI_UBH); } diff -Nru a/fs/ufs/inode.c b/fs/ufs/inode.c --- a/fs/ufs/inode.c Tue Feb 11 00:01:27 2003 +++ b/fs/ufs/inode.c Tue Feb 11 00:01:27 2003 @@ -298,10 +298,8 @@ } mark_buffer_dirty(bh); - if (IS_SYNC(inode)) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); - } + if (IS_SYNC(inode)) + sync_dirty_buffer(bh); inode->i_ctime = CURRENT_TIME; mark_inode_dirty(inode); out: @@ -635,10 +633,8 @@ memset (ufs_inode, 0, sizeof(struct ufs_inode)); mark_buffer_dirty(bh); - if (do_sync) { - ll_rw_block (WRITE, 1, &bh); - wait_on_buffer (bh); - } + if (do_sync) + sync_dirty_buffer(bh); brelse (bh); UFSD(("EXIT\n")) diff -Nru a/fs/ufs/truncate.c b/fs/ufs/truncate.c --- a/fs/ufs/truncate.c Tue Feb 11 00:01:27 2003 +++ b/fs/ufs/truncate.c Tue Feb 11 00:01:27 2003 @@ -284,6 +284,7 @@ } } if (IS_SYNC(inode) && ind_ubh && ubh_buffer_dirty(ind_ubh)) { + ubh_wait_on_buffer (ind_ubh); ubh_ll_rw_block (WRITE, 1, &ind_ubh); ubh_wait_on_buffer (ind_ubh); } @@ -351,6 +352,7 @@ } } if (IS_SYNC(inode) && dind_bh && ubh_buffer_dirty(dind_bh)) { + ubh_wait_on_buffer (dind_bh); ubh_ll_rw_block (WRITE, 1, &dind_bh); ubh_wait_on_buffer (dind_bh); } @@ -415,6 +417,7 @@ } } if (IS_SYNC(inode) && tind_bh && ubh_buffer_dirty(tind_bh)) { + ubh_wait_on_buffer (tind_bh); ubh_ll_rw_block (WRITE, 1, &tind_bh); ubh_wait_on_buffer (tind_bh); } diff -Nru a/include/linux/agp_backend.h b/include/linux/agp_backend.h --- a/include/linux/agp_backend.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/agp_backend.h Tue Feb 11 00:01:27 2003 @@ -53,17 +53,6 @@ INTEL_460GX, INTEL_I7505, VIA_GENERIC, - VIA_VP3, - VIA_MVP3, - VIA_MVP4, - VIA_APOLLO_PRO, - VIA_APOLLO_KX133, - VIA_APOLLO_KT133, - VIA_APOLLO_KT400, - VIA_APOLLO_KT400_3, - VIA_APOLLO_PRO_266, - VIA_VT8605, - VIA_P4X, SIS_GENERIC, AMD_GENERIC, AMD_IRONGATE, @@ -84,6 +73,7 @@ SVWRKS_LE, SVWRKS_GENERIC, HP_ZX1, + ALPHA_CORE_AGP, }; struct agp_version { @@ -102,6 +92,7 @@ int current_memory; int cant_use_aperture; unsigned long page_mask; + struct vm_operations_struct *vm_ops; } agp_kern_info; /* diff -Nru a/include/linux/buffer_head.h b/include/linux/buffer_head.h --- a/include/linux/buffer_head.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/buffer_head.h Tue Feb 11 00:01:27 2003 @@ -169,6 +169,7 @@ void free_buffer_head(struct buffer_head * bh); void FASTCALL(unlock_buffer(struct buffer_head *bh)); void ll_rw_block(int, int, struct buffer_head * bh[]); +void sync_dirty_buffer(struct buffer_head *bh); int submit_bh(int, struct buffer_head *); void write_boundary_block(struct block_device *bdev, sector_t bblock, unsigned blocksize); diff -Nru a/include/linux/ext3_jbd.h b/include/linux/ext3_jbd.h --- a/include/linux/ext3_jbd.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/ext3_jbd.h Tue Feb 11 00:01:27 2003 @@ -210,14 +210,6 @@ return journal_start(journal, nblocks); } -static inline handle_t * -ext3_journal_try_start(struct inode *inode, int nblocks) -{ - if (inode->i_sb->s_flags & MS_RDONLY) - return ERR_PTR(-EROFS); - return journal_try_start(EXT3_JOURNAL(inode), nblocks); -} - /* * The only special thing we need to do here is to make sure that all * journal_stop calls result in the superblock being marked dirty, so diff -Nru a/include/linux/hfs_sysdep.h b/include/linux/hfs_sysdep.h --- a/include/linux/hfs_sysdep.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/hfs_sysdep.h Tue Feb 11 00:01:27 2003 @@ -155,13 +155,8 @@ } static inline void hfs_buffer_sync(hfs_buffer buffer) { - while (buffer_locked(buffer)) { - wait_on_buffer(buffer); - } - if (buffer_dirty(buffer)) { - ll_rw_block(WRITE, 1, &buffer); - wait_on_buffer(buffer); - } + if (buffer_dirty(buffer)) + sync_dirty_buffer(buffer); } static inline void *hfs_buffer_data(const hfs_buffer buffer) { diff -Nru a/include/linux/hugetlb.h b/include/linux/hugetlb.h --- a/include/linux/hugetlb.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/hugetlb.h Tue Feb 11 00:01:27 2003 @@ -26,6 +26,7 @@ unsigned long address); struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address, pmd_t *pmd, int write); +int is_aligned_hugepage_range(unsigned long addr, unsigned long len); int pmd_huge(pmd_t pmd); extern int htlbpage_max; @@ -56,6 +57,7 @@ #define hugepage_vma(mm, addr) 0 #define mark_mm_hugetlb(mm, vma) do { } while (0) #define follow_huge_pmd(mm, addr, pmd, write) 0 +#define is_aligned_hugepage_range(addr, len) 0 #define pmd_huge(x) 0 #ifndef HPAGE_MASK diff -Nru a/include/linux/jbd.h b/include/linux/jbd.h --- a/include/linux/jbd.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/jbd.h Tue Feb 11 00:01:27 2003 @@ -726,7 +726,6 @@ */ extern handle_t *journal_start(journal_t *, int nblocks); -extern handle_t *journal_try_start(journal_t *, int nblocks); extern int journal_restart (handle_t *, int nblocks); extern int journal_extend (handle_t *, int nblocks); extern int journal_get_write_access (handle_t *, struct buffer_head *); diff -Nru a/include/linux/jiffies.h b/include/linux/jiffies.h --- a/include/linux/jiffies.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/jiffies.h Tue Feb 11 00:01:27 2003 @@ -15,24 +15,14 @@ extern u64 jiffies_64; extern unsigned long volatile jiffies; +#if (BITS_PER_LONG < 64) +u64 get_jiffies_64(void); +#else static inline u64 get_jiffies_64(void) { -#if BITS_PER_LONG < 64 - extern seqlock_t xtime_lock; - unsigned long seq; - u64 tmp; - - do { - seq = read_seqbegin(&xtime_lock); - tmp = jiffies_64; - } while (read_seqretry(&xtime_lock, seq)); - - return tmp; -#else return (u64)jiffies; -#endif } - +#endif /* * These inlines deal with timer wrapping correctly. You are diff -Nru a/include/linux/sched.h b/include/linux/sched.h --- a/include/linux/sched.h Tue Feb 11 00:01:27 2003 +++ b/include/linux/sched.h Tue Feb 11 00:01:27 2003 @@ -509,6 +509,7 @@ /* per-UID process charging. */ extern struct user_struct * alloc_uid(uid_t); extern void free_uid(struct user_struct *); +extern void switch_uid(struct user_struct *); #include diff -Nru a/kernel/exit.c b/kernel/exit.c --- a/kernel/exit.c Tue Feb 11 00:01:27 2003 +++ b/kernel/exit.c Tue Feb 11 00:01:27 2003 @@ -249,7 +249,7 @@ /* signals? */ security_task_reparent_to_init(current); memcpy(current->rlim, init_task.rlim, sizeof(*(current->rlim))); - current->user = INIT_USER; + switch_uid(INIT_USER); write_unlock_irq(&tasklist_lock); } diff -Nru a/kernel/kmod.c b/kernel/kmod.c --- a/kernel/kmod.c Tue Feb 11 00:01:27 2003 +++ b/kernel/kmod.c Tue Feb 11 00:01:27 2003 @@ -121,15 +121,7 @@ if (curtask->files->fd[i]) close(i); } - /* Drop the "current user" thing */ - { - struct user_struct *user = curtask->user; - curtask->user = INIT_USER; - atomic_inc(&INIT_USER->__count); - atomic_inc(&INIT_USER->processes); - atomic_dec(&user->processes); - free_uid(user); - } + switch_uid(INIT_USER); /* Give kmod all effective privileges.. */ curtask->euid = curtask->fsuid = 0; diff -Nru a/kernel/ksyms.c b/kernel/ksyms.c --- a/kernel/ksyms.c Tue Feb 11 00:01:26 2003 +++ b/kernel/ksyms.c Tue Feb 11 00:01:27 2003 @@ -208,6 +208,7 @@ EXPORT_SYMBOL(__brelse); EXPORT_SYMBOL(__bforget); EXPORT_SYMBOL(ll_rw_block); +EXPORT_SYMBOL(sync_dirty_buffer); EXPORT_SYMBOL(submit_bh); EXPORT_SYMBOL(unlock_buffer); EXPORT_SYMBOL(__wait_on_buffer); @@ -489,6 +490,9 @@ EXPORT_SYMBOL(xtime_lock); EXPORT_SYMBOL(do_gettimeofday); EXPORT_SYMBOL(do_settimeofday); +#if (BITS_PER_LONG < 64) +EXPORT_SYMBOL(get_jiffies_64); +#endif #ifdef CONFIG_DEBUG_SPINLOCK_SLEEP EXPORT_SYMBOL(__might_sleep); #endif diff -Nru a/kernel/sys.c b/kernel/sys.c --- a/kernel/sys.c Tue Feb 11 00:01:27 2003 +++ b/kernel/sys.c Tue Feb 11 00:01:27 2003 @@ -561,19 +561,12 @@ static int set_user(uid_t new_ruid, int dumpclear) { - struct user_struct *new_user, *old_user; + struct user_struct *new_user; - /* What if a process setreuid()'s and this brings the - * new uid over his NPROC rlimit? We can check this now - * cheaply with the new uid cache, so if it matters - * we should be checking for it. -DaveM - */ new_user = alloc_uid(new_ruid); if (!new_user) return -EAGAIN; - old_user = current->user; - atomic_dec(&old_user->processes); - atomic_inc(&new_user->processes); + switch_uid(new_user); if(dumpclear) { @@ -581,8 +574,6 @@ wmb(); } current->uid = new_ruid; - current->user = new_user; - free_uid(old_user); return 0; } diff -Nru a/kernel/time.c b/kernel/time.c --- a/kernel/time.c Tue Feb 11 00:01:27 2003 +++ b/kernel/time.c Tue Feb 11 00:01:27 2003 @@ -27,7 +27,6 @@ #include #include #include - #include /* @@ -416,3 +415,17 @@ return now; } + +#if (BITS_PER_LONG < 64) +u64 get_jiffies_64(void) +{ + unsigned long seq; + u64 ret; + + do { + seq = read_seqbegin(&xtime_lock); + ret = jiffies_64; + } while (read_seqretry(&xtime_lock, seq)); + return ret; +} +#endif diff -Nru a/kernel/user.c b/kernel/user.c --- a/kernel/user.c Tue Feb 11 00:01:27 2003 +++ b/kernel/user.c Tue Feb 11 00:01:27 2003 @@ -116,6 +116,23 @@ return up; } +void switch_uid(struct user_struct *new_user) +{ + struct user_struct *old_user; + + /* What if a process setreuid()'s and this brings the + * new uid over his NPROC rlimit? We can check this now + * cheaply with the new uid cache, so if it matters + * we should be checking for it. -DaveM + */ + old_user = current->user; + atomic_inc(&new_user->__count); + atomic_inc(&new_user->processes); + atomic_dec(&old_user->processes); + current->user = new_user; + free_uid(old_user); +} + static int __init uid_cache_init(void) { diff -Nru a/lib/radix-tree.c b/lib/radix-tree.c --- a/lib/radix-tree.c Tue Feb 11 00:01:27 2003 +++ b/lib/radix-tree.c Tue Feb 11 00:01:27 2003 @@ -154,8 +154,7 @@ /* Increase the height. */ node->slots[0] = root->rnode; - if (root->rnode) - node->count = 1; + node->count = 1; root->rnode = node; root->height++; } while (height > root->height); diff -Nru a/mm/mmap.c b/mm/mmap.c --- a/mm/mmap.c Tue Feb 11 00:01:27 2003 +++ b/mm/mmap.c Tue Feb 11 00:01:27 2003 @@ -801,6 +801,13 @@ return -ENOMEM; if (addr & ~PAGE_MASK) return -EINVAL; + if (is_file_hugepages(file)) { + unsigned long ret; + + ret = is_aligned_hugepage_range(addr, len); + if (ret) + return ret; + } return addr; } @@ -1224,8 +1231,10 @@ /* we have start < mpnt->vm_end */ if (is_vm_hugetlb_page(mpnt)) { - if ((start & ~HPAGE_MASK) || (len & ~HPAGE_MASK)) - return -EINVAL; + int ret = is_aligned_hugepage_range(start, len); + + if (ret) + return ret; } /* if it doesn't overlap, we have nothing.. */ diff -Nru a/net/bluetooth/af_bluetooth.c b/net/bluetooth/af_bluetooth.c --- a/net/bluetooth/af_bluetooth.c Tue Feb 11 00:01:27 2003 +++ b/net/bluetooth/af_bluetooth.c Tue Feb 11 00:01:27 2003 @@ -92,7 +92,7 @@ static int bt_sock_create(struct socket *sock, int proto) { - if (proto > BT_MAX_PROTO) + if (proto >= BT_MAX_PROTO) return -EINVAL; #if defined(CONFIG_KMOD) diff -Nru a/net/core/rtnetlink.c b/net/core/rtnetlink.c --- a/net/core/rtnetlink.c Tue Feb 11 00:01:27 2003 +++ b/net/core/rtnetlink.c Tue Feb 11 00:01:27 2003 @@ -351,7 +351,7 @@ return 0; family = ((struct rtgenmsg*)NLMSG_DATA(nlh))->rtgen_family; - if (family > NPROTO) { + if (family >= NPROTO) { *errp = -EAFNOSUPPORT; return -1; }