Chapter 5. Advanced board driver functions

Table of Contents

Multiple chip control
Hardware ECC support
Functions and constants
Hardware ECC with syndrome calculation
Bad block table support
Flash based tables
User defined tables
Spare area (auto)placement
Placement defined by fs driver
Automatic placement
Spare area autoplacement default schemes
256 byte pagesize
512 byte pagesize
2048 byte pagesize

This chapter describes the advanced functionality of the NAND driver. For a list of functions which can be overridden by the board driver see the documentation of the nand_chip structure.

Multiple chip control

The nand driver can control chip arrays. Therefore the board driver must provide an own select_chip function. This function must (de)select the requested chip. The function pointer in the nand_chip structure must be set before calling nand_scan(). The maxchip parameter of nand_scan() defines the maximum number of chips to scan for. Make sure that the select_chip function can handle the requested number of chips.

The nand driver concatenates the chips to one virtual chip and provides this virtual chip to the MTD layer.

Note: The driver can only handle linear chip arrays of equally sized chips. There is no support for parallel arrays which extend the buswidth.

GPIO based example

static void board_select_chip (struct mtd_info *mtd, int chip)
{
	/* Deselect all chips, set all nCE pins high */
	GPIO(BOARD_NAND_NCE) |= 0xff;	
	if (chip >= 0)
		GPIO(BOARD_NAND_NCE) &= ~ (1 << chip);
}
		

Address lines based example. Its assumed that the nCE pins are connected to an address decoder.

static void board_select_chip (struct mtd_info *mtd, int chip)
{
	struct nand_chip *this = mtd_to_nand(mtd);
	
	/* Deselect all chips */
	this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;
	this->IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK;
	switch (chip) {
	case 0:
		this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0;
		this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0;
		break;
	....	
	case n:
		this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn;
		this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn;
		break;
	}	
}