Chapter 17. Clock Framework

Table of Contents

struct clk_notifier — associate a clk with a notifier
struct clk_notifier_data — rate data to pass to the notifier callback
clk_notifier_register — change notifier callback
clk_notifier_unregister — change notifier callback
clk_get_accuracy — obtain the clock accuracy in ppb (parts per billion) for a clock source.
clk_set_phase — adjust the phase shift of a clock signal
clk_get_phase — return the phase shift of a clock signal
clk_is_match — check if two clk's point to the same hardware clock
clk_prepare — prepare a clock source
clk_unprepare — undo preparation of a clock source
clk_get — lookup and obtain a reference to a clock producer.
devm_clk_get — lookup and obtain a managed reference to a clock producer.
clk_enable — inform the system when the clock source should be running.
clk_disable — inform the system when the clock source is no longer required.
clk_get_rate — obtain the current clock rate (in Hz) for a clock source. This is only valid once the clock source has been enabled.
clk_put — "free" the clock source
devm_clk_put — "free" a managed clock source
clk_round_rate — adjust a rate to the exact rate a clock can provide
clk_set_rate — set the clock rate for a clock source
clk_has_parent — check if a clock is a possible parent for another
clk_set_rate_range — set a rate range for a clock source
clk_set_min_rate — set a minimum clock rate for a clock source
clk_set_max_rate — set a maximum clock rate for a clock source
clk_set_parent — set the parent clock source for this clock
clk_get_parent — get the parent clock source for this clock
clk_get_sys — get a clock based upon the device name

The clock framework defines programming interfaces to support software management of the system clock tree. This framework is widely used with System-On-Chip (SOC) platforms to support power management and various devices which may need custom clock rates. Note that these "clocks" don't relate to timekeeping or real time clocks (RTCs), each of which have separate frameworks. These struct clk instances may be used to manage for example a 96 MHz signal that is used to shift bits into and out of peripherals or busses, or otherwise trigger synchronous state machine transitions in system hardware.

Power management is supported by explicit software clock gating: unused clocks are disabled, so the system doesn't waste power changing the state of transistors that aren't in active use. On some systems this may be backed by hardware clock gating, where clocks are gated without being disabled in software. Sections of chips that are powered but not clocked may be able to retain their last state. This low power state is often called a retention mode. This mode still incurs leakage currents, especially with finer circuit geometries, but for CMOS circuits power is mostly used by clocked state changes.

Power-aware drivers only enable their clocks when the device they manage is in active use. Also, system sleep states often differ according to which clock domains are active: while a "standby" state may allow wakeup from several active domains, a "mem" (suspend-to-RAM) state may require a more wholesale shutdown of clocks derived from higher speed PLLs and oscillators, limiting the number of possible wakeup event sources. A driver's suspend method may need to be aware of system-specific clock constraints on the target sleep state.

Some platforms support programmable clock generators. These can be used by external chips of various kinds, such as other CPUs, multimedia codecs, and devices with strict requirements for interface clocking.