AD4134 driver

Device driver for Analog Devices Inc. AD4134 and similar ADCs.

Supported devices

• AD4134

• AD7134

Wiring connections

AD4134 and similar ADCs can operate in a few different wiring configurations. Because AD4134 also supports control modes other than through SPI protocol, the following pins must be statically set for all of the wiring modes described below.

Pin Function	Level	Description
PIN/SPI	High	SPI control mode
MODE	Low	ASRC slave mode
DEC0/DCLKI	Low	DCLK input
DEC1/DCLKMODE	Low	Gated DCLK

Minimum I/O mode

The minimum I/O mode wiring allows AD4134 register and data access with the conventional set of SPI bus lines. In this mode, the peripheral CS pin must be tied to GND. A possible connection schema that sets AD4134 digital interface for minimum I/O mode is:

+------------+         +-------------+
|  AD4134    |         | SPI         |
|            |         | Controller  |
|       DCLK |<--+     |             |
|       SCLK |<--+---- | SCLK        |
|        SDI |<--------| SDO         |
|        SDO |-------->| SDI         |
|        ODR |<--------| GPIO        |
|         CS |----+    |             |
+------------+    |    +-------------+
                  V
                 GND

Set adi,spi-mode = "no-cs" in device tree to indicate the device is connected in minimum I/O wiring configuration.

SPI 4-wire mode - single lane

The conventional SPI 4-wire configuration except a multiplexer is used to select between SDO (for register data) and DOUT0 (for ADC sample data).:

+-----------------------+                         +-----------------+
|         AD4134        |                         | SPI Controller  |
|                       |                         |                 |
| SPI interface    SCLK |<------------------------| SCLK            |
| for register       CS |<------------------------| CS              |
| access            SDI |<------------------------| SDO             |
|                   SDO |------->|¯¯¯¯\           |                 |
|                       |        |MUX  >--------->| SDI             |
| Data interface DOUT0  |------->|____/           |                 |
| for ADC sample        |          ^              |                 |
| data read             |          |              |                 |
|                  DCLK |<------------------------| DCLK            |
|                   ODR |<----------------+    +->| Offload Trigger |
+-----------------------+          |      |    |  +-----------------+
                                   |      |    +--| PWM1            |
                                   |      +-------| PWM0            |
                                   +--------------| GPIO            |
                                                  +-----------------+

Set adi,spi-mode = "4-wire" in device tree to indicate the device is connected in SPI 4-wire configuration.

For SPI offload operation, a PWM is connected to the ADC ODR pin. The pwms firmware property specifies the PWM that is connected to the ADC. The SPI offload will have a trigger-sources property to indicate the SPI offload (PWM) trigger source.

To achieve high sample rates while meeting ADC timing requirements, an offset must be added between the rising edges of PWM0 and PWM1 to delay the SPI transfer until ADC sample data is available. This requires a specialized PWM controller that can provide such an offset. The AD4134-FMC HDL project, for example, can be configured to sample AD4134 at high speed sample rates.

SPI 4-wire mode - multi-lane

Maximum throughput rate can be achieved by reading 4 input lines simultaneously.:

+-----------------------+                         +-----------------+
|         AD4134        |                         | SPI Controller  |
|                       |                         |                 |
| SPI interface    SCLK |<------------------------| SCLK            |
| for register       CS |<------------------------| CS              |
| access            SDI |<------------------------| SDO             |
|                   SDO |------->|¯¯¯¯\           |                 |
|                       |        |MUX  >--------->| SDI0            |
| Data interface  DOUT0 |------->|____/           |                 |
| for ADC sample        |          ^              |                 |
| data read       DOUT1 |------------------------>| SDI1            |
|                 DOUT2 |------------------------>| SDI2            |
|                 DOUT3 |------------------------>| SDI3            |
|                  DCLK |<------------------------| DCLK            |
|                   ODR |<----------------+    +->| Offload Trigger |
+-----------------------+          |      |    |  +-----------------+
                                   |      |    +--| PWM1            |
                                   |      +-------| PWM0            |
                                   +--------------| GPIO            |
                                                  +-----------------+

Each of SDI0 to SDI3 connect to a different SPI controller deserializer (spi-rx-bus-width = <1>, <1>, <1>, <1>).