€•M5Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ'/translations/zh_CN/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/zh_TW/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/it_IT/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ja_JP/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/ko_KR/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ'/translations/sp_SP/virt/kvm/x86/errata”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h”hhhžhhŸŒA/var/lib/git/docbuild/linux/Documentation/virt/kvm/x86/errata.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ'Known limitations of CPU virtualization”h]”hŒ'Known limitations of CPU virtualization”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ paragraph”“”)”}”(hŒŪWhenever perfect emulation of a CPU feature is impossible or too hard, KVM has to choose between not implementing the feature at all or introducing behavioral differences between virtual machines and bare metal systems.”h]”hŒŪWhenever perfect emulation of a CPU feature is impossible or too hard, KVM has to choose between not implementing the feature at all or introducing behavioral differences between virtual machines and bare metal systems.”…””}”(hhĖhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhŹ)”}”(hŒ\This file documents some of the known limitations that KVM has in virtualizing CPU features.”h]”hŒ\This file documents some of the known limitations that KVM has in virtualizing CPU features.”…””}”(hhŁhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hh¶hžhubhµ)”}”(hhh]”(hŗ)”}”(hŒx86”h]”hŒx86”…””}”(hhźhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhēhžhhŸh³h Kubhµ)”}”(hhh]”(hŗ)”}”(hŒ"``KVM_GET_SUPPORTED_CPUID`` issues”h]”(hŒliteral”“”)”}”(hŒ``KVM_GET_SUPPORTED_CPUID``”h]”hŒKVM_GET_SUPPORTED_CPUID”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h’hhūubhŒ issues”…””}”(hhūhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhųhžhhŸh³h Kubhµ)”}”(hhh]”(hŗ)”}”(hŒ x87 features”h]”hŒ x87 features”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjhžhhŸh³h KubhŹ)”}”(hŒĪUnlike most other CPUID feature bits, CPUID[EAX=7,ECX=0]:EBX[6] (FDP_EXCPTN_ONLY) and CPUID[EAX=7,ECX=0]:EBX]13] (ZERO_FCS_FDS) are clear if the features are present and set if the features are not present.”h]”hŒĪUnlike most other CPUID feature bits, CPUID[EAX=7,ECX=0]:EBX[6] (FDP_EXCPTN_ONLY) and CPUID[EAX=7,ECX=0]:EBX]13] (ZERO_FCS_FDS) are clear if the features are present and set if the features are not present.”…””}”(hj*hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjhžhubhŹ)”}”(hŒĄClearing these bits in CPUID has no effect on the operation of the guest; if these bits are set on hardware, the features will not be present on any virtual machine that runs on that hardware.”h]”hŒĄClearing these bits in CPUID has no effect on the operation of the guest; if these bits are set on hardware, the features will not be present on any virtual machine that runs on that hardware.”…””}”(hj8hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjhžhubhŹ)”}”(hX**Workaround:** It is recommended to always set these bits in guest CPUID. Note however that any software (e.g ``WIN87EM.DLL``) expecting these features to be present likely predates these CPUID feature bits, and therefore doesn't know to check for them anyway.”h]”(hŒstrong”“”)”}”(hŒ**Workaround:**”h]”hŒ Workaround:”…””}”(hjLhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jJhjFubhŒ` It is recommended to always set these bits in guest CPUID. Note however that any software (e.g ”…””}”(hjFhžhhŸNh Nubj)”}”(hŒ``WIN87EM.DLL``”h]”hŒ WIN87EM.DLL”…””}”(hj^hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h’hjFubhŒ‰) expecting these features to be present likely predates these CPUID feature bits, and therefore doesn’t know to check for them anyway.”…””}”(hjFhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khjhžhubeh}”(h]”Œ x87-features”ah ]”h"]”Œ x87 features”ah$]”h&]”uh1h“hhųhžhhŸh³h Kubeh}”(h]”Œkvm-get-supported-cpuid-issues”ah ]”h"]”Œkvm_get_supported_cpuid issues”ah$]”h&]”uh1h“hhēhžhhŸh³h Kubhµ)”}”(hhh]”(hŗ)”}”(hŒ``KVM_SET_VCPU_EVENTS`` issue”h]”(j)”}”(hŒ``KVM_SET_VCPU_EVENTS``”h]”hŒKVM_SET_VCPU_EVENTS”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h’hj‰ubhŒ issue”…””}”(hj‰hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj†hžhhŸh³h K%ubhŹ)”}”(hXNInvalid KVM_SET_VCPU_EVENTS input with respect to error codes *may* result in failed VM-Entry on Intel CPUs. Pre-CET Intel CPUs require that exception injection through the VMCS correctly set the "error code valid" flag, e.g. require the flag be set when injecting a #GP, clear when injecting a #UD, clear when injecting a soft exception, etc. Intel CPUs that enumerate IA32_VMX_BASIC[56] as '1' relax VMX's consistency checks, and AMD CPUs have no restrictions whatsoever. KVM_SET_VCPU_EVENTS doesn't sanity check the vector versus "has_error_code", i.e. KVM's ABI follows AMD behavior.”h]”(hŒ>Invalid KVM_SET_VCPU_EVENTS input with respect to error codes ”…””}”(hj„hžhhŸNh NubhŒemphasis”“”)”}”(hŒ*may*”h]”hŒmay”…””}”(hjÆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j­hj„ubhX result in failed VM-Entry on Intel CPUs. Pre-CET Intel CPUs require that exception injection through the VMCS correctly set the ā€œerror code validā€ flag, e.g. require the flag be set when injecting a #GP, clear when injecting a #UD, clear when injecting a soft exception, etc. Intel CPUs that enumerate IA32_VMX_BASIC[56] as ā€˜1’ relax VMX’s consistency checks, and AMD CPUs have no restrictions whatsoever. KVM_SET_VCPU_EVENTS doesn’t sanity check the vector versus ā€œhas_error_codeā€, i.e. KVM’s ABI follows AMD behavior.”…””}”(hj„hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K'hj†hžhubeh}”(h]”Œkvm-set-vcpu-events-issue”ah ]”h"]”Œkvm_set_vcpu_events issue”ah$]”h&]”uh1h“hhēhžhhŸh³h K%ubhµ)”}”(hhh]”(hŗ)”}”(hŒNested virtualization features”h]”hŒNested virtualization features”…””}”(hjŅhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjĻhžhhŸh³h K1ubhŹ)”}”(hŒTBD”h]”hŒTBD”…””}”(hjąhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K3hjĻhžhubeh}”(h]”Œnested-virtualization-features”ah ]”h"]”Œnested virtualization features”ah$]”h&]”uh1h“hhēhžhhŸh³h K1ubhµ)”}”(hhh]”(hŗ)”}”(hŒx2APIC”h]”hŒx2APIC”…””}”(hjłhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjöhžhhŸh³h K6ubhŹ)”}”(hX[When KVM_X2APIC_API_USE_32BIT_IDS is enabled, KVM activates a hack/quirk that allows sending events to a single vCPU using its x2APIC ID even if the target vCPU has legacy xAPIC enabled, e.g. to bring up hotplugged vCPUs via INIT-SIPI on VMs with > 255 vCPUs. A side effect of the quirk is that, if multiple vCPUs have the same physical APIC ID, KVM will deliver events targeting that APIC ID only to the vCPU with the lowest vCPU ID. If KVM_X2APIC_API_USE_32BIT_IDS is not enabled, KVM follows x86 architecture when processing interrupts (all vCPUs matching the target APIC ID receive the interrupt).”h]”hX[When KVM_X2APIC_API_USE_32BIT_IDS is enabled, KVM activates a hack/quirk that allows sending events to a single vCPU using its x2APIC ID even if the target vCPU has legacy xAPIC enabled, e.g. to bring up hotplugged vCPUs via INIT-SIPI on VMs with > 255 vCPUs. A side effect of the quirk is that, if multiple vCPUs have the same physical APIC ID, KVM will deliver events targeting that APIC ID only to the vCPU with the lowest vCPU ID. If KVM_X2APIC_API_USE_32BIT_IDS is not enabled, KVM follows x86 architecture when processing interrupts (all vCPUs matching the target APIC ID receive the interrupt).”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K7hjöhžhubeh}”(h]”Œx2apic”ah ]”h"]”Œx2apic”ah$]”h&]”uh1h“hhēhžhhŸh³h K6ubhµ)”}”(hhh]”(hŗ)”}”(hŒMTRRs”h]”hŒMTRRs”…””}”(hj hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjhžhhŸh³h KAubhŹ)”}”(hX!KVM does not virtualize guest MTRR memory types. KVM emulates accesses to MTRR MSRs, i.e. {RD,WR}MSR in the guest will behave as expected, but KVM does not honor guest MTRRs when determining the effective memory type, and instead treats all of guest memory as having Writeback (WB) MTRRs.”h]”hX!KVM does not virtualize guest MTRR memory types. KVM emulates accesses to MTRR MSRs, i.e. {RD,WR}MSR in the guest will behave as expected, but KVM does not honor guest MTRRs when determining the effective memory type, and instead treats all of guest memory as having Writeback (WB) MTRRs.”…””}”(hj.hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KBhjhžhubeh}”(h]”Œmtrrs”ah ]”h"]”Œmtrrs”ah$]”h&]”uh1h“hhēhžhhŸh³h KAubhµ)”}”(hhh]”(hŗ)”}”(hŒCR0.CD”h]”hŒCR0.CD”…””}”(hjGhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjDhžhhŸh³h KHubhŹ)”}”(hŒćKVM does not virtualize CR0.CD on Intel CPUs. Similar to MTRR MSRs, KVM emulates CR0.CD accesses so that loads and stores from/to CR0 behave as expected, but setting CR0.CD=1 has no impact on the cachaeability of guest memory.”h]”hŒćKVM does not virtualize CR0.CD on Intel CPUs. Similar to MTRR MSRs, KVM emulates CR0.CD accesses so that loads and stores from/to CR0 behave as expected, but setting CR0.CD=1 has no impact on the cachaeability of guest memory.”…””}”(hjUhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KIhjDhžhubhŹ)”}”(hŒ²Note, this erratum does not affect AMD CPUs, which fully virtualize CR0.CD in hardware, i.e. put the CPU caches into "no fill" mode when CR0.CD=1, even when running in the guest.”h]”hŒ¶Note, this erratum does not affect AMD CPUs, which fully virtualize CR0.CD in hardware, i.e. put the CPU caches into ā€œno fillā€ mode when CR0.CD=1, even when running in the guest.”…””}”(hjchžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KNhjDhžhubeh}”(h]”Œcr0-cd”ah ]”h"]”Œcr0.cd”ah$]”h&]”uh1h“hhēhžhhŸh³h KHubeh}”(h]”Œx86”ah ]”h"]”Œx86”ah$]”h&]”uh1h“hh¶hžhhŸh³h Kubeh}”(h]”Œ'known-limitations-of-cpu-virtualization”ah ]”h"]”Œ'known limitations of cpu virtualization”ah$]”h&]”uh1h“hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j¬Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j†jƒj~j{jƒj€j{jxjĢjÉjójšjjjAj>jvjsuŒ nametypes”}”(j†‰j~‰jƒ‰j{‰j̉jó‰j‰jA‰jv‰uh}”(jƒh¶j{hēj€hųjxjjÉj†jšjĻjjöj>jjsjDuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.