;sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/virt/kvm/devices/xivemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/virt/kvm/devices/xivemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/virt/kvm/devices/xivemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/virt/kvm/devices/xivemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/virt/kvm/devices/xivemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/virt/kvm/devices/xivemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/xive.rsthKubhsection)}(hhh](htitle)}(h;POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)h]h;POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubhdefinition_list)}(hhh]hdefinition_list_item)}(h^Device types supported: - KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1 h](hterm)}(hDevice types supported:h]hDevice types supported:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh definition)}(hhh]h bullet_list)}(hhh]h list_item)}(hDKVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1 h]h paragraph)}(hCKVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1h]hCKVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]bullet-uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhNhNubh)}(hThis device acts as a VM interrupt controller. It provides the KVM interface to configure the interrupt sources of a VM in the underlying POWER9 XIVE interrupt controller.h]hThis device acts as a VM interrupt controller. It provides the KVM interface to configure the interrupt sources of a VM in the underlying POWER9 XIVE interrupt controller.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXOnly one XIVE instance may be instantiated. A guest XIVE device requires a POWER9 host and the guest OS should have support for the XIVE native exploitation interrupt mode. If not, it should run using the legacy interrupt mode, referred as XICS (POWER7/8).h]hXOnly one XIVE instance may be instantiated. A guest XIVE device requires a POWER9 host and the guest OS should have support for the XIVE native exploitation interrupt mode. If not, it should run using the legacy interrupt mode, referred as XICS (POWER7/8).}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hXDevice Mappings The KVM device exposes different MMIO ranges of the XIVE HW which are required for interrupt management. These are exposed to the guest in VMAs populated with a custom VM fault handler. 1. Thread Interrupt Management Area (TIMA) Each thread has an associated Thread Interrupt Management context composed of a set of registers. These registers let the thread handle priority management and interrupt acknowledgment. The most important are : - Interrupt Pending Buffer (IPB) - Current Processor Priority (CPPR) - Notification Source Register (NSR) They are exposed to software in four different pages each proposing a view with a different privilege. The first page is for the physical thread context and the second for the hypervisor. Only the third (operating system) and the fourth (user level) are exposed the guest. 2. Event State Buffer (ESB) Each source is associated with an Event State Buffer (ESB) with either a pair of even/odd pair of pages which provides commands to manage the source: to trigger, to EOI, to turn off the source for instance. 3. Device pass-through When a device is passed-through into the guest, the source interrupts are from a different HW controller (PHB4) and the ESB pages exposed to the guest should accommodate this change. The passthru_irq helpers, kvmppc_xive_set_mapped() and kvmppc_xive_clr_mapped() are called when the device HW irqs are mapped into or unmapped from the guest IRQ number space. The KVM device extends these helpers to clear the ESB pages of the guest IRQ number being mapped and then lets the VM fault handler repopulate. The handler will insert the ESB page corresponding to the HW interrupt of the device being passed-through or the initial IPI ESB page if the device has being removed. The ESB remapping is fully transparent to the guest and the OS device driver. All handling is done within VFIO and the above helpers in KVM-PPC. h](h)}(hDevice Mappingsh]hDevice Mappings}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubh)}(hThe KVM device exposes different MMIO ranges of the XIVE HW which are required for interrupt management. These are exposed to the guest in VMAs populated with a custom VM fault handler.h]hThe KVM device exposes different MMIO ranges of the XIVE HW which are required for interrupt management. These are exposed to the guest in VMAs populated with a custom VM fault handler.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubhenumerated_list)}(hhh]h)}(h(Thread Interrupt Management Area (TIMA) h]h)}(h'Thread Interrupt Management Area (TIMA)h]h'Thread Interrupt Management Area (TIMA)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhubah}(h]h ]h"]h$]h&]uh1hhjeubah}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jchjCubh)}(hEach thread has an associated Thread Interrupt Management context composed of a set of registers. These registers let the thread handle priority management and interrupt acknowledgment. The most important are :h]hEach thread has an associated Thread Interrupt Management context composed of a set of registers. These registers let the thread handle priority management and interrupt acknowledgment. The most important are :}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubh block_quote)}(hp- Interrupt Pending Buffer (IPB) - Current Processor Priority (CPPR) - Notification Source Register (NSR) h]h)}(hhh](h)}(h"Interrupt Pending Buffer (IPB)h]h)}(hjh]h"Interrupt Pending Buffer (IPB)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#Current Processor Priority (CPPR)h]h)}(hjh]h#Current Processor Priority (CPPR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h#Notification Source Register (NSR) h]h)}(h"Notification Source Register (NSR)h]h"Notification Source Register (NSR)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhhhK hjCubh)}(hXThey are exposed to software in four different pages each proposing a view with a different privilege. The first page is for the physical thread context and the second for the hypervisor. Only the third (operating system) and the fourth (user level) are exposed the guest.h]hXThey are exposed to software in four different pages each proposing a view with a different privilege. The first page is for the physical thread context and the second for the hypervisor. Only the third (operating system) and the fourth (user level) are exposed the guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjCubjd)}(hhh]h)}(hEvent State Buffer (ESB) h]h)}(hEvent State Buffer (ESB)h]hEvent State Buffer (ESB)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jjjhjjstartKuh1jchjCubh)}(hEach source is associated with an Event State Buffer (ESB) with either a pair of even/odd pair of pages which provides commands to manage the source: to trigger, to EOI, to turn off the source for instance.h]hEach source is associated with an Event State Buffer (ESB) with either a pair of even/odd pair of pages which provides commands to manage the source: to trigger, to EOI, to turn off the source for instance.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjCubjd)}(hhh]h)}(hDevice pass-through h]h)}(hDevice pass-throughh]hDevice pass-through}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj5ubah}(h]h ]h"]h$]h&]uh1hhj2ubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jchjCubh)}(hWhen a device is passed-through into the guest, the source interrupts are from a different HW controller (PHB4) and the ESB pages exposed to the guest should accommodate this change.h]hWhen a device is passed-through into the guest, the source interrupts are from a different HW controller (PHB4) and the ESB pages exposed to the guest should accommodate this change.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjCubh)}(hXThe passthru_irq helpers, kvmppc_xive_set_mapped() and kvmppc_xive_clr_mapped() are called when the device HW irqs are mapped into or unmapped from the guest IRQ number space. The KVM device extends these helpers to clear the ESB pages of the guest IRQ number being mapped and then lets the VM fault handler repopulate. The handler will insert the ESB page corresponding to the HW interrupt of the device being passed-through or the initial IPI ESB page if the device has being removed.h]hXThe passthru_irq helpers, kvmppc_xive_set_mapped() and kvmppc_xive_clr_mapped() are called when the device HW irqs are mapped into or unmapped from the guest IRQ number space. The KVM device extends these helpers to clear the ESB pages of the guest IRQ number being mapped and then lets the VM fault handler repopulate. The handler will insert the ESB page corresponding to the HW interrupt of the device being passed-through or the initial IPI ESB page if the device has being removed.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjCubh)}(hThe ESB remapping is fully transparent to the guest and the OS device driver. All handling is done within VFIO and the above helpers in KVM-PPC.h]hThe ESB remapping is fully transparent to the guest and the OS device driver. All handling is done within VFIO and the above helpers in KVM-PPC.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjCubeh}(h]h ]h"]h$]h&]uh1hhj@hhhhhNubh)}(hGroups: h]h)}(hGroups:h]hGroups:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhNubeh}(h]h ]h"]h$]h&]j*uh1hhhhKhhhhubjd)}(hhh]h)}(h?KVM_DEV_XIVE_GRP_CTRL Provides global controls on the device h]h)}(hhh]h)}(h=KVM_DEV_XIVE_GRP_CTRL Provides global controls on the device h](h)}(hKVM_DEV_XIVE_GRP_CTRLh]hKVM_DEV_XIVE_GRP_CTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubh)}(hhh]h)}(h&Provides global controls on the deviceh]h&Provides global controls on the device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKGhjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhjhhhNhNubah}(h]h ]h"]h$]h&]jjjhjjuh1jchhhhhhhKFubj)}(hXSAttributes: 1.1 KVM_DEV_XIVE_RESET (write only) Resets the interrupt controller configuration for sources and event queues. To be used by kexec and kdump. Errors: none 1.2 KVM_DEV_XIVE_EQ_SYNC (write only) Sync all the sources and queues and mark the EQ pages dirty. This to make sure that a consistent memory state is captured when migrating the VM. Errors: none 1.3 KVM_DEV_XIVE_NR_SERVERS (write only) The kvm_device_attr.addr points to a __u32 value which is the number of interrupt server numbers (ie, highest possible vcpu id plus one). Errors: ======= ========================================== -EINVAL Value greater than KVM_MAX_VCPU_IDS. -EFAULT Invalid user pointer for attr->addr. -EBUSY A vCPU is already connected to the device. ======= ========================================== h]h)}(hhh]h)}(hX/Attributes: 1.1 KVM_DEV_XIVE_RESET (write only) Resets the interrupt controller configuration for sources and event queues. To be used by kexec and kdump. Errors: none 1.2 KVM_DEV_XIVE_EQ_SYNC (write only) Sync all the sources and queues and mark the EQ pages dirty. This to make sure that a consistent memory state is captured when migrating the VM. Errors: none 1.3 KVM_DEV_XIVE_NR_SERVERS (write only) The kvm_device_attr.addr points to a __u32 value which is the number of interrupt server numbers (ie, highest possible vcpu id plus one). Errors: ======= ========================================== -EINVAL Value greater than KVM_MAX_VCPU_IDS. -EFAULT Invalid user pointer for attr->addr. -EBUSY A vCPU is already connected to the device. ======= ========================================== h](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjubh)}(hhh](h)}(h1.1 KVM_DEV_XIVE_RESET (write only) Resets the interrupt controller configuration for sources and event queues. To be used by kexec and kdump.h]h1.1 KVM_DEV_XIVE_RESET (write only) Resets the interrupt controller configuration for sources and event queues. To be used by kexec and kdump.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhjubh)}(h Errors: noneh]h Errors: none}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubh)}(h1.2 KVM_DEV_XIVE_EQ_SYNC (write only) Sync all the sources and queues and mark the EQ pages dirty. This to make sure that a consistent memory state is captured when migrating the VM.h]h1.2 KVM_DEV_XIVE_EQ_SYNC (write only) Sync all the sources and queues and mark the EQ pages dirty. This to make sure that a consistent memory state is captured when migrating the VM.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKPhjubh)}(h Errors: noneh]h Errors: none}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubh)}(h1.3 KVM_DEV_XIVE_NR_SERVERS (write only) The kvm_device_attr.addr points to a __u32 value which is the number of interrupt server numbers (ie, highest possible vcpu id plus one).h]h1.3 KVM_DEV_XIVE_NR_SERVERS (write only) The kvm_device_attr.addr points to a __u32 value which is the number of interrupt server numbers (ie, highest possible vcpu id plus one).}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjubh)}(hErrors:h]hErrors:}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjubj)}(h======= ========================================== -EINVAL Value greater than KVM_MAX_VCPU_IDS. -EFAULT Invalid user pointer for attr->addr. -EBUSY A vCPU is already connected to the device. ======= ========================================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhjhubjl)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jkhjhubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Value greater than KVM_MAX_VCPU_IDS.h]h$Value greater than KVM_MAX_VCPU_IDS.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h*A vCPU is already connected to the device.h]h*A vCPU is already connected to the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK`hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]colsKuh1jfhjcubah}(h]h ]h"]h$]h&]uh1jahj]ubah}(h]h ]h"]h$]h&]uh1jhhhK]hjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKahjubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1jhhhKIhhhhubjd)}(hhh]h)}(h`KVM_DEV_XIVE_GRP_SOURCE (write only) Initializes a new source in the XIVE device and mask it. h]h)}(hhh]h)}(h^KVM_DEV_XIVE_GRP_SOURCE (write only) Initializes a new source in the XIVE device and mask it. h](h)}(h$KVM_DEV_XIVE_GRP_SOURCE (write only)h]h$KVM_DEV_XIVE_GRP_SOURCE (write only)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjjubh)}(hhh]h)}(h8Initializes a new source in the XIVE device and mask it.h]h8Initializes a new source in the XIVE device and mask it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhj|ubah}(h]h ]h"]h$]h&]uh1hhjjubeh}(h]h ]h"]h$]h&]uh1hhhhKdhjgubah}(h]h ]h"]h$]h&]uh1hhjcubah}(h]h ]h"]h$]h&]uh1hhj`hhhNhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jchhhhhhhKcubj)}(hX8Attributes: Interrupt source number (64-bit) The kvm_device_attr.addr points to a __u64 value:: bits: | 63 .... 2 | 1 | 0 values: | unused | level | type - type: 0:MSI 1:LSI - level: assertion level in case of an LSI. Errors: ======= ========================================== -E2BIG Interrupt source number is out of range -ENOMEM Could not create a new source block -EFAULT Invalid user pointer for attr->addr. -ENXIO Could not allocate underlying HW interrupt ======= ========================================== h](h)}(hhh]h)}(h.Attributes: Interrupt source number (64-bit) h](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjubh)}(hhh]h)}(h!Interrupt source number (64-bit)h]h!Interrupt source number (64-bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKghjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h2The kvm_device_attr.addr points to a __u64 value::h]h1The kvm_device_attr.addr points to a __u64 value:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjubh literal_block)}(hNbits: | 63 .... 2 | 1 | 0 values: | unused | level | typeh]hNbits: | 63 .... 2 | 1 | 0 values: | unused | level | type}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKkhjubh)}(hhh](h)}(htype: 0:MSI 1:LSIh]h)}(hj h]htype: 0:MSI 1:LSI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h*level: assertion level in case of an LSI. h]h)}(h)level: assertion level in case of an LSI.h]h)level: assertion level in case of an LSI.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKohjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]jjuh1hhhhKnhjubh)}(hErrors:h]hErrors:}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjubj)}(hX(======= ========================================== -E2BIG Interrupt source number is out of range -ENOMEM Could not create a new source block -EFAULT Invalid user pointer for attr->addr. -ENXIO Could not allocate underlying HW interrupt ======= ========================================== h]jb)}(hhh]jg)}(hhh](jl)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhjRubjl)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jkhjRubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-E2BIGh]h-E2BIG}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjoubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(hhh]h)}(h'Interrupt source number is out of rangeh]h'Interrupt source number is out of range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh](j)}(hhh]h)}(h-ENOMEMh]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h#Could not create a new source blockh]h#Could not create a new source block}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h*Could not allocate underlying HW interrupth]h*Could not allocate underlying HW interrupt}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKwhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]colsKuh1jfhjOubah}(h]h ]h"]h$]h&]uh1jahjKubah}(h]h ]h"]h$]h&]uh1jhhhKshjubeh}(h]h ]h"]h$]h&]uh1jhhhKfhhhhubjd)}(hhh]h)}(hJKVM_DEV_XIVE_GRP_SOURCE_CONFIG (write only) Configures source targeting h]h)}(hhh]h)}(hHKVM_DEV_XIVE_GRP_SOURCE_CONFIG (write only) Configures source targeting h](h)}(h+KVM_DEV_XIVE_GRP_SOURCE_CONFIG (write only)h]h+KVM_DEV_XIVE_GRP_SOURCE_CONFIG (write only)}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjqubh)}(hhh]h)}(hConfigures source targetingh]hConfigures source targeting}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1hhjqubeh}(h]h ]h"]h$]h&]uh1hhhhK{hjnubah}(h]h ]h"]h$]h&]uh1hhjjubah}(h]h ]h"]h$]h&]uh1hhjghhhNhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jchhhhhhhKzubj)}(hXXAttributes: Interrupt source number (64-bit) The kvm_device_attr.addr points to a __u64 value:: bits: | 63 .... 33 | 32 | 31 .. 3 | 2 .. 0 values: | eisn | mask | server | priority - priority: 0-7 interrupt priority level - server: CPU number chosen to handle the interrupt - mask: mask flag (unused) - eisn: Effective Interrupt Source Number Errors: ======= ======================================================= -ENOENT Unknown source number -EINVAL Not initialized source number -EINVAL Invalid priority -EINVAL Invalid CPU number. -EFAULT Invalid user pointer for attr->addr. -ENXIO CPU event queues not configured or configuration of the underlying HW interrupt failed -EBUSY No CPU available to serve interrupt ======= ======================================================= h](h)}(hhh]h)}(h.Attributes: Interrupt source number (64-bit) h](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjubh)}(hhh]h)}(h!Interrupt source number (64-bit)h]h!Interrupt source number (64-bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK~hjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(h2The kvm_device_attr.addr points to a __u64 value::h]h1The kvm_device_attr.addr points to a __u64 value:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(hjbits: | 63 .... 33 | 32 | 31 .. 3 | 2 .. 0 values: | eisn | mask | server | priorityh]hjbits: | 63 .... 33 | 32 | 31 .. 3 | 2 .. 0 values: | eisn | mask | server | priority}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubh)}(hhh](h)}(h&priority: 0-7 interrupt priority levelh]h)}(hjh]h&priority: 0-7 interrupt priority level}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(h1server: CPU number chosen to handle the interrupth]h)}(hj&h]h1server: CPU number chosen to handle the interrupt}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hmask: mask flag (unused)h]h)}(hj=h]hmask: mask flag (unused)}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj;ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(h(eisn: Effective Interrupt Source Number h]h)}(h'eisn: Effective Interrupt Source Numberh]h'eisn: Effective Interrupt Source Number}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]jjuh1hhhhKhjubh)}(hErrors:h]hErrors:}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(hX======= ======================================================= -ENOENT Unknown source number -EINVAL Not initialized source number -EINVAL Invalid priority -EINVAL Invalid CPU number. -EFAULT Invalid user pointer for attr->addr. -ENXIO CPU event queues not configured or configuration of the underlying HW interrupt failed -EBUSY No CPU available to serve interrupt ======= ======================================================= h]jb)}(hhh]jg)}(hhh](jl)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhjubjl)}(hhh]h}(h]h ]h"]h$]h&]colwidthK7uh1jkhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENOENTh]h-ENOENT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hUnknown source numberh]hUnknown source number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hNot initialized source numberh]hNot initialized source number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInvalid priorityh]hInvalid priority}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj'ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjGubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(hInvalid CPU number.h]hInvalid CPU number.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj^ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj~ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hVCPU event queues not configured or configuration of the underlying HW interrupt failedh]hVCPU event queues not configured or configuration of the underlying HW interrupt failed}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h#No CPU available to serve interrupth]h#No CPU available to serve interrupt}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jfhjubah}(h]h ]h"]h$]h&]uh1jahj~ubah}(h]h ]h"]h$]h&]uh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhhhK}hhhhubjd)}(hhh]h)}(hMKVM_DEV_XIVE_GRP_EQ_CONFIG (read-write) Configures an event queue of a CPU h]h)}(hhh]h)}(hKKVM_DEV_XIVE_GRP_EQ_CONFIG (read-write) Configures an event queue of a CPU h](h)}(h'KVM_DEV_XIVE_GRP_EQ_CONFIG (read-write)h]h'KVM_DEV_XIVE_GRP_EQ_CONFIG (read-write)}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjI ubh)}(hhh]h)}(h"Configures an event queue of a CPUh]h"Configures an event queue of a CPU}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj[ ubah}(h]h ]h"]h$]h&]uh1hhjI ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjF ubah}(h]h ]h"]h$]h&]uh1hhjB ubah}(h]h ]h"]h$]h&]uh1hhj? hhhNhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jchhhhhhhKubj)}(hXAAttributes: EQ descriptor identifier (64-bit) The EQ descriptor identifier is a tuple (server, priority):: bits: | 63 .... 32 | 31 .. 3 | 2 .. 0 values: | unused | server | priority The kvm_device_attr.addr points to:: struct kvm_ppc_xive_eq { __u32 flags; __u32 qshift; __u64 qaddr; __u32 qtoggle; __u32 qindex; __u8 pad[40]; }; - flags: queue flags KVM_XIVE_EQ_ALWAYS_NOTIFY (required) forces notification without using the coalescing mechanism provided by the XIVE END ESBs. - qshift: queue size (power of 2) - qaddr: real address of queue - qtoggle: current queue toggle bit - qindex: current queue index - pad: reserved for future use Errors: ======= ========================================= -ENOENT Invalid CPU number -EINVAL Invalid priority -EINVAL Invalid flags -EINVAL Invalid queue size -EINVAL Invalid queue address -EFAULT Invalid user pointer for attr->addr. -EIO Configuration of the underlying HW failed ======= ========================================= h](h)}(hhh]h)}(h.Attributes: EQ descriptor identifier (64-bit) h](h)}(h Attributes:h]h Attributes:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h!EQ descriptor identifier (64-bit)h]h!EQ descriptor identifier (64-bit)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(haddr. -EIO Configuration of the underlying HW failed ======= ========================================= h]jb)}(hhh]jg)}(hhh](jl)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhj ubjl)}(hhh]h}(h]h ]h"]h$]h&]colwidthK)uh1jkhj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENOENTh]h-ENOENT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInvalid CPU numberh]hInvalid CPU number}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj0 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjS hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjP ubah}(h]h ]h"]h$]h&]uh1jhjM ubj)}(hhh]h)}(hInvalid priorityh]hInvalid priority}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjg ubah}(h]h ]h"]h$]h&]uh1jhjM ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Invalid flagsh]h Invalid flags}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInvalid queue sizeh]hInvalid queue size}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInvalid queue addressh]hInvalid queue address}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj/ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj, ubah}(h]h ]h"]h$]h&]uh1jhj) ubj)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hjF hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjC ubah}(h]h ]h"]h$]h&]uh1jhj) ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EIOh]h-EIO}(hjf hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjc ubah}(h]h ]h"]h$]h&]uh1jhj` ubj)}(hhh]h)}(h)Configuration of the underlying HW failedh]h)Configuration of the underlying HW failed}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjz ubah}(h]h ]h"]h$]h&]uh1jhj` ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jfhj ubah}(h]h ]h"]h$]h&]uh1jahj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhhhhubjd)}(hhh]h)}(h`KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only) Synchronize the source to flush event notifications h]h)}(hhh]h)}(h^KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only) Synchronize the source to flush event notifications h](h)}(h)KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only)h]h)KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h3Synchronize the source to flush event notificationsh]h3Synchronize the source to flush event notifications}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhj hhhNhNubah}(h]h ]h"]h$]h&]jjjhjjj#Kuh1jchhhhhhhKubj)}(hAttributes: Interrupt source number (64-bit) Errors: ======= ============================= -ENOENT Unknown source number -EINVAL Not initialized source number ======= ============================= h](h)}(hhh]h)}(h.Attributes: Interrupt source number (64-bit) h](h)}(h Attributes:h]h Attributes:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hhh]h)}(h!Interrupt source number (64-bit)h]h!Interrupt source number (64-bit)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubh)}(hErrors:h]hErrors:}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubj)}(h======= ============================= -ENOENT Unknown source number -EINVAL Not initialized source number ======= ============================= h]jb)}(hhh]jg)}(hhh](jl)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhjR ubjl)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jkhjR ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENOENTh]h-ENOENT}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjo ubah}(h]h ]h"]h$]h&]uh1jhjl ubj)}(hhh]h)}(hUnknown source numberh]hUnknown source number}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjl ubeh}(h]h ]h"]h$]h&]uh1jhji ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hNot initialized source numberh]hNot initialized source number}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhji ubeh}(h]h ]h"]h$]h&]uh1jhjR ubeh}(h]h ]h"]h$]h&]colsKuh1jfhjO ubah}(h]h ]h"]h$]h&]uh1jahjK ubah}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhhhhubh)}(hhh](h)}(hXVCPU state The XIVE IC maintains VP interrupt state in an internal structure called the NVT. When a VP is not dispatched on a HW processor thread, this structure can be updated by HW if the VP is the target of an event notification. It is important for migration to capture the cached IPB from the NVT as it synthesizes the priorities of the pending interrupts. We capture a bit more to report debug information. KVM_REG_PPC_VP_STATE (2 * 64bits):: bits: | 63 .... 32 | 31 .... 0 | values: | TIMA word0 | TIMA word1 | bits: | 127 .......... 64 | values: | unused | h](h)}(h VCPU stateh]h VCPU state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hThe XIVE IC maintains VP interrupt state in an internal structure called the NVT. When a VP is not dispatched on a HW processor thread, this structure can be updated by HW if the VP is the target of an event notification.h]hThe XIVE IC maintains VP interrupt state in an internal structure called the NVT. When a VP is not dispatched on a HW processor thread, this structure can be updated by HW if the VP is the target of an event notification.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hIt is important for migration to capture the cached IPB from the NVT as it synthesizes the priorities of the pending interrupts. We capture a bit more to report debug information.h]hIt is important for migration to capture the cached IPB from the NVT as it synthesizes the priorities of the pending interrupts. We capture a bit more to report debug information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(h#KVM_REG_PPC_VP_STATE (2 * 64bits)::h]h"KVM_REG_PPC_VP_STATE (2 * 64bits):}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubj)}(hbits: | 63 .... 32 | 31 .... 0 | values: | TIMA word0 | TIMA word1 | bits: | 127 .......... 64 | values: | unused |h]hbits: | 63 .... 32 | 31 .... 0 | values: | TIMA word0 | TIMA word1 | bits: | 127 .......... 64 | values: | unused |}hj8sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hXMigration: Saving the state of a VM using the XIVE native exploitation mode should follow a specific sequence. When the VM is stopped : 1. Mask all sources (PQ=01) to stop the flow of events. 2. Sync the XIVE device with the KVM control KVM_DEV_XIVE_EQ_SYNC to flush any in-flight event notification and to stabilize the EQs. At this stage, the EQ pages are marked dirty to make sure they are transferred in the migration sequence. 3. Capture the state of the source targeting, the EQs configuration and the state of thread interrupt context registers. Restore is similar: 1. Restore the EQ configuration. As targeting depends on it. 2. Restore targeting 3. Restore the thread interrupt contexts 4. Restore the source states 5. Let the vCPU runh](h)}(h Migration:h]h Migration:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubh)}(h|Saving the state of a VM using the XIVE native exploitation mode should follow a specific sequence. When the VM is stopped :h]h|Saving the state of a VM using the XIVE native exploitation mode should follow a specific sequence. When the VM is stopped :}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubjd)}(hhh]h)}(h5Mask all sources (PQ=01) to stop the flow of events. h]h)}(h4Mask all sources (PQ=01) to stop the flow of events.h]h4Mask all sources (PQ=01) to stop the flow of events.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjoubah}(h]h ]h"]h$]h&]uh1hhjlubah}(h]h ]h"]h$]h&]jjjhjjuh1jchjLubh)}(h2. Sync the XIVE device with the KVM control KVM_DEV_XIVE_EQ_SYNC to flush any in-flight event notification and to stabilize the EQs. At this stage, the EQ pages are marked dirty to make sure they are transferred in the migration sequence.h]h2. Sync the XIVE device with the KVM control KVM_DEV_XIVE_EQ_SYNC to flush any in-flight event notification and to stabilize the EQs. At this stage, the EQ pages are marked dirty to make sure they are transferred in the migration sequence.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubh)}(hx3. Capture the state of the source targeting, the EQs configuration and the state of thread interrupt context registers.h]hx3. Capture the state of the source targeting, the EQs configuration and the state of thread interrupt context registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubh)}(hRestore is similar:h]hRestore is similar:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubjd)}(hhh](h)}(h9Restore the EQ configuration. As targeting depends on it.h]h)}(hjh]h9Restore the EQ configuration. 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