sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget)/translations/zh_CN/virt/kvm/devices/vcpumodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/zh_TW/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/it_IT/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ja_JP/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/ko_KR/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/pt_BR/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget)/translations/sp_SP/virt/kvm/devices/vcpumodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhC/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/vcpu.rsthKubhsection)}(hhh](htitle)}(hGeneric vcpu interfaceh]hGeneric vcpu interface}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hThe virtual cpu "device" also accepts the ioctls KVM_SET_DEVICE_ATTR, KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same struct kvm_device_attr as other devices, but targets VCPU-wide settings and controls.h]hThe virtual cpu “device” also accepts the ioctls KVM_SET_DEVICE_ATTR, KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same struct kvm_device_attr as other devices, but targets VCPU-wide settings and controls.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hMThe groups and attributes per virtual cpu, if any, are architecture specific.h]hMThe groups and attributes per virtual cpu, if any, are architecture specific.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hhh](h)}(h"1. GROUP: KVM_ARM_VCPU_PMU_V3_CTRLh]h"1. GROUP: KVM_ARM_VCPU_PMU_V3_CTRL}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubh field_body)}(hARM64 h]h)}(hARM64h]hARM64}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj(ubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubah}(h]h ]h"]h$]h&]uh1j hhhhhhhKubh)}(hhh](h)}(h'1.1. ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_IRQh]h'1.1. ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_IRQ}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhKubj )}(hhh]j)}(hhh](j)}(h Parametersh]h Parameters}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jhj`hhhKubj')}(hVin kvm_device_attr.addr the address for PMU overflow interrupt is a pointer to an int h]h)}(hUin kvm_device_attr.addr the address for PMU overflow interrupt is a pointer to an inth]hUin kvm_device_attr.addr the address for PMU overflow interrupt is a pointer to an int}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubah}(h]h ]h"]h$]h&]uh1j&hj`ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj]hhubah}(h]h ]h"]h$]h&]uh1j hjLhhhhhKubh)}(hReturns:h]hReturns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLhhubh block_quote)}(hX======= ======================================================== -EBUSY The PMU overflow interrupt is already set -EFAULT Error reading interrupt number -ENXIO PMUv3 not supported or the overflow interrupt not set when attempting to get it -ENODEV KVM_ARM_VCPU_PMU_V3 feature missing from VCPU -EINVAL Invalid PMU overflow interrupt number supplied or trying to set the IRQ number without using an in-kernel irqchip. ======= ======================================================== h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK8uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h)The PMU overflow interrupt is already seth]h)The PMU overflow interrupt is already set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hError reading interrupt numberh]hError reading interrupt number}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1jhj@ubj)}(hhh]h)}(hOPMUv3 not supported or the overflow interrupt not set when attempting to get ith]hOPMUv3 not supported or the overflow interrupt not set when attempting to get it}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjzubah}(h]h ]h"]h$]h&]uh1jhjwubj)}(hhh]h)}(h-KVM_ARM_VCPU_PMU_V3 feature missing from VCPUh]h-KVM_ARM_VCPU_PMU_V3 feature missing from VCPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hrInvalid PMU overflow interrupt number supplied or trying to set the IRQ number without using an in-kernel irqchip.h]hrInvalid PMU overflow interrupt number supplied or trying to set the IRQ number without using an in-kernel irqchip.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjLhhubh)}(hX-A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt type must be same for each vcpu. As a PPI, the interrupt number is the same for all vcpus, while as an SPI it must be a separate number per vcpu.h]hX-A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt type must be same for each vcpu. As a PPI, the interrupt number is the same for all vcpus, while as an SPI it must be a separate number per vcpu.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjLhhubh)}(hFor GICv5-based guests, the architected PPI (23) must be used, and must be communicated as the full GICv5-style Interrupt ID, i.e., 0x20000017. This ioctl can be omitted altogether for a GICv5-based guest.h]hFor GICv5-based guests, the architected PPI (23) must be used, and must be communicated as the full GICv5-style Interrupt ID, i.e., 0x20000017. This ioctl can be omitted altogether for a GICv5-based guest.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjLhhubeh}(h]!attribute-kvm-arm-vcpu-pmu-v3-irqah ]h"]'1.1. attribute: kvm_arm_vcpu_pmu_v3_irqah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h'1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INITh]h'1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhK/ubj )}(hhh]j)}(hhh](j)}(h Parametersh]h Parameters}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6hhhKubj')}(h0no additional parameter in kvm_device_attr.addr h]h)}(h/no additional parameter in kvm_device_attr.addrh]h/no additional parameter in kvm_device_attr.addr}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjGubah}(h]h ]h"]h$]h&]uh1j&hj6ubeh}(h]h ]h"]h$]h&]uh1jhhhK1hj3hhubah}(h]h ]h"]h$]h&]uh1j hj"hhhhhK1ubh)}(hReturns:h]hReturns:}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hj"hhubj)}(hX======= ====================================================== -EEXIST Interrupt number already used -ENODEV PMUv3 not supported or GIC not initialized -ENXIO PMUv3 not supported, missing VCPU feature, missing hardware PMU, or interrupt number not set (non-GICv5 guests, only) -EBUSY PMUv3 already initialized ======= ====================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK6uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-EEXISTh]h-EEXIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hInterrupt number already usedh]hInterrupt number already used}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h*PMUv3 not supported or GIC not initializedh]h*PMUv3 not supported or GIC not initialized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(huPMUv3 not supported, missing VCPU feature, missing hardware PMU, or interrupt number not set (non-GICv5 guests, only)h]huPMUv3 not supported, missing VCPU feature, missing hardware PMU, or interrupt number not set (non-GICv5 guests, only)}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK8hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(hPMUv3 already initializedh]hPMUv3 already initialized}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK;hjYubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhj}ubah}(h]h ]h"]h$]h&]uh1jhjyubah}(h]h ]h"]h$]h&]uh1jhhhK5hj"hhubh)}(hRequest the initialization of the PMUv3. If using the PMUv3 with an in-kernel virtual GIC implementation, this must be done after initializing the in-kernel irqchip.h]hRequest the initialization of the PMUv3. If using the PMUv3 with an in-kernel virtual GIC implementation, this must be done after initializing the in-kernel irqchip.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hj"hhubh)}(hmWhen the KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature is enabled this must be done after selecting a hardware PMU.h]hmWhen the KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature is enabled this must be done after selecting a hardware PMU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKBhj"hhubeh}(h]"attribute-kvm-arm-vcpu-pmu-v3-initah ]h"]'1.2 attribute: kvm_arm_vcpu_pmu_v3_initah$]h&]uh1hhhhhhhhK/ubh)}(hhh](h)}(h)1.3 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FILTERh]h)1.3 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FILTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKFubj )}(hhh](j)}(hhh](j)}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj')}(hiin kvm_device_attr.addr the address for a PMU event filter is a pointer to a struct kvm_pmu_event_filter h]h)}(hhin kvm_device_attr.addr the address for a PMU event filter is a pointer to a struct kvm_pmu_event_filterh]hhin kvm_device_attr.addr the address for a PMU event filter is a pointer to a struct kvm_pmu_event_filter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhKHhjhhubj)}(hhh](j)}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj')}(hX======= ====================================================== -ENODEV PMUv3 not supported or GIC not initialized -ENXIO PMUv3 not properly configured or in-kernel irqchip not configured as required prior to calling this attribute -EBUSY PMUv3 already initialized or a VCPU has already run -EINVAL Invalid filter range ======= ====================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK6uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhj+ubah}(h]h ]h"]h$]h&]uh1jhj(ubj)}(hhh]h)}(h*PMUv3 not supported or GIC not initializedh]h*PMUv3 not supported or GIC not initialized}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjBubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjbubah}(h]h ]h"]h$]h&]uh1jhj_ubj)}(hhh]h)}(hmPMUv3 not properly configured or in-kernel irqchip not configured as required prior to calling this attributeh]hmPMUv3 not properly configured or in-kernel irqchip not configured as required prior to calling this attribute}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjyubah}(h]h ]h"]h$]h&]uh1jhj_ubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h3PMUv3 already initialized or a VCPU has already runh]h3PMUv3 already initialized or a VCPU has already run}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hInvalid filter rangeh]hInvalid filter range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhKKhjhhubeh}(h]h ]h"]h$]h&]uh1j hjhhhhhKHubh)}(hERequest the installation of a PMU event filter described as follows::h]hDRequest the installation of a PMU event filter described as follows:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjhhubh literal_block)}(hstruct kvm_pmu_event_filter { __u16 base_event; __u16 nevents; #define KVM_PMU_EVENT_ALLOW 0 #define KVM_PMU_EVENT_DENY 1 __u8 action; __u8 pad[3]; };h]hstruct kvm_pmu_event_filter { __u16 base_event; __u16 nevents; #define KVM_PMU_EVENT_ALLOW 0 #define KVM_PMU_EVENT_DENY 1 __u8 action; __u8 pad[3]; };}hj9sbah}(h]h ]h"]h$]h&]hhuh1j7hhhKWhjhhubh)}(hXA filter range is defined as the range [@base_event, @base_event + @nevents), together with an @action (KVM_PMU_EVENT_ALLOW or KVM_PMU_EVENT_DENY). The first registered range defines the global policy (global ALLOW if the first @action is DENY, global DENY if the first @action is ALLOW). Multiple ranges can be programmed, and must fit within the event space defined by the PMU architecture (10 bits on ARMv8.0, 16 bits from ARMv8.1 onwards).h]hXA filter range is defined as the range [@base_event, @base_event + @nevents), together with an @action (KVM_PMU_EVENT_ALLOW or KVM_PMU_EVENT_DENY). The first registered range defines the global policy (global ALLOW if the first @action is DENY, global DENY if the first @action is ALLOW). Multiple ranges can be programmed, and must fit within the event space defined by the PMU architecture (10 bits on ARMv8.0, 16 bits from ARMv8.1 onwards).}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKbhjhhubh)}(hX"Note: "Cancelling" a filter by registering the opposite action for the same range doesn't change the default action. For example, installing an ALLOW filter for event range [0:10) as the first filter and then applying a DENY action for the same range will leave the whole range as disabled.h]hX(Note: “Cancelling” a filter by registering the opposite action for the same range doesn’t change the default action. For example, installing an ALLOW filter for event range [0:10) as the first filter and then applying a DENY action for the same range will leave the whole range as disabled.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjhhubh)}(hRestrictions: Event 0 (SW_INCR) is never filtered, as it doesn't count a hardware event. Filtering event 0x1E (CHAIN) has no effect either, as it isn't strictly speaking an event. Filtering the cycle counter is possible using event 0x11 (CPU_CYCLES).h]hRestrictions: Event 0 (SW_INCR) is never filtered, as it doesn’t count a hardware event. Filtering event 0x1E (CHAIN) has no effect either, as it isn’t strictly speaking an event. Filtering the cycle counter is possible using event 0x11 (CPU_CYCLES).}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubh)}(hmWhen the KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature is enabled this must be done after selecting a hardware PMU.h]hmWhen the KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature is enabled this must be done after selecting a hardware PMU.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjhhubeh}(h]$attribute-kvm-arm-vcpu-pmu-v3-filterah ]h"])1.3 attribute: kvm_arm_vcpu_pmu_v3_filterah$]h&]uh1hhhhhhhhKFubh)}(hhh](h)}(h*1.4 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_PMUh]h*1.4 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_PMU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKwubj )}(hhh](j)}(hhh](j)}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj')}(hOin kvm_device_attr.addr the address to an int representing the PMU identifier. h]h)}(hNin kvm_device_attr.addr the address to an int representing the PMU identifier.h]hNin kvm_device_attr.addr the address to an int representing the PMU identifier.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhKyhjhhubj)}(hhh](j)}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj')}(hX======= ==================================================== -EBUSY PMUv3 already initialized, a VCPU has already run or an event filter has already been set -EFAULT Error accessing the PMU identifier -ENXIO PMU not found -ENODEV PMUv3 not supported or GIC not initialized -ENOMEM Could not allocate memory ======= ==================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK4uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hYPMUv3 already initialized, a VCPU has already run or an event filter has already been seth]hYPMUv3 already initialized, a VCPU has already run or an event filter has already been set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj6ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]h)}(h"Error accessing the PMU identifierh]h"Error accessing the PMU identifier}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjMubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmubah}(h]h ]h"]h$]h&]uh1jhjjubj)}(hhh]h)}(h PMU not foundh]h PMU not found}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h*PMUv3 not supported or GIC not initializedh]h*PMUv3 not supported or GIC not initialized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENOMEMh]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCould not allocate memoryh]hCould not allocate memory}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhK|hjhhubeh}(h]h ]h"]h$]h&]uh1j hjhhhhhKyubh)}(hXRequest that the VCPU uses the specified hardware PMU when creating guest events for the purpose of PMU emulation. The PMU identifier can be read from the "type" file for the desired PMU instance under /sys/devices (or, equivalent, /sys/bus/even_source). This attribute is particularly useful on heterogeneous systems where there are at least two CPU PMUs on the system. The PMU that is set for one VCPU will be used by all the other VCPUs. It isn't possible to set a PMU if a PMU event filter is already present.h]hXRequest that the VCPU uses the specified hardware PMU when creating guest events for the purpose of PMU emulation. The PMU identifier can be read from the “type” file for the desired PMU instance under /sys/devices (or, equivalent, /sys/bus/even_source). This attribute is particularly useful on heterogeneous systems where there are at least two CPU PMUs on the system. The PMU that is set for one VCPU will be used by all the other VCPUs. It isn’t possible to set a PMU if a PMU event filter is already present.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hXNote that KVM will not make any attempts to run the VCPU on the physical CPUs associated with the PMU specified by this attribute. This is entirely left to userspace. However, attempting to run the VCPU on a physical CPU not supported by the PMU will fail and KVM_RUN will return with exit_reason = KVM_EXIT_FAIL_ENTRY and populate the fail_entry struct by setting hardare_entry_failure_reason field to KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED and the cpu field to the processor id.h]hXNote that KVM will not make any attempts to run the VCPU on the physical CPUs associated with the PMU specified by this attribute. This is entirely left to userspace. However, attempting to run the VCPU on a physical CPU not supported by the PMU will fail and KVM_RUN will return with exit_reason = KVM_EXIT_FAIL_ENTRY and populate the fail_entry struct by setting hardare_entry_failure_reason field to KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED and the cpu field to the processor id.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]%attribute-kvm-arm-vcpu-pmu-v3-set-pmuah ]h"]*1.4 attribute: kvm_arm_vcpu_pmu_v3_set_pmuah$]h&]uh1hhhhhhhhKwubh)}(hhh](h)}(h21.5 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERSh]h21.5 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhhhhhKubj )}(hhh](j)}(hhh](j)}(h Parametersh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jhjlhhhKubj')}(hjin kvm_device_attr.addr the address to an unsigned int representing the maximum value taken by PMCR_EL0.N h]h)}(hiin kvm_device_attr.addr the address to an unsigned int representing the maximum value taken by PMCR_EL0.Nh]hiin kvm_device_attr.addr the address to an unsigned int representing the maximum value taken by PMCR_EL0.N}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1j&hjlubeh}(h]h ]h"]h$]h&]uh1jhhhKhjihhubj)}(hhh](j)}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhhhKubj')}(hX======= ==================================================== -EBUSY PMUv3 already initialized, a VCPU has already run or an event filter has already been set -EFAULT Error accessing the value pointed to by addr -ENODEV PMUv3 not supported or GIC not initialized -EINVAL No PMUv3 explicitly selected, or value of N out of range ======= ==================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK4uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hYPMUv3 already initialized, a VCPU has already run or an event filter has already been seth]hYPMUv3 already initialized, a VCPU has already run or an event filter has already been set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h,Error accessing the value pointed to by addrh]h,Error accessing the value pointed to by addr}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj> ubah}(h]h ]h"]h$]h&]uh1jhj; ubj)}(hhh]h)}(h*PMUv3 not supported or GIC not initializedh]h*PMUv3 not supported or GIC not initialized}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjU ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhju ubah}(h]h ]h"]h$]h&]uh1jhjr ubj)}(hhh]h)}(h8No PMUv3 explicitly selected, or value of N out of rangeh]h8No PMUv3 explicitly selected, or value of N out of range}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjr ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1j&hjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjihhubeh}(h]h ]h"]h$]h&]uh1j hjXhhhhhKubh)}(hXQSet the number of implemented event counters in the virtual PMU. This mandates that a PMU has explicitly been selected via KVM_ARM_VCPU_PMU_V3_SET_PMU, and will fail when no PMU has been explicitly selected, or the number of counters is out of range for the selected PMU. Selecting a new PMU cancels the effect of setting this attribute.h]hXQSet the number of implemented event counters in the virtual PMU. This mandates that a PMU has explicitly been selected via KVM_ARM_VCPU_PMU_V3_SET_PMU, and will fail when no PMU has been explicitly selected, or the number of counters is out of range for the selected PMU. Selecting a new PMU cancels the effect of setting this attribute.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjXhhubeh}(h]-attribute-kvm-arm-vcpu-pmu-v3-set-nr-countersah ]h"]21.5 attribute: kvm_arm_vcpu_pmu_v3_set_nr_countersah$]h&]uh1hhhhhhhhKubeh}(h]group-kvm-arm-vcpu-pmu-v3-ctrlah ]h"]"1. group: kvm_arm_vcpu_pmu_v3_ctrlah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h!2. GROUP: KVM_ARM_VCPU_TIMER_CTRLh]h!2. GROUP: KVM_ARM_VCPU_TIMER_CTRL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj )}(hhh]j)}(hhh](j)}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hhhKubj')}(hARM64 h]h)}(hARM64h]hARM64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j&hj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubah}(h]h ]h"]h$]h&]uh1j hj hhhhhKubh)}(hhh](h)}(hG2.1. ATTRIBUTES: KVM_ARM_VCPU_TIMER_IRQ_{VTIMER,PTIMER,HVTIMER,HPTIMER}h]hG2.1. ATTRIBUTES: KVM_ARM_VCPU_TIMER_IRQ_{VTIMER,PTIMER,HVTIMER,HPTIMER}}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5 hhhhhKubj )}(hhh]j)}(hhh](j)}(h Parametersh]h Parameters}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjI hhhKubj')}(hSin kvm_device_attr.addr the address for the timer interrupt is a pointer to an int h]h)}(hRin kvm_device_attr.addr the address for the timer interrupt is a pointer to an inth]hRin kvm_device_attr.addr the address for the timer interrupt is a pointer to an int}(hj^ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZ ubah}(h]h ]h"]h$]h&]uh1j&hjI ubeh}(h]h ]h"]h$]h&]uh1jhhhKhjF hhubah}(h]h ]h"]h$]h&]uh1j hj5 hhhhhKubh)}(hReturns:h]hReturns:}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5 hhubj)}(h======= ================================= -EINVAL Invalid timer interrupt number -EBUSY One or more VCPUs has already run ======= ================================= h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1jhj ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hInvalid timer interrupt numberh]hInvalid timer interrupt number}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h!One or more VCPUs has already runh]h!One or more VCPUs has already run}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj5 hhubh)}(hA value describing the architected timer interrupt number when connected to an in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the attribute overrides the default values (see below).h]hA value describing the architected timer interrupt number when connected to an in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the attribute overrides the default values (see below).}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5 hhubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjE ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jhjE ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(hKVM_ARM_VCPU_TIMER_IRQ_VTIMERh]hKVM_ARM_VCPU_TIMER_IRQ_VTIMER}(hje hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjb ubah}(h]h ]h"]h$]h&]uh1jhj_ ubj)}(hhh]h)}(h)The EL1 virtual timer intid (default: 27)h]h)The EL1 virtual timer intid (default: 27)}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjy ubah}(h]h ]h"]h$]h&]uh1jhj_ ubeh}(h]h ]h"]h$]h&]uh1jhj\ ubj)}(hhh](j)}(hhh]h)}(hKVM_ARM_VCPU_TIMER_IRQ_PTIMERh]hKVM_ARM_VCPU_TIMER_IRQ_PTIMER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h*The EL1 physical timer intid (default: 30)h]h*The EL1 physical timer intid (default: 30)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj\ ubj)}(hhh](j)}(hhh]h)}(hKVM_ARM_VCPU_TIMER_IRQ_HVTIMERh]hKVM_ARM_VCPU_TIMER_IRQ_HVTIMER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h)The EL2 virtual timer intid (default: 28)h]h)The EL2 virtual timer intid (default: 28)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj\ ubj)}(hhh](j)}(hhh]h)}(hKVM_ARM_VCPU_TIMER_IRQ_HPTIMERh]hKVM_ARM_VCPU_TIMER_IRQ_HPTIMER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h*The EL2 physical timer intid (default: 26)h]h*The EL2 physical timer intid (default: 26)}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj\ ubeh}(h]h ]h"]h$]h&]uh1jhjE ubeh}(h]h ]h"]h$]h&]colsKuh1jhjB ubah}(h]h ]h"]h$]h&]uh1jhj5 hhhhhNubh)}(hXSetting the same PPI for different timers will prevent the VCPUs from running. Setting the interrupt number on a VCPU configures all VCPUs created at that time to use the number provided for a given timer, overwriting any previously configured values on other VCPUs. Userspace should configure the interrupt numbers on at least one VCPU after creating all VCPUs and before running any VCPUs.h]hXSetting the same PPI for different timers will prevent the VCPUs from running. Setting the interrupt number on a VCPU configures all VCPUs created at that time to use the number provided for a given timer, overwriting any previously configured values on other VCPUs. Userspace should configure the interrupt numbers on at least one VCPU after creating all VCPUs and before running any VCPUs.}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5 hhubhtarget)}(h.. _kvm_arm_vcpu_pvtime_ctrl:h]h}(h]h ]h"]h$]h&]refidkvm-arm-vcpu-pvtime-ctrluh1j\ hKhj5 hhhhubeh}(h]?attributes-kvm-arm-vcpu-timer-irq-vtimer-ptimer-hvtimer-hptimerah ]h"]G2.1. attributes: kvm_arm_vcpu_timer_irq_{vtimer,ptimer,hvtimer,hptimer}ah$]h&]uh1hhj hhhhhKubeh}(h]group-kvm-arm-vcpu-timer-ctrlah ]h"]!2. group: kvm_arm_vcpu_timer_ctrlah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h"3. GROUP: KVM_ARM_VCPU_PVTIME_CTRLh]h"3. GROUP: KVM_ARM_VCPU_PVTIME_CTRL}(hj} hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjz hhhhhKubj )}(hhh]j)}(hhh](j)}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hhhKubj')}(hARM64 h]h)}(hARM64h]hARM64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j&hj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubah}(h]h ]h"]h$]h&]uh1j hjz hhhhhKubh)}(hhh](h)}(h&3.1 ATTRIBUTE: KVM_ARM_VCPU_PVTIME_IPAh]h&3.1 ATTRIBUTE: KVM_ARM_VCPU_PVTIME_IPA}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubj )}(hhh]j)}(hhh](j)}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj hhhKubj')}(h64-bit base address h]h)}(h64-bit base addressh]h64-bit base address}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j&hj ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj hhubah}(h]h ]h"]h$]h&]uh1j hj hhhhhKubh)}(hReturns:h]hReturns:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj)}(h======= ====================================== -ENXIO Stolen time not implemented -EEXIST Base address already set for this VCPU -EINVAL Base address not 64 byte aligned ======= ====================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj! ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK&uh1jhj! ubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj> ubah}(h]h ]h"]h$]h&]uh1jhj; ubj)}(hhh]h)}(hStolen time not implementedh]hStolen time not implemented}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjU ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jhj8 ubj)}(hhh](j)}(hhh]h)}(h-EEXISTh]h-EEXIST}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhju ubah}(h]h ]h"]h$]h&]uh1jhjr ubj)}(hhh]h)}(h&Base address already set for this VCPUh]h&Base address already set for this VCPU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjr ubeh}(h]h ]h"]h$]h&]uh1jhj8 ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h Base address not 64 byte alignedh]h Base address not 64 byte aligned}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj8 ubeh}(h]h ]h"]h$]h&]uh1jhj! ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhhhKhj hhubh)}(hXSpecifies the base address of the stolen time structure for this VCPU. The base address must be 64 byte aligned and exist within a valid guest memory region. See Documentation/virt/kvm/arm/pvtime.rst for more information including the layout of the stolen time structure.h]hXSpecifies the base address of the stolen time structure for this VCPU. The base address must be 64 byte aligned and exist within a valid guest memory region. See Documentation/virt/kvm/arm/pvtime.rst for more information including the layout of the stolen time structure.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]!attribute-kvm-arm-vcpu-pvtime-ipaah ]h"]&3.1 attribute: kvm_arm_vcpu_pvtime_ipaah$]h&]uh1hhjz hhhhhKubeh}(h](group-kvm-arm-vcpu-pvtime-ctrlji eh ]h"]("3. group: kvm_arm_vcpu_pvtime_ctrlkvm_arm_vcpu_pvtime_ctrleh$]h&]uh1hhhhhhhhK֌expect_referenced_by_name}jj^ sexpect_referenced_by_id}ji j^ subh)}(hhh](h)}(h4. GROUP: KVM_VCPU_TSC_CTRLh]h4. GROUP: KVM_VCPU_TSC_CTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubj )}(hhh]j)}(hhh](j)}(h Architecturesh]h Architectures}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0hhhKubj')}(hx86 h]h)}(hx86h]hx86}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjAubah}(h]h ]h"]h$]h&]uh1j&hj0ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj-hhubah}(h]h ]h"]h$]h&]uh1j hjhhhhhKubh)}(h"4.1 ATTRIBUTE: KVM_VCPU_TSC_OFFSETh]h"4.1 ATTRIBUTE: KVM_VCPU_TSC_OFFSET}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj )}(hhh]j)}(hhh](j)}(h Parametersh]h Parameters}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjvhhhKubj')}(h64-bit unsigned TSC offset h]h)}(h64-bit unsigned TSC offseth]h64-bit unsigned TSC offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j&hjvubeh}(h]h ]h"]h$]h&]uh1jhhhKhjshhubah}(h]h ]h"]h$]h&]uh1j hjhhhhhKubh)}(hReturns:h]hReturns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h======= ====================================== -EFAULT Error reading/writing the provided parameter address. -ENXIO Attribute not supported ======= ====================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK&uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h5Error reading/writing the provided parameter address.h]h5Error reading/writing the provided parameter address.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAttribute not supportedh]hAttribute not supported}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhKhjhhubh)}(hwSpecifies the guest's TSC offset relative to the host's TSC. The guest's TSC is then derived by the following equation:h]h}Specifies the guest’s TSC offset relative to the host’s TSC. The guest’s TSC is then derived by the following equation:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h+guest_tsc = host_tsc + KVM_VCPU_TSC_OFFSET h]h)}(h*guest_tsc = host_tsc + KVM_VCPU_TSC_OFFSETh]h*guest_tsc = host_tsc + KVM_VCPU_TSC_OFFSET}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubah}(h]h ]h"]h$]h&]uh1jhhhMhjhhubh)}(hThis attribute is useful to adjust the guest's TSC on live migration, so that the TSC counts the time during which the VM was paused. The following describes a possible algorithm to use for this purpose.h]hThis attribute is useful to adjust the guest’s TSC on live migration, so that the TSC counts the time during which the VM was paused. The following describes a possible algorithm to use for this purpose.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hFrom the source VMM process:h]hFrom the source VMM process:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubhenumerated_list)}(hhh](h list_item)}(hInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_src), kvmclock nanoseconds (guest_src), and host CLOCK_REALTIME nanoseconds (host_src). h]h)}(hInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_src), kvmclock nanoseconds (guest_src), and host CLOCK_REALTIME nanoseconds (host_src).h]hInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_src), kvmclock nanoseconds (guest_src), and host CLOCK_REALTIME nanoseconds (host_src).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hcRead the KVM_VCPU_TSC_OFFSET attribute for every vCPU to record the guest TSC offset (ofs_src[i]). h]h)}(hbRead the KVM_VCPU_TSC_OFFSET attribute for every vCPU to record the guest TSC offset (ofs_src[i]).h]hbRead the KVM_VCPU_TSC_OFFSET attribute for every vCPU to record the guest TSC offset (ofs_src[i]).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hTInvoke the KVM_GET_TSC_KHZ ioctl to record the frequency of the guest's TSC (freq). h]h)}(hSInvoke the KVM_GET_TSC_KHZ ioctl to record the frequency of the guest's TSC (freq).h]hUInvoke the KVM_GET_TSC_KHZ ioctl to record the frequency of the guest’s TSC (freq).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1jhjhhhhhMubh)}(h!From the destination VMM process:h]h!From the destination VMM process:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(hX=Invoke the KVM_SET_CLOCK ioctl, providing the source nanoseconds from kvmclock (guest_src) and CLOCK_REALTIME (host_src) in their respective fields. Ensure that the KVM_CLOCK_REALTIME flag is set in the provided structure. KVM will advance the VM's kvmclock to account for elapsed time since recording the clock values. Note that this will cause problems in the guest (e.g., timeouts) unless CLOCK_REALTIME is synchronized between the source and destination, and a reasonably short time passes between the source pausing the VMs and the destination executing steps 4-7. h](h)}(hInvoke the KVM_SET_CLOCK ioctl, providing the source nanoseconds from kvmclock (guest_src) and CLOCK_REALTIME (host_src) in their respective fields. Ensure that the KVM_CLOCK_REALTIME flag is set in the provided structure.h]hInvoke the KVM_SET_CLOCK ioctl, providing the source nanoseconds from kvmclock (guest_src) and CLOCK_REALTIME (host_src) in their respective fields. Ensure that the KVM_CLOCK_REALTIME flag is set in the provided structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hX[KVM will advance the VM's kvmclock to account for elapsed time since recording the clock values. Note that this will cause problems in the guest (e.g., timeouts) unless CLOCK_REALTIME is synchronized between the source and destination, and a reasonably short time passes between the source pausing the VMs and the destination executing steps 4-7.h]hX]KVM will advance the VM’s kvmclock to account for elapsed time since recording the clock values. Note that this will cause problems in the guest (e.g., timeouts) unless CLOCK_REALTIME is synchronized between the source and destination, and a reasonably short time passes between the source pausing the VMs and the destination executing steps 4-7.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hhInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_dest) and kvmclock nanoseconds (guest_dest). h]h)}(hgInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_dest) and kvmclock nanoseconds (guest_dest).h]hgInvoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_dest) and kvmclock nanoseconds (guest_dest).}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj4ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hXAdjust the guest TSC offsets for every vCPU to account for (1) time elapsed since recording state and (2) difference in TSCs between the source and destination machine: ofs_dst[i] = ofs_src[i] - (guest_src - guest_dest) * freq + (tsc_src - tsc_dest) ("ofs[i] + tsc - guest * freq" is the guest TSC value corresponding to a time of 0 in kvmclock. The above formula ensures that it is the same on the destination as it was on the source). h](h)}(hAdjust the guest TSC offsets for every vCPU to account for (1) time elapsed since recording state and (2) difference in TSCs between the source and destination machine:h]hAdjust the guest TSC offsets for every vCPU to account for (1) time elapsed since recording state and (2) difference in TSCs between the source and destination machine:}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjLubhdefinition_list)}(hhh]hdefinition_list_item)}(hQofs_dst[i] = ofs_src[i] - (guest_src - guest_dest) * freq + (tsc_src - tsc_dest) h](hterm)}(hofs_dst[i] = ofs_src[i] -h]hofs_dst[i] = ofs_src[i] -}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jihhhM)hjeubh definition)}(hhh]h)}(h6(guest_src - guest_dest) * freq + (tsc_src - tsc_dest)h]h6(guest_src - guest_dest) * freq + (tsc_src - tsc_dest)}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj{ubah}(h]h ]h"]h$]h&]uh1jyhjeubeh}(h]h ]h"]h$]h&]uh1jchhhM)hj`ubah}(h]h ]h"]h$]h&]uh1j^hjLubh)}(h("ofs[i] + tsc - guest * freq" is the guest TSC value corresponding to a time of 0 in kvmclock. The above formula ensures that it is the same on the destination as it was on the source).h]h(“ofs[i] + tsc - guest * freq” is the guest TSC value corresponding to a time of 0 in kvmclock. The above formula ensures that it is the same on the destination as it was on the source).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjLubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hnWrite the KVM_VCPU_TSC_OFFSET attribute for every vCPU with the respective value derived in the previous step.h]h)}(hnWrite the KVM_VCPU_TSC_OFFSET attribute for every vCPU with the respective value derived in the previous step.h]hnWrite the KVM_VCPU_TSC_OFFSET attribute for every vCPU with the respective value derived in the previous step.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjstartKuh1jhjhhhhhMubeh}(h]group-kvm-vcpu-tsc-ctrlah ]h"]4. group: kvm_vcpu_tsc_ctrlah$]h&]uh1hhhhhhhhKubeh}(h]generic-vcpu-interfaceah ]h"]generic vcpu interfaceah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}ji ]j^ asnameids}(jjj j jjjjjjjUjRj j jw jt jo jl jji jjj j jju nametypes}(jj jjjjUj jw jo jjj juh}(jhj hjjLjj"jjjRjj jXjt j jl j5 ji jz jjz j j jju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]hsystem_message)}(hhh]h)}(h:Enumerated list start value not ordinal-1: "4" (ordinal 4)h]h>Enumerated list start value not ordinal-1: “4” (ordinal 4)}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehnjlineKuh1jfhjhhhhhMubatransform_messages]jg)}(hhh]h)}(hhh]h>Hyperlink target "kvm-arm-vcpu-pvtime-ctrl" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypejsourcehnjlineKuh1jfuba transformerN include_log] decorationNhhub.