€•«8      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ)/translations/zh_CN/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/zh_TW/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/it_IT/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/ja_JP/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/ko_KR/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/pt_BR/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ)/translations/sp_SP/virt/kvm/devices/mpic”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1hµhhh²hh³ŒC/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/mpic.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒMPIC interrupt controller”h]”hŒMPIC interrupt controller”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ	paragraph”“”)”}”(hŒDevice types supported:”h]”hŒDevice types supported:”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒblock_quote”“”)”}”(hŒf- KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0
- KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2
”h]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒ0KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0”h]”hÞ)”}”(hhüh]”hŒ0KVM_DEV_TYPE_FSL_MPIC_20     Freescale MPIC v2.0”…””}”(hhþh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K	hhúubah}”(h]”h ]”h"]”h$]”h&]”uh1høhhõubhù)”}”(hŒ1KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2
”h]”hÞ)”}”(hŒ0KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2”h]”hŒ0KVM_DEV_TYPE_FSL_MPIC_42     Freescale MPIC v4.2”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K
hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1høhhõubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hóh³hÇh´K	hhïubah}”(h]”h ]”h"]”h$]”h&]”uh1híh³hÇh´K	hhÊh²hubhÞ)”}”(hŒ¤Only one MPIC instance, of any type, may be instantiated.  The created
MPIC will act as the system interrupt controller, connecting to each
vcpu's interrupt inputs.”h]”hŒ¦Only one MPIC instance, of any type, may be instantiated.  The created
MPIC will act as the system interrupt controller, connecting to each
vcpuâ€™s interrupt inputs.”…””}”(hj7  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hXù  Groups:
KVM_DEV_MPIC_GRP_MISC
 Attributes:

  KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
    Base address of the 256 KiB MPIC register space.  Must be
    naturally aligned.  A value of zero disables the mapping.
    Reset value is zero.

KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
  Access an MPIC register, as if the access were made from the guest.
  "attr" is the byte offset into the MPIC register space.  Accesses
  must be 4-byte aligned.

  MSIs may be signaled by using this attribute group to write
  to the relevant MSIIR.

KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
  IRQ input line for each standard openpic source.  0 is inactive and 1
  is active, regardless of interrupt sense.

  For edge-triggered interrupts:  Writing 1 is considered an activating
  edge, and writing 0 is ignored.  Reading returns 1 if a previously
  signaled edge has not been acknowledged, and 0 otherwise.

  "attr" is the IRQ number.  IRQ numbers for standard sources are the
  byte offset of the relevant IVPR from EIVPR0, divided by 32.
”h]”(hŒterm”“”)”}”(hŒGroups:”h]”hŒGroups:”…””}”(hjR  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jP  h³hÇh´K*hjL  ubhŒ
definition”“”)”}”(hhh]”jF  )”}”(hhh]”(jK  )”}”(hŒÚKVM_DEV_MPIC_GRP_MISC
Attributes:

 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
   Base address of the 256 KiB MPIC register space.  Must be
   naturally aligned.  A value of zero disables the mapping.
   Reset value is zero.
”h]”(jQ  )”}”(hŒKVM_DEV_MPIC_GRP_MISC”h]”hŒKVM_DEV_MPIC_GRP_MISC”…””}”(hjl  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jP  h³hÇh´Khjh  ubja  )”}”(hhh]”(hÞ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hj}  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjz  ubhî)”}”(hŒ³KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
  Base address of the 256 KiB MPIC register space.  Must be
  naturally aligned.  A value of zero disables the mapping.
  Reset value is zero.
”h]”jF  )”}”(hhh]”jK  )”}”(hŒ­KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
Base address of the 256 KiB MPIC register space.  Must be
naturally aligned.  A value of zero disables the mapping.
Reset value is zero.
”h]”(jQ  )”}”(hŒ#KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)”h]”hŒ#KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)”…””}”(hj–  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jP  h³hÇh´Khj’  ubja  )”}”(hhh]”hÞ)”}”(hŒˆBase address of the 256 KiB MPIC register space.  Must be
naturally aligned.  A value of zero disables the mapping.
Reset value is zero.”h]”hŒˆBase address of the 256 KiB MPIC register space.  Must be
naturally aligned.  A value of zero disables the mapping.
Reset value is zero.”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj¤  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j`  hj’  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jJ  h³hÇh´Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jE  hj‹  ubah}”(h]”h ]”h"]”h$]”h&]”uh1híh³hÇh´Khjz  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j`  hjh  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jJ  h³hÇh´Khje  ubjK  )”}”(hX  KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
Access an MPIC register, as if the access were made from the guest.
"attr" is the byte offset into the MPIC register space.  Accesses
must be 4-byte aligned.

MSIs may be signaled by using this attribute group to write
to the relevant MSIIR.
”h]”(jQ  )”}”(hŒ&KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)”h]”hŒ&KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)”…””}”(hjÝ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jP  h³hÇh´KhjÙ  ubja  )”}”(hhh]”(hÞ)”}”(hŒAccess an MPIC register, as if the access were made from the guest.
"attr" is the byte offset into the MPIC register space.  Accesses
must be 4-byte aligned.”h]”hŒ¡Access an MPIC register, as if the access were made from the guest.
â€œattrâ€ is the byte offset into the MPIC register space.  Accesses
must be 4-byte aligned.”…””}”(hjî  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjë  ubhÞ)”}”(hŒRMSIs may be signaled by using this attribute group to write
to the relevant MSIIR.”h]”hŒRMSIs may be signaled by using this attribute group to write
to the relevant MSIIR.”…””}”(hjü  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjë  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j`  hjÙ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jJ  h³hÇh´Khje  ubjK  )”}”(hXß  KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
IRQ input line for each standard openpic source.  0 is inactive and 1
is active, regardless of interrupt sense.

For edge-triggered interrupts:  Writing 1 is considered an activating
edge, and writing 0 is ignored.  Reading returns 1 if a previously
signaled edge has not been acknowledged, and 0 otherwise.

"attr" is the IRQ number.  IRQ numbers for standard sources are the
byte offset of the relevant IVPR from EIVPR0, divided by 32.
”h]”(jQ  )”}”(hŒ(KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)”h]”hŒ(KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jP  h³hÇh´K*hj  ubja  )”}”(hhh]”(hÞ)”}”(hŒoIRQ input line for each standard openpic source.  0 is inactive and 1
is active, regardless of interrupt sense.”h]”hŒoIRQ input line for each standard openpic source.  0 is inactive and 1
is active, regardless of interrupt sense.”…””}”(hj+  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K"hj(  ubhÞ)”}”(hŒÂFor edge-triggered interrupts:  Writing 1 is considered an activating
edge, and writing 0 is ignored.  Reading returns 1 if a previously
signaled edge has not been acknowledged, and 0 otherwise.”h]”hŒÂFor edge-triggered interrupts:  Writing 1 is considered an activating
edge, and writing 0 is ignored.  Reading returns 1 if a previously
signaled edge has not been acknowledged, and 0 otherwise.”…””}”(hj9  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K%hj(  ubhÞ)”}”(hŒ€"attr" is the IRQ number.  IRQ numbers for standard sources are the
byte offset of the relevant IVPR from EIVPR0, divided by 32.”h]”hŒ„â€œattrâ€ is the IRQ number.  IRQ numbers for standard sources are the
byte offset of the relevant IVPR from EIVPR0, divided by 32.”…””}”(hjG  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K)hj(  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j`  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jJ  h³hÇh´K*hje  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jE  hjb  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j`  hjL  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jJ  h³hÇh´K*hjG  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jE  hhÊh²hh³Nh´NubhÞ)”}”(hŒIRQ Routing:”h]”hŒIRQ Routing:”…””}”(hjy  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K,hhÊh²hubhî)”}”(hX[  The MPIC emulation supports IRQ routing. Only a single MPIC device can
be instantiated. Once that device has been created, it's available as
irqchip id 0.

This irqchip 0 has 256 interrupt pins, which expose the interrupts in
the main array of interrupt sources (a.k.a. "SRC" interrupts).

The numbering is the same as the MPIC device tree binding -- based on
the register offset from the beginning of the sources array, without
regard to any subdivisions in chip documentation such as "internal"
or "external" interrupts.

Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.”h]”(hÞ)”}”(hŒšThe MPIC emulation supports IRQ routing. Only a single MPIC device can
be instantiated. Once that device has been created, it's available as
irqchip id 0.”h]”hŒœThe MPIC emulation supports IRQ routing. Only a single MPIC device can
be instantiated. Once that device has been created, itâ€™s available as
irqchip id 0.”…””}”(hj‹  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K.hj‡  ubhÞ)”}”(hŒ„This irqchip 0 has 256 interrupt pins, which expose the interrupts in
the main array of interrupt sources (a.k.a. "SRC" interrupts).”h]”hŒˆThis irqchip 0 has 256 interrupt pins, which expose the interrupts in
the main array of interrupt sources (a.k.a. â€œSRCâ€ interrupts).”…””}”(hj™  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K2hj‡  ubhÞ)”}”(hŒèThe numbering is the same as the MPIC device tree binding -- based on
the register offset from the beginning of the sources array, without
regard to any subdivisions in chip documentation such as "internal"
or "external" interrupts.”h]”hŒðThe numbering is the same as the MPIC device tree binding -- based on
the register offset from the beginning of the sources array, without
regard to any subdivisions in chip documentation such as â€œinternalâ€
or â€œexternalâ€ interrupts.”…””}”(hj§  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K5hj‡  ubhÞ)”}”(hŒOAccess to non-SRC interrupts is not implemented through IRQ routing mechanisms.”h]”hŒOAccess to non-SRC interrupts is not implemented through IRQ routing mechanisms.”…””}”(hjµ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K:hj‡  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1híh³hÇh´K.hhÊh²hubeh}”(h]”Œmpic-interrupt-controller”ah ]”h"]”Œmpic interrupt controller”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
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id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nh²hub.