sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget-/translations/zh_CN/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/zh_TW/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/it_IT/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ja_JP/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ko_KR/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/pt_BR/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/sp_SP/virt/kvm/devices/arm-vgicmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhG/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/arm-vgic.rsthKubhsection)}(hhh](htitle)}(h2ARM Virtual Generic Interrupt Controller v2 (VGIC)h]h2ARM Virtual Generic Interrupt Controller v2 (VGIC)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hDevice types supported:h]hDevice types supported:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hE- KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 h]h bullet_list)}(hhh]h list_item)}(hCKVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 h]h)}(hBKVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0h]hBKVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXOnly one VGIC instance may be instantiated through either this API or the legacy KVM_CREATE_IRQCHIP API. The created VGIC will act as the VM interrupt controller, requiring emulated user-space devices to inject interrupts to the VGIC instead of directly to CPUs.h]hXOnly one VGIC instance may be instantiated through either this API or the legacy KVM_CREATE_IRQCHIP API. The created VGIC will act as the VM interrupt controller, requiring emulated user-space devices to inject interrupts to the VGIC instead of directly to CPUs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXGICv3 implementations with hardware compatibility support allow creating a guest GICv2 through this interface. For information on creating a guest GICv3 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to create both a GICv3 and GICv2 device on the same VM.h]hXGICv3 implementations with hardware compatibility support allow creating a guest GICv2 through this interface. For information on creating a guest GICv3 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to create both a GICv3 and GICv2 device on the same VM.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhdefinition_list)}(hhh]hdefinition_list_item)}(hXGroups: KVM_DEV_ARM_VGIC_GRP_ADDR Attributes: KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) Base address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte. KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) Base address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte. Errors: ======= ============================================================= -E2BIG Address outside of addressable IPA range -EINVAL Incorrectly aligned address -EEXIST Address already configured -ENXIO The group or attribute is unknown/unsupported for this device or hardware support is missing. -EFAULT Invalid user pointer for attr->addr. ======= ============================================================= KVM_DEV_ARM_VGIC_GRP_DIST_REGS Attributes: The attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All distributor regs are (rw, 32-bit) The offset is relative to the "Distributor base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware from the cpu whose index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register. GICD_IIDR.Revision is updated when the KVM implementation of an emulated GICv2 is changed in a way directly observable by the guest or userspace. Userspace should read GICD_IIDR from KVM and write back the read value to confirm its expected behavior is aligned with the KVM implementation. Userspace should set GICD_IIDR before setting any other registers (both KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure the expected behavior. Unless GICD_IIDR has been set from userspace, writes to the interrupt group registers (GICD_IGROUPR) are ignored. Errors: ======= ===================================================== -ENXIO Getting or setting this register is not yet supported -EBUSY One or more VCPUs are running -EINVAL Invalid vcpu_index supplied ======= ===================================================== KVM_DEV_ARM_VGIC_GRP_CPU_REGS Attributes: The attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All CPU interface regs are (rw, 32-bit) The offset specifies the offset from the "CPU interface base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware. The Active Priorities Registers APRn are implementation defined, so we set a fixed format for our implementation that fits with the model of a "GICv2 implementation without the security extensions" which we present to the guest. This interface always exposes four register APR[0-3] describing the maximum possible 128 preemption levels. The semantics of the register indicate if any interrupts in a given preemption level are in the active state by setting the corresponding bit. Thus, preemption level X has one or more active interrupts if and only if: APRn[X mod 32] == 0b1, where n = X / 32 Bits for undefined preemption levels are RAZ/WI. Note that this differs from a CPU's view of the APRs on hardware in which a GIC without the security extensions expose group 0 and group 1 active priorities in separate register groups, whereas we show a combined view similar to GICv2's GICH_APR. For historical reasons and to provide ABI compatibility with userspace we export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. Errors: ======= ===================================================== -ENXIO Getting or setting this register is not yet supported -EBUSY One or more VCPUs are running -EINVAL Invalid vcpu_index supplied ======= ===================================================== KVM_DEV_ARM_VGIC_GRP_NR_IRQS Attributes: A value describing the number of interrupts (SGI, PPI and SPI) for this GIC instance, ranging from 64 to 1024, in increments of 32. Errors: ======= ============================================================= -EINVAL Value set is out of the expected range -EBUSY Value has already be set, or GIC has already been initialized with default values. ======= ============================================================= KVM_DEV_ARM_VGIC_GRP_CTRL Attributes: KVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr. Errors: ======= ========================================================= -ENXIO VGIC not properly configured as required prior to calling this attribute -ENODEV no online VCPU -ENOMEM memory shortage when allocating vgic internal data ======= =========================================================h](hterm)}(hGroups:h]hGroups:}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjCubh definition)}(hhh](j=)}(hhh]jB)}(hX#KVM_DEV_ARM_VGIC_GRP_ADDR Attributes: KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) Base address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte. KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) Base address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte. h](jH)}(hKVM_DEV_ARM_VGIC_GRP_ADDRh]hKVM_DEV_ARM_VGIC_GRP_ADDR}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhK"hj_ubjX)}(hhh](h)}(h Attributes:h]h Attributes:}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubh)}(hXKVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) Base address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte. KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) Base address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte. h]j=)}(hhh](jB)}(hKVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) Base address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte. h](jH)}(h'KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)h]h'KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjubjX)}(hhh]h)}(hBase address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte.h]hBase address in the guest physical address space of the GIC distributor register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 4 KByte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhKhjubjB)}(hKVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) Base address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte. h](jH)}(h&KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)h]h&KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhK"hjubjX)}(hhh]h)}(hBase address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte.h]hBase address in the guest physical address space of the GIC virtual cpu interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2. This address needs to be 4K aligned and the region covers 8 KByte.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhK"hjubeh}(h]h ]h"]h$]h&]uh1j<hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubeh}(h]h ]h"]h$]h&]uh1jWhj_ubeh}(h]h ]h"]h$]h&]uh1jAhhhK"hj\ubah}(h]h ]h"]h$]h&]uh1j<hjYubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjYubh)}(hX======= ============================================================= -E2BIG Address outside of addressable IPA range -EINVAL Incorrectly aligned address -EEXIST Address already configured -ENXIO The group or attribute is unknown/unsupported for this device or hardware support is missing. -EFAULT Invalid user pointer for attr->addr. ======= ============================================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j!hjubj")}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1j!hjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h-E2BIGh]h-E2BIG}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjCubah}(h]h ]h"]h$]h&]uh1jAhj>ubjB)}(hhh]h)}(h(Address outside of addressable IPA rangeh]h(Address outside of addressable IPA range}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjZubah}(h]h ]h"]h$]h&]uh1jAhj>ubeh}(h]h ]h"]h$]h&]uh1j<hj9ubj=)}(hhh](jB)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjzubah}(h]h ]h"]h$]h&]uh1jAhjwubjB)}(hhh]h)}(hIncorrectly aligned addressh]hIncorrectly aligned address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jAhjwubeh}(h]h ]h"]h$]h&]uh1j<hj9ubj=)}(hhh](jB)}(hhh]h)}(h-EEXISTh]h-EEXIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(hAddress already configuredh]hAddress already configured}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hj9ubj=)}(hhh](jB)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(h]The group or attribute is unknown/unsupported for this device or hardware support is missing.h]h]The group or attribute is unknown/unsupported for this device or hardware support is missing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hj9ubj=)}(hhh](jB)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hj6ubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hj9ubeh}(h]h ]h"]h$]h&]uh1j7hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK&hjYubj=)}(hhh]jB)}(hXKVM_DEV_ARM_VGIC_GRP_DIST_REGS Attributes: The attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All distributor regs are (rw, 32-bit) The offset is relative to the "Distributor base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware from the cpu whose index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register. GICD_IIDR.Revision is updated when the KVM implementation of an emulated GICv2 is changed in a way directly observable by the guest or userspace. Userspace should read GICD_IIDR from KVM and write back the read value to confirm its expected behavior is aligned with the KVM implementation. Userspace should set GICD_IIDR before setting any other registers (both KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure the expected behavior. Unless GICD_IIDR has been set from userspace, writes to the interrupt group registers (GICD_IGROUPR) are ignored. h](jH)}(hKVM_DEV_ARM_VGIC_GRP_DIST_REGSh]hKVM_DEV_ARM_VGIC_GRP_DIST_REGS}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKGhjoubjX)}(hhh](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubh)}(hXThe attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All distributor regs are (rw, 32-bit) The offset is relative to the "Distributor base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware from the cpu whose index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register. GICD_IIDR.Revision is updated when the KVM implementation of an emulated GICv2 is changed in a way directly observable by the guest or userspace. Userspace should read GICD_IIDR from KVM and write back the read value to confirm its expected behavior is aligned with the KVM implementation. Userspace should set GICD_IIDR before setting any other registers (both KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure the expected behavior. Unless GICD_IIDR has been set from userspace, writes to the interrupt group registers (GICD_IGROUPR) are ignored. h](h)}(h6The attr field of kvm_device_attr encodes two values::h]h5The attr field of kvm_device_attr encodes two values:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubh literal_block)}(hubits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset |h]hubits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset |}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK4hjubh)}(h%All distributor regs are (rw, 32-bit)h]h%All distributor regs are (rw, 32-bit)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjubh)}(hXThe offset is relative to the "Distributor base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware from the cpu whose index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register.h]hXThe offset is relative to the “Distributor base address” as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware from the cpu whose index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjubh)}(hX>GICD_IIDR.Revision is updated when the KVM implementation of an emulated GICv2 is changed in a way directly observable by the guest or userspace. Userspace should read GICD_IIDR from KVM and write back the read value to confirm its expected behavior is aligned with the KVM implementation. Userspace should set GICD_IIDR before setting any other registers (both KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure the expected behavior. Unless GICD_IIDR has been set from userspace, writes to the interrupt group registers (GICD_IGROUPR) are ignored.h]hX>GICD_IIDR.Revision is updated when the KVM implementation of an emulated GICv2 is changed in a way directly observable by the guest or userspace. Userspace should read GICD_IIDR from KVM and write back the read value to confirm its expected behavior is aligned with the KVM implementation. Userspace should set GICD_IIDR before setting any other registers (both KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure the expected behavior. Unless GICD_IIDR has been set from userspace, writes to the interrupt group registers (GICD_IGROUPR) are ignored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjubeh}(h]h ]h"]h$]h&]uh1hhhhK2hjubeh}(h]h ]h"]h$]h&]uh1jWhjoubeh}(h]h ]h"]h$]h&]uh1jAhhhKGhjlubah}(h]h ]h"]h$]h&]uh1j<hjYubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKIhjYubh)}(hX ======= ===================================================== -ENXIO Getting or setting this register is not yet supported -EBUSY One or more VCPUs are running -EINVAL Invalid vcpu_index supplied ======= ===================================================== h]j)}(hhh]j)}(hhh](j")}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j!hj ubj")}(hhh]h}(h]h ]h"]h$]h&]colwidthK5uh1j!hj ubj8)}(hhh](j=)}(hhh](jB)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj(ubah}(h]h ]h"]h$]h&]uh1jAhj%ubjB)}(hhh]h)}(h5Getting or setting this register is not yet supportedh]h5Getting or setting this register is not yet supported}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj?ubah}(h]h ]h"]h$]h&]uh1jAhj%ubeh}(h]h ]h"]h$]h&]uh1j<hj"ubj=)}(hhh](jB)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhj_ubah}(h]h ]h"]h$]h&]uh1jAhj\ubjB)}(hhh]h)}(hOne or more VCPUs are runningh]hOne or more VCPUs are running}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjvubah}(h]h ]h"]h$]h&]uh1jAhj\ubeh}(h]h ]h"]h$]h&]uh1j<hj"ubj=)}(hhh](jB)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(hInvalid vcpu_index suppliedh]hInvalid vcpu_index supplied}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hj"ubeh}(h]h ]h"]h$]h&]uh1j7hj ubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKKhjYubj=)}(hhh]jB)}(hXKVM_DEV_ARM_VGIC_GRP_CPU_REGS Attributes: The attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All CPU interface regs are (rw, 32-bit) The offset specifies the offset from the "CPU interface base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware. The Active Priorities Registers APRn are implementation defined, so we set a fixed format for our implementation that fits with the model of a "GICv2 implementation without the security extensions" which we present to the guest. This interface always exposes four register APR[0-3] describing the maximum possible 128 preemption levels. The semantics of the register indicate if any interrupts in a given preemption level are in the active state by setting the corresponding bit. Thus, preemption level X has one or more active interrupts if and only if: APRn[X mod 32] == 0b1, where n = X / 32 Bits for undefined preemption levels are RAZ/WI. Note that this differs from a CPU's view of the APRs on hardware in which a GIC without the security extensions expose group 0 and group 1 active priorities in separate register groups, whereas we show a combined view similar to GICv2's GICH_APR. For historical reasons and to provide ABI compatibility with userspace we export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. h](jH)}(hKVM_DEV_ARM_VGIC_GRP_CPU_REGSh]hKVM_DEV_ARM_VGIC_GRP_CPU_REGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKvhjubjX)}(hhh](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubh)}(hXThe attr field of kvm_device_attr encodes two values:: bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset | All CPU interface regs are (rw, 32-bit) The offset specifies the offset from the "CPU interface base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware. The Active Priorities Registers APRn are implementation defined, so we set a fixed format for our implementation that fits with the model of a "GICv2 implementation without the security extensions" which we present to the guest. This interface always exposes four register APR[0-3] describing the maximum possible 128 preemption levels. The semantics of the register indicate if any interrupts in a given preemption level are in the active state by setting the corresponding bit. Thus, preemption level X has one or more active interrupts if and only if: APRn[X mod 32] == 0b1, where n = X / 32 Bits for undefined preemption levels are RAZ/WI. Note that this differs from a CPU's view of the APRs on hardware in which a GIC without the security extensions expose group 0 and group 1 active priorities in separate register groups, whereas we show a combined view similar to GICv2's GICH_APR. For historical reasons and to provide ABI compatibility with userspace we export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. h](h)}(h6The attr field of kvm_device_attr encodes two values::h]h5The attr field of kvm_device_attr encodes two values:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThj ubj)}(hubits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset |h]hubits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | values: | reserved | vcpu_index | offset |}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKVhj ubh)}(h'All CPU interface regs are (rw, 32-bit)h]h'All CPU interface regs are (rw, 32-bit)}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhj ubh)}(hThe offset specifies the offset from the "CPU interface base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware.h]hThe offset specifies the offset from the “CPU interface base address” as defined in the GICv2 specs. Getting or setting such a register has the same effect as reading or writing the register on the actual hardware.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hj ubh)}(hXThe Active Priorities Registers APRn are implementation defined, so we set a fixed format for our implementation that fits with the model of a "GICv2 implementation without the security extensions" which we present to the guest. This interface always exposes four register APR[0-3] describing the maximum possible 128 preemption levels. The semantics of the register indicate if any interrupts in a given preemption level are in the active state by setting the corresponding bit.h]hXThe Active Priorities Registers APRn are implementation defined, so we set a fixed format for our implementation that fits with the model of a “GICv2 implementation without the security extensions” which we present to the guest. This interface always exposes four register APR[0-3] describing the maximum possible 128 preemption levels. The semantics of the register indicate if any interrupts in a given preemption level are in the active state by setting the corresponding bit.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hj ubh)}(hJThus, preemption level X has one or more active interrupts if and only if:h]hJThus, preemption level X has one or more active interrupts if and only if:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghj ubh)}(h)APRn[X mod 32] == 0b1, where n = X / 32 h]h)}(h(APRn[X mod 32] == 0b1, where n = X / 32h]h(APRn[X mod 32] == 0b1, where n = X / 32}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjaubah}(h]h ]h"]h$]h&]uh1hhhhKihj ubh)}(h0Bits for undefined preemption levels are RAZ/WI.h]h0Bits for undefined preemption levels are RAZ/WI.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhj ubh)}(hNote that this differs from a CPU's view of the APRs on hardware in which a GIC without the security extensions expose group 0 and group 1 active priorities in separate register groups, whereas we show a combined view similar to GICv2's GICH_APR.h]hNote that this differs from a CPU’s view of the APRs on hardware in which a GIC without the security extensions expose group 0 and group 1 active priorities in separate register groups, whereas we show a combined view similar to GICv2’s GICH_APR.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKmhj ubh)}(hXcFor historical reasons and to provide ABI compatibility with userspace we export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level.h]hXcFor historical reasons and to provide ABI compatibility with userspace we export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKThjubeh}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhKvhjubah}(h]h ]h"]h$]h&]uh1j<hjYubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjYubh)}(hX ======= ===================================================== -ENXIO Getting or setting this register is not yet supported -EBUSY One or more VCPUs are running -EINVAL Invalid vcpu_index supplied ======= ===================================================== h]j)}(hhh]j)}(hhh](j")}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j!hjubj")}(hhh]h}(h]h ]h"]h$]h&]colwidthK5uh1j!hjubj8)}(hhh](j=)}(hhh](jB)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(h5Getting or setting this register is not yet supportedh]h5Getting or setting this register is not yet supported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hjubj=)}(hhh](jB)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hj$ubah}(h]h ]h"]h$]h&]uh1jAhj!ubjB)}(hhh]h)}(hOne or more VCPUs are runningh]hOne or more VCPUs are running}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK|hj;ubah}(h]h ]h"]h$]h&]uh1jAhj!ubeh}(h]h ]h"]h$]h&]uh1j<hjubj=)}(hhh](jB)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hj[ubah}(h]h ]h"]h$]h&]uh1jAhjXubjB)}(hhh]h)}(hInvalid vcpu_index suppliedh]hInvalid vcpu_index supplied}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hjrubah}(h]h ]h"]h$]h&]uh1jAhjXubeh}(h]h ]h"]h$]h&]uh1j<hjubeh}(h]h ]h"]h$]h&]uh1j7hjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKzhjYubj=)}(hhh]jB)}(hKVM_DEV_ARM_VGIC_GRP_NR_IRQS Attributes: A value describing the number of interrupts (SGI, PPI and SPI) for this GIC instance, ranging from 64 to 1024, in increments of 32. h](jH)}(hKVM_DEV_ARM_VGIC_GRP_NR_IRQSh]hKVM_DEV_ARM_VGIC_GRP_NR_IRQS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjubjX)}(hhh](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hA value describing the number of interrupts (SGI, PPI and SPI) for this GIC instance, ranging from 64 to 1024, in increments of 32. h]h)}(hA value describing the number of interrupts (SGI, PPI and SPI) for this GIC instance, ranging from 64 to 1024, in increments of 32.h]hA value describing the number of interrupts (SGI, PPI and SPI) for this GIC instance, ranging from 64 to 1024, in increments of 32.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhKhjubah}(h]h ]h"]h$]h&]uh1j<hjYubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubh)}(hX#======= ============================================================= -EINVAL Value set is out of the expected range -EBUSY Value has already be set, or GIC has already been initialized with default values. ======= ============================================================= h]j)}(hhh]j)}(hhh](j")}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j!hj ubj")}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1j!hj ubj8)}(hhh](j=)}(hhh](jB)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj*ubah}(h]h ]h"]h$]h&]uh1jAhj'ubjB)}(hhh]h)}(h&Value set is out of the expected rangeh]h&Value set is out of the expected range}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjAubah}(h]h ]h"]h$]h&]uh1jAhj'ubeh}(h]h ]h"]h$]h&]uh1j<hj$ubj=)}(hhh](jB)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjaubah}(h]h ]h"]h$]h&]uh1jAhj^ubjB)}(hhh]h)}(hRValue has already be set, or GIC has already been initialized with default values.h]hRValue has already be set, or GIC has already been initialized with default values.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjxubah}(h]h ]h"]h$]h&]uh1jAhj^ubeh}(h]h ]h"]h$]h&]uh1j<hj$ubeh}(h]h ]h"]h$]h&]uh1j7hj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubj=)}(hhh]jB)}(hKVM_DEV_ARM_VGIC_GRP_CTRL Attributes: KVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr. h](jH)}(hKVM_DEV_ARM_VGIC_GRP_CTRLh]hKVM_DEV_ARM_VGIC_GRP_CTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjubjX)}(hhh](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hKVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr. h]j=)}(hhh]jB)}(h{KVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr. h](jH)}(hKVM_DEV_ARM_VGIC_CTRL_INITh]hKVM_DEV_ARM_VGIC_CTRL_INIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jGhhhKhjubjX)}(hhh]h)}(h_request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr.h]h_request the initialization of the VGIC or ITS, no additional parameter in kvm_device_attr.addr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhKhjubah}(h]h ]h"]h$]h&]uh1j<hjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1jWhjubeh}(h]h ]h"]h$]h&]uh1jAhhhKhjubah}(h]h ]h"]h$]h&]uh1j<hjYubh)}(hErrors:h]hErrors:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubh)}(hX4======= ========================================================= -ENXIO VGIC not properly configured as required prior to calling this attribute -ENODEV no online VCPU -ENOMEM memory shortage when allocating vgic internal data ======= =========================================================h]j)}(hhh]j)}(hhh](j")}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j!hj=ubj")}(hhh]h}(h]h ]h"]h$]h&]colwidthK9uh1j!hj=ubj8)}(hhh](j=)}(hhh](jB)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjZubah}(h]h ]h"]h$]h&]uh1jAhjWubjB)}(hhh]h)}(hHVGIC not properly configured as required prior to calling this attributeh]hHVGIC not properly configured as required prior to calling this attribute}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjqubah}(h]h ]h"]h$]h&]uh1jAhjWubeh}(h]h ]h"]h$]h&]uh1j<hjTubj=)}(hhh](jB)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(hno online VCPUh]hno online VCPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hjTubj=)}(hhh](jB)}(hhh]h)}(h-ENOMEMh]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jAhjubjB)}(hhh]h)}(h2memory shortage when allocating vgic internal datah]h2memory shortage when allocating vgic internal data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jAhjubeh}(h]h ]h"]h$]h&]uh1j<hjTubeh}(h]h ]h"]h$]h&]uh1j7hj=ubeh}(h]h ]h"]h$]h&]colsKuh1jhj:ubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhhhKhjYubeh}(h]h ]h"]h$]h&]uh1jWhjCubeh}(h]h ]h"]h$]h&]uh1jAhhhKhj>ubah}(h]h ]h"]h$]h&]uh1j<hhhhhhhNubeh}(h]0arm-virtual-generic-interrupt-controller-v2-vgicah ]h"]2arm virtual generic interrupt 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