€•ª      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ0/translations/zh_CN/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/zh_TW/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/it_IT/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ja_JP/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/ko_KR/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ0/translations/sp_SP/virt/kvm/devices/arm-vgic-v3”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒJ/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/arm-vgic-v3.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ>ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)”h]”hŒ>ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒ]Device types supported:
- KVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
”h]”(hŒterm”“”)”}”(hŒDevice types supported:”h]”hŒDevice types supported:”…””}”(hhÖhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h K	hhÐubhŒ
definition”“”)”}”(hhh]”hŒbullet_list”“”)”}”(hhh]”hŒ	list_item”“”)”}”(hŒCKVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
”h]”hŒ	paragraph”“”)”}”(hŒBKVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0”h]”hŒBKVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0”…””}”(hhöhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K	hhðubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhëubah}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1héhŸh³h K	hhæubah}”(h]”h ]”h"]”h$]”h&]”uh1hähhÐubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h K	hhËubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhh¶hžhhŸNh Nubhõ)”}”(hX   Only one VGIC instance may be instantiated through this API.  The created VGIC
will act as the VM interrupt controller, requiring emulated user-space devices
to inject interrupts to the VGIC instead of directly to CPUs.  It is not
possible to create both a GICv3 and GICv2 on the same VM.”h]”hX   Only one VGIC instance may be instantiated through this API.  The created VGIC
will act as the VM interrupt controller, requiring emulated user-space devices
to inject interrupts to the VGIC instead of directly to CPUs.  It is not
possible to create both a GICv3 and GICv2 on the same VM.”…””}”(hj$  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khh¶hžhubhõ)”}”(hŒ<Creating a guest GICv3 device requires a host GICv3 as well.”h]”hŒ<Creating a guest GICv3 device requires a host GICv3 as well.”…””}”(hj2  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khh¶hžhubhÊ)”}”(hhh]”hÏ)”}”(hXý/  Groups:
KVM_DEV_ARM_VGIC_GRP_ADDR
 Attributes:

  KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
    Base address in the guest physical address space of the GICv3 distributor
    register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
    This address needs to be 64K aligned and the region covers 64 KByte.

  KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
    Base address in the guest physical address space of the GICv3
    redistributor register mappings. There are two 64K pages for each
    VCPU and all of the redistributor pages are contiguous.
    Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
    This address needs to be 64K aligned.

  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
    The attribute data pointed to by kvm_device_attr.addr is a __u64 value::

      bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
      values:   |     count      |       base      |  flags   | index

    - index encodes the unique redistributor region index
    - flags: reserved for future use, currently 0
    - base field encodes bits [51:16] of the guest physical base address
      of the first redistributor in the region.
    - count encodes the number of redistributors in the region. Must be
      greater than 0.

    There are two 64K pages for each redistributor in the region and
    redistributors are laid out contiguously within the region. Regions
    are filled with redistributors in the index order. The sum of all
    region count fields must be greater than or equal to the number of
    VCPUs. Redistributor regions must be registered in the incremental
    index order, starting from index 0.

    The characteristics of a specific redistributor region can be read
    by presetting the index field in the attr data.
    Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.

It is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.

Note that to obtain reproducible results (the same VCPU being associated
with the same redistributor across a save/restore operation), VCPU creation
order, redistributor region creation order as well as the respective
interleaves of VCPU and region creation MUST be preserved.  Any change in
either ordering may result in a different vcpu_id/redistributor association,
resulting in a VM that will fail to run at restore time.

Errors:

  =======  =============================================================
  -E2BIG   Address outside of addressable IPA range
  -EINVAL  Incorrectly aligned address, bad redistributor region
           count/index, mixed redistributor region attribute usage
  -EEXIST  Address already configured
  -ENOENT  Attempt to read the characteristics of a non existing
           redistributor region
  -ENXIO   The group or attribute is unknown/unsupported for this device
           or hardware support is missing.
  -EFAULT  Invalid user pointer for attr->addr.
  =======  =============================================================


KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
 Attributes:

  The attr field of kvm_device_attr encodes two values::

    bits:     | 63   ....  32  |  31   ....    0 |
    values:   |      mpidr     |      offset     |

  All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
  __u32 value.  64-bit registers must be accessed by separately accessing the
  lower and higher word.

  Writes to read-only registers are ignored by the kernel.

  KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
  KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
  specified by the mpidr.

  The offset is relative to the "[Re]Distributor base address" as defined
  in the GICv3/4 specs.  Getting or setting such a register has the same
  effect as reading or writing the register on real hardware, except for the
  following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
  GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
  differently when accessed via this interface compared to their
  architecturally defined behavior to allow software a full view of the
  VGIC's internal state.

  The mpidr field is used to specify which
  redistributor is accessed.  The mpidr is ignored for the distributor.

  The mpidr encoding is based on the affinity information in the
  architecture defined MPIDR, and the field is encoded as follows::

    | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
    |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

  Note that distributor fields are not banked, but return the same value
  regardless of the mpidr used to access the register.

  GICD_IIDR.Revision is updated when the KVM implementation is changed in a
  way directly observable by the guest or userspace.  Userspace should read
  GICD_IIDR from KVM and write back the read value to confirm its expected
  behavior is aligned with the KVM implementation.  Userspace should set
  GICD_IIDR before setting any other registers to ensure the expected
  behavior.


  The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
  that a write of a clear bit has no effect, whereas a write with a set bit
  clears that value.  To allow userspace to freely set the values of these two
  registers, setting the attributes with the register offsets for these two
  registers simply sets the non-reserved bits to the value written.


  Accesses (reads and writes) to the GICD_ISPENDR register region and
  GICR_ISPENDR0 registers get/set the value of the latched pending state for
  the interrupts.

  This is identical to the value returned by a guest read from ISPENDR for an
  edge triggered interrupt, but may differ for level triggered interrupts.
  For edge triggered interrupts, once an interrupt becomes pending (whether
  because of an edge detected on the input line or because of a guest write
  to ISPENDR) this state is "latched", and only cleared when either the
  interrupt is activated or when the guest writes to ICPENDR. A level
  triggered interrupt may be pending either because the level input is held
  high by a device, or because of a guest write to the ISPENDR register. Only
  ISPENDR writes are latched; if the device lowers the line level then the
  interrupt is no longer pending unless the guest also wrote to ISPENDR, and
  conversely writes to ICPENDR or activations of the interrupt do not clear
  the pending status if the line level is still being held high.  (These
  rules are documented in the GICv3 specification descriptions of the ICPENDR
  and ISPENDR registers.) For a level triggered interrupt the value accessed
  here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
  interrupt activation, whereas the value returned by a guest read from
  ISPENDR is the logical OR of the latch value and the input line level.

  Raw access to the latch state is provided to userspace so that it can save
  and restore the entire GIC internal state (which is defined by the
  combination of the current input line level and the latch state, and cannot
  be deduced from purely the line level and the value of the ISPENDR
  registers).

  Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
  RAZ/WI semantics, meaning that reads always return 0 and writes are always
  ignored.

Errors:

  ======  =====================================================
  -ENXIO  Getting or setting this register is not yet supported
  -EBUSY  One or more VCPUs are running
  ======  =====================================================


KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
 Attributes:

  The attr field of kvm_device_attr encodes two values::

    bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
    values:   |         mpidr         |      RES     |    instr    |

  The mpidr field encodes the CPU ID based on the affinity information in the
  architecture defined MPIDR, and the field is encoded as follows::

    | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
    |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

  The instr field encodes the system register to access based on the fields
  defined in the A64 instruction set encoding for system register access
  (RES means the bits are reserved for future use and should be zero)::

    | 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
    |   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |

  All system regs accessed through this API are (rw, 64-bit) and
  kvm_device_attr.addr points to a __u64 value.

  KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
  CPU specified by the mpidr field.

  CPU interface registers access is not implemented for AArch32 mode.
  Error -ENXIO is returned when accessed in AArch32 mode.

Errors:

  =======  =====================================================
  -ENXIO   Getting or setting this register is not yet supported
  -EBUSY   VCPU is running
  -EINVAL  Invalid mpidr or register value supplied
  =======  =====================================================


KVM_DEV_ARM_VGIC_GRP_NR_IRQS
 Attributes:

  A value describing the number of interrupts (SGI, PPI and SPI) for
  this GIC instance, ranging from 64 to 1024, in increments of 32.

  kvm_device_attr.addr points to a __u32 value.

Errors:

  =======  ======================================
  -EINVAL  Value set is out of the expected range
  -EBUSY   Value has already be set.
  =======  ======================================


KVM_DEV_ARM_VGIC_GRP_CTRL
 Attributes:

  KVM_DEV_ARM_VGIC_CTRL_INIT
    request the initialization of the VGIC, no additional parameter in
    kvm_device_attr.addr. Must be called after all VCPUs have been created.
  KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
    save all LPI pending bits into guest RAM pending tables.

    The first kB of the pending table is not altered by this operation.

Errors:

  =======  ========================================================
  -ENXIO   VGIC not properly configured as required prior to calling
           this attribute
  -ENODEV  no online VCPU
  -ENOMEM  memory shortage when allocating vgic internal data
  -EFAULT  Invalid guest ram access
  -EBUSY   One or more VCPUS are running
  =======  ========================================================


KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
 Attributes:

  The attr field of kvm_device_attr encodes the following values::

    bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
    values:   |         mpidr         |      info       |   vINTID   |

  The vINTID specifies which set of IRQs is reported on.

  The info field specifies which information userspace wants to get or set
  using this interface.  Currently we support the following info values:

    VGIC_LEVEL_INFO_LINE_LEVEL:
      Get/Set the input level of the IRQ line for a set of 32 contiguously
      numbered interrupts.

      vINTID must be a multiple of 32.

      kvm_device_attr.addr points to a __u32 value which will contain a
      bitmap where a set bit means the interrupt level is asserted.

      Bit[n] indicates the status for interrupt vINTID + n.

  SGIs and any interrupt with a higher ID than the number of interrupts
  supported, will be RAZ/WI.  LPIs are always edge-triggered and are
  therefore not supported by this interface.

  PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
  reported with the same value regardless of the mpidr specified.

  The mpidr field encodes the CPU ID based on the affinity information in the
  architecture defined MPIDR, and the field is encoded as follows::

    | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
    |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

Errors:
  =======  =============================================
  -EINVAL  vINTID is not multiple of 32 or info field is
           not VGIC_LEVEL_INFO_LINE_LEVEL
  =======  =============================================

KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ
 Attributes:

  The attr field of kvm_device_attr encodes the following values:

    bits:     | 31   ....    5 | 4  ....  0 |
    values:   |      RES0      |   vINTID   |

  The vINTID specifies which interrupt is generated when the vGIC
  must generate a maintenance interrupt. This must be a PPI.”h]”(hÕ)”}”(hŒGroups:”h]”hŒGroups:”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h M3hjC  ubhå)”}”(hhh]”(hÊ)”}”(hhh]”hÏ)”}”(hXØ  KVM_DEV_ARM_VGIC_GRP_ADDR
Attributes:

 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
   Base address in the guest physical address space of the GICv3 distributor
   register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
   This address needs to be 64K aligned and the region covers 64 KByte.

 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
   Base address in the guest physical address space of the GICv3
   redistributor register mappings. There are two 64K pages for each
   VCPU and all of the redistributor pages are contiguous.
   Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
   This address needs to be 64K aligned.

 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
   The attribute data pointed to by kvm_device_attr.addr is a __u64 value::

     bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
     values:   |     count      |       base      |  flags   | index

   - index encodes the unique redistributor region index
   - flags: reserved for future use, currently 0
   - base field encodes bits [51:16] of the guest physical base address
     of the first redistributor in the region.
   - count encodes the number of redistributors in the region. Must be
     greater than 0.

   There are two 64K pages for each redistributor in the region and
   redistributors are laid out contiguously within the region. Regions
   are filled with redistributors in the index order. The sum of all
   region count fields must be greater than or equal to the number of
   VCPUs. Redistributor regions must be registered in the incremental
   index order, starting from index 0.

   The characteristics of a specific redistributor region can be read
   by presetting the index field in the attr data.
   Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_GRP_ADDR”h]”hŒKVM_DEV_ARM_VGIC_GRP_ADDR”…””}”(hj_  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h K9hj[  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hjp  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khjm  ubhŒblock_quote”“”)”}”(hX”  KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
  Base address in the guest physical address space of the GICv3 distributor
  register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
  This address needs to be 64K aligned and the region covers 64 KByte.

KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
  Base address in the guest physical address space of the GICv3
  redistributor register mappings. There are two 64K pages for each
  VCPU and all of the redistributor pages are contiguous.
  Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
  This address needs to be 64K aligned.

KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
  The attribute data pointed to by kvm_device_attr.addr is a __u64 value::

    bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
    values:   |     count      |       base      |  flags   | index

  - index encodes the unique redistributor region index
  - flags: reserved for future use, currently 0
  - base field encodes bits [51:16] of the guest physical base address
    of the first redistributor in the region.
  - count encodes the number of redistributors in the region. Must be
    greater than 0.

  There are two 64K pages for each redistributor in the region and
  redistributors are laid out contiguously within the region. Regions
  are filled with redistributors in the index order. The sum of all
  region count fields must be greater than or equal to the number of
  VCPUs. Redistributor regions must be registered in the incremental
  index order, starting from index 0.

  The characteristics of a specific redistributor region can be read
  by presetting the index field in the attr data.
  Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
”h]”hÊ)”}”(hhh]”(hÏ)”}”(hŒóKVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
Base address in the guest physical address space of the GICv3 distributor
register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned and the region covers 64 KByte.
”h]”(hÕ)”}”(hŒ'KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)”h]”hŒ'KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)”…””}”(hj‹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h Khj‡  ubhå)”}”(hhh]”hõ)”}”(hŒÊBase address in the guest physical address space of the GICv3 distributor
register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned and the region covers 64 KByte.”h]”hŒÊBase address in the guest physical address space of the GICv3 distributor
register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned and the region covers 64 KByte.”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Khj™  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hähj‡  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h Khj„  ubhÏ)”}”(hX1  KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
Base address in the guest physical address space of the GICv3
redistributor register mappings. There are two 64K pages for each
VCPU and all of the redistributor pages are contiguous.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned.
”h]”(hÕ)”}”(hŒ)KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)”h]”hŒ)KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h K!hj¶  ubhå)”}”(hhh]”hõ)”}”(hX  Base address in the guest physical address space of the GICv3
redistributor register mappings. There are two 64K pages for each
VCPU and all of the redistributor pages are contiguous.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned.”h]”hX  Base address in the guest physical address space of the GICv3
redistributor register mappings. There are two 64K pages for each
VCPU and all of the redistributor pages are contiguous.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
This address needs to be 64K aligned.”…””}”(hjË  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KhjÈ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hähj¶  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h K!hj„  ubhÏ)”}”(hX:  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
The attribute data pointed to by kvm_device_attr.addr is a __u64 value::

  bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
  values:   |     count      |       base      |  flags   | index

- index encodes the unique redistributor region index
- flags: reserved for future use, currently 0
- base field encodes bits [51:16] of the guest physical base address
  of the first redistributor in the region.
- count encodes the number of redistributors in the region. Must be
  greater than 0.

There are two 64K pages for each redistributor in the region and
redistributors are laid out contiguously within the region. Regions
are filled with redistributors in the index order. The sum of all
region count fields must be greater than or equal to the number of
VCPUs. Redistributor regions must be registered in the incremental
index order, starting from index 0.

The characteristics of a specific redistributor region can be read
by presetting the index field in the attr data.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
”h]”(hÕ)”}”(hŒ0KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)”h]”hŒ0KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h K9hjå  ubhå)”}”(hhh]”(hõ)”}”(hŒHThe attribute data pointed to by kvm_device_attr.addr is a __u64 value::”h]”hŒGThe attribute data pointed to by kvm_device_attr.addr is a __u64 value:”…””}”(hjú  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K$hj÷  ubhŒliteral_block”“”)”}”(hŒbits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
values:   |     count      |       base      |  flags   | index”h]”hŒbits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
values:   |     count      |       base      |  flags   | index”…””}”hj
  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K&hj÷  ubhê)”}”(hhh]”(hï)”}”(hŒ3index encodes the unique redistributor region index”h]”hõ)”}”(hj  h]”hŒ3index encodes the unique redistributor region index”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K)hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj  ubhï)”}”(hŒ+flags: reserved for future use, currently 0”h]”hõ)”}”(hj4  h]”hŒ+flags: reserved for future use, currently 0”…””}”(hj6  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K*hj2  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj  ubhï)”}”(hŒlbase field encodes bits [51:16] of the guest physical base address
of the first redistributor in the region.”h]”hõ)”}”(hŒlbase field encodes bits [51:16] of the guest physical base address
of the first redistributor in the region.”h]”hŒlbase field encodes bits [51:16] of the guest physical base address
of the first redistributor in the region.”…””}”(hjM  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K+hjI  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj  ubhï)”}”(hŒRcount encodes the number of redistributors in the region. Must be
greater than 0.
”h]”hõ)”}”(hŒQcount encodes the number of redistributors in the region. Must be
greater than 0.”h]”hŒQcount encodes the number of redistributors in the region. Must be
greater than 0.”…””}”(hje  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K-hja  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhj  ubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1héhŸh³h K)hj÷  ubhõ)”}”(hXp  There are two 64K pages for each redistributor in the region and
redistributors are laid out contiguously within the region. Regions
are filled with redistributors in the index order. The sum of all
region count fields must be greater than or equal to the number of
VCPUs. Redistributor regions must be registered in the incremental
index order, starting from index 0.”h]”hXp  There are two 64K pages for each redistributor in the region and
redistributors are laid out contiguously within the region. Regions
are filled with redistributors in the index order. The sum of all
region count fields must be greater than or equal to the number of
VCPUs. Redistributor regions must be registered in the incremental
index order, starting from index 0.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K0hj÷  ubhõ)”}”(hŒ›The characteristics of a specific redistributor region can be read
by presetting the index field in the attr data.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.”h]”hŒ›The characteristics of a specific redistributor region can be read
by presetting the index field in the attr data.
Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K7hj÷  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähjå  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h K9hj„  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhj€  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h Khjm  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj[  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h K9hjX  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubhõ)”}”(hŒpIt is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.”h]”hŒpIt is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K;hjU  ubhõ)”}”(hX©  Note that to obtain reproducible results (the same VCPU being associated
with the same redistributor across a save/restore operation), VCPU creation
order, redistributor region creation order as well as the respective
interleaves of VCPU and region creation MUST be preserved.  Any change in
either ordering may result in a different vcpu_id/redistributor association,
resulting in a VM that will fail to run at restore time.”h]”hX©  Note that to obtain reproducible results (the same VCPU being associated
with the same redistributor across a save/restore operation), VCPU creation
order, redistributor region creation order as well as the respective
interleaves of VCPU and region creation MUST be preserved.  Any change in
either ordering may result in a different vcpu_id/redistributor association,
resulting in a VM that will fail to run at restore time.”…””}”(hjÓ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K>hjU  ubhõ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KEhjU  ubj  )”}”(hX`  =======  =============================================================
-E2BIG   Address outside of addressable IPA range
-EINVAL  Incorrectly aligned address, bad redistributor region
         count/index, mixed redistributor region attribute usage
-EEXIST  Address already configured
-ENOENT  Attempt to read the characteristics of a non existing
         redistributor region
-ENXIO   The group or attribute is unknown/unsupported for this device
         or hardware support is missing.
-EFAULT  Invalid user pointer for attr->addr.
=======  =============================================================

”h]”hŒtable”“”)”}”(hhh]”hŒtgroup”“”)”}”(hhh]”(hŒcolspec”“”)”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hjú  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K=uh1jý  hjú  ubhŒtbody”“”)”}”(hhh]”(hŒrow”“”)”}”(hhh]”(hŒentry”“”)”}”(hhh]”hõ)”}”(hŒ-E2BIG”h]”hŒ-E2BIG”…””}”(hj"  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KHhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”hõ)”}”(hŒ(Address outside of addressable IPA range”h]”hŒ(Address outside of addressable IPA range”…””}”(hj9  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KHhj6  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EINVAL”h]”hŒ-EINVAL”…””}”(hjY  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KIhjV  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjS  ubj  )”}”(hhh]”hõ)”}”(hŒmIncorrectly aligned address, bad redistributor region
count/index, mixed redistributor region attribute usage”h]”hŒmIncorrectly aligned address, bad redistributor region
count/index, mixed redistributor region attribute usage”…””}”(hjp  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KIhjm  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjS  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EEXIST”h]”hŒ-EEXIST”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KKhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjŠ  ubj  )”}”(hhh]”hõ)”}”(hŒAddress already configured”h]”hŒAddress already configured”…””}”(hj§  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KKhj¤  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjŠ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENOENT”h]”hŒ-ENOENT”…””}”(hjÇ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KLhjÄ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÁ  ubj  )”}”(hhh]”hõ)”}”(hŒJAttempt to read the characteristics of a non existing
redistributor region”h]”hŒJAttempt to read the characteristics of a non existing
redistributor region”…””}”(hjÞ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KLhjÛ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÁ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENXIO”h]”hŒ-ENXIO”…””}”(hjþ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KNhjû  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjø  ubj  )”}”(hhh]”hõ)”}”(hŒ]The group or attribute is unknown/unsupported for this device
or hardware support is missing.”h]”hŒ]The group or attribute is unknown/unsupported for this device
or hardware support is missing.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KNhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjø  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EFAULT”h]”hŒ-EFAULT”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KPhj2  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj/  ubj  )”}”(hhh]”hõ)”}”(hŒ$Invalid user pointer for attr->addr.”h]”hŒ$Invalid user pointer for attr->addr.”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KPhjI  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj/  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjú  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hjõ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hjï  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KGhjU  ubhÊ)”}”(hhh]”hÏ)”}”(hXÆ  KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
Attributes:

 The attr field of kvm_device_attr encodes two values::

   bits:     | 63   ....  32  |  31   ....    0 |
   values:   |      mpidr     |      offset     |

 All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
 __u32 value.  64-bit registers must be accessed by separately accessing the
 lower and higher word.

 Writes to read-only registers are ignored by the kernel.

 KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
 KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
 specified by the mpidr.

 The offset is relative to the "[Re]Distributor base address" as defined
 in the GICv3/4 specs.  Getting or setting such a register has the same
 effect as reading or writing the register on real hardware, except for the
 following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
 differently when accessed via this interface compared to their
 architecturally defined behavior to allow software a full view of the
 VGIC's internal state.

 The mpidr field is used to specify which
 redistributor is accessed.  The mpidr is ignored for the distributor.

 The mpidr encoding is based on the affinity information in the
 architecture defined MPIDR, and the field is encoded as follows::

   | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
   |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

 Note that distributor fields are not banked, but return the same value
 regardless of the mpidr used to access the register.

 GICD_IIDR.Revision is updated when the KVM implementation is changed in a
 way directly observable by the guest or userspace.  Userspace should read
 GICD_IIDR from KVM and write back the read value to confirm its expected
 behavior is aligned with the KVM implementation.  Userspace should set
 GICD_IIDR before setting any other registers to ensure the expected
 behavior.


 The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
 that a write of a clear bit has no effect, whereas a write with a set bit
 clears that value.  To allow userspace to freely set the values of these two
 registers, setting the attributes with the register offsets for these two
 registers simply sets the non-reserved bits to the value written.


 Accesses (reads and writes) to the GICD_ISPENDR register region and
 GICR_ISPENDR0 registers get/set the value of the latched pending state for
 the interrupts.

 This is identical to the value returned by a guest read from ISPENDR for an
 edge triggered interrupt, but may differ for level triggered interrupts.
 For edge triggered interrupts, once an interrupt becomes pending (whether
 because of an edge detected on the input line or because of a guest write
 to ISPENDR) this state is "latched", and only cleared when either the
 interrupt is activated or when the guest writes to ICPENDR. A level
 triggered interrupt may be pending either because the level input is held
 high by a device, or because of a guest write to the ISPENDR register. Only
 ISPENDR writes are latched; if the device lowers the line level then the
 interrupt is no longer pending unless the guest also wrote to ISPENDR, and
 conversely writes to ICPENDR or activations of the interrupt do not clear
 the pending status if the line level is still being held high.  (These
 rules are documented in the GICv3 specification descriptions of the ICPENDR
 and ISPENDR registers.) For a level triggered interrupt the value accessed
 here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
 interrupt activation, whereas the value returned by a guest read from
 ISPENDR is the logical OR of the latch value and the input line level.

 Raw access to the latch state is provided to userspace so that it can save
 and restore the entire GIC internal state (which is defined by the
 combination of the current input line level and the latch state, and cannot
 be deduced from purely the line level and the value of the ISPENDR
 registers).

 Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
 RAZ/WI semantics, meaning that reads always return 0 and writes are always
 ignored.
”h]”(hÕ)”}”(hŒ@KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS”h]”hŒ@KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h K¨hj‚  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KUhj”  ubj  )”}”(hX7  The attr field of kvm_device_attr encodes two values::

  bits:     | 63   ....  32  |  31   ....    0 |
  values:   |      mpidr     |      offset     |

All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
__u32 value.  64-bit registers must be accessed by separately accessing the
lower and higher word.

Writes to read-only registers are ignored by the kernel.

KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
specified by the mpidr.

The offset is relative to the "[Re]Distributor base address" as defined
in the GICv3/4 specs.  Getting or setting such a register has the same
effect as reading or writing the register on real hardware, except for the
following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
differently when accessed via this interface compared to their
architecturally defined behavior to allow software a full view of the
VGIC's internal state.

The mpidr field is used to specify which
redistributor is accessed.  The mpidr is ignored for the distributor.

The mpidr encoding is based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::

  | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
  |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

Note that distributor fields are not banked, but return the same value
regardless of the mpidr used to access the register.

GICD_IIDR.Revision is updated when the KVM implementation is changed in a
way directly observable by the guest or userspace.  Userspace should read
GICD_IIDR from KVM and write back the read value to confirm its expected
behavior is aligned with the KVM implementation.  Userspace should set
GICD_IIDR before setting any other registers to ensure the expected
behavior.


The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
that a write of a clear bit has no effect, whereas a write with a set bit
clears that value.  To allow userspace to freely set the values of these two
registers, setting the attributes with the register offsets for these two
registers simply sets the non-reserved bits to the value written.


Accesses (reads and writes) to the GICD_ISPENDR register region and
GICR_ISPENDR0 registers get/set the value of the latched pending state for
the interrupts.

This is identical to the value returned by a guest read from ISPENDR for an
edge triggered interrupt, but may differ for level triggered interrupts.
For edge triggered interrupts, once an interrupt becomes pending (whether
because of an edge detected on the input line or because of a guest write
to ISPENDR) this state is "latched", and only cleared when either the
interrupt is activated or when the guest writes to ICPENDR. A level
triggered interrupt may be pending either because the level input is held
high by a device, or because of a guest write to the ISPENDR register. Only
ISPENDR writes are latched; if the device lowers the line level then the
interrupt is no longer pending unless the guest also wrote to ISPENDR, and
conversely writes to ICPENDR or activations of the interrupt do not clear
the pending status if the line level is still being held high.  (These
rules are documented in the GICv3 specification descriptions of the ICPENDR
and ISPENDR registers.) For a level triggered interrupt the value accessed
here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
interrupt activation, whereas the value returned by a guest read from
ISPENDR is the logical OR of the latch value and the input line level.

Raw access to the latch state is provided to userspace so that it can save
and restore the entire GIC internal state (which is defined by the
combination of the current input line level and the latch state, and cannot
be deduced from purely the line level and the value of the ISPENDR
registers).

Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
RAZ/WI semantics, meaning that reads always return 0 and writes are always
ignored.
”h]”(hõ)”}”(hŒ6The attr field of kvm_device_attr encodes two values::”h]”hŒ5The attr field of kvm_device_attr encodes two values:”…””}”(hj©  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KWhj¥  ubj	  )”}”(hŒ]bits:     | 63   ....  32  |  31   ....    0 |
values:   |      mpidr     |      offset     |”h]”hŒ]bits:     | 63   ....  32  |  31   ....    0 |
values:   |      mpidr     |      offset     |”…””}”hj·  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KYhj¥  ubhõ)”}”(hŒ­All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
__u32 value.  64-bit registers must be accessed by separately accessing the
lower and higher word.”h]”hŒ­All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
__u32 value.  64-bit registers must be accessed by separately accessing the
lower and higher word.”…””}”(hjÅ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K\hj¥  ubhõ)”}”(hŒ8Writes to read-only registers are ignored by the kernel.”h]”hŒ8Writes to read-only registers are ignored by the kernel.”…””}”(hjÓ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K`hj¥  ubhõ)”}”(hŒ¦KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
specified by the mpidr.”h]”hŒ¦KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
specified by the mpidr.”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kbhj¥  ubhõ)”}”(hXü  The offset is relative to the "[Re]Distributor base address" as defined
in the GICv3/4 specs.  Getting or setting such a register has the same
effect as reading or writing the register on real hardware, except for the
following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
differently when accessed via this interface compared to their
architecturally defined behavior to allow software a full view of the
VGIC's internal state.”h]”hX  The offset is relative to the â€œ[Re]Distributor base addressâ€ as defined
in the GICv3/4 specs.  Getting or setting such a register has the same
effect as reading or writing the register on real hardware, except for the
following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
differently when accessed via this interface compared to their
architecturally defined behavior to allow software a full view of the
VGICâ€™s internal state.”…””}”(hjï  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kfhj¥  ubhõ)”}”(hŒnThe mpidr field is used to specify which
redistributor is accessed.  The mpidr is ignored for the distributor.”h]”hŒnThe mpidr field is used to specify which
redistributor is accessed.  The mpidr is ignored for the distributor.”…””}”(hjý  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kohj¥  ubhõ)”}”(hŒ€The mpidr encoding is based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::”h]”hŒThe mpidr encoding is based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Krhj¥  ubj	  )”}”(hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”h]”hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h Kuhj¥  ubhõ)”}”(hŒ{Note that distributor fields are not banked, but return the same value
regardless of the mpidr used to access the register.”h]”hŒ{Note that distributor fields are not banked, but return the same value
regardless of the mpidr used to access the register.”…””}”(hj'  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kxhj¥  ubhõ)”}”(hXq  GICD_IIDR.Revision is updated when the KVM implementation is changed in a
way directly observable by the guest or userspace.  Userspace should read
GICD_IIDR from KVM and write back the read value to confirm its expected
behavior is aligned with the KVM implementation.  Userspace should set
GICD_IIDR before setting any other registers to ensure the expected
behavior.”h]”hXq  GICD_IIDR.Revision is updated when the KVM implementation is changed in a
way directly observable by the guest or userspace.  Userspace should read
GICD_IIDR from KVM and write back the read value to confirm its expected
behavior is aligned with the KVM implementation.  Userspace should set
GICD_IIDR before setting any other registers to ensure the expected
behavior.”…””}”(hj5  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K{hj¥  ubhõ)”}”(hXo  The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
that a write of a clear bit has no effect, whereas a write with a set bit
clears that value.  To allow userspace to freely set the values of these two
registers, setting the attributes with the register offsets for these two
registers simply sets the non-reserved bits to the value written.”h]”hXo  The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
that a write of a clear bit has no effect, whereas a write with a set bit
clears that value.  To allow userspace to freely set the values of these two
registers, setting the attributes with the register offsets for these two
registers simply sets the non-reserved bits to the value written.”…””}”(hjC  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kƒhj¥  ubhõ)”}”(hŒžAccesses (reads and writes) to the GICD_ISPENDR register region and
GICR_ISPENDR0 registers get/set the value of the latched pending state for
the interrupts.”h]”hŒžAccesses (reads and writes) to the GICD_ISPENDR register region and
GICR_ISPENDR0 registers get/set the value of the latched pending state for
the interrupts.”…””}”(hjQ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KŠhj¥  ubhõ)”}”(hXÝ  This is identical to the value returned by a guest read from ISPENDR for an
edge triggered interrupt, but may differ for level triggered interrupts.
For edge triggered interrupts, once an interrupt becomes pending (whether
because of an edge detected on the input line or because of a guest write
to ISPENDR) this state is "latched", and only cleared when either the
interrupt is activated or when the guest writes to ICPENDR. A level
triggered interrupt may be pending either because the level input is held
high by a device, or because of a guest write to the ISPENDR register. Only
ISPENDR writes are latched; if the device lowers the line level then the
interrupt is no longer pending unless the guest also wrote to ISPENDR, and
conversely writes to ICPENDR or activations of the interrupt do not clear
the pending status if the line level is still being held high.  (These
rules are documented in the GICv3 specification descriptions of the ICPENDR
and ISPENDR registers.) For a level triggered interrupt the value accessed
here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
interrupt activation, whereas the value returned by a guest read from
ISPENDR is the logical OR of the latch value and the input line level.”h]”hXá  This is identical to the value returned by a guest read from ISPENDR for an
edge triggered interrupt, but may differ for level triggered interrupts.
For edge triggered interrupts, once an interrupt becomes pending (whether
because of an edge detected on the input line or because of a guest write
to ISPENDR) this state is â€œlatchedâ€, and only cleared when either the
interrupt is activated or when the guest writes to ICPENDR. A level
triggered interrupt may be pending either because the level input is held
high by a device, or because of a guest write to the ISPENDR register. Only
ISPENDR writes are latched; if the device lowers the line level then the
interrupt is no longer pending unless the guest also wrote to ISPENDR, and
conversely writes to ICPENDR or activations of the interrupt do not clear
the pending status if the line level is still being held high.  (These
rules are documented in the GICv3 specification descriptions of the ICPENDR
and ISPENDR registers.) For a level triggered interrupt the value accessed
here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
interrupt activation, whereas the value returned by a guest read from
ISPENDR is the logical OR of the latch value and the input line level.”…””}”(hj_  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KŽhj¥  ubhõ)”}”(hX(  Raw access to the latch state is provided to userspace so that it can save
and restore the entire GIC internal state (which is defined by the
combination of the current input line level and the latch state, and cannot
be deduced from purely the line level and the value of the ISPENDR
registers).”h]”hX(  Raw access to the latch state is provided to userspace so that it can save
and restore the entire GIC internal state (which is defined by the
combination of the current input line level and the latch state, and cannot
be deduced from purely the line level and the value of the ISPENDR
registers).”…””}”(hjm  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K hj¥  ubhõ)”}”(hŒAccesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
RAZ/WI semantics, meaning that reads always return 0 and writes are always
ignored.”h]”hŒAccesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
RAZ/WI semantics, meaning that reads always return 0 and writes are always
ignored.”…””}”(hj{  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K¦hj¥  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KWhj”  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj‚  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h K¨hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubhõ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hj¡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KªhjU  ubj  )”}”(hŒá======  =====================================================
-ENXIO  Getting or setting this register is not yet supported
-EBUSY  One or more VCPUs are running
======  =====================================================

”h]”jô  )”}”(hhh]”jù  )”}”(hhh]”(jþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hj¶  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K5uh1jý  hj¶  ubj  )”}”(hhh]”(j  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENXIO”h]”hŒ-ENXIO”…””}”(hjÖ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K­hjÓ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÐ  ubj  )”}”(hhh]”hõ)”}”(hŒ5Getting or setting this register is not yet supported”h]”hŒ5Getting or setting this register is not yet supported”…””}”(hjí  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K­hjê  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÐ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÍ  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EBUSY”h]”hŒ-EBUSY”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K®hj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hhh]”hõ)”}”(hŒOne or more VCPUs are running”h]”hŒOne or more VCPUs are running”…””}”(hj$  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K®hj!  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÍ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj¶  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hj³  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hj¯  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h K¬hjU  ubhÊ)”}”(hhh]”hÏ)”}”(hX©  KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
Attributes:

 The attr field of kvm_device_attr encodes two values::

   bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
   values:   |         mpidr         |      RES     |    instr    |

 The mpidr field encodes the CPU ID based on the affinity information in the
 architecture defined MPIDR, and the field is encoded as follows::

   | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
   |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

 The instr field encodes the system register to access based on the fields
 defined in the A64 instruction set encoding for system register access
 (RES means the bits are reserved for future use and should be zero)::

   | 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
   |   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |

 All system regs accessed through this API are (rw, 64-bit) and
 kvm_device_attr.addr points to a __u64 value.

 KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
 CPU specified by the mpidr field.

 CPU interface registers access is not implemented for AArch32 mode.
 Error -ENXIO is returned when accessed in AArch32 mode.
”h]”(hÕ)”}”(hŒ KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS”h]”hŒ KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS”…””}”(hj^  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h KÎhjZ  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hjo  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K³hjl  ubj  )”}”(hXi  The attr field of kvm_device_attr encodes two values::

  bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
  values:   |         mpidr         |      RES     |    instr    |

The mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::

  | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
  |    Aff3    |    Aff2    |    Aff1    |    Aff0    |

The instr field encodes the system register to access based on the fields
defined in the A64 instruction set encoding for system register access
(RES means the bits are reserved for future use and should be zero)::

  | 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
  |   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |

All system regs accessed through this API are (rw, 64-bit) and
kvm_device_attr.addr points to a __u64 value.

KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
CPU specified by the mpidr field.

CPU interface registers access is not implemented for AArch32 mode.
Error -ENXIO is returned when accessed in AArch32 mode.
”h]”(hõ)”}”(hŒ6The attr field of kvm_device_attr encodes two values::”h]”hŒ5The attr field of kvm_device_attr encodes two values:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kµhj}  ubj	  )”}”(hŒbits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
values:   |         mpidr         |      RES     |    instr    |”h]”hŒbits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
values:   |         mpidr         |      RES     |    instr    |”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K·hj}  ubhõ)”}”(hŒThe mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::”h]”hŒŒThe mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kºhj}  ubj	  )”}”(hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”h]”hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”…””}”hj«  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h K½hj}  ubhõ)”}”(hŒÖThe instr field encodes the system register to access based on the fields
defined in the A64 instruction set encoding for system register access
(RES means the bits are reserved for future use and should be zero)::”h]”hŒÕThe instr field encodes the system register to access based on the fields
defined in the A64 instruction set encoding for system register access
(RES means the bits are reserved for future use and should be zero):”…””}”(hj¹  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÀhj}  ubj	  )”}”(hŒq| 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
|   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |”h]”hŒq| 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
|   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |”…””}”hjÇ  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h KÄhj}  ubhõ)”}”(hŒlAll system regs accessed through this API are (rw, 64-bit) and
kvm_device_attr.addr points to a __u64 value.”h]”hŒlAll system regs accessed through this API are (rw, 64-bit) and
kvm_device_attr.addr points to a __u64 value.”…””}”(hjÕ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÇhj}  ubhõ)”}”(hŒoKVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
CPU specified by the mpidr field.”h]”hŒoKVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
CPU specified by the mpidr field.”…””}”(hjã  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÊhj}  ubhõ)”}”(hŒ{CPU interface registers access is not implemented for AArch32 mode.
Error -ENXIO is returned when accessed in AArch32 mode.”h]”hŒ{CPU interface registers access is not implemented for AArch32 mode.
Error -ENXIO is returned when accessed in AArch32 mode.”…””}”(hjñ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÍhj}  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h Kµhjl  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähjZ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h KÎhjW  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubhõ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÐhjU  ubj  )”}”(hX	  =======  =====================================================
-ENXIO   Getting or setting this register is not yet supported
-EBUSY   VCPU is running
-EINVAL  Invalid mpidr or register value supplied
=======  =====================================================

”h]”jô  )”}”(hhh]”jù  )”}”(hhh]”(jþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hj,  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K5uh1jý  hj,  ubj  )”}”(hhh]”(j  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENXIO”h]”hŒ-ENXIO”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÓhjI  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjF  ubj  )”}”(hhh]”hõ)”}”(hŒ5Getting or setting this register is not yet supported”h]”hŒ5Getting or setting this register is not yet supported”…””}”(hjc  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÓhj`  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjF  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjC  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EBUSY”h]”hŒ-EBUSY”…””}”(hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÔhj€  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj}  ubj  )”}”(hhh]”hõ)”}”(hŒVCPU is running”h]”hŒVCPU is running”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÔhj—  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj}  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjC  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EINVAL”h]”hŒ-EINVAL”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÕhj·  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj´  ubj  )”}”(hhh]”hõ)”}”(hŒ(Invalid mpidr or register value supplied”h]”hŒ(Invalid mpidr or register value supplied”…””}”(hjÑ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÕhjÎ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj´  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjC  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hj,  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hj)  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hj%  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KÒhjU  ubhÊ)”}”(hhh]”hÏ)”}”(hŒàKVM_DEV_ARM_VGIC_GRP_NR_IRQS
Attributes:

 A value describing the number of interrupts (SGI, PPI and SPI) for
 this GIC instance, ranging from 64 to 1024, in increments of 32.

 kvm_device_attr.addr points to a __u32 value.
”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_GRP_NR_IRQS”h]”hŒKVM_DEV_ARM_VGIC_GRP_NR_IRQS”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h Kßhj  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÚhj  ubj  )”}”(hŒ³A value describing the number of interrupts (SGI, PPI and SPI) for
this GIC instance, ranging from 64 to 1024, in increments of 32.

kvm_device_attr.addr points to a __u32 value.
”h]”(hõ)”}”(hŒƒA value describing the number of interrupts (SGI, PPI and SPI) for
this GIC instance, ranging from 64 to 1024, in increments of 32.”h]”hŒƒA value describing the number of interrupts (SGI, PPI and SPI) for
this GIC instance, ranging from 64 to 1024, in increments of 32.”…””}”(hj.  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KÜhj*  ubhõ)”}”(hŒ-kvm_device_attr.addr points to a __u32 value.”h]”hŒ-kvm_device_attr.addr points to a __u32 value.”…””}”(hj<  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kßhj*  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KÜhj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h Kßhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubhõ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hjb  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KáhjU  ubj  )”}”(hŒ´=======  ======================================
-EINVAL  Value set is out of the expected range
-EBUSY   Value has already be set.
=======  ======================================

”h]”jô  )”}”(hhh]”jù  )”}”(hhh]”(jþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hjw  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K&uh1jý  hjw  ubj  )”}”(hhh]”(j  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EINVAL”h]”hŒ-EINVAL”…””}”(hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kähj”  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj‘  ubj  )”}”(hhh]”hõ)”}”(hŒ&Value set is out of the expected range”h]”hŒ&Value set is out of the expected range”…””}”(hj®  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kähj«  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj‘  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjŽ  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EBUSY”h]”hŒ-EBUSY”…””}”(hjÎ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KåhjË  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÈ  ubj  )”}”(hhh]”hõ)”}”(hŒValue has already be set.”h]”hŒValue has already be set.”…””}”(hjå  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kåhjâ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÈ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjŽ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjw  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hjt  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hjp  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KãhjU  ubhÊ)”}”(hhh]”hÏ)”}”(hX~  KVM_DEV_ARM_VGIC_GRP_CTRL
Attributes:

 KVM_DEV_ARM_VGIC_CTRL_INIT
   request the initialization of the VGIC, no additional parameter in
   kvm_device_attr.addr. Must be called after all VCPUs have been created.
 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
   save all LPI pending bits into guest RAM pending tables.

   The first kB of the pending table is not altered by this operation.
”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_GRP_CTRL”h]”hŒKVM_DEV_ARM_VGIC_GRP_CTRL”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h Kòhj	  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hj0	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kêhj-	  ubj  )”}”(hXQ  KVM_DEV_ARM_VGIC_CTRL_INIT
  request the initialization of the VGIC, no additional parameter in
  kvm_device_attr.addr. Must be called after all VCPUs have been created.
KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
  save all LPI pending bits into guest RAM pending tables.

  The first kB of the pending table is not altered by this operation.
”•ôI      h]”hÊ)”}”(hhh]”(hÏ)”}”(hŒ¥KVM_DEV_ARM_VGIC_CTRL_INIT
request the initialization of the VGIC, no additional parameter in
kvm_device_attr.addr. Must be called after all VCPUs have been created.”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_CTRL_INIT”h]”hŒKVM_DEV_ARM_VGIC_CTRL_INIT”…””}”(hjI	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h KíhjE	  ubhå)”}”(hhh]”hõ)”}”(hŒŠrequest the initialization of the VGIC, no additional parameter in
kvm_device_attr.addr. Must be called after all VCPUs have been created.”h]”hŒŠrequest the initialization of the VGIC, no additional parameter in
kvm_device_attr.addr. Must be called after all VCPUs have been created.”…””}”(hjZ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KíhjW	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hähjE	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h KíhjB	  ubhÏ)”}”(hŒ£KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
save all LPI pending bits into guest RAM pending tables.

The first kB of the pending table is not altered by this operation.
”h]”(hÕ)”}”(hŒ$KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES”h]”hŒ$KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES”…””}”(hjx	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h Kòhjt	  ubhå)”}”(hhh]”(hõ)”}”(hŒ8save all LPI pending bits into guest RAM pending tables.”h]”hŒ8save all LPI pending bits into guest RAM pending tables.”…””}”(hj‰	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kðhj†	  ubhõ)”}”(hŒCThe first kB of the pending table is not altered by this operation.”h]”hŒCThe first kB of the pending table is not altered by this operation.”…””}”(hj—	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kòhj†	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähjt	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h KòhjB	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhj>	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h Kìhj-	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h Kòhj	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubhõ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hjÏ	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KôhjU  ubj  )”}”(hX}  =======  ========================================================
-ENXIO   VGIC not properly configured as required prior to calling
         this attribute
-ENODEV  no online VCPU
-ENOMEM  memory shortage when allocating vgic internal data
-EFAULT  Invalid guest ram access
-EBUSY   One or more VCPUS are running
=======  ========================================================

”h]”jô  )”}”(hhh]”jù  )”}”(hhh]”(jþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hjä	  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K9uh1jý  hjä	  ubj  )”}”(hhh]”(j  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENXIO”h]”hŒ-ENXIO”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K÷hj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjþ	  ubj  )”}”(hhh]”hõ)”}”(hŒHVGIC not properly configured as required prior to calling
this attribute”h]”hŒHVGIC not properly configured as required prior to calling
this attribute”…””}”(hj
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h K÷hj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjþ	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjû	  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENODEV”h]”hŒ-ENODEV”…””}”(hj;
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kùhj8
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj5
  ubj  )”}”(hhh]”hõ)”}”(hŒno online VCPU”h]”hŒno online VCPU”…””}”(hjR
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KùhjO
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj5
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjû	  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-ENOMEM”h]”hŒ-ENOMEM”…””}”(hjr
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kúhjo
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjl
  ubj  )”}”(hhh]”hõ)”}”(hŒ2memory shortage when allocating vgic internal data”h]”hŒ2memory shortage when allocating vgic internal data”…””}”(hj‰
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kúhj†
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjl
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjû	  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EFAULT”h]”hŒ-EFAULT”…””}”(hj©
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kûhj¦
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj£
  ubj  )”}”(hhh]”hõ)”}”(hŒInvalid guest ram access”h]”hŒInvalid guest ram access”…””}”(hjÀ
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kûhj½
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj£
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjû	  ubj  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EBUSY”h]”hŒ-EBUSY”…””}”(hjà
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h KühjÝ
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÚ
  ubj  )”}”(hhh]”hõ)”}”(hŒOne or more VCPUS are running”h]”hŒOne or more VCPUS are running”…””}”(hj÷
  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Kühjô
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjÚ
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjû	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjä	  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hjá	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hjÝ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h KöhjU  ubhÊ)”}”(hhh]”(hÏ)”}”(hX‚  KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
Attributes:

 The attr field of kvm_device_attr encodes the following values::

   bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
   values:   |         mpidr         |      info       |   vINTID   |

 The vINTID specifies which set of IRQs is reported on.

 The info field specifies which information userspace wants to get or set
 using this interface.  Currently we support the following info values:

   VGIC_LEVEL_INFO_LINE_LEVEL:
     Get/Set the input level of the IRQ line for a set of 32 contiguously
     numbered interrupts.

     vINTID must be a multiple of 32.

     kvm_device_attr.addr points to a __u32 value which will contain a
     bitmap where a set bit means the interrupt level is asserted.

     Bit[n] indicates the status for interrupt vINTID + n.

 SGIs and any interrupt with a higher ID than the number of interrupts
 supported, will be RAZ/WI.  LPIs are always edge-triggered and are
 therefore not supported by this interface.

 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
 reported with the same value regardless of the mpidr specified.

 The mpidr field encodes the CPU ID based on the affinity information in the
 architecture defined MPIDR, and the field is encoded as follows::

   | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
   |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_GRP_LEVEL_INFO”h]”hŒKVM_DEV_ARM_VGIC_GRP_LEVEL_INFO”…””}”(hj1  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h M#hj-  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hjB  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Mhj?  ubj  )”}”(hX?  The attr field of kvm_device_attr encodes the following values::

  bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
  values:   |         mpidr         |      info       |   vINTID   |

The vINTID specifies which set of IRQs is reported on.

The info field specifies which information userspace wants to get or set
using this interface.  Currently we support the following info values:

  VGIC_LEVEL_INFO_LINE_LEVEL:
    Get/Set the input level of the IRQ line for a set of 32 contiguously
    numbered interrupts.

    vINTID must be a multiple of 32.

    kvm_device_attr.addr points to a __u32 value which will contain a
    bitmap where a set bit means the interrupt level is asserted.

    Bit[n] indicates the status for interrupt vINTID + n.

SGIs and any interrupt with a higher ID than the number of interrupts
supported, will be RAZ/WI.  LPIs are always edge-triggered and are
therefore not supported by this interface.

PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
reported with the same value regardless of the mpidr specified.

The mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::

  | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
  |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
”h]”(hõ)”}”(hŒ@The attr field of kvm_device_attr encodes the following values::”h]”hŒ?The attr field of kvm_device_attr encodes the following values:”…””}”(hjT  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h MhjP  ubj	  )”}”(hŒ…bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
values:   |         mpidr         |      info       |   vINTID   |”h]”hŒ…bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
values:   |         mpidr         |      info       |   vINTID   |”…””}”hjb  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h MhjP  ubhõ)”}”(hŒ6The vINTID specifies which set of IRQs is reported on.”h]”hŒ6The vINTID specifies which set of IRQs is reported on.”…””}”(hjp  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h MhjP  ubhõ)”}”(hŒThe info field specifies which information userspace wants to get or set
using this interface.  Currently we support the following info values:”h]”hŒThe info field specifies which information userspace wants to get or set
using this interface.  Currently we support the following info values:”…””}”(hj~  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M
hjP  ubj  )”}”(hX\  VGIC_LEVEL_INFO_LINE_LEVEL:
  Get/Set the input level of the IRQ line for a set of 32 contiguously
  numbered interrupts.

  vINTID must be a multiple of 32.

  kvm_device_attr.addr points to a __u32 value which will contain a
  bitmap where a set bit means the interrupt level is asserted.

  Bit[n] indicates the status for interrupt vINTID + n.
”h]”hÊ)”}”(hhh]”hÏ)”}”(hXP  VGIC_LEVEL_INFO_LINE_LEVEL:
Get/Set the input level of the IRQ line for a set of 32 contiguously
numbered interrupts.

vINTID must be a multiple of 32.

kvm_device_attr.addr points to a __u32 value which will contain a
bitmap where a set bit means the interrupt level is asserted.

Bit[n] indicates the status for interrupt vINTID + n.
”h]”(hÕ)”}”(hŒVGIC_LEVEL_INFO_LINE_LEVEL:”h]”hŒVGIC_LEVEL_INFO_LINE_LEVEL:”…””}”(hj—  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h Mhj“  ubhå)”}”(hhh]”(hõ)”}”(hŒYGet/Set the input level of the IRQ line for a set of 32 contiguously
numbered interrupts.”h]”hŒYGet/Set the input level of the IRQ line for a set of 32 contiguously
numbered interrupts.”…””}”(hj¨  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Mhj¥  ubhõ)”}”(hŒ vINTID must be a multiple of 32.”h]”hŒ vINTID must be a multiple of 32.”…””}”(hj¶  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Mhj¥  ubhõ)”}”(hŒkvm_device_attr.addr points to a __u32 value which will contain a
bitmap where a set bit means the interrupt level is asserted.”h]”hŒkvm_device_attr.addr points to a __u32 value which will contain a
bitmap where a set bit means the interrupt level is asserted.”…””}”(hjÄ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Mhj¥  ubhõ)”}”(hŒ5Bit[n] indicates the status for interrupt vINTID + n.”h]”hŒ5Bit[n] indicates the status for interrupt vINTID + n.”…””}”(hjÒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h Mhj¥  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj“  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h Mhj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjŒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h MhjP  ubhõ)”}”(hŒ³SGIs and any interrupt with a higher ID than the number of interrupts
supported, will be RAZ/WI.  LPIs are always edge-triggered and are
therefore not supported by this interface.”h]”hŒ³SGIs and any interrupt with a higher ID than the number of interrupts
supported, will be RAZ/WI.  LPIs are always edge-triggered and are
therefore not supported by this interface.”…””}”(hjø  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h MhjP  ubhõ)”}”(hŒˆPPIs are reported per VCPU as specified in the mpidr field, and SPIs are
reported with the same value regardless of the mpidr specified.”h]”hŒˆPPIs are reported per VCPU as specified in the mpidr field, and SPIs are
reported with the same value regardless of the mpidr specified.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h MhjP  ubhõ)”}”(hŒThe mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows::”h]”hŒŒThe mpidr field encodes the CPU ID based on the affinity information in the
architecture defined MPIDR, and the field is encoded as follows:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h MhjP  ubj	  )”}”(hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”h]”hŒk| 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
|    Aff3    |    Aff2    |    Aff1    |    Aff0    |”…””}”hj"  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1j  hŸh³h M"hjP  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h Mhj?  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähj-  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h M#hj*  ubhÏ)”}”(hŒÕErrors:
=======  =============================================
-EINVAL  vINTID is not multiple of 32 or info field is
         not VGIC_LEVEL_INFO_LINE_LEVEL
=======  =============================================
”h]”(hÕ)”}”(hŒErrors:”h]”hŒErrors:”…””}”(hjF  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h M)hjB  ubhå)”}”(hhh]”jô  )”}”(hhh]”jù  )”}”(hhh]”(jþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”Kuh1jý  hjZ  ubjþ  )”}”(hhh]”h}”(h]”h ]”h"]”h$]”h&]”Œcolwidth”K-uh1jý  hjZ  ubj  )”}”(hhh]”j  )”}”(hhh]”(j  )”}”(hhh]”hõ)”}”(hŒ-EINVAL”h]”hŒ-EINVAL”…””}”(hjz  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M'hjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjt  ubj  )”}”(hhh]”hõ)”}”(hŒLvINTID is not multiple of 32 or info field is
not VGIC_LEVEL_INFO_LINE_LEVEL”h]”hŒLvINTID is not multiple of 32 or info field is
not VGIC_LEVEL_INFO_LINE_LEVEL”…””}”(hj‘  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M'hjŽ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjt  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j  hjq  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hjZ  ubeh}”(h]”h ]”h"]”h$]”h&]”Œcols”Kuh1jø  hjW  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jó  hjT  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hähjB  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h M)hj*  ubhÏ)”}”(hXE  KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ
Attributes:

 The attr field of kvm_device_attr encodes the following values:

   bits:     | 31   ....    5 | 4  ....  0 |
   values:   |      RES0      |   vINTID   |

 The vINTID specifies which interrupt is generated when the vGIC
 must generate a maintenance interrupt. This must be a PPI.”h]”(hÕ)”}”(hŒKVM_DEV_ARM_VGIC_GRP_MAINT_IRQ”h]”hŒKVM_DEV_ARM_VGIC_GRP_MAINT_IRQ”…””}”(hjÎ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÔhŸh³h M3hjÊ  ubhå)”}”(hhh]”(hõ)”}”(hŒAttributes:”h]”hŒAttributes:”…””}”(hjß  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M,hjÜ  ubj  )”}”(hX  The attr field of kvm_device_attr encodes the following values:

  bits:     | 31   ....    5 | 4  ....  0 |
  values:   |      RES0      |   vINTID   |

The vINTID specifies which interrupt is generated when the vGIC
must generate a maintenance interrupt. This must be a PPI.”h]”(hõ)”}”(hŒ?The attr field of kvm_device_attr encodes the following values:”h]”hŒ?The attr field of kvm_device_attr encodes the following values:”…””}”(hjñ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M.hjí  ubj  )”}”(hŒTbits:     | 31   ....    5 | 4  ....  0 |
values:   |      RES0      |   vINTID   |
”h]”hõ)”}”(hŒSbits:     | 31   ....    5 | 4  ....  0 |
values:   |      RES0      |   vINTID   |”h]”hŒSbits:     | 31   ....    5 | 4  ....  0 |
values:   |      RES0      |   vINTID   |”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M0hjÿ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h M0hjí  ubhõ)”}”(hŒzThe vINTID specifies which interrupt is generated when the vGIC
must generate a maintenance interrupt. This must be a PPI.”h]”hŒzThe vINTID specifies which interrupt is generated when the vGIC
must generate a maintenance interrupt. This must be a PPI.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hôhŸh³h M3hjí  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j~  hŸh³h M.hjÜ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähjÊ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h M3hj*  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhjU  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hähjC  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÎhŸh³h M3hj@  ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhh¶hžhhŸNh Nubeh}”(h]”Œ<arm-virtual-generic-interrupt-controller-v3-and-later-vgicv3”ah ]”h"]”Œ>arm virtual generic interrupt controller v3 and later (vgicv3)”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”j  Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jy  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”jT  jQ  sŒ	nametypes”}”jT  ‰sh}”jQ  h¶sŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.