sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget1/translations/zh_CN/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/zh_TW/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/it_IT/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ja_JP/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/ko_KR/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget1/translations/sp_SP/virt/kvm/devices/arm-vgic-itsmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhK/var/lib/git/docbuild/linux/Documentation/virt/kvm/devices/arm-vgic-its.rsthKubhsection)}(hhh](htitle)}(h/ARM Virtual Interrupt Translation Service (ITS)h]h/ARM Virtual Interrupt Translation Service (ITS)}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubhdefinition_list)}(hhh]hdefinition_list_item)}(hbDevice types supported: KVM_DEV_TYPE_ARM_VGIC_ITS ARM Interrupt Translation Service Controller h](hterm)}(hDevice types supported:h]hDevice types supported:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubh definition)}(hhh]h paragraph)}(hIKVM_DEV_TYPE_ARM_VGIC_ITS ARM Interrupt Translation Service Controllerh]hIKVM_DEV_TYPE_ARM_VGIC_ITS ARM Interrupt Translation Service Controller}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hThe ITS allows MSI(-X) interrupts to be injected into guests. This extension is optional. Creating a virtual ITS controller also requires a host GICv3 (see arm-vgic-v3.txt), but does not depend on having physical ITS controllers.h]hThe ITS allows MSI(-X) interrupts to be injected into guests. This extension is optional. Creating a virtual ITS controller also requires a host GICv3 (see arm-vgic-v3.txt), but does not depend on having physical ITS controllers.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hrThere can be multiple ITS controllers per guest, each of them has to have a separate, non-overlapping MMIO region.h]hrThere can be multiple ITS controllers per guest, each of them has to have a separate, non-overlapping MMIO region.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hGroupsh]hGroups}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhKubh)}(hhh](h)}(hKVM_DEV_ARM_VGIC_GRP_ADDRh]hKVM_DEV_ARM_VGIC_GRP_ADDR}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhKubh block_quote)}(hXKAttributes: KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit) Base address in the guest physical address space of the GICv3 ITS control register frame. This address needs to be 64K aligned and the region covers 128K. Errors: ======= ================================================= -E2BIG Address outside of addressable IPA range -EINVAL Incorrectly aligned address -EEXIST Address already configured -EFAULT Invalid user pointer for attr->addr. -ENODEV Incorrect attribute or the ITS is not supported. ======= ================================================= h](h)}(hhh]h)}(hAttributes: KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit) Base address in the guest physical address space of the GICv3 ITS control register frame. This address needs to be 64K aligned and the region covers 128K. h](h)}(h Attributes:h]h Attributes:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjRubh)}(hhh]h)}(hhh]h)}(hKVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit) Base address in the guest physical address space of the GICv3 ITS control register frame. This address needs to be 64K aligned and the region covers 128K. h](h)}(h#KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit)h]h#KVM_VGIC_ITS_ADDR_TYPE (rw, 64-bit)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjjubh)}(hhh]h)}(hBase address in the guest physical address space of the GICv3 ITS control register frame. This address needs to be 64K aligned and the region covers 128K.h]hBase address in the guest physical address space of the GICv3 ITS control register frame. This address needs to be 64K aligned and the region covers 128K.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj|ubah}(h]h ]h"]h$]h&]uh1hhjjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjgubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]uh1hhjRubeh}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1hhjKubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjKubjJ)}(hXZ======= ================================================= -E2BIG Address outside of addressable IPA range -EINVAL Incorrectly aligned address -EEXIST Address already configured -EFAULT Invalid user pointer for attr->addr. -ENODEV Incorrect attribute or the ITS is not supported. ======= ================================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK1uh1jhjubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h-E2BIGh]h-E2BIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h(Address outside of addressable IPA rangeh]h(Address outside of addressable IPA range}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hj&ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(hIncorrectly aligned addressh]hIncorrectly aligned address}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hj=ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EEXISTh]h-EEXIST}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hj]ubah}(h]h ]h"]h$]h&]uh1jhjZubj)}(hhh]h)}(hAddress already configuredh]hAddress already configured}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjtubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h$Invalid user pointer for attr->addr.h]h$Invalid user pointer for attr->addr.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENODEVh]h-ENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h0Incorrect attribute or the ITS is not supported.h]h0Incorrect attribute or the ITS is not supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jIhhhK hjKubeh}(h]h ]h"]h$]h&]uh1jIhhhKhj8hhubeh}(h]kvm-dev-arm-vgic-grp-addrah ]h"]kvm_dev_arm_vgic_grp_addrah$]h&]uh1hhj'hhhhhKubh)}(hhh](h)}(hKVM_DEV_ARM_VGIC_GRP_CTRLh]hKVM_DEV_ARM_VGIC_GRP_CTRL}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhhhK*ubjJ)}(hXFAttributes: KVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the ITS, no additional parameter in kvm_device_attr.addr. KVM_DEV_ARM_ITS_CTRL_RESET reset the ITS, no additional parameter in kvm_device_attr.addr. See "ITS Reset State" section. KVM_DEV_ARM_ITS_SAVE_TABLES save the ITS table data into guest RAM, at the location provisioned by the guest in corresponding registers/table entries. Should userspace require a form of dirty tracking to identify which pages are modified by the saving process, it should use a bitmap even if using another mechanism to track the memory dirtied by the vCPUs. The layout of the tables in guest memory defines an ABI. The entries are laid out in little endian format as described in the last paragraph. KVM_DEV_ARM_ITS_RESTORE_TABLES restore the ITS tables from guest RAM to ITS internal structures. The GICV3 must be restored before the ITS and all ITS registers but the GITS_CTLR must be restored before restoring the ITS tables. The GITS_IIDR read-only register must also be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES as the IIDR revision field encodes the ABI revision. The expected ordering when restoring the GICv3/ITS is described in section "ITS Restore Sequence". Errors: ======= ========================================================== -ENXIO ITS not properly configured as required prior to setting this attribute -ENOMEM Memory shortage when allocating ITS internal data -EINVAL Inconsistent restored data -EFAULT Invalid guest ram access -EBUSY One or more VCPUS are running -EACCES The virtual ITS is backed by a physical GICv4 ITS, and the state is not available without GICv4.1 ======= ========================================================== h](h)}(hhh]h)}(hXAttributes: KVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the ITS, no additional parameter in kvm_device_attr.addr. KVM_DEV_ARM_ITS_CTRL_RESET reset the ITS, no additional parameter in kvm_device_attr.addr. See "ITS Reset State" section. KVM_DEV_ARM_ITS_SAVE_TABLES save the ITS table data into guest RAM, at the location provisioned by the guest in corresponding registers/table entries. Should userspace require a form of dirty tracking to identify which pages are modified by the saving process, it should use a bitmap even if using another mechanism to track the memory dirtied by the vCPUs. The layout of the tables in guest memory defines an ABI. The entries are laid out in little endian format as described in the last paragraph. KVM_DEV_ARM_ITS_RESTORE_TABLES restore the ITS tables from guest RAM to ITS internal structures. The GICV3 must be restored before the ITS and all ITS registers but the GITS_CTLR must be restored before restoring the ITS tables. The GITS_IIDR read-only register must also be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES as the IIDR revision field encodes the ABI revision. The expected ordering when restoring the GICv3/ITS is described in section "ITS Restore Sequence". h](h)}(h Attributes:h]h Attributes:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKJhj>ubh)}(hhh]h)}(hhh](h)}(hsKVM_DEV_ARM_VGIC_CTRL_INIT request the initialization of the ITS, no additional parameter in kvm_device_attr.addr. h](h)}(hKVM_DEV_ARM_VGIC_CTRL_INITh]hKVM_DEV_ARM_VGIC_CTRL_INIT}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjVubh)}(hhh]h)}(hWrequest the initialization of the ITS, no additional parameter in kvm_device_attr.addr.h]hWrequest the initialization of the ITS, no additional parameter in kvm_device_attr.addr.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjhubah}(h]h ]h"]h$]h&]uh1hhjVubeh}(h]h ]h"]h$]h&]uh1hhhhK/hjSubh)}(hzKVM_DEV_ARM_ITS_CTRL_RESET reset the ITS, no additional parameter in kvm_device_attr.addr. See "ITS Reset State" section. h](h)}(hKVM_DEV_ARM_ITS_CTRL_RESETh]hKVM_DEV_ARM_ITS_CTRL_RESET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubh)}(hhh]h)}(h^reset the ITS, no additional parameter in kvm_device_attr.addr. See "ITS Reset State" section.h]hbreset the ITS, no additional parameter in kvm_device_attr.addr. See “ITS Reset State” section.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK3hjSubh)}(hXKVM_DEV_ARM_ITS_SAVE_TABLES save the ITS table data into guest RAM, at the location provisioned by the guest in corresponding registers/table entries. Should userspace require a form of dirty tracking to identify which pages are modified by the saving process, it should use a bitmap even if using another mechanism to track the memory dirtied by the vCPUs. The layout of the tables in guest memory defines an ABI. The entries are laid out in little endian format as described in the last paragraph. h](h)}(hKVM_DEV_ARM_ITS_SAVE_TABLESh]hKVM_DEV_ARM_ITS_SAVE_TABLES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hjubh)}(hhh](h)}(hXIsave the ITS table data into guest RAM, at the location provisioned by the guest in corresponding registers/table entries. Should userspace require a form of dirty tracking to identify which pages are modified by the saving process, it should use a bitmap even if using another mechanism to track the memory dirtied by the vCPUs.h]hXIsave the ITS table data into guest RAM, at the location provisioned by the guest in corresponding registers/table entries. Should userspace require a form of dirty tracking to identify which pages are modified by the saving process, it should use a bitmap even if using another mechanism to track the memory dirtied by the vCPUs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubh)}(hThe layout of the tables in guest memory defines an ABI. The entries are laid out in little endian format as described in the last paragraph.h]hThe layout of the tables in guest memory defines an ABI. The entries are laid out in little endian format as described in the last paragraph.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKubeh}(h]h ]h"]h$]h&]uh1hhhhKJhj;ubah}(h]h ]h"]h$]h&]uh1hhj7ubh)}(hErrors:h]hErrors:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKLhj7ubjJ)}(hX======= ========================================================== -ENXIO ITS not properly configured as required prior to setting this attribute -ENOMEM Memory shortage when allocating ITS internal data -EINVAL Inconsistent restored data -EFAULT Invalid guest ram access -EBUSY One or more VCPUS are running -EACCES The virtual ITS is backed by a physical GICv4 ITS, and the state is not available without GICv4.1 ======= ========================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjwubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK:uh1jhjwubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hGITS not properly configured as required prior to setting this attributeh]hGITS not properly configured as required prior to setting this attribute}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-ENOMEMh]h-ENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h1Memory shortage when allocating ITS internal datah]h1Memory shortage when allocating ITS internal data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hInconsistent restored datah]hInconsistent restored data}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShj9ubah}(h]h ]h"]h$]h&]uh1jhj6ubj)}(hhh]h)}(hInvalid guest ram accessh]hInvalid guest ram access}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjPubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjpubah}(h]h ]h"]h$]h&]uh1jhjmubj)}(hhh]h)}(hOne or more VCPUS are runningh]hOne or more VCPUS are running}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKThjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EACCESh]h-EACCES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(haThe virtual ITS is backed by a physical GICv4 ITS, and the state is not available without GICv4.1h]haThe virtual ITS is backed by a physical GICv4 ITS, and the state is not available without GICv4.1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]colsKuh1jhjtubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1jIhhhKNhj7ubeh}(h]h ]h"]h$]h&]uh1jIhhhK,hj&hhubeh}(h]kvm-dev-arm-vgic-grp-ctrlah ]h"]kvm_dev_arm_vgic_grp_ctrlah$]h&]uh1hhj'hhhhhK*ubh)}(hhh](h)}(hKVM_DEV_ARM_VGIC_GRP_ITS_REGSh]hKVM_DEV_ARM_VGIC_GRP_ITS_REGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKZubjJ)}(hXAttributes: The attr field of kvm_device_attr encodes the offset of the ITS register, relative to the ITS control frame base address (ITS_base). kvm_device_attr.addr points to a __u64 value whatever the width of the addressed register (32/64 bits). 64 bit registers can only be accessed with full length. Writes to read-only registers are ignored by the kernel except for: - GITS_CREADR. It must be restored otherwise commands in the queue will be re-executed after restoring CWRITER. GITS_CREADR must be restored before restoring the GITS_CTLR which is likely to enable the ITS. Also it must be restored after GITS_CBASER since a write to GITS_CBASER resets GITS_CREADR. - GITS_IIDR. The Revision field encodes the table layout ABI revision. In the future we might implement direct injection of virtual LPIs. This will require an upgrade of the table layout and an evolution of the ABI. GITS_IIDR must be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES. For other registers, getting or setting a register has the same effect as reading/writing the register on real hardware. Errors: ======= ==================================================== -ENXIO Offset does not correspond to any supported register -EFAULT Invalid user pointer for attr->addr -EINVAL Offset is not 64-bit aligned -EBUSY one or more VCPUS are running ======= ==================================================== h](h)}(hhh]h)}(hXOAttributes: The attr field of kvm_device_attr encodes the offset of the ITS register, relative to the ITS control frame base address (ITS_base). kvm_device_attr.addr points to a __u64 value whatever the width of the addressed register (32/64 bits). 64 bit registers can only be accessed with full length. Writes to read-only registers are ignored by the kernel except for: - GITS_CREADR. It must be restored otherwise commands in the queue will be re-executed after restoring CWRITER. GITS_CREADR must be restored before restoring the GITS_CTLR which is likely to enable the ITS. Also it must be restored after GITS_CBASER since a write to GITS_CBASER resets GITS_CREADR. - GITS_IIDR. The Revision field encodes the table layout ABI revision. In the future we might implement direct injection of virtual LPIs. This will require an upgrade of the table layout and an evolution of the ABI. GITS_IIDR must be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES. For other registers, getting or setting a register has the same effect as reading/writing the register on real hardware. h](h)}(h Attributes:h]h Attributes:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubh)}(hhh](h)}(hThe attr field of kvm_device_attr encodes the offset of the ITS register, relative to the ITS control frame base address (ITS_base).h]hThe attr field of kvm_device_attr encodes the offset of the ITS register, relative to the ITS control frame base address (ITS_base).}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK]hj,ubh)}(hkvm_device_attr.addr points to a __u64 value whatever the width of the addressed register (32/64 bits). 64 bit registers can only be accessed with full length.h]hkvm_device_attr.addr points to a __u64 value whatever the width of the addressed register (32/64 bits). 64 bit registers can only be accessed with full length.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahj,ubh)}(hCWrites to read-only registers are ignored by the kernel except for:h]hCWrites to read-only registers are ignored by the kernel except for:}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKehj,ubh bullet_list)}(hhh](h list_item)}(hX(GITS_CREADR. It must be restored otherwise commands in the queue will be re-executed after restoring CWRITER. GITS_CREADR must be restored before restoring the GITS_CTLR which is likely to enable the ITS. Also it must be restored after GITS_CBASER since a write to GITS_CBASER resets GITS_CREADR.h]h)}(hX(GITS_CREADR. It must be restored otherwise commands in the queue will be re-executed after restoring CWRITER. GITS_CREADR must be restored before restoring the GITS_CTLR which is likely to enable the ITS. Also it must be restored after GITS_CBASER since a write to GITS_CBASER resets GITS_CREADR.h]hX(GITS_CREADR. It must be restored otherwise commands in the queue will be re-executed after restoring CWRITER. GITS_CREADR must be restored before restoring the GITS_CTLR which is likely to enable the ITS. Also it must be restored after GITS_CBASER since a write to GITS_CBASER resets GITS_CREADR.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKghj`ubah}(h]h ]h"]h$]h&]uh1j^hj[ubj_)}(hX GITS_IIDR. The Revision field encodes the table layout ABI revision. In the future we might implement direct injection of virtual LPIs. This will require an upgrade of the table layout and an evolution of the ABI. GITS_IIDR must be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES. h]h)}(hXGITS_IIDR. The Revision field encodes the table layout ABI revision. In the future we might implement direct injection of virtual LPIs. This will require an upgrade of the table layout and an evolution of the ABI. GITS_IIDR must be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES.h]hXGITS_IIDR. The Revision field encodes the table layout ABI revision. In the future we might implement direct injection of virtual LPIs. This will require an upgrade of the table layout and an evolution of the ABI. GITS_IIDR must be restored before calling KVM_DEV_ARM_ITS_RESTORE_TABLES.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjxubah}(h]h ]h"]h$]h&]uh1j^hj[ubeh}(h]h ]h"]h$]h&]bullet-uh1jYhhhKghj,ubh)}(hxFor other registers, getting or setting a register has the same effect as reading/writing the register on real hardware.h]hxFor other registers, getting or setting a register has the same effect as reading/writing the register on real hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKrhj,ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKshjubah}(h]h ]h"]h$]h&]uh1hhjubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubjJ)}(hX4======= ==================================================== -ENXIO Offset does not correspond to any supported register -EFAULT Invalid user pointer for attr->addr -EINVAL Offset is not 64-bit aligned -EBUSY one or more VCPUS are running ======= ==================================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK4uh1jhjubj)}(hhh](j)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h4Offset does not correspond to any supported registerh]h4Offset does not correspond to any supported register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h#Invalid user pointer for attr->addrh]h#Invalid user pointer for attr->addr}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKyhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hOffset is not 64-bit alignedh]hOffset is not 64-bit aligned}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjoubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]h)}(h-EBUSYh]h-EBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hone or more VCPUS are runningh]hone or more VCPUS are running}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jIhhhKwhjubeh}(h]h ]h"]h$]h&]uh1jIhhhK\hjhhubeh}(h]kvm-dev-arm-vgic-grp-its-regsah ]h"]kvm_dev_arm_vgic_grp_its_regsah$]h&]uh1hhj'hhhhhKZubh)}(hhh](h)}(hITS Restore Sequence:h]hITS Restore Sequence:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h_The following ordering must be followed when restoring the GIC, ITS, and KVM_IRQFD assignments:h]h_The following ordering must be followed when restoring the GIC, ITS, and KVM_IRQFD assignments:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhenumerated_list)}(hhh](j_)}(h)restore all guest memory and create vcpush]h)}(hjh]h)restore all guest memory and create vcpus}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hj hhhhhNubj_)}(hrestore all redistributorsh]h)}(hj'h]hrestore all redistributors}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj%ubah}(h]h ]h"]h$]h&]uh1j^hj hhhhhNubj_)}(h8provide the ITS base address (KVM_DEV_ARM_VGIC_GRP_ADDR)h]h)}(h8provide the ITS base address (KVM_DEV_ARM_VGIC_GRP_ADDR)h]h8provide the ITS base address (KVM_DEV_ARM_VGIC_GRP_ADDR)}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj<ubah}(h]h ]h"]h$]h&]uh1j^hj hhhhhNubj_)}(hrestore the ITS in the following order: 1. Restore GITS_CBASER 2. Restore all other ``GITS_`` registers, except GITS_CTLR! 3. Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES) 4. Restore GITS_CTLR h](h)}(h'restore the ITS in the following order:h]h'restore the ITS in the following order:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjTubjJ)}(h1. Restore GITS_CBASER 2. Restore all other ``GITS_`` registers, except GITS_CTLR! 3. Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES) 4. Restore GITS_CTLR h]j )}(hhh](j_)}(hRestore GITS_CBASERh]h)}(hjoh]hRestore GITS_CBASER}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjmubah}(h]h ]h"]h$]h&]uh1j^hjjubj_)}(h8Restore all other ``GITS_`` registers, except GITS_CTLR!h]h)}(hjh](hRestore all other }(hjhhhNhNubhliteral)}(h ``GITS_``h]hGITS_}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh registers, except GITS_CTLR!}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjjubj_)}(h8Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES)h]h)}(hjh]h8Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjjubj_)}(hRestore GITS_CTLR h]h)}(hRestore GITS_CTLRh]hRestore GITS_CTLR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjjubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j hjfubah}(h]h ]h"]h$]h&]uh1jIhhhKhjTubeh}(h]h ]h"]h$]h&]uh1j^hj hhhhhNubj_)}(h'restore KVM_IRQFD assignments for MSIs h]h)}(h&restore KVM_IRQFD assignments for MSIsh]h&restore KVM_IRQFD assignments for MSIs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hj hhhhhNubeh}(h]h ]h"]h$]h&]j loweralphajhj)uh1j hjhhhhhKubh)}(hThen vcpus can be started.h]hThen vcpus can be started.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]its-restore-sequenceah ]h"]its restore sequence:ah$]h&]uh1hhj'hhhhhKubh)}(hhh](h)}(hITS Table ABI REV0:h]hITS Table ABI REV0:}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+ hhhhhKubjJ)}(hXRevision 0 of the ABI only supports the features of a virtual GICv3, and does not support a virtual GICv4 with support for direct injection of virtual interrupts for nested hypervisors. The device table and ITT are indexed by the DeviceID and EventID, respectively. The collection table is not indexed by CollectionID, and the entries in the collection are listed in no particular order. All entries are 8 bytes. Device Table Entry (DTE):: bits: | 63| 62 ... 49 | 48 ... 5 | 4 ... 0 | values: | V | next | ITT_addr | Size | where: - V indicates whether the entry is valid. If not, other fields are not meaningful. - next: equals to 0 if this entry is the last one; otherwise it corresponds to the DeviceID offset to the next DTE, capped by 2^14 -1. - ITT_addr matches bits [51:8] of the ITT address (256 Byte aligned). - Size specifies the supported number of bits for the EventID, minus one Collection Table Entry (CTE):: bits: | 63| 62 .. 52 | 51 ... 16 | 15 ... 0 | values: | V | RES0 | RDBase | ICID | where: - V indicates whether the entry is valid. If not, other fields are not meaningful. - RES0: reserved field with Should-Be-Zero-or-Preserved behavior. - RDBase is the PE number (GICR_TYPER.Processor_Number semantic), - ICID is the collection ID Interrupt Translation Entry (ITE):: bits: | 63 ... 48 | 47 ... 16 | 15 ... 0 | values: | next | pINTID | ICID | where: - next: equals to 0 if this entry is the last one; otherwise it corresponds to the EventID offset to the next ITE capped by 2^16 -1. - pINTID is the physical LPI ID; if zero, it means the entry is not valid and other fields are not meaningful. - ICID is the collection ID h](h)}(hRevision 0 of the ABI only supports the features of a virtual GICv3, and does not support a virtual GICv4 with support for direct injection of virtual interrupts for nested hypervisors.h]hRevision 0 of the ABI only supports the features of a virtual GICv3, and does not support a virtual GICv4 with support for direct injection of virtual interrupts for nested hypervisors.}(hj@ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubh)}(hThe device table and ITT are indexed by the DeviceID and EventID, respectively. The collection table is not indexed by CollectionID, and the entries in the collection are listed in no particular order. All entries are 8 bytes.h]hThe device table and ITT are indexed by the DeviceID and EventID, respectively. The collection table is not indexed by CollectionID, and the entries in the collection are listed in no particular order. All entries are 8 bytes.}(hjN hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubh)}(hDevice Table Entry (DTE)::h]hDevice Table Entry (DTE):}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubh literal_block)}(habits: | 63| 62 ... 49 | 48 ... 5 | 4 ... 0 | values: | V | next | ITT_addr | Size |h]habits: | 63| 62 ... 49 | 48 ... 5 | 4 ... 0 | values: | V | next | ITT_addr | Size |}hjl sbah}(h]h ]h"]h$]h&]hhuh1jj hhhKhj< ubh)}(hwhere:h]hwhere:}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubjZ)}(hhh](j_)}(hPV indicates whether the entry is valid. If not, other fields are not meaningful.h]h)}(hPV indicates whether the entry is valid. If not, other fields are not meaningful.h]hPV indicates whether the entry is valid. If not, other fields are not meaningful.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the DeviceID offset to the next DTE, capped by 2^14 -1.h]h)}(hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the DeviceID offset to the next DTE, capped by 2^14 -1.h]hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the DeviceID offset to the next DTE, capped by 2^14 -1.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hCITT_addr matches bits [51:8] of the ITT address (256 Byte aligned).h]h)}(hj h]hCITT_addr matches bits [51:8] of the ITT address (256 Byte aligned).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hGSize specifies the supported number of bits for the EventID, minus one h]h)}(hFSize specifies the supported number of bits for the EventID, minus oneh]hFSize specifies the supported number of bits for the EventID, minus one}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubeh}(h]h ]h"]h$]h&]jjuh1jYhhhKhj< ubh)}(hCollection Table Entry (CTE)::h]hCollection Table Entry (CTE):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubjk )}(hmbits: | 63| 62 .. 52 | 51 ... 16 | 15 ... 0 | values: | V | RES0 | RDBase | ICID |h]hmbits: | 63| 62 .. 52 | 51 ... 16 | 15 ... 0 | values: | V | RES0 | RDBase | ICID |}hj sbah}(h]h ]h"]h$]h&]hhuh1jj hhhKhj< ubh)}(hwhere:h]hwhere:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubjZ)}(hhh](j_)}(hPV indicates whether the entry is valid. If not, other fields are not meaningful.h]h)}(hPV indicates whether the entry is valid. If not, other fields are not meaningful.h]hPV indicates whether the entry is valid. If not, other fields are not meaningful.}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(h?RES0: reserved field with Should-Be-Zero-or-Preserved behavior.h]h)}(hj7 h]h?RES0: reserved field with Should-Be-Zero-or-Preserved behavior.}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj5 ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(h?RDBase is the PE number (GICR_TYPER.Processor_Number semantic),h]h)}(hjN h]h?RDBase is the PE number (GICR_TYPER.Processor_Number semantic),}(hjP hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjL ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hICID is the collection ID h]h)}(hICID is the collection IDh]hICID is the collection ID}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjc ubah}(h]h ]h"]h$]h&]uh1j^hj ubeh}(h]h ]h"]h$]h&]jjuh1jYhhhKhj< ubh)}(h#Interrupt Translation Entry (ITE)::h]h"Interrupt Translation Entry (ITE):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubjk )}(h]bits: | 63 ... 48 | 47 ... 16 | 15 ... 0 | values: | next | pINTID | ICID |h]h]bits: | 63 ... 48 | 47 ... 16 | 15 ... 0 | values: | next | pINTID | ICID |}hj sbah}(h]h ]h"]h$]h&]hhuh1jj hhhKhj< ubh)}(hwhere:h]hwhere:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj< ubjZ)}(hhh](j_)}(hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the EventID offset to the next ITE capped by 2^16 -1.h]h)}(hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the EventID offset to the next ITE capped by 2^16 -1.h]hnext: equals to 0 if this entry is the last one; otherwise it corresponds to the EventID offset to the next ITE capped by 2^16 -1.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hlpINTID is the physical LPI ID; if zero, it means the entry is not valid and other fields are not meaningful.h]h)}(hlpINTID is the physical LPI ID; if zero, it means the entry is not valid and other fields are not meaningful.h]hlpINTID is the physical LPI ID; if zero, it means the entry is not valid and other fields are not meaningful.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hICID is the collection ID h]h)}(hICID is the collection IDh]hICID is the collection ID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj ubeh}(h]h ]h"]h$]h&]jjuh1jYhhhKhj< ubeh}(h]h ]h"]h$]h&]uh1jIhhhKhj+ hhubeh}(h]its-table-abi-rev0ah ]h"]its table abi rev0:ah$]h&]uh1hhj'hhhhhKubh)}(hhh](h)}(hITS Reset State:h]hITS Reset State:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hRESET returns the ITS to the same state that it was when first created and initialized. When the RESET command returns, the following things are guaranteed:h]hRESET returns the ITS to the same state that it was when first created and initialized. When the RESET command returns, the following things are guaranteed:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjZ)}(hhh](j_)}(hGThe ITS is not enabled and quiescent GITS_CTLR.Enabled = 0 .Quiescent=1h]h)}(hGThe ITS is not enabled and quiescent GITS_CTLR.Enabled = 0 .Quiescent=1h]hGThe ITS is not enabled and quiescent GITS_CTLR.Enabled = 0 .Quiescent=1}(hj0 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj, ubah}(h]h ]h"]h$]h&]uh1j^hj) hhhhhNubj_)}(h#There is no internally cached stateh]h)}(hjF h]h#There is no internally cached state}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjD ubah}(h]h ]h"]h$]h&]uh1j^hj) hhhhhNubj_)}(h>No collection or device table are used GITS_BASER.Valid = 0h]h)}(h>No collection or device table are used GITS_BASER.Valid = 0h]h>No collection or device table are used GITS_BASER.Valid = 0}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj[ ubah}(h]h ]h"]h$]h&]uh1j^hj) hhhhhNubj_)}(h2GITS_CBASER = 0, GITS_CREADR = 0, GITS_CWRITER = 0h]h)}(hju h]h2GITS_CBASER = 0, GITS_CREADR = 0, GITS_CWRITER = 0}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjs ubah}(h]h ]h"]h$]h&]uh1j^hj) hhhhhNubj_)}(h[The ABI version is unchanged and remains the one set when the ITS device was first created.h]h)}(h[The ABI version is unchanged and remains the one set when the ITS device was first created.h]h[The ABI version is unchanged and remains the one set when the ITS device was first created.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1j^hj) hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jYhhhKhj hhubeh}(h]its-reset-stateah ]h"]its reset state:ah$]h&]uh1hhj'hhhhhKubeh}(h]groupsah ]h"]groupsah$]h&]uh1hhhhhhhhKubeh}(h]-arm-virtual-interrupt-translation-service-itsah ]h"]/arm virtual interrupt translation service (its)ah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(j j j j j#j jjjjj( j% j j j j u nametypes}(j j j#jjj( j j uh}(j hj j'j j8jj&jjj% jj j+ j j u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.