sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget /translations/zh_CN/virt/kvm/apimodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/zh_TW/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/it_IT/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ja_JP/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/ko_KR/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/pt_BR/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget /translations/sp_SP/virt/kvm/apimodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh:/var/lib/git/docbuild/linux/Documentation/virt/kvm/api.rsthKubhsection)}(hhh](htitle)}(hCThe Definitive KVM (Kernel-based Virtual Machine) API Documentationh]hCThe Definitive KVM (Kernel-based Virtual Machine) API Documentation}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h1. General descriptionh]h1. General description}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe kvm API is centered around different kinds of file descriptors and ioctls that can be issued to these file descriptors. An initial open("/dev/kvm") obtains a handle to the kvm subsystem; this handle can be used to issue system ioctls. A KVM_CREATE_VM ioctl on this handle will create a VM file descriptor which can be used to issue VM ioctls. A KVM_CREATE_VCPU or KVM_CREATE_DEVICE ioctl on a VM fd will create a virtual cpu or device and return a file descriptor pointing to the new resource.h]hXThe kvm API is centered around different kinds of file descriptors and ioctls that can be issued to these file descriptors. An initial open(“/dev/kvm”) obtains a handle to the kvm subsystem; this handle can be used to issue system ioctls. A KVM_CREATE_VM ioctl on this handle will create a VM file descriptor which can be used to issue VM ioctls. A KVM_CREATE_VCPU or KVM_CREATE_DEVICE ioctl on a VM fd will create a virtual cpu or device and return a file descriptor pointing to the new resource.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hIn other words, the kvm API is a set of ioctls that are issued to different kinds of file descriptor in order to control various aspects of a virtual machine. Depending on the file descriptor that accepts them, ioctls belong to the following classes:h]hIn other words, the kvm API is a set of ioctls that are issued to different kinds of file descriptor in order to control various aspects of a virtual machine. Depending on the file descriptor that accepts them, ioctls belong to the following classes:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh block_quote)}(hX- System ioctls: These query and set global attributes which affect the whole kvm subsystem. In addition a system ioctl is used to create virtual machines. - VM ioctls: These query and set attributes that affect an entire virtual machine, for example memory layout. In addition a VM ioctl is used to create virtual cpus (vcpus) and devices. VM ioctls must be issued from the same process (address space) that was used to create the VM. - vcpu ioctls: These query and set attributes that control the operation of a single virtual cpu. vcpu ioctls should be issued from the same thread that was used to create the vcpu, except for asynchronous vcpu ioctl that are marked as such in the documentation. Otherwise, the first ioctl after switching threads could see a performance impact. - device ioctls: These query and set attributes that control the operation of a single device. device ioctls must be issued from the same process (address space) that was used to create the VM. h]h bullet_list)}(hhh](h list_item)}(hSystem ioctls: These query and set global attributes which affect the whole kvm subsystem. In addition a system ioctl is used to create virtual machines. h]h)}(hSystem ioctls: These query and set global attributes which affect the whole kvm subsystem. In addition a system ioctl is used to create virtual machines.h]hSystem ioctls: These query and set global attributes which affect the whole kvm subsystem. In addition a system ioctl is used to create virtual machines.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hXVM ioctls: These query and set attributes that affect an entire virtual machine, for example memory layout. In addition a VM ioctl is used to create virtual cpus (vcpus) and devices. VM ioctls must be issued from the same process (address space) that was used to create the VM. h](h)}(hVM ioctls: These query and set attributes that affect an entire virtual machine, for example memory layout. In addition a VM ioctl is used to create virtual cpus (vcpus) and devices.h]hVM ioctls: These query and set attributes that affect an entire virtual machine, for example memory layout. In addition a VM ioctl is used to create virtual cpus (vcpus) and devices.}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj1ubh)}(h^VM ioctls must be issued from the same process (address space) that was used to create the VM.h]h^VM ioctls must be issued from the same process (address space) that was used to create the VM.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj1ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hXZvcpu ioctls: These query and set attributes that control the operation of a single virtual cpu. vcpu ioctls should be issued from the same thread that was used to create the vcpu, except for asynchronous vcpu ioctl that are marked as such in the documentation. Otherwise, the first ioctl after switching threads could see a performance impact. h](h)}(h_vcpu ioctls: These query and set attributes that control the operation of a single virtual cpu.h]h_vcpu ioctls: These query and set attributes that control the operation of a single virtual cpu.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjWubh)}(hvcpu ioctls should be issued from the same thread that was used to create the vcpu, except for asynchronous vcpu ioctl that are marked as such in the documentation. Otherwise, the first ioctl after switching threads could see a performance impact.h]hvcpu ioctls should be issued from the same thread that was used to create the vcpu, except for asynchronous vcpu ioctl that are marked as such in the documentation. Otherwise, the first ioctl after switching threads could see a performance impact.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjWubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hdevice ioctls: These query and set attributes that control the operation of a single device. device ioctls must be issued from the same process (address space) that was used to create the VM. h](h)}(h\device ioctls: These query and set attributes that control the operation of a single device.h]h\device ioctls: These query and set attributes that control the operation of a single device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hj}ubh)}(hbdevice ioctls must be issued from the same process (address space) that was used to create the VM.h]hbdevice ioctls must be issued from the same process (address space) that was used to create the VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hj}ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1j hhhKhhhhubh)}(h~While most ioctls are specific to one kind of file descriptor, in some cases the same ioctl can belong to more than one class.h]h~While most ioctls are specific to one kind of file descriptor, in some cases the same ioctl can belong to more than one class.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hhhhubh)}(hXThe KVM API grew over time. For this reason, KVM defines many constants of the form ``KVM_CAP_*``, each corresponding to a set of functionality provided by one or more ioctls. Availability of these "capabilities" can be checked with :ref:`KVM_CHECK_EXTENSION `. Some capabilities also need to be enabled for VMs or VCPUs where their functionality is desired (see :ref:`cap_enable` and :ref:`cap_enable_vm`).h](hUThe KVM API grew over time. For this reason, KVM defines many constants of the form }(hjhhhNhNubhliteral)}(h ``KVM_CAP_*``h]h KVM_CAP_*}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, each corresponding to a set of functionality provided by one or more ioctls. Availability of these “capabilities” can be checked with }(hjhhhNhNubh)}(h0:ref:`KVM_CHECK_EXTENSION `h]hinline)}(hjh]hKVM_CHECK_EXTENSION}(hjhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc virt/kvm/api refdomainjreftyperef refexplicitrefwarn reftargetkvm_check_extensionuh1hhhhK4hjubhh. Some capabilities also need to be enabled for VMs or VCPUs where their functionality is desired (see }(hjhhhNhNubh)}(h:ref:`cap_enable`h]j)}(hjh]h cap_enable}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj cap_enableuh1hhhhK4hjubh and }(hjhhhNhNubh)}(h:ref:`cap_enable_vm`h]j)}(hj*h]h cap_enable_vm}(hj,hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]refdocj refdomainj6reftyperef refexplicitrefwarnj cap_enable_vmuh1hhhhK4hjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK4hhhhubeh}(h]general-descriptionah ]h"]1. general descriptionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h2. Restrictionsh]h2. Restrictions}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhK=ubh)}(hXxIn general file descriptors can be migrated among processes by means of fork() and the SCM_RIGHTS facility of unix domain socket. These kinds of tricks are explicitly not supported by kvm. While they will not cause harm to the host, their actual behavior is not guaranteed by the API. See "General description" for details on the ioctl usage model that is supported by KVM.h]hX|In general file descriptors can be migrated among processes by means of fork() and the SCM_RIGHTS facility of unix domain socket. These kinds of tricks are explicitly not supported by kvm. While they will not cause harm to the host, their actual behavior is not guaranteed by the API. See “General description” for details on the ioctl usage model that is supported by KVM.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hjZhhubh)}(hX+It is important to note that although VM ioctls may only be issued from the process that created the VM, a VM's lifecycle is associated with its file descriptor, not its creator (process). In other words, the VM and its resources, *including the associated address space*, are not freed until the last reference to the VM's file descriptor has been released. For example, if fork() is issued after ioctl(KVM_CREATE_VM), the VM will not be freed until both the parent (original) process and its child have put their references to the VM's file descriptor.h](hIt is important to note that although VM ioctls may only be issued from the process that created the VM, a VM’s lifecycle is associated with its file descriptor, not its creator (process). In other words, the VM and its resources, }(hjyhhhNhNubhemphasis)}(h(*including the associated address space*h]h&including the associated address space}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjyubhX, are not freed until the last reference to the VM’s file descriptor has been released. For example, if fork() is issued after ioctl(KVM_CREATE_VM), the VM will not be freed until both the parent (original) process and its child have put their references to the VM’s file descriptor.}(hjyhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKFhjZhhubh)}(hXpBecause a VM's resources are not freed until the last reference to its file descriptor is released, creating additional references to a VM via fork(), dup(), etc... without careful consideration is strongly discouraged and may have unwanted side effects, e.g. memory allocated by and on behalf of the VM's process may not be freed/unaccounted when the VM is shut down.h]hXtBecause a VM’s resources are not freed until the last reference to its file descriptor is released, creating additional references to a VM via fork(), dup(), etc... without careful consideration is strongly discouraged and may have unwanted side effects, e.g. memory allocated by and on behalf of the VM’s process may not be freed/unaccounted when the VM is shut down.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKOhjZhhubeh}(h] restrictionsah ]h"]2. restrictionsah$]h&]uh1hhhhhhhhK=ubh)}(hhh](h)}(h 3. Extensionsh]h 3. Extensions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKXubh)}(hAs of Linux 2.6.22, the KVM ABI has been stabilized: no backward incompatible change are allowed. However, there is an extension facility that allows backward-compatible extensions to the API to be queried and used.h]hAs of Linux 2.6.22, the KVM ABI has been stabilized: no backward incompatible change are allowed. However, there is an extension facility that allows backward-compatible extensions to the API to be queried and used.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKZhjhhubh)}(hThe extension mechanism is not based on the Linux version number. Instead, kvm defines extension identifiers and a facility to query whether a particular extension identifier is available. If it is, a set of ioctls is available for application use.h]hThe extension mechanism is not based on the Linux version number. Instead, kvm defines extension identifiers and a facility to query whether a particular extension identifier is available. If it is, a set of ioctls is available for application use.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK_hjhhubeh}(h] extensionsah ]h"] 3. extensionsah$]h&]uh1hhhhhhhhKXubh)}(hhh](h)}(h4. API descriptionh]h4. API description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKfubh)}(hThis section describes ioctls that can be used to control kvm guests. For each ioctl, the following information is provided along with a description:h]hThis section describes ioctls that can be used to control kvm guests. For each ioctl, the following information is provided along with a description:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjhhubj )}(hXCapability: which KVM extension provides this ioctl. Can be 'basic', which means that is will be provided by any kernel that supports API version 12 (see :ref:`KVM_GET_API_VERSION `), or a KVM_CAP_xyz constant that can be checked with :ref:`KVM_CHECK_EXTENSION `. Architectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. Type: system, vm, or vcpu. Parameters: what parameters are accepted by the ioctl. Returns: the return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are. h]hdefinition_list)}(hhh](hdefinition_list_item)}(hX3Capability: which KVM extension provides this ioctl. Can be 'basic', which means that is will be provided by any kernel that supports API version 12 (see :ref:`KVM_GET_API_VERSION `), or a KVM_CAP_xyz constant that can be checked with :ref:`KVM_CHECK_EXTENSION `. h](hterm)}(h Capability:h]h Capability:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKqhjubh definition)}(hhh]h)}(hX&which KVM extension provides this ioctl. Can be 'basic', which means that is will be provided by any kernel that supports API version 12 (see :ref:`KVM_GET_API_VERSION `), or a KVM_CAP_xyz constant that can be checked with :ref:`KVM_CHECK_EXTENSION `.h](hwhich KVM extension provides this ioctl. Can be ‘basic’, which means that is will be provided by any kernel that supports API version 12 (see }(hj)hhhNhNubh)}(h0:ref:`KVM_GET_API_VERSION `h]j)}(hj3h]hKVM_GET_API_VERSION}(hj5hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj1ubah}(h]h ]h"]h$]h&]refdocj refdomainj?reftyperef refexplicitrefwarnjkvm_get_api_versionuh1hhhhKmhj)ubh6), or a KVM_CAP_xyz constant that can be checked with }(hj)hhhNhNubh)}(h0:ref:`KVM_CHECK_EXTENSION `h]j)}(hjWh]hKVM_CHECK_EXTENSION}(hjYhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjUubah}(h]h ]h"]h$]h&]refdocj refdomainjcreftyperef refexplicitrefwarnjkvm_check_extensionuh1hhhhKmhj)ubh.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKmhj&ubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhKqhj ubj)}(hjArchitectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. h](j)}(hArchitectures:h]hArchitectures:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKuhjubj%)}(hhh]h)}(hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.h]hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKthjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhKuhj ubj)}(hType: system, vm, or vcpu. h](j)}(hType:h]hType:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKxhjubj%)}(hhh]h)}(hsystem, vm, or vcpu.h]hsystem, vm, or vcpu.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKxhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhKxhj ubj)}(h7Parameters: what parameters are accepted by the ioctl. h](j)}(h Parameters:h]h Parameters:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhK{hjubj%)}(hhh]h)}(h*what parameters are accepted by the ioctl.h]h*what parameters are accepted by the ioctl.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK{hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhK{hj ubj)}(hReturns: the return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are. h](j)}(hReturns:h]hReturns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj%)}(hhh]h)}(hythe return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are.h]hythe return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK~hj*ubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hhhKlhjhhubhtarget)}(h.. _KVM_GET_API_VERSION:h]h}(h]h ]h"]h$]h&]refidkvm-get-api-versionuh1jShKhjhhhhubh)}(hhh](h)}(h4.1 KVM_GET_API_VERSIONh]h4.1 KVM_GET_API_VERSION}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjahhhhhKubh field_list)}(hhh](hfield)}(hhh](h field_name)}(h Capabilityh]h Capability}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubh field_body)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjthhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjthhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h system ioctlh]h)}(hjh]h system ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjthhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjthhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(h#the constant KVM_API_VERSION (=12) h]h)}(h"the constant KVM_API_VERSION (=12)h]h"the constant KVM_API_VERSION (=12)}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjFubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjthhubeh}(h]h ]h"]h$]h&]uh1jrhjahhhhhKubh)}(hXqThis identifies the API version as the stable kvm API. It is not expected that this number will change. However, Linux 2.6.20 and 2.6.21 report earlier versions; these are not documented and not supported. Applications should refuse to run if KVM_GET_API_VERSION returns a value other than 12. If this check passes, all ioctls described as 'basic' will be available.h]hXuThis identifies the API version as the stable kvm API. It is not expected that this number will change. However, Linux 2.6.20 and 2.6.21 report earlier versions; these are not documented and not supported. Applications should refuse to run if KVM_GET_API_VERSION returns a value other than 12. If this check passes, all ioctls described as ‘basic’ will be available.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjahhubeh}(h](j`id1eh ]h"](4.1 kvm_get_api_versionkvm_get_api_versioneh$]h&]uh1hhjhhhhhKexpect_referenced_by_name}j~jUsexpect_referenced_by_id}j`jUsubh)}(hhh](h)}(h4.2 KVM_CREATE_VMh]h4.2 KVM_CREATE_VM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h system ioctlh]h)}(hjh]h system ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(h"machine type identifier (KVM_VM_*)h]h)}(hj6h]h"machine type identifier (KVM_VM_*)}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj4ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQhhhKubj)}(h=a VM fd that can be used to control the new virtual machine. h]h)}(he.g, to configure a guest to use 48bit physical address size::h]h=e.g, to configure a guest to use 48bit physical address size:}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh literal_block)}(hCvm_fd = ioctl(dev_fd, KVM_CREATE_VM, KVM_VM_TYPE_ARM_IPA_SIZE(48));h]hCvm_fd = ioctl(dev_fd, KVM_CREATE_VM, KVM_VM_TYPE_ARM_IPA_SIZE(48));}hj9sbah}(h]h ]h"]h$]h&]hhuh1j7hhhKhj hhubh)}(h&The requested size (IPA_Bits) must be:h]h&The requested size (IPA_Bits) must be:}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubj )}(hX== ========================================================= 0 Implies default size, 40bits (for backward compatibility) N Implies N bits, where N is a positive integer such that, 32 <= N <= Host_IPA_Limit == ========================================================= h]htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj`ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK9uh1jchj`ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(h0h]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h9Implies default size, 40bits (for backward compatibility)h]h9Implies default size, 40bits (for backward compatibility)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj{ubj)}(hhh](j)}(hhh]h)}(hNh]hN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRImplies N bits, where N is a positive integer such that, 32 <= N <= Host_IPA_Limith]hRImplies N bits, where N is a positive integer such that, 32 <= N <= Host_IPA_Limit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj{ubeh}(h]h ]h"]h$]h&]uh1jyhj`ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj[ubah}(h]h ]h"]h$]h&]uh1jYhjUubah}(h]h ]h"]h$]h&]uh1j hhhKhj hhubh)}(hHost_IPA_Limit is the maximum possible value for IPA_Bits on the host and is dependent on the CPU capability and the kernel configuration. The limit can be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the KVM_CHECK_EXTENSION ioctl() at run-time.h]hHost_IPA_Limit is the maximum possible value for IPA_Bits on the host and is dependent on the CPU capability and the kernel configuration. The limit can be retrieved using KVM_CAP_ARM_VM_IPA_SIZE of the KVM_CHECK_EXTENSION ioctl() at run-time.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hwCreation of the VM will fail if the requested IPA size (whether it is implicit or explicit) is unsupported on the host.h]hwCreation of the VM will fail if the requested IPA size (whether it is implicit or explicit) is unsupported on the host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hPlease note that configuring the IPA size does not affect the capability exposed by the guest CPUs in ID_AA64MMFR0_EL1[PARange]. It only affects size of the address translated by the stage2 level (guest physical to host physical address translations).h]hPlease note that configuring the IPA size does not affect the capability exposed by the guest CPUs in ID_AA64MMFR0_EL1[PARange]. It only affects size of the address translated by the stage2 level (guest physical to host physical address translations).}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]arm64ah ]h"]h$]arm64:ah&]uh1hhjhhhhhKjKubeh}(h] kvm-create-vmah ]h"]4.2 kvm_create_vmah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h:4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LISTh]h:4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LIST}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChhhhhKubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjWhhhKubj)}(hBbasic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LISTh]h)}(hjjh]hBbasic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LIST}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjThhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjThhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h system ioctlh]h)}(hjh]h system ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjThhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_msr_list (in/out)h]h)}(hjh]hstruct kvm_msr_list (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjThhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhKhjThhubeh}(h]h ]h"]h$]h&]uh1jrhjChhhhhKubh)}(hErrors:h]hErrors:}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjChhubj )}(hX/====== ============================================================ EFAULT the msr index list cannot be read from or written to E2BIG the msr index list is too big to fit in the array specified by the user. ====== ============================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjY ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jchjY ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEFAULTh]hEFAULT}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjv ubah}(h]h ]h"]h$]h&]uh1jhjs ubj)}(hhh]h)}(h4the msr index list cannot be read from or written toh]h4the msr index list cannot be read from or written to}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhjs ubeh}(h]h ]h"]h$]h&]uh1j~hjp ubj)}(hhh](j)}(hhh]h)}(hE2BIGh]hE2BIG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hHthe msr index list is too big to fit in the array specified by the user.h]hHthe msr index list is too big to fit in the array specified by the user.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hjp ubeh}(h]h ]h"]h$]h&]uh1jyhjY ubeh}(h]h ]h"]h$]h&]colsKuh1j^hjV ubah}(h]h ]h"]h$]h&]uh1jYhjR ubah}(h]h ]h"]h$]h&]uh1j hhhKhjChhubj8)}(hcstruct kvm_msr_list { __u32 nmsrs; /* number of msrs in entries */ __u32 indices[0]; };h]hcstruct kvm_msr_list { __u32 nmsrs; /* number of msrs in entries */ __u32 indices[0]; };}hj sbah}(h]h ]h"]h$]h&]hhuh1j7hhhKhjChhubh)}(hThe user fills in the size of the indices array in nmsrs, and in return kvm adjusts nmsrs to reflect the actual number of msrs and fills in the indices array with their numbers.h]hThe user fills in the size of the indices array in nmsrs, and in return kvm adjusts nmsrs to reflect the actual number of msrs and fills in the indices array with their numbers.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjChhubh)}(hKVM_GET_MSR_INDEX_LIST returns the guest msrs that are supported. The list varies by kvm version and host processor, but does not change otherwise.h]hKVM_GET_MSR_INDEX_LIST returns the guest msrs that are supported. The list varies by kvm version and host processor, but does not change otherwise.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjChhubh)}(hNote: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are not returned in the MSR list, as different vcpus can have a different number of banks, as set via the KVM_X86_SETUP_MCE ioctl.h]hNote: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are not returned in the MSR list, as different vcpus can have a different number of banks, as set via the KVM_X86_SETUP_MCE ioctl.}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjChhubh)}(hX<KVM_GET_MSR_FEATURE_INDEX_LIST returns the list of MSRs that can be passed to the KVM_GET_MSRS system ioctl. This lets userspace probe host capabilities and processor features that are exposed via MSRs (e.g., VMX capabilities). This list also varies by kvm version and host processor, but does not change otherwise.h]hX<KVM_GET_MSR_FEATURE_INDEX_LIST returns the list of MSRs that can be passed to the KVM_GET_MSRS system ioctl. This lets userspace probe host capabilities and processor features that are exposed via MSRs (e.g., VMX capabilities). This list also varies by kvm version and host processor, but does not change otherwise.}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjChhubjT)}(h.. _KVM_CHECK_EXTENSION:h]h}(h]h ]h"]h$]h&]j_kvm-check-extensionuh1jShMhjChhhhubeh}(h]5kvm-get-msr-index-list-kvm-get-msr-feature-index-listah ]h"]:4.3 kvm_get_msr_index_list, kvm_get_msr_feature_index_listah$]h&]uh1hhjhhhhhKubh)}(hhh](h)}(h4.4 KVM_CHECK_EXTENSIONh]h4.4 KVM_CHECK_EXTENSION}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjS hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjg hhhKubj)}(h.basic, KVM_CAP_CHECK_EXTENSION_VM for vm ioctlh]h)}(hjz h]h.basic, KVM_CAP_CHECK_EXTENSION_VM for vm ioctl}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjx ubah}(h]h ]h"]h$]h&]uh1jhjg ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjd hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hallh]h)}(hj h]hall}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjd hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hsystem ioctl, vm ioctlh]h)}(hj h]hsystem ioctl, vm ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjd hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h extension identifier (KVM_CAP_*)h]h)}(hj h]h extension identifier (KVM_CAP_*)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjd hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hB0 if unsupported; 1 (or some other positive integer) if supported h]h)}(hA0 if unsupported; 1 (or some other positive integer) if supportedh]hA0 if unsupported; 1 (or some other positive integer) if supported}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj0 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjd hhubeh}(h]h ]h"]h$]h&]uh1jrhjS hhhhhM ubh)}(hX@The API allows the application to query about extensions to the core kvm API. Userspace passes an extension identifier (an integer) and receives an integer that describes the extension availability. Generally 0 means no and 1 means yes, but some extensions may report additional information in the integer return value.h]hX@The API allows the application to query about extensions to the core kvm API. Userspace passes an extension identifier (an integer) and receives an integer that describes the extension availability. Generally 0 means no and 1 means yes, but some extensions may report additional information in the integer return value.}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjS hhubh)}(hBased on their initialization different VMs may have different capabilities. It is thus encouraged to use the vm ioctl to query for capabilities (available with KVM_CAP_CHECK_EXTENSION_VM on the vm fd)h]hBased on their initialization different VMs may have different capabilities. It is thus encouraged to use the vm ioctl to query for capabilities (available with KVM_CAP_CHECK_EXTENSION_VM on the vm fd)}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjS hhubeh}(h](jJ id2eh ]h"](4.4 kvm_check_extensionkvm_check_extensioneh$]h&]uh1hhjhhhhhMj}jv j@ sj}jJ j@ subh)}(hhh](h)}(h4.5 KVM_GET_VCPU_MMAP_SIZEh]h4.5 KVM_GET_VCPU_MMAP_SIZE}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{ hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hbasich]h)}(hj h]hbasic}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hallh]h)}(hj h]hall}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h system ioctlh]h)}(hj h]h system ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hnoneh]h)}(hj, h]hnone}(hj. hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj* ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjG hhhKubj)}(h!size of vcpu mmap area, in bytes h]h)}(h size of vcpu mmap area, in bytesh]h size of vcpu mmap area, in bytes}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjX ubah}(h]h ]h"]h$]h&]uh1jhjG ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj hhubeh}(h]h ]h"]h$]h&]uh1jrhj{ hhhhhMubh)}(hThe KVM_RUN ioctl (cf.) communicates with userspace via a shared memory region. This ioctl returns the size of that region. See the KVM_RUN documentation for details.h]hThe KVM_RUN ioctl (cf.) communicates with userspace via a shared memory region. This ioctl returns the size of that region. See the KVM_RUN documentation for details.}(hj| hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj{ hhubh)}(hxBesides the size of the KVM_RUN communication region, other areas of the VCPU file descriptor can be mmap-ed, including:h]hxBesides the size of the KVM_RUN communication region, other areas of the VCPU file descriptor can be mmap-ed, including:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hj{ hhubj)}(hhh](j)}(hif KVM_CAP_COALESCED_MMIO is available, a page at KVM_COALESCED_MMIO_PAGE_OFFSET * PAGE_SIZE; for historical reasons, this page is included in the result of KVM_GET_VCPU_MMAP_SIZE. KVM_CAP_COALESCED_MMIO is not documented yet. h]h)}(hif KVM_CAP_COALESCED_MMIO is available, a page at KVM_COALESCED_MMIO_PAGE_OFFSET * PAGE_SIZE; for historical reasons, this page is included in the result of KVM_GET_VCPU_MMAP_SIZE. KVM_CAP_COALESCED_MMIO is not documented yet.h]hif KVM_CAP_COALESCED_MMIO is available, a page at KVM_COALESCED_MMIO_PAGE_OFFSET * PAGE_SIZE; for historical reasons, this page is included in the result of KVM_GET_VCPU_MMAP_SIZE. KVM_CAP_COALESCED_MMIO is not documented yet.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hif KVM_CAP_DIRTY_LOG_RING is available, a number of pages at KVM_DIRTY_LOG_PAGE_OFFSET * PAGE_SIZE. For more information on KVM_CAP_DIRTY_LOG_RING, see :ref:`KVM_CAP_DIRTY_LOG_RING`. h]h)}(hif KVM_CAP_DIRTY_LOG_RING is available, a number of pages at KVM_DIRTY_LOG_PAGE_OFFSET * PAGE_SIZE. For more information on KVM_CAP_DIRTY_LOG_RING, see :ref:`KVM_CAP_DIRTY_LOG_RING`.h](hif KVM_CAP_DIRTY_LOG_RING is available, a number of pages at KVM_DIRTY_LOG_PAGE_OFFSET * PAGE_SIZE. For more information on KVM_CAP_DIRTY_LOG_RING, see }(hj hhhNhNubh)}(h:ref:`KVM_CAP_DIRTY_LOG_RING`h]j)}(hj h]hKVM_CAP_DIRTY_LOG_RING}(hj hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]refdocj refdomainj reftyperef refexplicitrefwarnjkvm_cap_dirty_log_ringuh1hhhhM.hj ubh.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM.hj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM)hj{ hhubeh}(h]kvm-get-vcpu-mmap-sizeah ]h"]4.5 kvm_get_vcpu_mmap_sizeah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.7 KVM_CREATE_VCPUh]h4.7 KVM_CREATE_VCPU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM4ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hbasich]h)}(hj$ h]hbasic}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj" ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hj hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj? hhhKubj)}(hallh]h)}(hjR h]hall}(hjT hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjP ubah}(h]h ]h"]h$]h&]uh1jhj? ubeh}(h]h ]h"]h$]h&]uh1jwhhhM7hj hhubjx)}(hhh](j})}(hTypeh]hType}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjm hhhKubj)}(hvm ioctlh]h)}(hj h]hvm ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj~ ubah}(h]h ]h"]h$]h&]uh1jhjm ubeh}(h]h ]h"]h$]h&]uh1jwhhhM8hj hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvcpu id (apic id on x86)h]h)}(hj h]hvcpu id (apic id on x86)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM9hj hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h vcpu fd on success, -1 on error h]h)}(hvcpu fd on success, -1 on errorh]hvcpu fd on success, -1 on error}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM:hj hhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhM6ubh)}(hThis API adds a vcpu to a virtual machine. No more than max_vcpus may be added. The vcpu id is an integer in the range [0, max_vcpu_id).h]hThis API adds a vcpu to a virtual machine. No more than max_vcpus may be added. The vcpu id is an integer in the range [0, max_vcpu_id).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj hhubh)}(hXThe recommended max_vcpus value can be retrieved using the KVM_CAP_NR_VCPUS of the KVM_CHECK_EXTENSION ioctl() at run-time. The maximum possible value for max_vcpus can be retrieved using the KVM_CAP_MAX_VCPUS of the KVM_CHECK_EXTENSION ioctl() at run-time.h]hXThe recommended max_vcpus value can be retrieved using the KVM_CAP_NR_VCPUS of the KVM_CHECK_EXTENSION ioctl() at run-time. The maximum possible value for max_vcpus can be retrieved using the KVM_CAP_MAX_VCPUS of the KVM_CHECK_EXTENSION ioctl() at run-time.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj hhubh)}(hIf the KVM_CAP_NR_VCPUS does not exist, you should assume that max_vcpus is 4 cpus max. If the KVM_CAP_MAX_VCPUS does not exist, you should assume that max_vcpus is same as the value returned from KVM_CAP_NR_VCPUS.h]hIf the KVM_CAP_NR_VCPUS does not exist, you should assume that max_vcpus is 4 cpus max. If the KVM_CAP_MAX_VCPUS does not exist, you should assume that max_vcpus is same as the value returned from KVM_CAP_NR_VCPUS.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhj hhubh)}(hThe maximum possible value for max_vcpu_id can be retrieved using the KVM_CAP_MAX_VCPU_ID of the KVM_CHECK_EXTENSION ioctl() at run-time.h]hThe maximum possible value for max_vcpu_id can be retrieved using the KVM_CAP_MAX_VCPU_ID of the KVM_CHECK_EXTENSION ioctl() at run-time.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj hhubh)}(hIf the KVM_CAP_MAX_VCPU_ID does not exist, you should assume that max_vcpu_id is the same as the value returned from KVM_CAP_MAX_VCPUS.h]hIf the KVM_CAP_MAX_VCPU_ID does not exist, you should assume that max_vcpu_id is the same as the value returned from KVM_CAP_MAX_VCPUS.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj hhubh)}(hXOn powerpc using book3s_hv mode, the vcpus are mapped onto virtual threads in one or more virtual CPU cores. (This is because the hardware requires all the hardware threads in a CPU core to be in the same partition.) The KVM_CAP_PPC_SMT capability indicates the number of vcpus per virtual core (vcore). The vcore id is obtained by dividing the vcpu id by the number of vcpus per vcore. The vcpus in a given vcore will always be in the same physical core as each other (though that might be a different physical core from time to time). Userspace can control the threading (SMT) mode of the guest by its allocation of vcpu ids. For example, if userspace wants single-threaded guest vcpus, it should make all vcpu ids be a multiple of the number of vcpus per vcore.h]hXOn powerpc using book3s_hv mode, the vcpus are mapped onto virtual threads in one or more virtual CPU cores. (This is because the hardware requires all the hardware threads in a CPU core to be in the same partition.) The KVM_CAP_PPC_SMT capability indicates the number of vcpus per virtual core (vcore). The vcore id is obtained by dividing the vcpu id by the number of vcpus per vcore. The vcpus in a given vcore will always be in the same physical core as each other (though that might be a different physical core from time to time). Userspace can control the threading (SMT) mode of the guest by its allocation of vcpu ids. For example, if userspace wants single-threaded guest vcpus, it should make all vcpu ids be a multiple of the number of vcpus per vcore.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj hhubh)}(hFor virtual cpus that have been created with S390 user controlled virtual machines, the resulting vcpu fd can be memory mapped at page offset KVM_S390_SIE_PAGE_OFFSET in order to obtain a memory map of the virtual cpu's hardware control block.h]hFor virtual cpus that have been created with S390 user controlled virtual machines, the resulting vcpu fd can be memory mapped at page offset KVM_S390_SIE_PAGE_OFFSET in order to obtain a memory map of the virtual cpu’s hardware control block.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj hhubeh}(h]kvm-create-vcpuah ]h"]4.7 kvm_create_vcpuah$]h&]uh1hhjhhhhhM4ubh)}(hhh](h)}(h4.8 KVM_GET_DIRTY_LOGh]h4.8 KVM_GET_DIRTY_LOG}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhMcubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj|hhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jwhhhMehjyhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMfhjyhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMghjyhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_dirty_log (in/out)h]h)}(hjh]hstruct kvm_dirty_log (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhhjyhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMihjyhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhhMeubj8)}(h/* for KVM_GET_DIRTY_LOG */ struct kvm_dirty_log { __u32 slot; __u32 padding; union { void __user *dirty_bitmap; /* one bit per page */ __u64 padding; }; };h]h/* for KVM_GET_DIRTY_LOG */ struct kvm_dirty_log { __u32 slot; __u32 padding; union { void __user *dirty_bitmap; /* one bit per page */ __u64 padding; }; };}hjisbah}(h]h ]h"]h$]h&]hhuh1j7hhhMmhjhhhubh)}(hGiven a memory slot, return a bitmap containing any pages dirtied since the last call to this ioctl. Bit 0 is the first page in the memory slot. Ensure the entire structure is cleared to avoid padding issues.h]hGiven a memory slot, return a bitmap containing any pages dirtied since the last call to this ioctl. Bit 0 is the first page in the memory slot. Ensure the entire structure is cleared to avoid padding issues.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjhhhubh)}(hIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of slot field specifies the address space for which you want to return the dirty bitmap. See KVM_SET_USER_MEMORY_REGION for details on the usage of slot field.h]hIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of slot field specifies the address space for which you want to return the dirty bitmap. See KVM_SET_USER_MEMORY_REGION for details on the usage of slot field.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjhhhubh)}(hThe bits in the dirty bitmap are cleared before the ioctl returns, unless KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is enabled. For more information, see the description of the capability.h]hThe bits in the dirty bitmap are cleared before the ioctl returns, unless KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is enabled. For more information, see the description of the capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhhubh)}(h}Note that the Xen shared_info page, if configured, shall always be assumed to be dirty. KVM will not explicitly mark it such.h]h}Note that the Xen shared_info page, if configured, shall always be assumed to be dirty. KVM will not explicitly mark it such.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhhubeh}(h]kvm-get-dirty-logah ]h"]4.8 kvm_get_dirty_logah$]h&]uh1hhjhhhhhMcubh)}(hhh](h)}(h 4.10 KVM_RUNh]h 4.10 KVM_RUN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hj h]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj'hhhKubj)}(h vcpu ioctlh]h)}(hj:h]h vcpu ioctl}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hnoneh]h)}(hjhh]hnone}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hX======= ============================================================== EINTR an unmasked signal is pending ENOEXEC the vcpu hasn't been initialized or the guest tried to execute instructions from device memory (arm64) ENOSYS data abort outside memslots with no syndrome info and KVM_CAP_ARM_NISV_TO_USER not enabled (arm64) EPERM SVE feature set but not finalized (arm64) ======= ============================================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEINTRh]hEINTR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(han unmasked signal is pendingh]han unmasked signal is pending}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hENOEXECh]hENOEXEC}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hfthe vcpu hasn't been initialized or the guest tried to execute instructions from device memory (arm64)h]hhthe vcpu hasn’t been initialized or the guest tried to execute instructions from device memory (arm64)}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hENOSYSh]hENOSYS}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hbdata abort outside memslots with no syndrome info and KVM_CAP_ARM_NISV_TO_USER not enabled (arm64)h]hbdata abort outside memslots with no syndrome info and KVM_CAP_ARM_NISV_TO_USER not enabled (arm64)}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEPERMh]hEPERM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h)SVE feature set but not finalized (arm64)h]h)SVE feature set but not finalized (arm64)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhMhjhhubh)}(hX+This ioctl is used to run a guest virtual cpu. While there are no explicit parameters, there is an implicit parameter block that can be obtained by mmap()ing the vcpu fd at offset 0, with the size given by KVM_GET_VCPU_MMAP_SIZE. The parameter block is formatted as a 'struct kvm_run' (see below).h]hX/This ioctl is used to run a guest virtual cpu. While there are no explicit parameters, there is an implicit parameter block that can be obtained by mmap()ing the vcpu fd at offset 0, with the size given by KVM_GET_VCPU_MMAP_SIZE. The parameter block is formatted as a ‘struct kvm_run’ (see below).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-runah ]h"] 4.10 kvm_runah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.11 KVM_GET_REGSh]h4.11 KVM_GET_REGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hall except arm64h]h)}(hjGh]hall except arm64}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(h vcpu ioctlh]h)}(hjuh]h vcpu ioctl}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_regs (out)h]h)}(hjh]hstruct kvm_regs (out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(h2Reads the general purpose registers from the vcpu.h]h2Reads the general purpose registers from the vcpu.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hX/* x86 */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ __u64 rax, rbx, rcx, rdx; __u64 rsi, rdi, rsp, rbp; __u64 r8, r9, r10, r11; __u64 r12, r13, r14, r15; __u64 rip, rflags; }; /* mips */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ __u64 gpr[32]; __u64 hi; __u64 lo; __u64 pc; }; /* LoongArch */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ unsigned long gpr[32]; unsigned long pc; };h]hX/* x86 */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ __u64 rax, rbx, rcx, rdx; __u64 rsi, rdi, rsp, rbp; __u64 r8, r9, r10, r11; __u64 r12, r13, r14, r15; __u64 rip, rflags; }; /* mips */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ __u64 gpr[32]; __u64 hi; __u64 lo; __u64 pc; }; /* LoongArch */ struct kvm_regs { /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ unsigned long gpr[32]; unsigned long pc; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubeh}(h] kvm-get-regsah ]h"]4.11 kvm_get_regsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.12 KVM_SET_REGSh]h4.12 KVM_SET_REGS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(hbasich]h)}(hj>h]hbasic}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hall except arm64h]h)}(hjlh]hall except arm64}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_regs (in)h]h)}(hjh]hstruct kvm_regs (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(h3Writes the general purpose registers into the vcpu.h]h3Writes the general purpose registers into the vcpu.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h(See KVM_GET_REGS for the data structure.h]h(See KVM_GET_REGS for the data structure.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h] kvm-set-regsah ]h"]4.12 kvm_set_regsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.13 KVM_GET_SREGSh]h4.13 KVM_GET_SREGS}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hbasich]h)}(hjch]hbasic}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjaubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjMhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(hx86, ppch]h)}(hjh]hx86, ppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjMhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjMhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_sregs (out)h]h)}(hjh]hstruct kvm_sregs (out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjMhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjMhhubeh}(h]h ]h"]h$]h&]uh1jrhj<hhhhhMubh)}(h&Reads special registers from the vcpu.h]h&Reads special registers from the vcpu.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubj8)}(hXU/* x86 */ struct kvm_sregs { struct kvm_segment cs, ds, es, fs, gs, ss; struct kvm_segment tr, ldt; struct kvm_dtable gdt, idt; __u64 cr0, cr2, cr3, cr4, cr8; __u64 efer; __u64 apic_base; __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; }; /* ppc -- see arch/powerpc/include/uapi/asm/kvm.h */h]hXU/* x86 */ struct kvm_sregs { struct kvm_segment cs, ds, es, fs, gs, ss; struct kvm_segment tr, ldt; struct kvm_dtable gdt, idt; __u64 cr0, cr2, cr3, cr4, cr8; __u64 efer; __u64 apic_base; __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; }; /* ppc -- see arch/powerpc/include/uapi/asm/kvm.h */}hjKsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj<hhubh)}(hinterrupt_bitmap is a bitmap of pending external interrupts. At most one bit may be set. This interrupt has been acknowledged by the APIC but not yet injected into the cpu core.h]hinterrupt_bitmap is a bitmap of pending external interrupts. At most one bit may be set. This interrupt has been acknowledged by the APIC but not yet injected into the cpu core.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<hhubeh}(h] kvm-get-sregsah ]h"]4.13 kvm_get_sregsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.14 KVM_SET_SREGSh]h4.14 KVM_SET_SREGS}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86, ppch]h)}(hjh]hx86, ppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hstruct kvm_sregs (in)h]h)}(hj h]hstruct kvm_sregs (in)}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj;hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjohhhhhMubh)}(hSWrites special registers into the vcpu. See KVM_GET_SREGS for the data structures.h]hSWrites special registers into the vcpu. See KVM_GET_SREGS for the data structures.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjohhubeh}(h] kvm-set-sregsah ]h"]4.14 kvm_set_sregsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.15 KVM_TRANSLATEh]h4.15 KVM_TRANSLATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hj h]h vcpu ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(hstruct kvm_translation (in/out)h]h)}(hj7h]hstruct kvm_translation (in/out)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj5ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjcubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hVTranslates a virtual address according to the vcpu's current address translation mode.h]hXTranslates a virtual address according to the vcpu’s current address translation mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hstruct kvm_translation { /* in */ __u64 linear_address; /* out */ __u64 physical_address; __u8 valid; __u8 writeable; __u8 usermode; __u8 pad[5]; };h]hstruct kvm_translation { /* in */ __u64 linear_address; /* out */ __u64 physical_address; __u8 valid; __u8 writeable; __u8 usermode; __u8 pad[5]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubeh}(h] kvm-translateah ]h"]4.15 kvm_translateah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.16 KVM_INTERRUPTh]h4.16 KVM_INTERRUPT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM!ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h x86, ppc, mips, riscv, loongarchh]h)}(hjh]h x86, ppc, mips, riscv, loongarch}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hj.h]h vcpu ioctl}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjIhhhKubj)}(hstruct kvm_interrupt (in)h]h)}(hj\h]hstruct kvm_interrupt (in)}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjZubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jwhhhM&hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjwhhhKubj)}(h#0 on success, negative on failure. h]h)}(h"0 on success, negative on failure.h]h"0 on success, negative on failure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jwhhhM'hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM#ubh)}(h2Queues a hardware interrupt vector to be injected.h]h2Queues a hardware interrupt vector to be injected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjhhubj8)}(hQ/* for KVM_INTERRUPT */ struct kvm_interrupt { /* in */ __u32 irq; };h]hQ/* for KVM_INTERRUPT */ struct kvm_interrupt { /* in */ __u32 irq; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM-hjhhubh)}(hhh](h)}(hX86:h]hX86:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM4ubjs)}(hhh]jx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hX========= =================================== 0 on success, -EEXIST if an interrupt is already enqueued -EINVAL the irq number is invalid -ENXIO if the PIC is in the kernel -EFAULT if the pointer is invalid ========= =================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK#uh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h on success,h]h on success,}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj ubj)}(hhh](j)}(hhh]h)}(h-EEXISTh]h-EEXIST}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjGubah}(h]h ]h"]h$]h&]uh1jhjDubj)}(hhh]h)}(h#if an interrupt is already enqueuedh]h#if an interrupt is already enqueued}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj^ubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1j~hj ubj)}(hhh](j)}(hhh]h)}(h-EINVALh]h-EINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj~ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(hthe irq number is invalidh]hthe irq number is invalid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j~hj ubj)}(hhh](j)}(hhh]h)}(h-ENXIOh]h-ENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hif the PIC is in the kernelh]hif the PIC is in the kernel}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj ubj)}(hhh](j)}(hhh]h)}(h-EFAULTh]h-EFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hif the pointer is invalidh]hif the pointer is invalid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj ubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM6ubh)}(hwNote 'irq' is an interrupt vector, not an interrupt pin or line. This ioctl is useful if the in-kernel PIC is not used.h]h{Note ‘irq’ is an interrupt vector, not an interrupt pin or line. This ioctl is useful if the in-kernel PIC is not used.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjhhubeh}(h]id3ah ]h"]h$]jah&]uh1hhjhhhhhM4jKubh)}(hhh](h)}(hPPC:h]hPPC:}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhMDubh)}(hbQueues an external interrupt to be injected. This ioctl is overloaded with 3 different irq values:h]hbQueues an external interrupt to be injected. This ioctl is overloaded with 3 different irq values:}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjZhhubhenumerated_list)}(hhh](j)}(hKVM_INTERRUPT_SET This injects an edge type external interrupt into the guest once it's ready to receive interrupts. When injected, the interrupt is done. h](h)}(hKVM_INTERRUPT_SETh]hKVM_INTERRUPT_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj~ubh)}(hThis injects an edge type external interrupt into the guest once it's ready to receive interrupts. When injected, the interrupt is done.h]hThis injects an edge type external interrupt into the guest once it’s ready to receive interrupts. When injected, the interrupt is done.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhj~ubeh}(h]h ]h"]h$]h&]uh1jhj{hhhhhNubj)}(hdKVM_INTERRUPT_UNSET This unsets any pending interrupt. Only available with KVM_CAP_PPC_UNSET_IRQ. h](h)}(hKVM_INTERRUPT_UNSETh]hKVM_INTERRUPT_UNSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjubh)}(h"This unsets any pending interrupt.h]h"This unsets any pending interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubh)}(h*Only available with KVM_CAP_PPC_UNSET_IRQ.h]h*Only available with KVM_CAP_PPC_UNSET_IRQ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhjubeh}(h]h ]h"]h$]h&]uh1jhj{hhhhhNubj)}(hKVM_INTERRUPT_SET_LEVEL This injects a level type external interrupt into the guest context. The interrupt stays pending until a specific ioctl with KVM_INTERRUPT_UNSET is triggered. Only available with KVM_CAP_PPC_IRQ_LEVEL. h](h)}(hKVM_INTERRUPT_SET_LEVELh]hKVM_INTERRUPT_SET_LEVEL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjubh)}(hThis injects a level type external interrupt into the guest context. The interrupt stays pending until a specific ioctl with KVM_INTERRUPT_UNSET is triggered.h]hThis injects a level type external interrupt into the guest context. The interrupt stays pending until a specific ioctl with KVM_INTERRUPT_UNSET is triggered.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjubh)}(h*Only available with KVM_CAP_PPC_IRQ_LEVEL.h]h*Only available with KVM_CAP_PPC_IRQ_LEVEL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjubeh}(h]h ]h"]h$]h&]uh1jhj{hhhhhNubeh}(h]h ]h"]h$]h&]enumtype loweralphaprefixhsuffix)uh1jyhjZhhhhhMIubh)}(hiNote that any value for 'irq' other than the ones stated above is invalid and incurs unexpected behavior.h]hmNote that any value for ‘irq’ other than the ones stated above is invalid and incurs unexpected behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjZhhubh)}(hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.h]hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hjZhhubeh}(h]ppcah ]h"]ppc:ah$]h&]uh1hhjhhhhhMDubh)}(hhh](h)}(hMIPS:h]hMIPS:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;hhhhhMbubh)}(huQueues an external interrupt to be injected into the virtual CPU. A negative interrupt number dequeues the interrupt.h]huQueues an external interrupt to be injected into the virtual CPU. A negative interrupt number dequeues the interrupt.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhj;hhubh)}(hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.h]hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj;hhubeh}(h]id4ah ]h"]h$]jah&]uh1hhjhhhhhMbjKubh)}(hhh](h)}(hRISC-V:h]hRISC-V:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjohhhhhMjubh)}(hwQueues an external interrupt to be injected into the virtual CPU. This ioctl is overloaded with 2 different irq values:h]hwQueues an external interrupt to be injected into the virtual CPU. This ioctl is overloaded with 2 different irq values:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjohhubjz)}(hhh](j)}(hhKVM_INTERRUPT_SET This sets external interrupt for a virtual CPU and it will receive once it is ready. h](h)}(hKVM_INTERRUPT_SETh]hKVM_INTERRUPT_SET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjubh)}(hTThis sets external interrupt for a virtual CPU and it will receive once it is ready.h]hTThis sets external interrupt for a virtual CPU and it will receive once it is ready.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hOKVM_INTERRUPT_UNSET This clears pending external interrupt for a virtual CPU. h](h)}(hKVM_INTERRUPT_UNSETh]hKVM_INTERRUPT_UNSET}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjubh)}(h9This clears pending external interrupt for a virtual CPU.h]h9This clears pending external interrupt for a virtual CPU.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjjhjjuh1jyhjohhhhhMoubh)}(hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.h]hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjohhubeh}(h]risc-vah ]h"]risc-v:ah$]h&]uh1hhjhhhhhMjubh)}(hhh](h)}(h LOONGARCH:h]h LOONGARCH:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM{ubh)}(huQueues an external interrupt to be injected into the virtual CPU. A negative interrupt number dequeues the interrupt.h]huQueues an external interrupt to be injected into the virtual CPU. A negative interrupt number dequeues the interrupt.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjhhubh)}(hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.h]hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h] loongarchah ]h"] loongarch:ah$]h&]uh1hhjhhhhhM{ubeh}(h] kvm-interruptah ]h"]4.16 kvm_interruptah$]h&]uh1hhjhhhhhM!ubh)}(hhh](h)}(h4.18 KVM_GET_MSRSh]h4.18 KVM_GET_MSRS}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJhhhKubj)}(h/basic (vcpu), KVM_CAP_GET_MSR_FEATURES (system)h]h)}(hj]h]h/basic (vcpu), KVM_CAP_GET_MSR_FEATURES (system)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hsystem ioctl, vcpu ioctlh]h)}(hjh]hsystem ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_msrs (in/out)h]h)}(hjh]hstruct kvm_msrs (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h2number of msrs successfully returned; -1 on error h]h)}(h1number of msrs successfully returned; -1 on errorh]h1number of msrs successfully returned; -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubeh}(h]h ]h"]h$]h&]uh1jrhj6hhhhhMubh)}(hXWhen used as a system ioctl: Reads the values of MSR-based features that are available for the VM. This is similar to KVM_GET_SUPPORTED_CPUID, but it returns MSR indices and values. The list of msr-based features can be obtained using KVM_GET_MSR_FEATURE_INDEX_LIST in a system ioctl.h]hXWhen used as a system ioctl: Reads the values of MSR-based features that are available for the VM. This is similar to KVM_GET_SUPPORTED_CPUID, but it returns MSR indices and values. The list of msr-based features can be obtained using KVM_GET_MSR_FEATURE_INDEX_LIST in a system ioctl.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hWhen used as a vcpu ioctl: Reads model-specific registers from the vcpu. Supported msr indices can be obtained using KVM_GET_MSR_INDEX_LIST in a system ioctl.h]hWhen used as a vcpu ioctl: Reads model-specific registers from the vcpu. Supported msr indices can be obtained using KVM_GET_MSR_INDEX_LIST in a system ioctl.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubj8)}(hstruct kvm_msrs { __u32 nmsrs; /* number of msrs in entries */ __u32 pad; struct kvm_msr_entry entries[0]; }; struct kvm_msr_entry { __u32 index; __u32 reserved; __u64 data; };h]hstruct kvm_msrs { __u32 nmsrs; /* number of msrs in entries */ __u32 pad; struct kvm_msr_entry entries[0]; }; struct kvm_msr_entry { __u32 index; __u32 reserved; __u64 data; };}hjSsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj6hhubh)}(hApplication code should set the 'nmsrs' member (which indicates the size of the entries array) and the 'index' member of each array entry. kvm will fill in the 'data' member.h]hApplication code should set the ‘nmsrs’ member (which indicates the size of the entries array) and the ‘index’ member of each array entry. kvm will fill in the ‘data’ member.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubeh}(h] kvm-get-msrsah ]h"]4.18 kvm_get_msrsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.19 KVM_SET_MSRSh]h4.19 KVM_SET_MSRS}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_msrs (in)h]h)}(hj(h]hstruct kvm_msrs (in)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(h9number of msrs successfully set (see below), -1 on error h]h)}(h8number of msrs successfully set (see below), -1 on errorh]h8number of msrs successfully set (see below), -1 on error}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjwhhhhhMubh)}(hWWrites model-specific registers to the vcpu. See KVM_GET_MSRS for the data structures.h]hWWrites model-specific registers to the vcpu. See KVM_GET_MSRS for the data structures.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwhhubh)}(hApplication code should set the 'nmsrs' member (which indicates the size of the entries array), and the 'index' and 'data' members of each array entry.h]hApplication code should set the ‘nmsrs’ member (which indicates the size of the entries array), and the ‘index’ and ‘data’ members of each array entry.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwhhubh)}(hXIt tries to set the MSRs in array entries[] one by one. If setting an MSR fails, e.g., due to setting reserved bits, the MSR isn't supported/emulated by KVM, etc..., it stops processing the MSR list and returns the number of MSRs that have been set successfully.h]hXIt tries to set the MSRs in array entries[] one by one. If setting an MSR fails, e.g., due to setting reserved bits, the MSR isn’t supported/emulated by KVM, etc..., it stops processing the MSR list and returns the number of MSRs that have been set successfully.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwhhubeh}(h] kvm-set-msrsah ]h"]4.19 kvm_set_msrsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.20 KVM_SET_CPUIDh]h4.20 KVM_SET_CPUID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hj-h]h vcpu ioctl}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjHhhhKubj)}(hstruct kvm_cpuid (in)h]h)}(hj[h]hstruct kvm_cpuid (in)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjvhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(htDefines the vcpu responses to the cpuid instruction. Applications should use the KVM_SET_CPUID2 ioctl if available.h]htDefines the vcpu responses to the cpuid instruction. Applications should use the KVM_SET_CPUID2 ioctl if available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hhh]j)}(hXCaveat emptor: - If this IOCTL fails, KVM gives no guarantees that previous valid CPUID configuration (if there is) is not corrupted. Userspace can get a copy of the resulting CPUID configuration through KVM_GET_CPUID2 in case. - Using KVM_SET_CPUID{,2} after KVM_RUN, i.e. changing the guest vCPU model after running the guest, may cause guest instability. - Using heterogeneous CPUID configurations, modulo APIC IDs, topology, etc... may cause guest instability. h](j)}(hCaveat emptor:h]hCaveat emptor:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj%)}(hhh]j)}(hhh](j)}(hIf this IOCTL fails, KVM gives no guarantees that previous valid CPUID configuration (if there is) is not corrupted. Userspace can get a copy of the resulting CPUID configuration through KVM_GET_CPUID2 in case.h]h)}(hIf this IOCTL fails, KVM gives no guarantees that previous valid CPUID configuration (if there is) is not corrupted. Userspace can get a copy of the resulting CPUID configuration through KVM_GET_CPUID2 in case.h]hIf this IOCTL fails, KVM gives no guarantees that previous valid CPUID configuration (if there is) is not corrupted. Userspace can get a copy of the resulting CPUID configuration through KVM_GET_CPUID2 in case.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hUsing KVM_SET_CPUID{,2} after KVM_RUN, i.e. changing the guest vCPU model after running the guest, may cause guest instability.h]h)}(hUsing KVM_SET_CPUID{,2} after KVM_RUN, i.e. changing the guest vCPU model after running the guest, may cause guest instability.h]hUsing KVM_SET_CPUID{,2} after KVM_RUN, i.e. changing the guest vCPU model after running the guest, may cause guest instability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hiUsing heterogeneous CPUID configurations, modulo APIC IDs, topology, etc... may cause guest instability. h]h)}(hhUsing heterogeneous CPUID configurations, modulo APIC IDs, topology, etc... may cause guest instability.h]hhUsing heterogeneous CPUID configurations, modulo APIC IDs, topology, etc... may cause guest instability.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubj8)}(hX struct kvm_cpuid_entry { __u32 function; __u32 eax; __u32 ebx; __u32 ecx; __u32 edx; __u32 padding; }; /* for KVM_SET_CPUID */ struct kvm_cpuid { __u32 nent; __u32 padding; struct kvm_cpuid_entry entries[0]; };h]hX struct kvm_cpuid_entry { __u32 function; __u32 eax; __u32 ebx; __u32 ecx; __u32 edx; __u32 padding; }; /* for KVM_SET_CPUID */ struct kvm_cpuid { __u32 nent; __u32 padding; struct kvm_cpuid_entry entries[0]; };}hj4 sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubeh}(h] kvm-set-cpuidah ]h"]4.20 kvm_set_cpuidah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.21 KVM_SET_SIGNAL_MASKh]h4.21 KVM_SET_SIGNAL_MASK}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^ hhhKubj)}(hbasich]h)}(hjq h]hbasic}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjo ubah}(h]h ]h"]h$]h&]uh1jhj^ ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj[ hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hallh]h)}(hj h]hall}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj[ hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h vcpu ioctlh]h)}(hj h]h vcpu ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj[ hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hstruct kvm_signal_mask (in)h]h)}(hj h]hstruct kvm_signal_mask (in)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj[ hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj!hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj+!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj[ hhubeh}(h]h ]h"]h$]h&]uh1jrhjJ hhhhhMubh)}(hXDefines which signals are blocked during execution of KVM_RUN. This signal mask temporarily overrides the threads signal mask. Any unblocked signal received (except SIGKILL and SIGSTOP, which retain their traditional behaviour) will cause KVM_RUN to return with -EINTR.h]hXDefines which signals are blocked during execution of KVM_RUN. This signal mask temporarily overrides the threads signal mask. Any unblocked signal received (except SIGKILL and SIGSTOP, which retain their traditional behaviour) will cause KVM_RUN to return with -EINTR.}(hjK!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJ hhubh)}(hRNote the signal will only be delivered if not blocked by the original signal mask.h]hRNote the signal will only be delivered if not blocked by the original signal mask.}(hjY!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJ hhubj8)}(ha/* for KVM_SET_SIGNAL_MASK */ struct kvm_signal_mask { __u32 len; __u8 sigset[0]; };h]ha/* for KVM_SET_SIGNAL_MASK */ struct kvm_signal_mask { __u32 len; __u8 sigset[0]; };}hjg!sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjJ hhubeh}(h]kvm-set-signal-maskah ]h"]4.21 kvm_set_signal_maskah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.22 KVM_GET_FPUh]h4.22 KVM_GET_FPU}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj}!hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj!hhhKubj)}(hbasich]h)}(hj!h]hbasic}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj!hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj!hhhKubj)}(hx86, loongarchh]h)}(hj!h]hx86, loongarch}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj!hhubjx)}(hhh](j})}(hTypeh]hType}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj!hhhKubj)}(h vcpu ioctlh]h)}(hj"h]h vcpu ioctl}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj!hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj"hhhKubj)}(hstruct kvm_fpu (out)h]h)}(hj."h]hstruct kvm_fpu (out)}(hj0"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj,"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj!hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjL"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjI"hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj^"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjZ"ubah}(h]h ]h"]h$]h&]uh1jhjI"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj!hhubeh}(h]h ]h"]h$]h&]uh1jrhj}!hhhhhMubh)}(h-Reads the floating point state from the vcpu.h]h-Reads the floating point state from the vcpu.}(hj~"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}!hhubj8)}(hX/* x86: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u8 fpr[8][16]; __u16 fcw; __u16 fsw; __u8 ftwx; /* in fxsave format */ __u8 pad1; __u16 last_opcode; __u64 last_ip; __u64 last_dp; __u8 xmm[16][16]; __u32 mxcsr; __u32 pad2; }; /* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u32 fcsr; __u64 fcc; struct kvm_fpureg { __u64 val64[4]; }fpr[32]; };h]hX/* x86: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u8 fpr[8][16]; __u16 fcw; __u16 fsw; __u8 ftwx; /* in fxsave format */ __u8 pad1; __u16 last_opcode; __u64 last_ip; __u64 last_dp; __u8 xmm[16][16]; __u32 mxcsr; __u32 pad2; }; /* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u32 fcsr; __u64 fcc; struct kvm_fpureg { __u64 val64[4]; }fpr[32]; };}hj"sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj}!hhubeh}(h] kvm-get-fpuah ]h"]4.22 kvm_get_fpuah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.23 KVM_SET_FPUh]h4.23 KVM_SET_FPU}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM*ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj"hhhKubj)}(hbasich]h)}(hj"h]hbasic}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM,hj"hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj"hhhKubj)}(hx86, loongarchh]h)}(hj"h]hx86, loongarch}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj"ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM-hj"hhubjx)}(hhh](j})}(hTypeh]hType}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(h vcpu ioctlh]h)}(hj%#h]h vcpu ioctl}(hj'#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hj##ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhM.hj"hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjC#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@#hhhKubj)}(hstruct kvm_fpu (in)h]h)}(hjS#h]hstruct kvm_fpu (in)}(hjU#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjQ#ubah}(h]h ]h"]h$]h&]uh1jhj@#ubeh}(h]h ]h"]h$]h&]uh1jwhhhM/hj"hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjq#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjn#hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj#ubah}(h]h ]h"]h$]h&]uh1jhjn#ubeh}(h]h ]h"]h$]h&]uh1jwhhhM0hj"hhubeh}(h]h ]h"]h$]h&]uh1jrhj"hhhhhM,ubh)}(h,Writes the floating point state to the vcpu.h]h,Writes the floating point state to the vcpu.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj"hhubj8)}(hX/* x86: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u8 fpr[8][16]; __u16 fcw; __u16 fsw; __u8 ftwx; /* in fxsave format */ __u8 pad1; __u16 last_opcode; __u64 last_ip; __u64 last_dp; __u8 xmm[16][16]; __u32 mxcsr; __u32 pad2; }; /* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u32 fcsr; __u64 fcc; struct kvm_fpureg { __u64 val64[4]; }fpr[32]; };h]hX/* x86: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u8 fpr[8][16]; __u16 fcw; __u16 fsw; __u8 ftwx; /* in fxsave format */ __u8 pad1; __u16 last_opcode; __u64 last_ip; __u64 last_dp; __u8 xmm[16][16]; __u32 mxcsr; __u32 pad2; }; /* LoongArch: for KVM_GET_FPU and KVM_SET_FPU */ struct kvm_fpu { __u32 fcsr; __u64 fcc; struct kvm_fpureg { __u64 val64[4]; }fpr[32]; };}hj#sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM6hj"hhubeh}(h] kvm-set-fpuah ]h"]4.23 kvm_set_fpuah$]h&]uh1hhjhhhhhM*ubh)}(hhh](h)}(h4.24 KVM_CREATE_IRQCHIPh]h4.24 KVM_CREATE_IRQCHIP}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMPubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(h,KVM_CAP_IRQCHIP, KVM_CAP_S390_IRQCHIP (s390)h]h)}(hj#h]h,KVM_CAP_IRQCHIP, KVM_CAP_S390_IRQCHIP (s390)}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhMRhj#hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj $hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj $hhhKubj)}(hx86, arm64, s390h]h)}(hj$h]hx86, arm64, s390}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj$ubah}(h]h ]h"]h$]h&]uh1jhj $ubeh}(h]h ]h"]h$]h&]uh1jwhhhMShj#hhubjx)}(hhh](j})}(hTypeh]hType}(hj:$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7$hhhKubj)}(hvm ioctlh]h)}(hjJ$h]hvm ioctl}(hjL$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjH$ubah}(h]h ]h"]h$]h&]uh1jhj7$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMThj#hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjh$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hje$hhhKubj)}(hnoneh]h)}(hjx$h]hnone}(hjz$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjv$ubah}(h]h ]h"]h$]h&]uh1jhje$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMUhj#hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMVhj#hhubeh}(h]h ]h"]h$]h&]uh1jrhj#hhhhhMRubh)}(hX7Creates an interrupt controller model in the kernel. On x86, creates a virtual ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a local APIC. IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23 only go to the IOAPIC. This ioctl can only be called before creating any vcpus. On arm64, a GICv2 is created. Any other GIC versions require the usage of KVM_CREATE_DEVICE, which also supports creating a GICv2. Using KVM_CREATE_DEVICE is preferred over KVM_CREATE_IRQCHIP for GICv2. On s390, a dummy irq routing table is created.h]hX7Creates an interrupt controller model in the kernel. On x86, creates a virtual ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a local APIC. IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23 only go to the IOAPIC. This ioctl can only be called before creating any vcpus. On arm64, a GICv2 is created. Any other GIC versions require the usage of KVM_CREATE_DEVICE, which also supports creating a GICv2. Using KVM_CREATE_DEVICE is preferred over KVM_CREATE_IRQCHIP for GICv2. On s390, a dummy irq routing table is created.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhj#hhubh)}(hXOn x86, subsequent vcpu creation may install a private 4 KiB memory slot at the default APIC base address (0xfee00000). User memory regions must not overlap this address; doing so will cause vcpu creation to fail with ``EEXIST``, or the memory region to be rejected if created after the vcpu. This occurs when APIC access acceleration is enabled (APICv on Intel, AVIC on AMD), which is the default on supported hardware. The same constraint applies when using ``KVM_CAP_SPLIT_IRQCHIP``.h](hOn x86, subsequent vcpu creation may install a private 4 KiB memory slot at the default APIC base address (0xfee00000). User memory regions must not overlap this address; doing so will cause vcpu creation to fail with }(hj$hhhNhNubj)}(h ``EEXIST``h]hEEXIST}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh, or the memory region to be rejected if created after the vcpu. This occurs when APIC access acceleration is enabled (APICv on Intel, AVIC on AMD), which is the default on supported hardware. The same constraint applies when using }(hj$hhhNhNubj)}(h``KVM_CAP_SPLIT_IRQCHIP``h]hKVM_CAP_SPLIT_IRQCHIP}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh.}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMbhj#hhubh)}(hsNote that on s390 the KVM_CAP_S390_IRQCHIP vm capability needs to be enabled before KVM_CREATE_IRQCHIP can be used.h]hsNote that on s390 the KVM_CAP_S390_IRQCHIP vm capability needs to be enabled before KVM_CREATE_IRQCHIP can be used.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj#hhubeh}(h]kvm-create-irqchipah ]h"]4.24 kvm_create_irqchipah$]h&]uh1hhjhhhhhMPubh)}(hhh](h)}(h4.25 KVM_IRQ_LINEh]h4.25 KVM_IRQ_LINE}(hj!%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhMoubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj5%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj2%hhhKubj)}(hKVM_CAP_IRQCHIPh]h)}(hjE%h]hKVM_CAP_IRQCHIP}(hjG%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjC%ubah}(h]h ]h"]h$]h&]uh1jhj2%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMqhj/%hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjc%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj`%hhhKubj)}(h x86, arm64h]h)}(hjs%h]h x86, arm64}(hju%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjq%ubah}(h]h ]h"]h$]h&]uh1jhj`%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMrhj/%hhubjx)}(hhh](j})}(hTypeh]hType}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(hvm ioctlh]h)}(hj%h]hvm ioctl}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMshj/%hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(hstruct kvm_irq_levelh]h)}(hj%h]hstruct kvm_irq_level}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMthj/%hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMuhj/%hhubeh}(h]h ]h"]h$]h&]uh1jrhj%hhhhhMqubh)}(hX%Sets the level of a GSI input to the interrupt controller model in the kernel. On some architectures it is required that an interrupt controller model has been previously created with KVM_CREATE_IRQCHIP. Note that edge-triggered interrupts require the level to be set to 1 and then back to 0.h]hX%Sets the level of a GSI input to the interrupt controller model in the kernel. On some architectures it is required that an interrupt controller model has been previously created with KVM_CREATE_IRQCHIP. Note that edge-triggered interrupts require the level to be set to 1 and then back to 0.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhj%hhubh)}(hOn real hardware, interrupt pins can be active-low or active-high. This does not matter for the level field of struct kvm_irq_level: 1 always means active (asserted), 0 means inactive (deasserted).h]hOn real hardware, interrupt pins can be active-low or active-high. This does not matter for the level field of struct kvm_irq_level: 1 always means active (asserted), 0 means inactive (deasserted).}(hj-&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hj%hhubh)}(hXx86 allows the operating system to program the interrupt polarity (active-low/active-high) for level-triggered interrupts, and KVM used to consider the polarity. However, due to bitrot in the handling of active-low interrupts, the above convention is now valid on x86 too. This is signaled by KVM_CAP_X86_IOAPIC_POLARITY_IGNORED. Userspace should not present interrupts to the guest as active-low unless this capability is present (or unless it is not using the in-kernel irqchip, of course).Ch]hXx86 allows the operating system to program the interrupt polarity (active-low/active-high) for level-triggered interrupts, and KVM used to consider the polarity. However, due to bitrot in the handling of active-low interrupts, the above convention is now valid on x86 too. This is signaled by KVM_CAP_X86_IOAPIC_POLARITY_IGNORED. Userspace should not present interrupts to the guest as active-low unless this capability is present (or unless it is not using the in-kernel irqchip, of course).}(hj;&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(harm64 can signal an interrupt either at the CPU level, or at the in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for specific cpus. The irq field is interpreted like this::h]harm64 can signal an interrupt either at the CPU level, or at the in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for specific cpus. The irq field is interpreted like this:}(hjI&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubj8)}(hubits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 | field: | vcpu2_index | irq_type | vcpu_index | irq_id |h]hubits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 | field: | vcpu2_index | irq_type | vcpu_index | irq_id |}hjW&sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj%hhubh)}(h,The irq_type field has the following values:h]h,The irq_type field has the following values:}(hje&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubj)}(hhh](j)}(hVKVM_ARM_IRQ_TYPE_CPU: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQh]j )}(hhh]j)}(hIKVM_ARM_IRQ_TYPE_CPU: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQh](j)}(hKVM_ARM_IRQ_TYPE_CPU:h]hKVM_ARM_IRQ_TYPE_CPU:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj}&ubj%)}(hhh]h)}(h3out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQh]h3out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j$hj}&ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjz&ubah}(h]h ]h"]h$]h&]uh1j hjv&ubah}(h]h ]h"]h$]h&]uh1jhjs&hhhNhNubj)}(hKVM_ARM_IRQ_TYPE_SPI: in-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.) (the vcpu_index field is ignored) in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)h]j )}(hhh]j)}(hKVM_ARM_IRQ_TYPE_SPI: in-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.) (the vcpu_index field is ignored) in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)h](j)}(hKVM_ARM_IRQ_TYPE_SPI:h]hKVM_ARM_IRQ_TYPE_SPI:}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj&ubj%)}(hhh]h)}(hin-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.) (the vcpu_index field is ignored) in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)h]hin-kernel GICv2/GICv3: SPI, irq_id between 32 and 1019 (incl.) (the vcpu_index field is ignored) in-kernel GICv5: SPI, irq_id between 0 and 65535 (incl.)}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j$hj&ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j hj&ubah}(h]h ]h"]h$]h&]uh1jhjs&hhhNhNubj)}(hKVM_ARM_IRQ_TYPE_PPI: in-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.) in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.) h]j )}(hhh]j)}(hKVM_ARM_IRQ_TYPE_PPI: in-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.) in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.) h](j)}(hKVM_ARM_IRQ_TYPE_PPI:h]hKVM_ARM_IRQ_TYPE_PPI:}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj'ubj%)}(hhh]h)}(hsin-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.) in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.)h]hsin-kernel GICv2/GICv3: PPI, irq_id between 16 and 31 (incl.) in-kernel GICv5: PPI, irq_id between 0 and 127 (incl.)}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1j$hj'ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j hj&ubah}(h]h ]h"]h$]h&]uh1jhjs&hhhNhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj%hhubh)}(hM(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)h]hM(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)}(hjB'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(h9In both cases, level is used to assert/deassert the line.h]h9In both cases, level is used to assert/deassert the line.}(hjP'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hWhen KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 is supported, the target vcpu is identified as (256 * vcpu2_index + vcpu_index). Otherwise, vcpu2_index must be zero.h]hWhen KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 is supported, the target vcpu is identified as (256 * vcpu2_index + vcpu_index). Otherwise, vcpu2_index must be zero.}(hj^'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hNote that on arm64, the KVM_CAP_IRQCHIP capability only conditions injection of interrupts for the in-kernel irqchip. KVM_IRQ_LINE can always be used for a userspace interrupt controller.h]hNote that on arm64, the KVM_CAP_IRQCHIP capability only conditions injection of interrupts for the in-kernel irqchip. KVM_IRQ_LINE can always be used for a userspace interrupt controller.}(hjl'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubj8)}(hstruct kvm_irq_level { union { __u32 irq; /* GSI */ __s32 status; /* not used for KVM_IRQ_LEVEL */ }; __u32 level; /* 0 or 1 */ };h]hstruct kvm_irq_level { union { __u32 irq; /* GSI */ __s32 status; /* not used for KVM_IRQ_LEVEL */ }; __u32 level; /* 0 or 1 */ };}hjz'sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj%hhubeh}(h] kvm-irq-lineah ]h"]4.25 kvm_irq_lineah$]h&]uh1hhjhhhhhMoubh)}(hhh](h)}(h4.26 KVM_GET_IRQCHIPh]h4.26 KVM_GET_IRQCHIP}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj'hhhKubj)}(hKVM_CAP_IRQCHIPh]h)}(hj'h]hKVM_CAP_IRQCHIP}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj'hhhKubj)}(hx86h]h)}(hj'h]hx86}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubjx)}(hhh](j})}(hTypeh]hType}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj(hhhKubj)}(hvm ioctlh]h)}(hj(h]hvm ioctl}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj1(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.(hhhKubj)}(hstruct kvm_irqchip (in/out)h]h)}(hjA(h]hstruct kvm_irqchip (in/out)}(hjC(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?(ubah}(h]h ]h"]h$]h&]uh1jhj.(ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj_(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj\(hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjq(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjm(ubah}(h]h ]h"]h$]h&]uh1jhj\(ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubeh}(h]h ]h"]h$]h&]uh1jrhj'hhhhhMubh)}(hvReads the state of a kernel interrupt controller created with KVM_CREATE_IRQCHIP into a buffer provided by the caller.h]hvReads the state of a kernel interrupt controller created with KVM_CREATE_IRQCHIP into a buffer provided by the caller.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'hhubj8)}(hX struct kvm_irqchip { __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */ __u32 pad; union { char dummy[512]; /* reserving space */ struct kvm_pic_state pic; struct kvm_ioapic_state ioapic; } chip; };h]hX struct kvm_irqchip { __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */ __u32 pad; union { char dummy[512]; /* reserving space */ struct kvm_pic_state pic; struct kvm_ioapic_state ioapic; } chip; };}hj(sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj'hhubeh}(h]kvm-get-irqchipah ]h"]4.26 kvm_get_irqchipah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.27 KVM_SET_IRQCHIPh]h4.27 KVM_SET_IRQCHIP}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj(hhhKubj)}(hKVM_CAP_IRQCHIPh]h)}(hj(h]hKVM_CAP_IRQCHIP}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj(hhhKubj)}(hx86h]h)}(hj )h]hx86}(hj )hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj(ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(hTypeh]hType}(hj()hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%)hhhKubj)}(hvm ioctlh]h)}(hj8)h]hvm ioctl}(hj:)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6)ubah}(h]h ]h"]h$]h&]uh1jhj%)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjV)hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjS)hhhKubj)}(hstruct kvm_irqchip (in)h]h)}(hjf)h]hstruct kvm_irqchip (in)}(hjh)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjd)ubah}(h]h ]h"]h$]h&]uh1jhjS)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj(hhubeh}(h]h ]h"]h$]h&]uh1jrhj(hhhhhMubh)}(huSets the state of a kernel interrupt controller created with KVM_CREATE_IRQCHIP from a buffer provided by the caller.h]huSets the state of a kernel interrupt controller created with KVM_CREATE_IRQCHIP from a buffer provided by the caller.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(hhubj8)}(hX struct kvm_irqchip { __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */ __u32 pad; union { char dummy[512]; /* reserving space */ struct kvm_pic_state pic; struct kvm_ioapic_state ioapic; } chip; };h]hX struct kvm_irqchip { __u32 chip_id; /* 0 = PIC1, 1 = PIC2, 2 = IOAPIC */ __u32 pad; union { char dummy[512]; /* reserving space */ struct kvm_pic_state pic; struct kvm_ioapic_state ioapic; } chip; };}hj)sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj(hhubeh}(h]kvm-set-irqchipah ]h"]4.27 kvm_set_irqchipah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.28 KVM_XEN_HVM_CONFIGh]h4.28 KVM_XEN_HVM_CONFIG}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(hKVM_CAP_XEN_HVMh]h)}(hj*h]hKVM_CAP_XEN_HVM}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj*hhhKubj)}(hx86h]h)}(hj/*h]hx86}(hj1*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)hhubjx)}(hhh](j})}(hTypeh]hType}(hjM*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJ*hhhKubj)}(hvm ioctlh]h)}(hj]*h]hvm ioctl}(hj_*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[*ubah}(h]h ]h"]h$]h&]uh1jhjJ*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj{*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjx*hhhKubj)}(hstruct kvm_xen_hvm_config (in)h]h)}(hj*h]hstruct kvm_xen_hvm_config (in)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhjx*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj*hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)hhubeh}(h]h ]h"]h$]h&]uh1jrhj)hhhhhMubh)}(hXSets the MSR that the Xen HVM guest uses to initialize its hypercall page, and provides the starting address and size of the hypercall blobs in userspace. When the guest writes the MSR, kvm copies one page of a blob (32- or 64-bit, depending on the vcpu mode) to guest memory.h]hXSets the MSR that the Xen HVM guest uses to initialize its hypercall page, and provides the starting address and size of the hypercall blobs in userspace. When the guest writes the MSR, kvm copies one page of a blob (32- or 64-bit, depending on the vcpu mode) to guest memory.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubh)}(hThe MSR index must be in the range [0x40000000, 0x4fffffff], i.e. must reside in the range that is unofficially reserved for use by hypervisors. The min/max values are enumerated via KVM_XEN_MSR_MIN_INDEX and KVM_XEN_MSR_MAX_INDEX.h]hThe MSR index must be in the range [0x40000000, 0x4fffffff], i.e. must reside in the range that is unofficially reserved for use by hypervisors. The min/max values are enumerated via KVM_XEN_MSR_MIN_INDEX and KVM_XEN_MSR_MAX_INDEX.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubj8)}(hstruct kvm_xen_hvm_config { __u32 flags; __u32 msr; __u64 blob_addr_32; __u64 blob_addr_64; __u8 blob_size_32; __u8 blob_size_64; __u8 pad2[30]; };h]hstruct kvm_xen_hvm_config { __u32 flags; __u32 msr; __u64 blob_addr_32; __u64 blob_addr_64; __u8 blob_size_32; __u8 blob_size_64; __u8 pad2[30]; };}hj*sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj)hhubh)}(hoIf certain flags are returned from the KVM_CAP_XEN_HVM check, they may be set in the flags field of this ioctl:h]hoIf certain flags are returned from the KVM_CAP_XEN_HVM check, they may be set in the flags field of this ioctl:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubh)}(hXThe KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL flag requests KVM to generate the contents of the hypercall page automatically; hypercalls will be intercepted and passed to userspace through KVM_EXIT_XEN. In this case, all of the blob size and address fields must be zero.h]hXThe KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL flag requests KVM to generate the contents of the hypercall page automatically; hypercalls will be intercepted and passed to userspace through KVM_EXIT_XEN. In this case, all of the blob size and address fields must be zero.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj)hhubh)}(hX The KVM_XEN_HVM_CONFIG_EVTCHN_SEND flag indicates to KVM that userspace will always use the KVM_XEN_HVM_EVTCHN_SEND ioctl to deliver event channel interrupts rather than manipulating the guest's shared_info structures directly. This, in turn, may allow KVM to enable features such as intercepting the SCHEDOP_poll hypercall to accelerate PV spinlock operation for the guest. Userspace may still use the ioctl to deliver events if it was advertised, even if userspace does not send this indication that it will always do soh]hX The KVM_XEN_HVM_CONFIG_EVTCHN_SEND flag indicates to KVM that userspace will always use the KVM_XEN_HVM_EVTCHN_SEND ioctl to deliver event channel interrupts rather than manipulating the guest’s shared_info structures directly. This, in turn, may allow KVM to enable features such as intercepting the SCHEDOP_poll hypercall to accelerate PV spinlock operation for the guest. Userspace may still use the ioctl to deliver events if it was advertised, even if userspace does not send this indication that it will always do so}(hj!+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubh)}(hDNo other flags are currently valid in the struct kvm_xen_hvm_config.h]hDNo other flags are currently valid in the struct kvm_xen_hvm_config.}(hj/+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)hhubeh}(h]kvm-xen-hvm-configah ]h"]4.28 kvm_xen_hvm_configah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.29 KVM_GET_CLOCKh]h4.29 KVM_GET_CLOCK}(hjH+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE+hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj\+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjY+hhhKubj)}(hKVM_CAP_ADJUST_CLOCKh]h)}(hjl+h]hKVM_CAP_ADJUST_CLOCK}(hjn+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjj+ubah}(h]h ]h"]h$]h&]uh1jhjY+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjV+hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(hx86h]h)}(hj+h]hx86}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjV+hhubjx)}(hhh](j})}(hTypeh]hType}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(hvm ioctlh]h)}(hj+h]hvm ioctl}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjV+hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(hstruct kvm_clock_data (out)h]h)}(hj+h]hstruct kvm_clock_data (out)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjV+hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj,hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj&,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj",ubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjV+hhubeh}(h]h ]h"]h$]h&]uh1jrhjE+hhhhhMubh)}(hGets the current timestamp of kvmclock as seen by the current guest. In conjunction with KVM_SET_CLOCK, it is used to ensure monotonicity on scenarios such as migration.h]hGets the current timestamp of kvmclock as seen by the current guest. In conjunction with KVM_SET_CLOCK, it is used to ensure monotonicity on scenarios such as migration.}(hjF,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjE+hhubh)}(hWhen KVM_CAP_ADJUST_CLOCK is passed to KVM_CHECK_EXTENSION, it returns the set of bits that KVM can return in struct kvm_clock_data's flag member.h]hWhen KVM_CAP_ADJUST_CLOCK is passed to KVM_CHECK_EXTENSION, it returns the set of bits that KVM can return in struct kvm_clock_data’s flag member.}(hjT,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjE+hhubh)}(h The following flags are defined:h]h The following flags are defined:}(hjb,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjE+hhubj )}(hhh](j)}(hXKVM_CLOCK_TSC_STABLE If set, the returned value is the exact kvmclock value seen by all VCPUs at the instant when KVM_GET_CLOCK was called. If clear, the returned value is simply CLOCK_MONOTONIC plus a constant offset; the offset can be modified with KVM_SET_CLOCK. KVM will try to make all VCPUs follow this clock, but the exact value read by each VCPU could differ, because the host TSC is not stable. h](j)}(hKVM_CLOCK_TSC_STABLEh]hKVM_CLOCK_TSC_STABLE}(hjw,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM1hjs,ubj%)}(hhh]h)}(hXIf set, the returned value is the exact kvmclock value seen by all VCPUs at the instant when KVM_GET_CLOCK was called. If clear, the returned value is simply CLOCK_MONOTONIC plus a constant offset; the offset can be modified with KVM_SET_CLOCK. KVM will try to make all VCPUs follow this clock, but the exact value read by each VCPU could differ, because the host TSC is not stable.h]hXIf set, the returned value is the exact kvmclock value seen by all VCPUs at the instant when KVM_GET_CLOCK was called. If clear, the returned value is simply CLOCK_MONOTONIC plus a constant offset; the offset can be modified with KVM_SET_CLOCK. KVM will try to make all VCPUs follow this clock, but the exact value read by each VCPU could differ, because the host TSC is not stable.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj,ubah}(h]h ]h"]h$]h&]uh1j$hjs,ubeh}(h]h ]h"]h$]h&]uh1jhhhM1hjp,ubj)}(hKVM_CLOCK_REALTIME If set, the `realtime` field in the kvm_clock_data structure is populated with the value of the host's real time clocksource at the instant when KVM_GET_CLOCK was called. If clear, the `realtime` field does not contain a value. h](j)}(hKVM_CLOCK_REALTIMEh]hKVM_CLOCK_REALTIME}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM7hj,ubj%)}(hhh]h)}(hIf set, the `realtime` field in the kvm_clock_data structure is populated with the value of the host's real time clocksource at the instant when KVM_GET_CLOCK was called. If clear, the `realtime` field does not contain a value.h](h If set, the }(hj,hhhNhNubhtitle_reference)}(h `realtime`h]hrealtime}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj,ubh field in the kvm_clock_data structure is populated with the value of the host’s real time clocksource at the instant when KVM_GET_CLOCK was called. If clear, the }(hj,hhhNhNubj,)}(h `realtime`h]hrealtime}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj,ubh field does not contain a value.}(hj,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM4hj,ubah}(h]h ]h"]h$]h&]uh1j$hj,ubeh}(h]h ]h"]h$]h&]uh1jhhhM7hjp,hhubj)}(hKVM_CLOCK_HOST_TSC If set, the `host_tsc` field in the kvm_clock_data structure is populated with the value of the host's timestamp counter (TSC) at the instant when KVM_GET_CLOCK was called. If clear, the `host_tsc` field does not contain a value. h](j)}(hKVM_CLOCK_HOST_TSCh]hKVM_CLOCK_HOST_TSC}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM=hj,ubj%)}(hhh]h)}(hIf set, the `host_tsc` field in the kvm_clock_data structure is populated with the value of the host's timestamp counter (TSC) at the instant when KVM_GET_CLOCK was called. If clear, the `host_tsc` field does not contain a value.h](h If set, the }(hj -hhhNhNubj,)}(h `host_tsc`h]hhost_tsc}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj -ubh field in the kvm_clock_data structure is populated with the value of the host’s timestamp counter (TSC) at the instant when KVM_GET_CLOCK was called. If clear, the }(hj -hhhNhNubj,)}(h `host_tsc`h]hhost_tsc}(hj&-hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj -ubh field does not contain a value.}(hj -hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM:hj -ubah}(h]h ]h"]h$]h&]uh1j$hj,ubeh}(h]h ]h"]h$]h&]uh1jhhhM=hjp,hhubeh}(h]h ]h"]h$]h&]uh1j hjE+hhhhhNubj8)}(hstruct kvm_clock_data { __u64 clock; /* kvmclock current value */ __u32 flags; __u32 pad0; __u64 realtime; __u64 host_tsc; __u32 pad[4]; };h]hstruct kvm_clock_data { __u64 clock; /* kvmclock current value */ __u32 flags; __u32 pad0; __u64 realtime; __u64 host_tsc; __u32 pad[4]; };}hjP-sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMAhjE+hhubeh}(h] kvm-get-clockah ]h"]4.29 kvm_get_clockah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.30 KVM_SET_CLOCKh]h4.30 KVM_SET_CLOCK}(hji-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf-hhhhhMLubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj}-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjz-hhhKubj)}(hKVM_CAP_ADJUST_CLOCKh]h)}(hj-h]hKVM_CAP_ADJUST_CLOCK}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj-ubah}(h]h ]h"]h$]h&]uh1jhjz-ubeh}(h]h ]h"]h$]h&]uh1jwhhhMNhjw-hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj-hhhKubj)}(hx86h]h)}(hj-h]hx86}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jwhhhMOhjw-hhubjx)}(hhh](j})}(hTypeh]hType}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj-hhhKubj)}(hvm ioctlh]h)}(hj-h]hvm ioctl}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhj-ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1jwhhhMPhjw-hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.hhhKubj)}(hstruct kvm_clock_data (in)h]h)}(hj.h]hstruct kvm_clock_data (in)}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMQhjw-hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj5.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj2.hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjG.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhjC.ubah}(h]h ]h"]h$]h&]uh1jhj2.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMRhjw-hhubeh}(h]h ]h"]h$]h&]uh1jrhjf-hhhhhMNubh)}(hSets the current timestamp of kvmclock to the value specified in its parameter. In conjunction with KVM_GET_CLOCK, it is used to ensure monotonicity on scenarios such as migration.h]hSets the current timestamp of kvmclock to the value specified in its parameter. In conjunction with KVM_GET_CLOCK, it is used to ensure monotonicity on scenarios such as migration.}(hjg.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjf-hhubh)}(h"The following flags can be passed:h]h"The following flags can be passed:}(hju.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjf-hhubj )}(hhh]j)}(hXKVM_CLOCK_REALTIME If set, KVM will compare the value of the `realtime` field with the value of the host's real time clocksource at the instant when KVM_SET_CLOCK was called. The difference in elapsed time is added to the final kvmclock value that will be provided to guests. h](j)}(hKVM_CLOCK_REALTIMEh]hKVM_CLOCK_REALTIME}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM^hj.ubj%)}(hhh]h)}(hXIf set, KVM will compare the value of the `realtime` field with the value of the host's real time clocksource at the instant when KVM_SET_CLOCK was called. The difference in elapsed time is added to the final kvmclock value that will be provided to guests.h](h*If set, KVM will compare the value of the }(hj.hhhNhNubj,)}(h `realtime`h]hrealtime}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj.ubh field with the value of the host’s real time clocksource at the instant when KVM_SET_CLOCK was called. The difference in elapsed time is added to the final kvmclock value that will be provided to guests.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM[hj.ubah}(h]h ]h"]h$]h&]uh1j$hj.ubeh}(h]h ]h"]h$]h&]uh1jhhhM^hj.ubah}(h]h ]h"]h$]h&]uh1j hjf-hhhhhNubh)}(hCOther flags returned by ``KVM_GET_CLOCK`` are accepted but ignored.h](hOther flags returned by }(hj.hhhNhNubj)}(h``KVM_GET_CLOCK``h]h KVM_GET_CLOCK}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh are accepted but ignored.}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM`hjf-hhubj8)}(hstruct kvm_clock_data { __u64 clock; /* kvmclock current value */ __u32 flags; __u32 pad0; __u64 realtime; __u64 host_tsc; __u32 pad[4]; };h]hstruct kvm_clock_data { __u64 clock; /* kvmclock current value */ __u32 flags; __u32 pad0; __u64 realtime; __u64 host_tsc; __u32 pad[4]; };}hj.sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMdhjf-hhubeh}(h] kvm-set-clockah ]h"]4.30 kvm_set_clockah$]h&]uh1hhjhhhhhMLubh)}(hhh](h)}(h4.31 KVM_GET_VCPU_EVENTSh]h4.31 KVM_GET_VCPU_EVENTS}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhMoubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(hKVM_CAP_VCPU_EVENTSh]h)}(hj*/h]hKVM_CAP_VCPU_EVENTS}(hj,/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj(/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMqhj/hhubjx)}(hhh](j})}(h Extended byh]h Extended by}(hjH/hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjE/hhhKubj)}(hKVM_CAP_INTR_SHADOWh]h)}(hjX/h]hKVM_CAP_INTR_SHADOW}(hjZ/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjV/ubah}(h]h ]h"]h$]h&]uh1jhjE/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMrhj/hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjv/hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjs/hhhKubj)}(h x86, arm64h]h)}(hj/h]h x86, arm64}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj/ubah}(h]h ]h"]h$]h&]uh1jhjs/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMshj/hhubjx)}(hhh](j})}(hTypeh]hType}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(h vcpu ioctlh]h)}(hj/h]h vcpu ioctl}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMthj/hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(hstruct kvm_vcpu_events (out)h]h)}(hj/h]hstruct kvm_vcpu_events (out)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMuhj/hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhj0ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMvhj/hhubeh}(h]h ]h"]h$]h&]uh1jrhj/hhhhhMqubh)}(hhh](h)}(hX86:h]hX86:}(hj50hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj20hhhhhMyubh)}(h^Gets currently pending exceptions, interrupts, and NMIs as well as related states of the vcpu.h]h^Gets currently pending exceptions, interrupts, and NMIs as well as related states of the vcpu.}(hjC0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj20hhubj8)}(hXstruct kvm_vcpu_events { struct { __u8 injected; __u8 nr; __u8 has_error_code; __u8 pending; __u32 error_code; } exception; struct { __u8 injected; __u8 nr; __u8 soft; __u8 shadow; } interrupt; struct { __u8 injected; __u8 pending; __u8 masked; __u8 pad; } nmi; __u32 sipi_vector; __u32 flags; struct { __u8 smm; __u8 pending; __u8 smm_inside_nmi; __u8 latched_init; } smi; __u8 reserved[27]; __u8 exception_has_payload; __u64 exception_payload; };h]hXstruct kvm_vcpu_events { struct { __u8 injected; __u8 nr; __u8 has_error_code; __u8 pending; __u32 error_code; } exception; struct { __u8 injected; __u8 nr; __u8 soft; __u8 shadow; } interrupt; struct { __u8 injected; __u8 pending; __u8 masked; __u8 pad; } nmi; __u32 sipi_vector; __u32 flags; struct { __u8 smm; __u8 pending; __u8 smm_inside_nmi; __u8 latched_init; } smi; __u8 reserved[27]; __u8 exception_has_payload; __u64 exception_payload; };}hjQ0sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj20hhubh)}(h2The following bits are defined in the flags field:h]h2The following bits are defined in the flags field:}(hj_0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj20hhubj)}(hhh](j)}(h^KVM_VCPUEVENT_VALID_SHADOW may be set to signal that interrupt.shadow contains a valid state. h]h)}(h]KVM_VCPUEVENT_VALID_SHADOW may be set to signal that interrupt.shadow contains a valid state.h]h]KVM_VCPUEVENT_VALID_SHADOW may be set to signal that interrupt.shadow contains a valid state.}(hjt0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjp0ubah}(h]h ]h"]h$]h&]uh1jhjm0hhhhhNubj)}(hNKVM_VCPUEVENT_VALID_SMM may be set to signal that smi contains a valid state. h]h)}(hMKVM_VCPUEVENT_VALID_SMM may be set to signal that smi contains a valid state.h]hMKVM_VCPUEVENT_VALID_SMM may be set to signal that smi contains a valid state.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1jhjm0hhhhhNubj)}(hKVM_VCPUEVENT_VALID_PAYLOAD may be set to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state. This bit will be set whenever KVM_CAP_EXCEPTION_PAYLOAD is enabled. h]h)}(hKVM_VCPUEVENT_VALID_PAYLOAD may be set to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state. This bit will be set whenever KVM_CAP_EXCEPTION_PAYLOAD is enabled.h]hKVM_VCPUEVENT_VALID_PAYLOAD may be set to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state. This bit will be set whenever KVM_CAP_EXCEPTION_PAYLOAD is enabled.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1jhjm0hhhhhNubj)}(hKVM_VCPUEVENT_VALID_TRIPLE_FAULT may be set to signal that the triple_fault_pending field contains a valid state. This bit will be set whenever KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled. h]h)}(hKVM_VCPUEVENT_VALID_TRIPLE_FAULT may be set to signal that the triple_fault_pending field contains a valid state. This bit will be set whenever KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled.h]hKVM_VCPUEVENT_VALID_TRIPLE_FAULT may be set to signal that the triple_fault_pending field contains a valid state. This bit will be set whenever KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1jhjm0hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj20hhubeh}(h]id5ah ]h"]h$]x86:ah&]uh1hhj/hhhhhMyjKubh)}(hhh](h)}(hARM64:h]hARM64:}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhhhMubh)}(hX'If the guest accesses a device that is being emulated by the host kernel in such a way that a real device would generate a physical SError, KVM may make a virtual SError pending for that VCPU. This system error interrupt remains pending until the guest takes the exception by unmasking PSTATE.A.h]hX'If the guest accesses a device that is being emulated by the host kernel in such a way that a real device would generate a physical SError, KVM may make a virtual SError pending for that VCPU. This system error interrupt remains pending until the guest takes the exception by unmasking PSTATE.A.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hRunning the VCPU may cause it to take a pending SError, or make an access that causes an SError to become pending. The event's description is only valid while the VPCU is not running.h]hRunning the VCPU may cause it to take a pending SError, or make an access that causes an SError to become pending. The event’s description is only valid while the VPCU is not running.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hXNThis API provides a way to read and write the pending 'event' state that is not visible to the guest. To save, restore or migrate a VCPU the struct representing the state can be read then written using this GET/SET API, along with the other guest-visible registers. It is not possible to 'cancel' an SError that has been made pending.h]hXVThis API provides a way to read and write the pending ‘event’ state that is not visible to the guest. To save, restore or migrate a VCPU the struct representing the state can be read then written using this GET/SET API, along with the other guest-visible registers. It is not possible to ‘cancel’ an SError that has been made pending.}(hj 1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hXA device being emulated in user-space may also wish to generate an SError. To do this the events structure can be populated by user-space. The current state should be read first, to ensure no existing SError is pending. If an existing SError is pending, the architecture's 'Multiple SError interrupts' rules should be followed. (2.5.3 of DDI0587.a "ARM Reliability, Availability, and Serviceability (RAS) Specification").h]hXA device being emulated in user-space may also wish to generate an SError. To do this the events structure can be populated by user-space. The current state should be read first, to ensure no existing SError is pending. If an existing SError is pending, the architecture’s ‘Multiple SError interrupts’ rules should be followed. (2.5.3 of DDI0587.a “ARM Reliability, Availability, and Serviceability (RAS) Specification”).}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hXSError exceptions always have an ESR value. Some CPUs have the ability to specify what the virtual SError's ESR value should be. These systems will advertise KVM_CAP_ARM_INJECT_SERROR_ESR. In this case exception.has_esr will always have a non-zero value when read, and the agent making an SError pending should specify the ISS field in the lower 24 bits of exception.serror_esr. If the system supports KVM_CAP_ARM_INJECT_SERROR_ESR, but user-space sets the events with exception.has_esr as zero, KVM will choose an ESR.h]hX SError exceptions always have an ESR value. Some CPUs have the ability to specify what the virtual SError’s ESR value should be. These systems will advertise KVM_CAP_ARM_INJECT_SERROR_ESR. In this case exception.has_esr will always have a non-zero value when read, and the agent making an SError pending should specify the ISS field in the lower 24 bits of exception.serror_esr. If the system supports KVM_CAP_ARM_INJECT_SERROR_ESR, but user-space sets the events with exception.has_esr as zero, KVM will choose an ESR.}(hj'1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hSpecifying exception.has_esr on a system that does not support it will return -EINVAL. Setting anything other than the lower 24bits of exception.serror_esr will return -EINVAL.h]hSpecifying exception.has_esr on a system that does not support it will return -EINVAL. Setting anything other than the lower 24bits of exception.serror_esr will return -EINVAL.}(hj51hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hIt is not possible to read back a pending external abort (injected via KVM_SET_VCPU_EVENTS or otherwise) because such an exception is always delivered directly to the virtual CPU).h]hIt is not possible to read back a pending external abort (injected via KVM_SET_VCPU_EVENTS or otherwise) because such an exception is always delivered directly to the virtual CPU).}(hjC1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubh)}(hOCalling this ioctl on a vCPU that hasn't been initialized will return -ENOEXEC.h]hQCalling this ioctl on a vCPU that hasn’t been initialized will return -ENOEXEC.}(hjQ1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0hhubj8)}(hX%struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; __u8 ext_dabt_pending; /* Align it to 8 bytes */ __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; };h]hX%struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; __u8 ext_dabt_pending; /* Align it to 8 bytes */ __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; };}hj_1sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj0hhubeh}(h]id6ah ]h"]h$]j9ah&]uh1hhj/hhhhhMjKubeh}(h]kvm-get-vcpu-eventsah ]h"]4.31 kvm_get_vcpu_eventsah$]h&]uh1hhjhhhhhMoubh)}(hhh](h)}(h4.32 KVM_SET_VCPU_EVENTSh]h4.32 KVM_SET_VCPU_EVENTS}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|1hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj1hhhKubj)}(hKVM_CAP_VCPU_EVENTSh]h)}(hj1h]hKVM_CAP_VCPU_EVENTS}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubjx)}(hhh](j})}(h Extended byh]h Extended by}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj1hhhKubj)}(hKVM_CAP_INTR_SHADOWh]h)}(hj1h]hKVM_CAP_INTR_SHADOW}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj1hhhKubj)}(h x86, arm64h]h)}(hj1h]h x86, arm64}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubjx)}(hhh](j})}(hTypeh]hType}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj2hhhKubj)}(h vcpu ioctlh]h)}(hj-2h]h vcpu ioctl}(hj/2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+2ubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjK2hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjH2hhhKubj)}(hstruct kvm_vcpu_events (in)h]h)}(hj[2h]hstruct kvm_vcpu_events (in)}(hj]2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjY2ubah}(h]h ]h"]h$]h&]uh1jhjH2ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjy2hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjv2hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2ubah}(h]h ]h"]h$]h&]uh1jhjv2ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj1hhubeh}(h]h ]h"]h$]h&]uh1jrhj|1hhhhhMubh)}(hhh](h)}(hX86:h]hX86:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhhhMubh)}(hSSet pending exceptions, interrupts, and NMIs as well as related states of the vcpu.h]hSSet pending exceptions, interrupts, and NMIs as well as related states of the vcpu.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubh)}(h/See KVM_GET_VCPU_EVENTS for the data structure.h]h/See KVM_GET_VCPU_EVENTS for the data structure.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubh)}(hXFields that may be modified asynchronously by running VCPUs can be excluded from the update. These fields are nmi.pending, sipi_vector, smi.smm, smi.pending. Keep the corresponding bits in the flags field cleared to suppress overwriting the current in-kernel state. The bits are:h]hXFields that may be modified asynchronously by running VCPUs can be excluded from the update. These fields are nmi.pending, sipi_vector, smi.smm, smi.pending. Keep the corresponding bits in the flags field cleared to suppress overwriting the current in-kernel state. The bits are:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj2ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jchj2ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hKVM_VCPUEVENT_VALID_NMI_PENDINGh]hKVM_VCPUEVENT_VALID_NMI_PENDING}(hj 3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubj)}(hhh]h)}(h"transfer nmi.pending to the kernelh]h"transfer nmi.pending to the kernel}(hj 3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1j~hj3ubj)}(hhh](j)}(hhh]h)}(hKVM_VCPUEVENT_VALID_SIPI_VECTORh]hKVM_VCPUEVENT_VALID_SIPI_VECTOR}(hj@3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=3ubah}(h]h ]h"]h$]h&]uh1jhj:3ubj)}(hhh]h)}(htransfer sipi_vectorh]htransfer sipi_vector}(hjW3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjT3ubah}(h]h ]h"]h$]h&]uh1jhj:3ubeh}(h]h ]h"]h$]h&]uh1j~hj3ubj)}(hhh](j)}(hhh]h)}(hKVM_VCPUEVENT_VALID_SMMh]hKVM_VCPUEVENT_VALID_SMM}(hjw3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjt3ubah}(h]h ]h"]h$]h&]uh1jhjq3ubj)}(hhh]h)}(htransfer the smi sub-struct.h]htransfer the smi sub-struct.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3ubah}(h]h ]h"]h$]h&]uh1jhjq3ubeh}(h]h ]h"]h$]h&]uh1j~hj3ubeh}(h]h ]h"]h$]h&]uh1jyhj2ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj2ubah}(h]h ]h"]h$]h&]uh1jYhj2hhhhhNubh)}(hIf KVM_CAP_INTR_SHADOW is available, KVM_VCPUEVENT_VALID_SHADOW can be set in the flags field to signal that interrupt.shadow contains a valid state and shall be written into the VCPU.h]hIf KVM_CAP_INTR_SHADOW is available, KVM_VCPUEVENT_VALID_SHADOW can be set in the flags field to signal that interrupt.shadow contains a valid state and shall be written into the VCPU.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2hhubh)}(hHKVM_VCPUEVENT_VALID_SMM can only be set if KVM_CAP_X86_SMM is available.h]hHKVM_VCPUEVENT_VALID_SMM can only be set if KVM_CAP_X86_SMM is available.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2hhubh)}(hIf KVM_CAP_EXCEPTION_PAYLOAD is enabled, KVM_VCPUEVENT_VALID_PAYLOAD can be set in the flags field to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state and shall be written into the VCPU.h]hIf KVM_CAP_EXCEPTION_PAYLOAD is enabled, KVM_VCPUEVENT_VALID_PAYLOAD can be set in the flags field to signal that the exception_has_payload, exception_payload, and exception.pending fields contain a valid state and shall be written into the VCPU.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubh)}(hIf KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled, KVM_VCPUEVENT_VALID_TRIPLE_FAULT can be set in flags field to signal that the triple_fault field contains a valid state and shall be written into the VCPU.h]hIf KVM_CAP_X86_TRIPLE_FAULT_EVENT is enabled, KVM_VCPUEVENT_VALID_TRIPLE_FAULT can be set in flags field to signal that the triple_fault field contains a valid state and shall be written into the VCPU.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj2hhubeh}(h]id7ah ]h"]h$]x86:ah&]uh1hhj|1hhhhhMjKubh)}(hhh](h)}(hARM64:h]hARM64:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj3hhhhhMubh)}(hCUser space may need to inject several types of events to the guest.h]hCUser space may need to inject several types of events to the guest.}(hj 4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hzSet the pending SError exception state for this VCPU. It is not possible to 'cancel' an Serror that has been made pending.h]h~Set the pending SError exception state for this VCPU. It is not possible to ‘cancel’ an Serror that has been made pending.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hXIIf the guest performed an access to I/O memory which could not be handled by userspace, for example because of missing instruction syndrome decode information or because there is no device mapped at the accessed IPA, then userspace can ask the kernel to inject an external abort using the address from the exiting fault on the VCPU. It is a programming error to set ext_dabt_pending after an exit which was not either KVM_EXIT_MMIO, KVM_EXIT_ARM_NISV, or KVM_EXIT_ARM_LDST64B. This feature is only available if the system supports KVM_CAP_ARM_INJECT_EXT_DABT. This is a helper which provides commonality in how userspace reports accesses for the above cases to guests, across different userspace implementations. Nevertheless, userspace can still emulate all Arm exceptions by manipulating individual registers using the KVM_SET_ONE_REG API.h]hXIIf the guest performed an access to I/O memory which could not be handled by userspace, for example because of missing instruction syndrome decode information or because there is no device mapped at the accessed IPA, then userspace can ask the kernel to inject an external abort using the address from the exiting fault on the VCPU. It is a programming error to set ext_dabt_pending after an exit which was not either KVM_EXIT_MMIO, KVM_EXIT_ARM_NISV, or KVM_EXIT_ARM_LDST64B. This feature is only available if the system supports KVM_CAP_ARM_INJECT_EXT_DABT. This is a helper which provides commonality in how userspace reports accesses for the above cases to guests, across different userspace implementations. Nevertheless, userspace can still emulate all Arm exceptions by manipulating individual registers using the KVM_SET_ONE_REG API.}(hj(4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj3hhubh)}(h/See KVM_GET_VCPU_EVENTS for the data structure.h]h/See KVM_GET_VCPU_EVENTS for the data structure.}(hj64hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj3hhubh)}(hOCalling this ioctl on a vCPU that hasn't been initialized will return -ENOEXEC.h]hQCalling this ioctl on a vCPU that hasn’t been initialized will return -ENOEXEC.}(hjD4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj3hhubeh}(h]id8ah ]h"]h$]arm64:ah&]uh1hhj|1hhhhhMjKubeh}(h]kvm-set-vcpu-eventsah ]h"]4.32 kvm_set_vcpu_eventsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.33 KVM_GET_DEBUGREGSh]h4.33 KVM_GET_DEBUGREGS}(hje4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb4hhhhhM3ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjy4hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjv4hhhKubj)}(hKVM_CAP_DEBUGREGSh]h)}(hj4h]hKVM_CAP_DEBUGREGS}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj4ubah}(h]h ]h"]h$]h&]uh1jhjv4ubeh}(h]h ]h"]h$]h&]uh1jwhhhM5hjs4hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hx86h]h)}(hj4h]hx86}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hjs4hhubjx)}(hhh](j})}(hTypeh]hType}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(h vcpu ioctlh]h)}(hj4h]h vcpu ioctl}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj4ubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhM7hjs4hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(hstruct kvm_debugregs (out)h]h)}(hj5h]hstruct kvm_debugregs (out)}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhM8hjs4hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj15hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.5hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjC5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj?5ubah}(h]h ]h"]h$]h&]uh1jhj.5ubeh}(h]h ]h"]h$]h&]uh1jwhhhM9hjs4hhubeh}(h]h ]h"]h$]h&]uh1jrhjb4hhhhhM5ubh)}(h$Reads debug registers from the vcpu.h]h$Reads debug registers from the vcpu.}(hjc5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjb4hhubj8)}(hzstruct kvm_debugregs { __u64 db[4]; __u64 dr6; __u64 dr7; __u64 flags; __u64 reserved[9]; };h]hzstruct kvm_debugregs { __u64 db[4]; __u64 dr6; __u64 dr7; __u64 flags; __u64 reserved[9]; };}hjq5sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM?hjb4hhubeh}(h]kvm-get-debugregsah ]h"]4.33 kvm_get_debugregsah$]h&]uh1hhjhhhhhM3ubh)}(hhh](h)}(h4.34 KVM_SET_DEBUGREGSh]h4.34 KVM_SET_DEBUGREGS}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMIubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(hKVM_CAP_DEBUGREGSh]h)}(hj5h]hKVM_CAP_DEBUGREGS}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhMKhj5hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(hx86h]h)}(hj5h]hx86}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhMLhj5hhubjx)}(hhh](j})}(hTypeh]hType}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(h vcpu ioctlh]h)}(hj 6h]h vcpu ioctl}(hj 6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhMMhj5hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj(6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%6hhhKubj)}(hstruct kvm_debugregs (in)h]h)}(hj86h]hstruct kvm_debugregs (in)}(hj:6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj66ubah}(h]h ]h"]h$]h&]uh1jhj%6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMNhj5hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjV6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjS6hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjh6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjd6ubah}(h]h ]h"]h$]h&]uh1jhjS6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMOhj5hhubeh}(h]h ]h"]h$]h&]uh1jrhj5hhhhhMKubh)}(h%Writes debug registers into the vcpu.h]h%Writes debug registers into the vcpu.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj5hhubh)}(hiSee KVM_GET_DEBUGREGS for the data structure. The flags field is unused yet and must be cleared on entry.h]hiSee KVM_GET_DEBUGREGS for the data structure. The flags field is unused yet and must be cleared on entry.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj5hhubeh}(h]kvm-set-debugregsah ]h"]4.34 kvm_set_debugregsah$]h&]uh1hhjhhhhhMIubh)}(hhh](h)}(h4.35 KVM_SET_USER_MEMORY_REGIONh]h4.35 KVM_SET_USER_MEMORY_REGION}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMXubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj6hhhKubj)}(hKVM_CAP_USER_MEMORYh]h)}(hj6h]hKVM_CAP_USER_MEMORY}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMZhj6hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj6hhhKubj)}(hallh]h)}(hj7h]hall}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj6ubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jwhhhM[hj6hhubjx)}(hhh](j})}(hTypeh]hType}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(hvm ioctlh]h)}(hj/7h]hvm ioctl}(hj17hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj-7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM\hj6hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjM7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJ7hhhKubj)}(h'struct kvm_userspace_memory_region (in)h]h)}(hj]7h]h'struct kvm_userspace_memory_region (in)}(hj_7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hj[7ubah}(h]h ]h"]h$]h&]uh1jhjJ7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM]hj6hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj{7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjx7hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj7ubah}(h]h ]h"]h$]h&]uh1jhjx7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM^hj6hhubeh}(h]h ]h"]h$]h&]uh1jrhj6hhhhhMZubj8)}(hX`struct kvm_userspace_memory_region { __u32 slot; __u32 flags; __u64 guest_phys_addr; __u64 memory_size; /* bytes */ __u64 userspace_addr; /* start of the userspace allocated memory */ }; /* for kvm_userspace_memory_region::flags */ #define KVM_MEM_LOG_DIRTY_PAGES (1UL << 0) #define KVM_MEM_READONLY (1UL << 1)h]hX`struct kvm_userspace_memory_region { __u32 slot; __u32 flags; __u64 guest_phys_addr; __u64 memory_size; /* bytes */ __u64 userspace_addr; /* start of the userspace allocated memory */ }; /* for kvm_userspace_memory_region::flags */ #define KVM_MEM_LOG_DIRTY_PAGES (1UL << 0) #define KVM_MEM_READONLY (1UL << 1)}hj7sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMbhj6hhubh)}(hXVThis ioctl allows the user to create, modify or delete a guest physical memory slot. Bits 0-15 of "slot" specify the slot id and this value should be less than the maximum number of user memory slots supported per VM. The maximum allowed slots can be queried using KVM_CAP_NR_MEMSLOTS. Slots may not overlap in guest physical address space.h]hXZThis ioctl allows the user to create, modify or delete a guest physical memory slot. Bits 0-15 of “slot” specify the slot id and this value should be less than the maximum number of user memory slots supported per VM. The maximum allowed slots can be queried using KVM_CAP_NR_MEMSLOTS. Slots may not overlap in guest physical address space.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhj6hhubh)}(hXgIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of "slot" specifies the address space which is being modified. They must be less than the value that KVM_CHECK_EXTENSION returns for the KVM_CAP_MULTI_ADDRESS_SPACE capability. Slots in separate address spaces are unrelated; the restriction on overlapping slots only applies within each address space.h]hXkIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of “slot” specifies the address space which is being modified. They must be less than the value that KVM_CHECK_EXTENSION returns for the KVM_CAP_MULTI_ADDRESS_SPACE capability. Slots in separate address spaces are unrelated; the restriction on overlapping slots only applies within each address space.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthj6hhubh)}(hDeleting a slot is done by passing zero for memory_size. When changing an existing slot, it may be moved in the guest physical memory space, or its flags may be modified, but it may not be resized.h]hDeleting a slot is done by passing zero for memory_size. When changing an existing slot, it may be moved in the guest physical memory space, or its flags may be modified, but it may not be resized.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj6hhubh)}(hXMemory for the region is taken starting at the address denoted by the field userspace_addr, which must point at user addressable memory for the entire memory slot size. Any object may back this memory, including anonymous memory, ordinary files, and hugetlbfs. Changes in the backing of the memory region are automatically reflected into the guest. For example, an mmap() that affects the region will be made visible immediately. Another example is madvise(MADV_DROP).h]hXMemory for the region is taken starting at the address denoted by the field userspace_addr, which must point at user addressable memory for the entire memory slot size. Any object may back this memory, including anonymous memory, ordinary files, and hugetlbfs. Changes in the backing of the memory region are automatically reflected into the guest. For example, an mmap() that affects the region will be made visible immediately. Another example is madvise(MADV_DROP).}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hdOn architectures that support a form of address tagging, userspace_addr must be an untagged address.h]hdOn architectures that support a form of address tagging, userspace_addr must be an untagged address.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hIt is recommended that the lower 21 bits of guest_phys_addr and userspace_addr be identical. This allows large pages in the guest to be backed by large pages in the host.h]hIt is recommended that the lower 21 bits of guest_phys_addr and userspace_addr be identical. This allows large pages in the guest to be backed by large pages in the host.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hXThe flags field supports two flags: KVM_MEM_LOG_DIRTY_PAGES and KVM_MEM_READONLY. The former can be set to instruct KVM to keep track of writes to memory within the slot. See KVM_GET_DIRTY_LOG ioctl to know how to use it. The latter can be set, if KVM_CAP_READONLY_MEM capability allows it, to make a new slot read-only. In this case, writes to this memory will be posted to userspace as KVM_EXIT_MMIO exits.h]hXThe flags field supports two flags: KVM_MEM_LOG_DIRTY_PAGES and KVM_MEM_READONLY. The former can be set to instruct KVM to keep track of writes to memory within the slot. See KVM_GET_DIRTY_LOG ioctl to know how to use it. The latter can be set, if KVM_CAP_READONLY_MEM capability allows it, to make a new slot read-only. In this case, writes to this memory will be posted to userspace as KVM_EXIT_MMIO exits.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hFor TDX guest, deleting/moving memory region loses guest memory contents. Read only region isn't supported. Only as-id 0 is supported.h]hFor TDX guest, deleting/moving memory region loses guest memory contents. Read only region isn’t supported. Only as-id 0 is supported.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hXNote: On arm64, a write generated by the page-table walker (to update the Access and Dirty flags, for example) never results in a KVM_EXIT_MMIO exit when the slot has the KVM_MEM_READONLY flag. This is because KVM cannot provide the data that would be written by the page-table walker, making it impossible to emulate the access. Instead, an abort (data abort if the cause of the page-table update was a load or a store, instruction abort if it was an instruction fetch) is injected in the guest.h]hXNote: On arm64, a write generated by the page-table walker (to update the Access and Dirty flags, for example) never results in a KVM_EXIT_MMIO exit when the slot has the KVM_MEM_READONLY flag. This is because KVM cannot provide the data that would be written by the page-table walker, making it impossible to emulate the access. Instead, an abort (data abort if the cause of the page-table update was a load or a store, instruction abort if it was an instruction fetch) is injected in the guest.}(hj+8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubh)}(hhh](h)}(hS390:h]hS390:}(hj<8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj98hhhhhMubh)}(hxReturns -EINVAL or -EEXIST if the VM has the KVM_VM_S390_UCONTROL flag set. Returns -EINVAL if called on a protected VM.h]hxReturns -EINVAL or -EEXIST if the VM has the KVM_VM_S390_UCONTROL flag set. Returns -EINVAL if called on a protected VM.}(hjJ8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj98hhubeh}(h]id9ah ]h"]h$]jah&]uh1hhj6hhhhhMjKubeh}(h]kvm-set-user-memory-regionah ]h"]4.35 kvm_set_user_memory_regionah$]h&]uh1hhjhhhhhMXubh)}(hhh](h)}(h4.36 KVM_SET_TSS_ADDRh]h4.36 KVM_SET_TSS_ADDR}(hjj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg8hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj~8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj{8hhhKubj)}(hKVM_CAP_SET_TSS_ADDRh]h)}(hj8h]hKVM_CAP_SET_TSS_ADDR}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj{8ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjx8hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(hx86h]h)}(hj8h]hx86}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjx8hhubjx)}(hhh](j})}(hTypeh]hType}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(hvm ioctlh]h)}(hj8h]hvm ioctl}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjx8hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj9hhhKubj)}(hunsigned long tss_address (in)h]h)}(hj9h]hunsigned long tss_address (in)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjx8hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj69hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj39hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjH9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjD9ubah}(h]h ]h"]h$]h&]uh1jhj39ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjx8hhubeh}(h]h ]h"]h$]h&]uh1jrhjg8hhhhhMubh)}(hX.This ioctl defines the physical address of a three-page region in the guest physical address space. The region must be within the first 4GB of the guest physical address space and must not conflict with any memory slot or any mmio address. The guest may malfunction if it accesses this memory region.h]hX.This ioctl defines the physical address of a three-page region in the guest physical address space. The region must be within the first 4GB of the guest physical address space and must not conflict with any memory slot or any mmio address. The guest may malfunction if it accesses this memory region.}(hjh9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjg8hhubh)}(hThis ioctl is required on Intel-based hosts. This is needed on Intel hardware because of a quirk in the virtualization implementation (see the internals documentation when it pops into existence).h]hThis ioctl is required on Intel-based hosts. This is needed on Intel hardware because of a quirk in the virtualization implementation (see the internals documentation when it pops into existence).}(hjv9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjg8hhubjT)}(h.. _KVM_ENABLE_CAP:h]h}(h]h ]h"]h$]h&]j_kvm-enable-capuh1jShMhjg8hhhhubeh}(h]kvm-set-tss-addrah ]h"]4.36 kvm_set_tss_addrah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.37 KVM_ENABLE_CAPh]h4.37 KVM_ENABLE_CAP}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj9hhhKubj)}(hKVM_CAP_ENABLE_CAPh]h)}(hj9h]hKVM_CAP_ENABLE_CAP}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj9hhhKubj)}(hmips, ppc, s390, x86, loongarchh]h)}(hj9h]hmips, ppc, s390, x86, loongarch}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(hTypeh]hType}(hj :hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj:hhhKubj)}(h vcpu ioctlh]h)}(hj:h]h vcpu ioctl}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj8:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5:hhhKubj)}(hstruct kvm_enable_cap (in)h]h)}(hjH:h]hstruct kvm_enable_cap (in)}(hjJ:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjF:ubah}(h]h ]h"]h$]h&]uh1jhj5:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjf:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjc:hhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjx:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjt:ubah}(h]h ]h"]h$]h&]uh1jhjc:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(h Capabilityh]h Capability}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj:hhhKubj)}(hKVM_CAP_ENABLE_CAP_VMh]h)}(hj:h]hKVM_CAP_ENABLE_CAP_VM}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj:hhhKubj)}(hallh]h)}(hj:h]hall}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(hTypeh]hType}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj:hhhKubj)}(hvm ioctlh]h)}(hj;h]hvm ioctl}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj;hhhKubj)}(hstruct kvm_enable_cap (in)h]h)}(hj/;h]hstruct kvm_enable_cap (in)}(hj1;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-;ubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjM;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJ;hhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj_;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[;ubah}(h]h ]h"]h$]h&]uh1jhjJ;ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj9hhubeh}(h]h ]h"]h$]h&]uh1jrhj9hhhhhMubhnote)}(hNot all extensions are enabled by default. Using this ioctl the application can enable an extension, making it available to the guest.h]h)}(hNot all extensions are enabled by default. Using this ioctl the application can enable an extension, making it available to the guest.h]hNot all extensions are enabled by default. Using this ioctl the application can enable an extension, making it available to the guest.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1j;hj9hhhhhNubh)}(hOn systems that do not support this ioctl, it always fails. On systems that do support it, it only works for extensions that are supported for enablement.h]hOn systems that do not support this ioctl, it always fails. On systems that do support it, it only works for extensions that are supported for enablement.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hVTo check if a capability can be enabled, the KVM_CHECK_EXTENSION ioctl should be used.h]hVTo check if a capability can be enabled, the KVM_CHECK_EXTENSION ioctl should be used.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubj8)}(h5struct kvm_enable_cap { /* in */ __u32 cap;h]h5struct kvm_enable_cap { /* in */ __u32 cap;}hj;sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj9hhubh)}(h/The capability that is supposed to get enabled.h]h/The capability that is supposed to get enabled.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubj8)}(h __u32 flags;h]h __u32 flags;}hj;sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj9hhubh)}(h?A bitfield indicating future enhancements. Has to be 0 for now.h]h?A bitfield indicating future enhancements. Has to be 0 for now.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubj8)}(h__u64 args[4];h]h__u64 args[4];}hj;sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj9hhubh)}(hxArguments for enabling a feature. If a feature needs initial values to function properly, this is the place to put them.h]hxArguments for enabling a feature. If a feature needs initial values to function properly, this is the place to put them.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubj8)}(h __u8 pad[64]; };h]h __u8 pad[64]; };}hj <sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj9hhubh)}(hdThe vcpu ioctl should be used for vcpu-specific capabilities, the vm ioctl for vm-wide capabilities.h]hdThe vcpu ioctl should be used for vcpu-specific capabilities, the vm ioctl for vm-wide capabilities.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubeh}(h](j9id10eh ]h"](4.37 kvm_enable_capkvm_enable_capeh$]h&]uh1hhjhhhhhMj}j+<j9sj}j9j9subh)}(hhh](h)}(h4.38 KVM_GET_MP_STATEh]h4.38 KVM_GET_MP_STATE}(hj3<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0<hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjG<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjD<hhhKubj)}(hKVM_CAP_MP_STATEh]h)}(hjW<h]hKVM_CAP_MP_STATE}(hjY<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjU<ubah}(h]h ]h"]h$]h&]uh1jhjD<ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjA<hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hju<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjr<hhhKubj)}(h"x86, s390, arm64, riscv, loongarchh]h)}(hj<h]h"x86, s390, arm64, riscv, loongarch}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhjr<ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjA<hhubjx)}(hhh](j})}(hTypeh]hType}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj<hhhKubj)}(h vcpu ioctlh]h)}(hj<h]h vcpu ioctl}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjA<hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj<hhhKubj)}(hstruct kvm_mp_state (out)h]h)}(hj<h]hstruct kvm_mp_state (out)}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjA<hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj<hhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj =ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjA<hhubeh}(h]h ]h"]h$]h&]uh1jrhj0<hhhhhMubj8)}(h.struct kvm_mp_state { __u32 mp_state; };h]h.struct kvm_mp_state { __u32 mp_state; };}hj1=sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj0<hhubh)}(h^Returns the vcpu's current "multiprocessing state" (though also valid on uniprocessor guests).h]hdReturns the vcpu’s current “multiprocessing state” (though also valid on uniprocessor guests).}(hj?=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0<hhubh)}(hPossible values are:h]hPossible values are:}(hjM=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0<hhubj )}(hX6========================== =============================================== KVM_MP_STATE_RUNNABLE the vcpu is currently running [x86,arm64,riscv,loongarch] KVM_MP_STATE_UNINITIALIZED the vcpu is an application processor (AP) which has not yet received an INIT signal [x86] KVM_MP_STATE_INIT_RECEIVED the vcpu has received an INIT signal, and is now ready for a SIPI [x86] KVM_MP_STATE_HALTED the vcpu has executed a HLT instruction and is waiting for an interrupt [x86] KVM_MP_STATE_SIPI_RECEIVED the vcpu has just received a SIPI (vector accessible via KVM_GET_VCPU_EVENTS) [x86] KVM_MP_STATE_STOPPED the vcpu is stopped [s390,arm64,riscv] KVM_MP_STATE_CHECK_STOP the vcpu is in a special error state [s390] KVM_MP_STATE_OPERATING the vcpu is operating (running or halted) [s390] KVM_MP_STATE_LOAD the vcpu is in a special load/startup state [s390] KVM_MP_STATE_SUSPENDED the vcpu is in a suspend state and is waiting for a wakeup event [arm64] ========================== =============================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjb=ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK/uh1jchjb=ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_RUNNABLEh]hKVM_MP_STATE_RUNNABLE}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj|=ubj)}(hhh]h)}(h9the vcpu is currently running [x86,arm64,riscv,loongarch]h]h9the vcpu is currently running [x86,arm64,riscv,loongarch]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj|=ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_UNINITIALIZEDh]hKVM_MP_STATE_UNINITIALIZED}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh]h)}(hYthe vcpu is an application processor (AP) which has not yet received an INIT signal [x86]h]hYthe vcpu is an application processor (AP) which has not yet received an INIT signal [x86]}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_INIT_RECEIVEDh]hKVM_MP_STATE_INIT_RECEIVED}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj=ubj)}(hhh]h)}(hGthe vcpu has received an INIT signal, and is now ready for a SIPI [x86]h]hGthe vcpu has received an INIT signal, and is now ready for a SIPI [x86]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj>ubah}(h]h ]h"]h$]h&]uh1jhj=ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_HALTEDh]hKVM_MP_STATE_HALTED}(hj'>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$>ubah}(h]h ]h"]h$]h&]uh1jhj!>ubj)}(hhh]h)}(hMthe vcpu has executed a HLT instruction and is waiting for an interrupt [x86]h]hMthe vcpu has executed a HLT instruction and is waiting for an interrupt [x86]}(hj>>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;>ubah}(h]h ]h"]h$]h&]uh1jhj!>ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_SIPI_RECEIVEDh]hKVM_MP_STATE_SIPI_RECEIVED}(hj^>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[>ubah}(h]h ]h"]h$]h&]uh1jhjX>ubj)}(hhh]h)}(hSthe vcpu has just received a SIPI (vector accessible via KVM_GET_VCPU_EVENTS) [x86]h]hSthe vcpu has just received a SIPI (vector accessible via KVM_GET_VCPU_EVENTS) [x86]}(hju>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjr>ubah}(h]h ]h"]h$]h&]uh1jhjX>ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_STOPPEDh]hKVM_MP_STATE_STOPPED}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h&the vcpu is stopped [s390,arm64,riscv]h]h&the vcpu is stopped [s390,arm64,riscv]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_CHECK_STOPh]hKVM_MP_STATE_CHECK_STOP}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h+the vcpu is in a special error state [s390]h]h+the vcpu is in a special error state [s390]}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_OPERATINGh]hKVM_MP_STATE_OPERATING}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?ubah}(h]h ]h"]h$]h&]uh1jhj>ubj)}(hhh]h)}(h0the vcpu is operating (running or halted) [s390]h]h0the vcpu is operating (running or halted) [s390]}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?ubah}(h]h ]h"]h$]h&]uh1jhj>ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_LOADh]hKVM_MP_STATE_LOAD}(hj:?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7?ubah}(h]h ]h"]h$]h&]uh1jhj4?ubj)}(hhh]h)}(h2the vcpu is in a special load/startup state [s390]h]h2the vcpu is in a special load/startup state [s390]}(hjQ?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjN?ubah}(h]h ]h"]h$]h&]uh1jhj4?ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubj)}(hhh](j)}(hhh]h)}(hKVM_MP_STATE_SUSPENDEDh]hKVM_MP_STATE_SUSPENDED}(hjq?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjn?ubah}(h]h ]h"]h$]h&]uh1jhjk?ubj)}(hhh]h)}(hHthe vcpu is in a suspend state and is waiting for a wakeup event [arm64]h]hHthe vcpu is in a suspend state and is waiting for a wakeup event [arm64]}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?ubah}(h]h ]h"]h$]h&]uh1jhjk?ubeh}(h]h ]h"]h$]h&]uh1j~hjy=ubeh}(h]h ]h"]h$]h&]uh1jyhjb=ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj_=ubah}(h]h ]h"]h$]h&]uh1jYhj[=ubah}(h]h ]h"]h$]h&]uh1j hhhMhj0<hhubh)}(hOn x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures.h]hOn x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0<hhubh)}(hhh](h)}(h For arm64:h]h For arm64:}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhM"ubh)}(htIf a vCPU is in the KVM_MP_STATE_SUSPENDED state, KVM will emulate the architectural execution of a WFI instruction.h]htIf a vCPU is in the KVM_MP_STATE_SUSPENDED state, KVM will emulate the architectural execution of a WFI instruction.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj?hhubh)}(hXFIf a wakeup event is recognized, KVM will exit to userspace with a KVM_SYSTEM_EVENT exit, where the event type is KVM_SYSTEM_EVENT_WAKEUP. If userspace wants to honor the wakeup, it must set the vCPU's MP state to KVM_MP_STATE_RUNNABLE. If it does not, KVM will continue to await a wakeup event in subsequent calls to KVM_RUN.h]hXHIf a wakeup event is recognized, KVM will exit to userspace with a KVM_SYSTEM_EVENT exit, where the event type is KVM_SYSTEM_EVENT_WAKEUP. If userspace wants to honor the wakeup, it must set the vCPU’s MP state to KVM_MP_STATE_RUNNABLE. If it does not, KVM will continue to await a wakeup event in subsequent calls to KVM_RUN.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hj?hhubhwarning)}(hXIf userspace intends to keep the vCPU in a SUSPENDED state, it is strongly recommended that userspace take action to suppress the wakeup event (such as masking an interrupt). Otherwise, subsequent calls to KVM_RUN will immediately exit with a KVM_SYSTEM_EVENT_WAKEUP event and inadvertently waste CPU cycles. Additionally, if userspace takes action to suppress a wakeup event, it is strongly recommended that it also restores the vCPU to its original state when the vCPU is made RUNNABLE again. For example, if userspace masked a pending interrupt to suppress the wakeup, the interrupt should be unmasked before returning control to the guest.h](h)}(hX4If userspace intends to keep the vCPU in a SUSPENDED state, it is strongly recommended that userspace take action to suppress the wakeup event (such as masking an interrupt). Otherwise, subsequent calls to KVM_RUN will immediately exit with a KVM_SYSTEM_EVENT_WAKEUP event and inadvertently waste CPU cycles.h]hX4If userspace intends to keep the vCPU in a SUSPENDED state, it is strongly recommended that userspace take action to suppress the wakeup event (such as masking an interrupt). Otherwise, subsequent calls to KVM_RUN will immediately exit with a KVM_SYSTEM_EVENT_WAKEUP event and inadvertently waste CPU cycles.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj?ubh)}(hXNAdditionally, if userspace takes action to suppress a wakeup event, it is strongly recommended that it also restores the vCPU to its original state when the vCPU is made RUNNABLE again. For example, if userspace masked a pending interrupt to suppress the wakeup, the interrupt should be unmasked before returning control to the guest.h]hXNAdditionally, if userspace takes action to suppress a wakeup event, it is strongly recommended that it also restores the vCPU to its original state when the vCPU is made RUNNABLE again. For example, if userspace masked a pending interrupt to suppress the wakeup, the interrupt should be unmasked before returning control to the guest.}(hj @hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj?ubeh}(h]h ]h"]h$]h&]uh1j?hj?hhhhhNubeh}(h] for-arm64ah ]h"]h$] for arm64:ah&]uh1hhj0<hhhhhM"jKubh)}(hhh](h)}(h For riscv:h]h For riscv:}(hj)@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&@hhhhhM=ubh)}(h}The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not.h]h}The only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not.}(hj7@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj&@hhubh)}(hcOn LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect whether the vcpu is runnable.h]hcOn LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect whether the vcpu is runnable.}(hjE@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhj&@hhubeh}(h] for-riscvah ]h"] for riscv:ah$]h&]uh1hhj0<hhhhhM=ubeh}(h]kvm-get-mp-stateah ]h"]4.38 kvm_get_mp_stateah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.39 KVM_SET_MP_STATEh]h4.39 KVM_SET_MP_STATE}(hjf@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjc@hhhhhMFubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjz@hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjw@hhhKubj)}(hKVM_CAP_MP_STATEh]h)}(hj@h]hKVM_CAP_MP_STATE}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhj@ubah}(h]h ]h"]h$]h&]uh1jhjw@ubeh}(h]h ]h"]h$]h&]uh1jwhhhMHhjt@hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@hhhKubj)}(h"x86, s390, arm64, riscv, loongarchh]h)}(hj@h]h"x86, s390, arm64, riscv, loongarch}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jwhhhMIhjt@hhubjx)}(hhh](j})}(hTypeh]hType}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@hhhKubj)}(h vcpu ioctlh]h)}(hj@h]h vcpu ioctl}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jwhhhMJhjt@hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hstruct kvm_mp_state (in)h]h)}(hjAh]hstruct kvm_mp_state (in)}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMKhjt@hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj2AhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/AhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjDAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj@Aubah}(h]h ]h"]h$]h&]uh1jhj/Aubeh}(h]h ]h"]h$]h&]uh1jwhhhMLhjt@hhubeh}(h]h ]h"]h$]h&]uh1jrhjc@hhhhhMHubh)}(hTSets the vcpu's current "multiprocessing state"; see KVM_GET_MP_STATE for arguments.h]hZSets the vcpu’s current “multiprocessing state”; see KVM_GET_MP_STATE for arguments.}(hjdAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjc@hhubh)}(hOn x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures.h]hOn x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel irqchip, the multiprocessing state must be maintained by userspace on these architectures.}(hjrAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjc@hhubh)}(hhh](h)}(hFor arm64/riscv:h]hFor arm64/riscv:}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMVubh)}(hThe only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not.h]hThe only states that are valid are KVM_MP_STATE_STOPPED and KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjAhhubh)}(hcOn LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect whether the vcpu is runnable.h]hcOn LoongArch, only the KVM_MP_STATE_RUNNABLE state is used to reflect whether the vcpu is runnable.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjAhhubeh}(h]for-arm64-riscvah ]h"]for arm64/riscv:ah$]h&]uh1hhjc@hhhhhMVubeh}(h]kvm-set-mp-stateah ]h"]4.39 kvm_set_mp_stateah$]h&]uh1hhjhhhhhMFubh)}(hhh](h)}(h4.40 KVM_SET_IDENTITY_MAP_ADDRh]h4.40 KVM_SET_IDENTITY_MAP_ADDR}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhM_ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hKVM_CAP_SET_IDENTITY_MAP_ADDRh]h)}(hjAh]hKVM_CAP_SET_IDENTITY_MAP_ADDR}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMahjAhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hx86h]h)}(hjBh]hx86}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjBubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMbhjAhhubjx)}(hhh](j})}(hTypeh]hType}(hj0BhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj-BhhhKubj)}(hvm ioctlh]h)}(hj@Bh]hvm ioctl}(hjBBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchj>Bubah}(h]h ]h"]h$]h&]uh1jhj-Bubeh}(h]h ]h"]h$]h&]uh1jwhhhMchjAhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj^BhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj[BhhhKubj)}(hunsigned long identity (in)h]h)}(hjnBh]hunsigned long identity (in)}(hjpBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjlBubah}(h]h ]h"]h$]h&]uh1jhj[Bubeh}(h]h ]h"]h$]h&]uh1jwhhhMdhjAhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jwhhhMehjAhhubeh}(h]h ]h"]h$]h&]uh1jrhjAhhhhhMaubh)}(hX,This ioctl defines the physical address of a one-page region in the guest physical address space. The region must be within the first 4GB of the guest physical address space and must not conflict with any memory slot or any mmio address. The guest may malfunction if it accesses this memory region.h]hX,This ioctl defines the physical address of a one-page region in the guest physical address space. The region must be within the first 4GB of the guest physical address space and must not conflict with any memory slot or any mmio address. The guest may malfunction if it accesses this memory region.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjAhhubh)}(hZSetting the address to 0 will result in resetting the address to its default (0xfffbc000).h]hZSetting the address to 0 will result in resetting the address to its default (0xfffbc000).}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjAhhubh)}(hThis ioctl is required on Intel-based hosts. This is needed on Intel hardware because of a quirk in the virtualization implementation (see the internals documentation when it pops into existence).h]hThis ioctl is required on Intel-based hosts. This is needed on Intel hardware because of a quirk in the virtualization implementation (see the internals documentation when it pops into existence).}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphjAhhubh)}(h+Fails if any VCPU has already been created.h]h+Fails if any VCPU has already been created.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjAhhubeh}(h]kvm-set-identity-map-addrah ]h"]4.40 kvm_set_identity_map_addrah$]h&]uh1hhjhhhhhM_ubh)}(hhh](h)}(h4.41 KVM_SET_BOOT_CPU_IDh]h4.41 KVM_SET_BOOT_CPU_ID}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhMwubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(hKVM_CAP_SET_BOOT_CPU_IDh]h)}(hj%Ch]hKVM_CAP_SET_BOOT_CPU_ID}(hj'ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj#Cubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhMyhjChhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjCChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@ChhhKubj)}(hx86h]h)}(hjSCh]hx86}(hjUChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhjQCubah}(h]h ]h"]h$]h&]uh1jhj@Cubeh}(h]h ]h"]h$]h&]uh1jwhhhMzhjChhubjx)}(hhh](j})}(hTypeh]hType}(hjqChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjnChhhKubj)}(hvm ioctlh]h)}(hjCh]hvm ioctl}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hjCubah}(h]h ]h"]h$]h&]uh1jhjnCubeh}(h]h ]h"]h$]h&]uh1jwhhhM{hjChhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(hunsigned long vcpu_idh]h)}(hjCh]hunsigned long vcpu_id}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM|hjChhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM}hjChhubeh}(h]h ]h"]h$]h&]uh1jrhjBhhhhhMyubh)}(hDefine which vcpu is the Bootstrap Processor (BSP). Values are the same as the vcpu id in KVM_CREATE_VCPU. If this ioctl is not called, the default is vcpu 0. This ioctl has to be called before vcpu creation, otherwise it will return EBUSY error.h]hDefine which vcpu is the Bootstrap Processor (BSP). Values are the same as the vcpu id in KVM_CREATE_VCPU. If this ioctl is not called, the default is vcpu 0. This ioctl has to be called before vcpu creation, otherwise it will return EBUSY error.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBhhubeh}(h]kvm-set-boot-cpu-idah ]h"]4.41 kvm_set_boot_cpu_idah$]h&]uh1hhjhhhhhMwubh)}(hhh](h)}(h4.42 KVM_GET_XSAVEh]h4.42 KVM_GET_XSAVE}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj,DhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)DhhhKubj)}(h KVM_CAP_XSAVEh]h)}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:Dubah}(h]h ]h"]h$]h&]uh1jhj)Dubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj&Dhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjZDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjWDhhhKubj)}(hx86h]h)}(hjjDh]hx86}(hjlDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhDubah}(h]h ]h"]h$]h&]uh1jhjWDubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj&Dhhubjx)}(hhh](j})}(hTypeh]hType}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDhhhKubj)}(h vcpu ioctlh]h)}(hjDh]h vcpu ioctl}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj&Dhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDhhhKubj)}(hstruct kvm_xsave (out)h]h)}(hjDh]hstruct kvm_xsave (out)}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj&Dhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj&Dhhubeh}(h]h ]h"]h$]h&]uh1jrhjDhhhhhMubj8)}(hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };h]hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };}hjEsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjDhhubh)}(hCThis ioctl would copy current vcpu's xsave struct to the userspace.h]hEThis ioctl would copy current vcpu’s xsave struct to the userspace.}(hj$EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDhhubeh}(h] kvm-get-xsaveah ]h"]4.42 kvm_get_xsaveah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.43 KVM_SET_XSAVEh]h4.43 KVM_SET_XSAVE}(hj=EhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:EhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjQEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjNEhhhKubj)}(h KVM_CAP_XSAVE and KVM_CAP_XSAVE2h]h)}(hjaEh]h KVM_CAP_XSAVE and KVM_CAP_XSAVE2}(hjcEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_Eubah}(h]h ]h"]h$]h&]uh1jhjNEubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjKEhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj|EhhhKubj)}(hx86h]h)}(hjEh]hx86}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhj|Eubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjKEhhubjx)}(hhh](j})}(hTypeh]hType}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(h vcpu ioctlh]h)}(hjEh]h vcpu ioctl}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjKEhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(hstruct kvm_xsave (in)h]h)}(hjEh]hstruct kvm_xsave (in)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjKEhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj FhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjKEhhubeh}(h]h ]h"]h$]h&]uh1jrhj:EhhhhhMubj8)}(hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };h]hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };}hj;Fsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj:Ehhubh)}(hXThis ioctl would copy userspace's xsave struct to the kernel. It copies as many bytes as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2), when invoked on the vm file descriptor. The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) will always be at least 4096. Currently, it is only greater than 4096 if a dynamic feature has been enabled with ``arch_prctl()``, but this may change in the future.h](hXhThis ioctl would copy userspace’s xsave struct to the kernel. It copies as many bytes as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2), when invoked on the vm file descriptor. The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) will always be at least 4096. Currently, it is only greater than 4096 if a dynamic feature has been enabled with }(hjIFhhhNhNubj)}(h``arch_prctl()``h]h arch_prctl()}(hjQFhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIFubh$, but this may change in the future.}(hjIFhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj:Ehhubh)}(hjThe offsets of the state save areas in struct kvm_xsave follow the contents of CPUID leaf 0xD on the host.h]hjThe offsets of the state save areas in struct kvm_xsave follow the contents of CPUID leaf 0xD on the host.}(hjiFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:Ehhubeh}(h] kvm-set-xsaveah ]h"]4.43 kvm_set_xsaveah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.44 KVM_GET_XCRSh]h4.44 KVM_GET_XCRS}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(h KVM_CAP_XCRSh]h)}(hjFh]h KVM_CAP_XCRS}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjFhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(hx86h]h)}(hjFh]hx86}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjFhhubjx)}(hhh](j})}(hTypeh]hType}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(h vcpu ioctlh]h)}(hjGh]h vcpu ioctl}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjFhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj GhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(hstruct kvm_xcrs (out)h]h)}(hj0Gh]hstruct kvm_xcrs (out)}(hj2GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.Gubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjFhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjNGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKGhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj`GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\Gubah}(h]h ]h"]h$]h&]uh1jhjKGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjFhhubeh}(h]h ]h"]h$]h&]uh1jrhjFhhhhhMubj8)}(hstruct kvm_xcr { __u32 xcr; __u32 reserved; __u64 value; }; struct kvm_xcrs { __u32 nr_xcrs; __u32 flags; struct kvm_xcr xcrs[KVM_MAX_XCRS]; __u64 padding[16]; };h]hstruct kvm_xcr { __u32 xcr; __u32 reserved; __u64 value; }; struct kvm_xcrs { __u32 nr_xcrs; __u32 flags; struct kvm_xcr xcrs[KVM_MAX_XCRS]; __u64 padding[16]; };}hjGsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjFhhubh)}(h;This ioctl would copy current vcpu's xcrs to the userspace.h]h=This ioctl would copy current vcpu’s xcrs to the userspace.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFhhubeh}(h] kvm-get-xcrsah ]h"]4.44 kvm_get_xcrsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.45 KVM_SET_XCRSh]h4.45 KVM_SET_XCRS}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(h KVM_CAP_XCRSh]h)}(hjGh]h KVM_CAP_XCRS}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(hx86h]h)}(hjGh]hx86}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hTypeh]hType}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjHhhhKubj)}(h vcpu ioctlh]h)}(hj'Hh]h vcpu ioctl}(hj)HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%Hubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjEHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBHhhhKubj)}(hstruct kvm_xcrs (in)h]h)}(hjUHh]hstruct kvm_xcrs (in)}(hjWHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjSHubah}(h]h ]h"]h$]h&]uh1jhjBHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjsHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjpHhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhjpHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubeh}(h]h ]h"]h$]h&]uh1jrhjGhhhhhMubj8)}(hstruct kvm_xcr { __u32 xcr; __u32 reserved; __u64 value; }; struct kvm_xcrs { __u32 nr_xcrs; __u32 flags; struct kvm_xcr xcrs[KVM_MAX_XCRS]; __u64 padding[16]; };h]hstruct kvm_xcr { __u32 xcr; __u32 reserved; __u64 value; }; struct kvm_xcrs { __u32 nr_xcrs; __u32 flags; struct kvm_xcr xcrs[KVM_MAX_XCRS]; __u64 padding[16]; };}hjHsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjGhhubh)}(hAThis ioctl would set vcpu's xcr to the value userspace specified.h]hCThis ioctl would set vcpu’s xcr to the value userspace specified.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGhhubeh}(h] kvm-set-xcrsah ]h"]4.45 kvm_set_xcrsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.46 KVM_GET_SUPPORTED_CPUIDh]h4.46 KVM_GET_SUPPORTED_CPUID}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjHhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjHhhhKubj)}(hKVM_CAP_EXT_CPUIDh]h)}(hjHh]hKVM_CAP_EXT_CPUID}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjHhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj IhhhKubj)}(hx86h]h)}(hjIh]hx86}(hj IhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIubah}(h]h ]h"]h$]h&]uh1jhj Iubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjHhhubjx)}(hhh](j})}(hTypeh]hType}(hjhjHhhubh)}(hif that returns true and you use KVM_CREATE_IRQCHIP, or if you emulate the feature in userspace, then you can enable the feature for KVM_SET_CPUID2.h]hif that returns true and you use KVM_CREATE_IRQCHIP, or if you emulate the feature in userspace, then you can enable the feature for KVM_SET_CPUID2.}(hjpKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjHhhubh)}(hEnabling x2APIC in KVM_SET_CPUID2 requires KVM_CREATE_IRQCHIP as KVM doesn't support forwarding x2APIC MSR accesses to userspace, i.e. KVM does not support emulating x2APIC in userspace.h]hEnabling x2APIC in KVM_SET_CPUID2 requires KVM_CREATE_IRQCHIP as KVM doesn’t support forwarding x2APIC MSR accesses to userspace, i.e. KVM does not support emulating x2APIC in userspace.}(hj~KhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjHhhubeh}(h]kvm-get-supported-cpuidah ]h"]4.46 kvm_get_supported_cpuidah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.47 KVM_PPC_GET_PVINFOh]h4.47 KVM_PPC_GET_PVINFO}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhhhhhMHubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hKVM_CAP_PPC_GET_PVINFOh]h)}(hjKh]hKVM_CAP_PPC_GET_PVINFO}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMJhjKhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hppch]h)}(hjKh]hppc}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMKhjKhhubjx)}(hhh](j})}(hTypeh]hType}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(hvm ioctlh]h)}(hjLh]hvm ioctl}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhMLhjKhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj5LhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj2LhhhKubj)}(hstruct kvm_ppc_pvinfo (out)h]h)}(hjELh]hstruct kvm_ppc_pvinfo (out)}(hjGLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjCLubah}(h]h ]h"]h$]h&]uh1jhj2Lubeh}(h]h ]h"]h$]h&]uh1jwhhhMMhjKhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjcLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj`LhhhKubj)}(h0 on success, !0 on error h]h)}(h0 on success, !0 on errorh]h0 on success, !0 on error}(hjuLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjqLubah}(h]h ]h"]h$]h&]uh1jhj`Lubeh}(h]h ]h"]h$]h&]uh1jwhhhMNhjKhhubeh}(h]h ]h"]h$]h&]uh1jrhjKhhhhhMJubj8)}(hYstruct kvm_ppc_pvinfo { __u32 flags; __u32 hcall[4]; __u8 pad[108]; };h]hYstruct kvm_ppc_pvinfo { __u32 flags; __u32 hcall[4]; __u8 pad[108]; };}hjLsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMRhjKhhubh)}(hThis ioctl fetches PV specific information that need to be passed to the guest using the device tree or other means from vm context.h]hThis ioctl fetches PV specific information that need to be passed to the guest using the device tree or other means from vm context.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjKhhubh)}(h@The hcall array defines 4 instructions that make up a hypercall.h]h@The hcall array defines 4 instructions that make up a hypercall.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjKhhubh)}(hIf any additional field gets added to this structure later on, a bit for that additional piece of information will be set in the flags bitmap.h]hIf any additional field gets added to this structure later on, a bit for that additional piece of information will be set in the flags bitmap.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjKhhubh)}(h The flags bitmap is defined as::h]hThe flags bitmap is defined as:}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjKhhubj8)}(hW/* the host supports the ePAPR idle hcall #define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)h]hW/* the host supports the ePAPR idle hcall #define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)}hjLsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMbhjKhhubeh}(h]kvm-ppc-get-pvinfoah ]h"]4.47 kvm_ppc_get_pvinfoah$]h&]uh1hhjhhhhhMHubh)}(hhh](h)}(h4.52 KVM_SET_GSI_ROUTINGh]h4.52 KVM_SET_GSI_ROUTING}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhMfubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hKVM_CAP_IRQ_ROUTINGh]h)}(hjMh]hKVM_CAP_IRQ_ROUTING}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhMhhjMhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj6MhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj3MhhhKubj)}(hx86 s390 arm64h]h)}(hjFMh]hx86 s390 arm64}(hjHMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjDMubah}(h]h ]h"]h$]h&]uh1jhj3Mubeh}(h]h ]h"]h$]h&]uh1jwhhhMihjMhhubjx)}(hhh](j})}(hTypeh]hType}(hjdMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjaMhhhKubj)}(hvm ioctlh]h)}(hjtMh]hvm ioctl}(hjvMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjrMubah}(h]h ]h"]h$]h&]uh1jhjaMubeh}(h]h ]h"]h$]h&]uh1jwhhhMjhjMhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hstruct kvm_irq_routing (in)h]h)}(hjMh]hstruct kvm_irq_routing (in)}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhMkhjMhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhMlhjMhhubeh}(h]h ]h"]h$]h&]uh1jrhjLhhhhhMhubh)}(hKSets the GSI routing table entries, overwriting any previously set entries.h]hKSets the GSI routing table entries, overwriting any previously set entries.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjLhhubh)}(h3On arm64, GSI routing has the following limitation:h]h3On arm64, GSI routing has the following limitation:}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMphjLhhubj)}(hhh]j)}(hBGSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD. h]h)}(hAGSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD.h]hAGSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjNubah}(h]h ]h"]h$]h&]uh1jhjNhhhhhNubah}(h]h ]h"]h$]h&]jjuh1jhhhMrhjLhhubj8)}(hmstruct kvm_irq_routing { __u32 nr; __u32 flags; struct kvm_irq_routing_entry entries[0]; };h]hmstruct kvm_irq_routing { __u32 nr; __u32 flags; struct kvm_irq_routing_entry entries[0]; };}hj/Nsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMvhjLhhubh)}(hKNo flags are specified so far, the corresponding field must be set to zero.h]hKNo flags are specified so far, the corresponding field must be set to zero.}(hj=NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjLhhubj8)}(hX{struct kvm_irq_routing_entry { __u32 gsi; __u32 type; __u32 flags; __u32 pad; union { struct kvm_irq_routing_irqchip irqchip; struct kvm_irq_routing_msi msi; struct kvm_irq_routing_s390_adapter adapter; struct kvm_irq_routing_hv_sint hv_sint; struct kvm_irq_routing_xen_evtchn xen_evtchn; __u32 pad[8]; } u; }; /* gsi routing entry types */ #define KVM_IRQ_ROUTING_IRQCHIP 1 #define KVM_IRQ_ROUTING_MSI 2 #define KVM_IRQ_ROUTING_S390_ADAPTER 3 #define KVM_IRQ_ROUTING_HV_SINT 4 #define KVM_IRQ_ROUTING_XEN_EVTCHN 5h]hX{struct kvm_irq_routing_entry { __u32 gsi; __u32 type; __u32 flags; __u32 pad; union { struct kvm_irq_routing_irqchip irqchip; struct kvm_irq_routing_msi msi; struct kvm_irq_routing_s390_adapter adapter; struct kvm_irq_routing_hv_sint hv_sint; struct kvm_irq_routing_xen_evtchn xen_evtchn; __u32 pad[8]; } u; }; /* gsi routing entry types */ #define KVM_IRQ_ROUTING_IRQCHIP 1 #define KVM_IRQ_ROUTING_MSI 2 #define KVM_IRQ_ROUTING_S390_ADAPTER 3 #define KVM_IRQ_ROUTING_HV_SINT 4 #define KVM_IRQ_ROUTING_XEN_EVTCHN 5}hjKNsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjLhhubh)}(h^On s390, adding a KVM_IRQ_ROUTING_S390_ADAPTER is rejected on ucontrol VMs with error -EINVAL.h]h^On s390, adding a KVM_IRQ_ROUTING_S390_ADAPTER is rejected on ucontrol VMs with error -EINVAL.}(hjYNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLhhubh)}(hflags:h]hflags:}(hjgNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLhhubj)}(hhh](j)}(hXXKVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry type, specifies that the devid field contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail.h]h)}(hXXKVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry type, specifies that the devid field contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail.h]hXXKVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry type, specifies that the devid field contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail.}(hj|NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjxNubah}(h]h ]h"]h$]h&]uh1jhjuNhhhhhNubj)}(hzero otherwise h]h)}(hzero otherwiseh]hzero otherwise}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNubah}(h]h ]h"]h$]h&]uh1jhjuNhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjLhhubj8)}(hstruct kvm_irq_routing_irqchip { __u32 irqchip; __u32 pin; }; struct kvm_irq_routing_msi { __u32 address_lo; __u32 address_hi; __u32 data; union { __u32 pad; __u32 devid; }; };h]hstruct kvm_irq_routing_irqchip { __u32 irqchip; __u32 pin; }; struct kvm_irq_routing_msi { __u32 address_lo; __u32 address_hi; __u32 data; union { __u32 pad; __u32 devid; }; };}hjNsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjLhhubh)}(hIf KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier for the device that wrote the MSI message. For PCI, this is usually a BDF identifier in the lower 16 bits.h]hIf KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier for the device that wrote the MSI message. For PCI, this is usually a BDF identifier in the lower 16 bits.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLhhubh)}(hOn x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of address_hi must be zero.h]hOn x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of address_hi must be zero.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLhhubj8)}(hXOstruct kvm_irq_routing_s390_adapter { __u64 ind_addr; __u64 summary_addr; __u64 ind_offset; __u32 summary_offset; __u32 adapter_id; }; struct kvm_irq_routing_hv_sint { __u32 vcpu; __u32 sint; }; struct kvm_irq_routing_xen_evtchn { __u32 port; __u32 vcpu; __u32 priority; };h]hXOstruct kvm_irq_routing_s390_adapter { __u64 ind_addr; __u64 summary_addr; __u64 ind_offset; __u32 summary_offset; __u32 adapter_id; }; struct kvm_irq_routing_hv_sint { __u32 vcpu; __u32 sint; }; struct kvm_irq_routing_xen_evtchn { __u32 port; __u32 vcpu; __u32 priority; };}hjNsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjLhhubh)}(hXhWhen KVM_CAP_XEN_HVM includes the KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL bit in its indication of supported features, routing to Xen event channels is supported. Although the priority field is present, only the value KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL is supported, which means delivery by 2 level event channels. FIFO event channel support may be added in the future.h]hXhWhen KVM_CAP_XEN_HVM includes the KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL bit in its indication of supported features, routing to Xen event channels is supported. Although the priority field is present, only the value KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL is supported, which means delivery by 2 level event channels. FIFO event channel support may be added in the future.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLhhubeh}(h]kvm-set-gsi-routingah ]h"]4.52 kvm_set_gsi_routingah$]h&]uh1hhjhhhhhMfubh)}(hhh](h)}(h4.55 KVM_SET_TSC_KHZh]h4.55 KVM_SET_TSC_KHZ}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjOhhhKubj)}(h,KVM_CAP_TSC_CONTROL / KVM_CAP_VM_TSC_CONTROLh]h)}(hj#Oh]h,KVM_CAP_TSC_CONTROL / KVM_CAP_VM_TSC_CONTROL}(hj%OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!Oubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj Ohhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjAOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj>OhhhKubj)}(hx86h]h)}(hjQOh]hx86}(hjSOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjOOubah}(h]h ]h"]h$]h&]uh1jhj>Oubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj Ohhubjx)}(hhh](j})}(hTypeh]hType}(hjoOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjlOhhhKubj)}(hvcpu ioctl / vm ioctlh]h)}(hjOh]hvcpu ioctl / vm ioctl}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}Oubah}(h]h ]h"]h$]h&]uh1jhjlOubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj Ohhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjOhhhKubj)}(hvirtual tsc_khzh]h)}(hjOh]hvirtual tsc_khz}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj Ohhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjOhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj Ohhubeh}(h]h ]h"]h$]h&]uh1jrhjNhhhhhMubh)}(hVSpecifies the tsc frequency for the virtual machine. The unit of the frequency is KHz.h]hVSpecifies the tsc frequency for the virtual machine. The unit of the frequency is KHz.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hIf the KVM_CAP_VM_TSC_CONTROL capability is advertised, this can also be used as a vm ioctl to set the initial tsc frequency of subsequently created vCPUs. Note, the vm ioctl is only allowed prior to creating vCPUs.h]hIf the KVM_CAP_VM_TSC_CONTROL capability is advertised, this can also be used as a vm ioctl to set the initial tsc frequency of subsequently created vCPUs. Note, the vm ioctl is only allowed prior to creating vCPUs.}(hj PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hFor TSC protected Confidential Computing (CoCo) VMs where TSC frequency is configured once at VM scope and remains unchanged during VM's lifetime, the vm ioctl should be used to configure the TSC frequency and the vcpu ioctl is not supported.h]hFor TSC protected Confidential Computing (CoCo) VMs where TSC frequency is configured once at VM scope and remains unchanged during VM’s lifetime, the vm ioctl should be used to configure the TSC frequency and the vcpu ioctl is not supported.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(h%Example of such CoCo VMs: TDX guests.h]h%Example of such CoCo VMs: TDX guests.}(hj'PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubeh}(h]kvm-set-tsc-khzah ]h"]4.55 kvm_set_tsc_khzah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.56 KVM_GET_TSC_KHZh]h4.56 KVM_GET_TSC_KHZ}(hj@PhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=PhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjTPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQPhhhKubj)}(h,KVM_CAP_GET_TSC_KHZ / KVM_CAP_VM_TSC_CONTROLh]h)}(hjdPh]h,KVM_CAP_GET_TSC_KHZ / KVM_CAP_VM_TSC_CONTROL}(hjfPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjbPubah}(h]h ]h"]h$]h&]uh1jhjQPubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNPhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hx86h]h)}(hjPh]hx86}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNPhhubjx)}(hhh](j})}(hTypeh]hType}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hvcpu ioctl / vm ioctlh]h)}(hjPh]hvcpu ioctl / vm ioctl}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNPhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hnoneh]h)}(hjPh]hnone}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNPhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj QhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj QhhhKubj)}(h4virtual tsc-khz on success, negative value on error h]h)}(h3virtual tsc-khz on success, negative value on errorh]h3virtual tsc-khz on success, negative value on error}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQubah}(h]h ]h"]h$]h&]uh1jhj Qubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNPhhubeh}(h]h ]h"]h$]h&]uh1jrhj=PhhhhhMubh)}(hReturns the tsc frequency of the guest. The unit of the return value is KHz. If the host has unstable tsc this ioctl returns -EIO instead as an error.h]hReturns the tsc frequency of the guest. The unit of the return value is KHz. If the host has unstable tsc this ioctl returns -EIO instead as an error.}(hj>QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=Phhubeh}(h]kvm-get-tsc-khzah ]h"]4.56 kvm_get_tsc_khzah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.57 KVM_GET_LAPICh]h4.57 KVM_GET_LAPIC}(hjWQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjTQhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjkQhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhQhhhKubj)}(hKVM_CAP_IRQCHIPh]h)}(hj{Qh]hKVM_CAP_IRQCHIP}(hj}QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyQubah}(h]h ]h"]h$]h&]uh1jhjhQubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjeQhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQhhhKubj)}(hx86h]h)}(hjQh]hx86}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjeQhhubjx)}(hhh](j})}(hTypeh]hType}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQhhhKubj)}(h vcpu ioctlh]h)}(hjQh]h vcpu ioctl}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjeQhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQhhhKubj)}(hstruct kvm_lapic_state (out)h]h)}(hjRh]hstruct kvm_lapic_state (out)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjeQhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj#RhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj RhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj5RhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1Rubah}(h]h ]h"]h$]h&]uh1jhj Rubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjeQhhubeh}(h]h ]h"]h$]h&]uh1jrhjTQhhhhhMubj8)}(h_#define KVM_APIC_REG_SIZE 0x400 struct kvm_lapic_state { char regs[KVM_APIC_REG_SIZE]; };h]h_#define KVM_APIC_REG_SIZE 0x400 struct kvm_lapic_state { char regs[KVM_APIC_REG_SIZE]; };}hjURsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjTQhhubh)}(hReads the Local APIC registers and copies them into the input argument. The data format and layout are the same as documented in the architecture manual.h]hReads the Local APIC registers and copies them into the input argument. The data format and layout are the same as documented in the architecture manual.}(hjcRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTQhhubh)}(hXIf KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API is enabled, then the format of APIC_ID register depends on the APIC mode (reported by MSR_IA32_APICBASE) of its VCPU. x2APIC stores APIC ID in the APIC_ID register (bytes 32-35). xAPIC only allows an 8-bit APIC ID which is stored in bits 31-24 of the APIC register, or equivalently in byte 35 of struct kvm_lapic_state's regs field. KVM_GET_LAPIC must then be called after MSR_IA32_APICBASE has been set with KVM_SET_MSR.h]hXIf KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API is enabled, then the format of APIC_ID register depends on the APIC mode (reported by MSR_IA32_APICBASE) of its VCPU. x2APIC stores APIC ID in the APIC_ID register (bytes 32-35). xAPIC only allows an 8-bit APIC ID which is stored in bits 31-24 of the APIC register, or equivalently in byte 35 of struct kvm_lapic_state’s regs field. KVM_GET_LAPIC must then be called after MSR_IA32_APICBASE has been set with KVM_SET_MSR.}(hjqRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTQhhubh)}(heIf KVM_X2APIC_API_USE_32BIT_IDS feature is disabled, struct kvm_lapic_state always uses xAPIC format.h]heIf KVM_X2APIC_API_USE_32BIT_IDS feature is disabled, struct kvm_lapic_state always uses xAPIC format.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTQhhubeh}(h] kvm-get-lapicah ]h"]4.57 kvm_get_lapicah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.58 KVM_SET_LAPICh]h4.58 KVM_SET_LAPIC}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjRhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hKVM_CAP_IRQCHIPh]h)}(hjRh]hKVM_CAP_IRQCHIP}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhM!hjRhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hx86h]h)}(hjRh]hx86}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjRhhubjx)}(hhh](j})}(hTypeh]hType}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjShhhKubj)}(h vcpu ioctlh]h)}(hjSh]h vcpu ioctl}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjRhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj6ShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj3ShhhKubj)}(hstruct kvm_lapic_state (in)h]h)}(hjFSh]hstruct kvm_lapic_state (in)}(hjHShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjDSubah}(h]h ]h"]h$]h&]uh1jhj3Subeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjRhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjdShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjaShhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjvShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjrSubah}(h]h ]h"]h$]h&]uh1jhjaSubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hjRhhubeh}(h]h ]h"]h$]h&]uh1jrhjRhhhhhM!ubj8)}(h_#define KVM_APIC_REG_SIZE 0x400 struct kvm_lapic_state { char regs[KVM_APIC_REG_SIZE]; };h]h_#define KVM_APIC_REG_SIZE 0x400 struct kvm_lapic_state { char regs[KVM_APIC_REG_SIZE]; };}hjSsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM)hjRhhubh)}(hCopies the input argument into the Local APIC registers. The data format and layout are the same as documented in the architecture manual.h]hCopies the input argument into the Local APIC registers. The data format and layout are the same as documented in the architecture manual.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjRhhubh)}(hThe format of the APIC ID register (bytes 32-35 of struct kvm_lapic_state's regs field) depends on the state of the KVM_CAP_X2APIC_API capability. See the note in KVM_GET_LAPIC.h]hThe format of the APIC ID register (bytes 32-35 of struct kvm_lapic_state’s regs field) depends on the state of the KVM_CAP_X2APIC_API capability. See the note in KVM_GET_LAPIC.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjRhhubeh}(h] kvm-set-lapicah ]h"]4.58 kvm_set_lapicah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.59 KVM_IOEVENTFDh]h4.59 KVM_IOEVENTFD}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhM7ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjShhhKubj)}(hKVM_CAP_IOEVENTFDh]h)}(hjSh]hKVM_CAP_IOEVENTFD}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjSubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jwhhhM9hjShhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj ThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj ThhhKubj)}(hallh]h)}(hjTh]hall}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjTubah}(h]h ]h"]h$]h&]uh1jhj Tubeh}(h]h ]h"]h$]h&]uh1jwhhhM:hjShhubjx)}(hhh](j})}(hTypeh]hType}(hj;ThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8ThhhKubj)}(hvm ioctlh]h)}(hjKTh]hvm ioctl}(hjMThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjITubah}(h]h ]h"]h$]h&]uh1jhj8Tubeh}(h]h ]h"]h$]h&]uh1jwhhhM;hjShhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjiThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjfThhhKubj)}(hstruct kvm_ioeventfd (in)h]h)}(hjyTh]hstruct kvm_ioeventfd (in)}(hj{ThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjwTubah}(h]h ]h"]h$]h&]uh1jhjfTubeh}(h]h ]h"]h$]h&]uh1jwhhhM<hjShhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjThhhKubj)}(h0 on success, !0 on error h]h)}(h0 on success, !0 on errorh]h0 on success, !0 on error}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jwhhhM=hjShhubeh}(h]h ]h"]h$]h&]uh1jrhjShhhhhM9ubh)}(hThis ioctl attaches or detaches an ioeventfd to a legal pio/mmio address within the guest. A guest write in the registered address will signal the provided event instead of triggering an exit.h]hThis ioctl attaches or detaches an ioeventfd to a legal pio/mmio address within the guest. A guest write in the registered address will signal the provided event instead of triggering an exit.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hjShhubj8)}(hstruct kvm_ioeventfd { __u64 datamatch; __u64 addr; /* legal pio/mmio address */ __u32 len; /* 0, 1, 2, 4, or 8 bytes */ __s32 fd; __u32 flags; __u8 pad[36]; };h]hstruct kvm_ioeventfd { __u64 datamatch; __u64 addr; /* legal pio/mmio address */ __u32 len; /* 0, 1, 2, 4, or 8 bytes */ __s32 fd; __u32 flags; __u8 pad[36]; };}hjTsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMEhjShhubh)}(hsFor the special case of virtio-ccw devices on s390, the ioevent is matched to a subchannel/virtqueue tuple instead.h]hsFor the special case of virtio-ccw devices on s390, the ioevent is matched to a subchannel/virtqueue tuple instead.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjShhubh)}(h!The following flags are defined::h]h The following flags are defined:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjShhubj8)}(hX@#define KVM_IOEVENTFD_FLAG_DATAMATCH (1 << kvm_ioeventfd_flag_nr_datamatch) #define KVM_IOEVENTFD_FLAG_PIO (1 << kvm_ioeventfd_flag_nr_pio) #define KVM_IOEVENTFD_FLAG_DEASSIGN (1 << kvm_ioeventfd_flag_nr_deassign) #define KVM_IOEVENTFD_FLAG_VIRTIO_CCW_NOTIFY \ (1 << kvm_ioeventfd_flag_nr_virtio_ccw_notify)h]hX@#define KVM_IOEVENTFD_FLAG_DATAMATCH (1 << kvm_ioeventfd_flag_nr_datamatch) #define KVM_IOEVENTFD_FLAG_PIO (1 << kvm_ioeventfd_flag_nr_pio) #define KVM_IOEVENTFD_FLAG_DEASSIGN (1 << kvm_ioeventfd_flag_nr_deassign) #define KVM_IOEVENTFD_FLAG_VIRTIO_CCW_NOTIFY \ (1 << kvm_ioeventfd_flag_nr_virtio_ccw_notify)}hjUsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMShjShhubh)}(hIf datamatch flag is set, the event will be signaled only if the written value to the registered address is equal to datamatch in struct kvm_ioeventfd.h]hIf datamatch flag is set, the event will be signaled only if the written value to the registered address is equal to datamatch in struct kvm_ioeventfd.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjShhubh)}(hZFor virtio-ccw devices, addr contains the subchannel id and datamatch the virtqueue index.h]hZFor virtio-ccw devices, addr contains the subchannel id and datamatch the virtqueue index.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjShhubh)}(hWith KVM_CAP_IOEVENTFD_ANY_LENGTH, a zero length ioeventfd is allowed, and the kernel will ignore the length of guest write and may get a faster vmexit. The speedup may only apply to specific architectures, but the ioeventfd will work anyway.h]hWith KVM_CAP_IOEVENTFD_ANY_LENGTH, a zero length ioeventfd is allowed, and the kernel will ignore the length of guest write and may get a faster vmexit. The speedup may only apply to specific architectures, but the ioeventfd will work anyway.}(hj+UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hjShhubeh}(h] kvm-ioeventfdah ]h"]4.59 kvm_ioeventfdah$]h&]uh1hhjhhhhhM7ubh)}(hhh](h)}(h4.60 KVM_DIRTY_TLBh]h4.60 KVM_DIRTY_TLB}(hjDUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAUhhhhhMeubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjXUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUUhhhKubj)}(hKVM_CAP_SW_TLBh]h)}(hjhUh]hKVM_CAP_SW_TLB}(hjjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjfUubah}(h]h ]h"]h$]h&]uh1jhjUUubeh}(h]h ]h"]h$]h&]uh1jwhhhMghjRUhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hppch]h)}(hjUh]hppc}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhMhhjRUhhubjx)}(hhh](j})}(hTypeh]hType}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(h vcpu ioctlh]h)}(hjUh]h vcpu ioctl}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhMihjRUhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hstruct kvm_dirty_tlb (in)h]h)}(hjUh]hstruct kvm_dirty_tlb (in)}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhMjhjRUhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj VhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj"VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjVubah}(h]h ]h"]h$]h&]uh1jhj Vubeh}(h]h ]h"]h$]h&]uh1jwhhhMkhjRUhhubeh}(h]h ]h"]h$]h&]uh1jrhjAUhhhhhMgubj8)}(hDstruct kvm_dirty_tlb { __u64 bitmap; __u32 num_dirty; };h]hDstruct kvm_dirty_tlb { __u64 bitmap; __u32 num_dirty; };}hjBVsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMohjAUhhubh)}(hThis must be called whenever userspace has changed an entry in the shared TLB, prior to calling KVM_RUN on the associated vcpu.h]hThis must be called whenever userspace has changed an entry in the shared TLB, prior to calling KVM_RUN on the associated vcpu.}(hjPVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjAUhhubh)}(hXThe "bitmap" field is the userspace address of an array. This array consists of a number of bits, equal to the total number of TLB entries as determined by the last successful call to ``KVM_ENABLE_CAP(KVM_CAP_SW_TLB)``, rounded up to the nearest multiple of 64.h](hThe “bitmap” field is the userspace address of an array. This array consists of a number of bits, equal to the total number of TLB entries as determined by the last successful call to }(hj^VhhhNhNubj)}(h"``KVM_ENABLE_CAP(KVM_CAP_SW_TLB)``h]hKVM_ENABLE_CAP(KVM_CAP_SW_TLB)}(hjfVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj^Vubh+, rounded up to the nearest multiple of 64.}(hj^VhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMwhjAUhhubh)}(hSEach bit corresponds to one TLB entry, ordered the same as in the shared TLB array.h]hSEach bit corresponds to one TLB entry, ordered the same as in the shared TLB array.}(hj~VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjAUhhubh)}(hThe array is little-endian: the bit 0 is the least significant bit of the first byte, bit 8 is the least significant bit of the second byte, etc. This avoids any complications with differing word sizes.h]hThe array is little-endian: the bit 0 is the least significant bit of the first byte, bit 8 is the least significant bit of the second byte, etc. This avoids any complications with differing word sizes.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAUhhubh)}(hThe "num_dirty" field is a performance hint for KVM to determine whether it should skip processing the bitmap and just invalidate everything. It must be set to the number of set bits in the bitmap.h]hThe “num_dirty” field is a performance hint for KVM to determine whether it should skip processing the bitmap and just invalidate everything. It must be set to the number of set bits in the bitmap.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAUhhubeh}(h] kvm-dirty-tlbah ]h"]4.60 kvm_dirty_tlbah$]h&]uh1hhjhhhhhMeubh)}(hhh](h)}(h4.62 KVM_CREATE_SPAPR_TCEh]h4.62 KVM_CREATE_SPAPR_TCE}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjVhhhKubj)}(hKVM_CAP_SPAPR_TCEh]h)}(hjVh]hKVM_CAP_SPAPR_TCE}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjVhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjVhhhKubj)}(hpowerpch]h)}(hjWh]hpowerpc}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjVhhubjx)}(hhh](j})}(hTypeh]hType}(hj#WhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj WhhhKubj)}(hvm ioctlh]h)}(hj3Wh]hvm ioctl}(hj5WhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj1Wubah}(h]h ]h"]h$]h&]uh1jhj Wubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjVhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjQWhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjNWhhhKubj)}(h struct kvm_create_spapr_tce (in)h]h)}(hjaWh]h struct kvm_create_spapr_tce (in)}(hjcWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_Wubah}(h]h ]h"]h$]h&]uh1jhjNWubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjVhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj|WhhhKubj)}(h7file descriptor for manipulating the created TCE table h]h)}(h6file descriptor for manipulating the created TCE tableh]h6file descriptor for manipulating the created TCE table}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubah}(h]h ]h"]h$]h&]uh1jhj|Wubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjVhhubeh}(h]h ]h"]h$]h&]uh1jrhjVhhhhhMubh)}(hXThis creates a virtual TCE (translation control entry) table, which is an IOMMU for PAPR-style virtual I/O. It is used to translate logical addresses used in virtual I/O into guest physical addresses, and provides a scatter/gather capability for PAPR virtual I/O.h]hXThis creates a virtual TCE (translation control entry) table, which is an IOMMU for PAPR-style virtual I/O. It is used to translate logical addresses used in virtual I/O into guest physical addresses, and provides a scatter/gather capability for PAPR virtual I/O.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubj8)}(hh/* for KVM_CAP_SPAPR_TCE */ struct kvm_create_spapr_tce { __u64 liobn; __u32 window_size; };h]hh/* for KVM_CAP_SPAPR_TCE */ struct kvm_create_spapr_tce { __u64 liobn; __u32 window_size; };}hjWsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjVhhubh)}(hXThe liobn field gives the logical IO bus number for which to create a TCE table. The window_size field specifies the size of the DMA window which this TCE table will translate - the table will contain one 64 bit TCE entry for every 4kiB of the DMA window.h]hXThe liobn field gives the logical IO bus number for which to create a TCE table. The window_size field specifies the size of the DMA window which this TCE table will translate - the table will contain one 64 bit TCE entry for every 4kiB of the DMA window.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubh)}(hXWhen the guest issues an H_PUT_TCE hcall on a liobn for which a TCE table has been created using this ioctl(), the kernel will handle it in real mode, updating the TCE table. H_PUT_TCE calls for other liobns will cause a vm exit and must be handled by userspace.h]hXWhen the guest issues an H_PUT_TCE hcall on a liobn for which a TCE table has been created using this ioctl(), the kernel will handle it in real mode, updating the TCE table. H_PUT_TCE calls for other liobns will cause a vm exit and must be handled by userspace.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubh)}(hXThe return value is a file descriptor which can be passed to mmap(2) to map the created TCE table into userspace. This lets userspace read the entries written by kernel-handled H_PUT_TCE calls, and also lets userspace update the TCE table directly which is useful in some circumstances.h]hXThe return value is a file descriptor which can be passed to mmap(2) to map the created TCE table into userspace. This lets userspace read the entries written by kernel-handled H_PUT_TCE calls, and also lets userspace update the TCE table directly which is useful in some circumstances.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubeh}(h]kvm-create-spapr-tceah ]h"]4.62 kvm_create_spapr_tceah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h 4.64 KVM_NMIh]h 4.64 KVM_NMI}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(hKVM_CAP_USER_NMIh]h)}(hj&Xh]hKVM_CAP_USER_NMI}(hj(XhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$Xubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjXhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjDXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAXhhhKubj)}(hx86h]h)}(hjTXh]hx86}(hjVXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRXubah}(h]h ]h"]h$]h&]uh1jhjAXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjXhhubjx)}(hhh](j})}(hTypeh]hType}(hjrXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjoXhhhKubj)}(h vcpu ioctlh]h)}(hjXh]h vcpu ioctl}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjoXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjXhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(hnoneh]h)}(hjXh]hnone}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjXhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjXhhubeh}(h]h ]h"]h$]h&]uh1jrhjWhhhhhMubh)}(hX$Queues an NMI on the thread's vcpu. Note this is well defined only when KVM_CREATE_IRQCHIP has not been called, since this is an interface between the virtual cpu core and virtual local APIC. After KVM_CREATE_IRQCHIP has been called, this interface is completely emulated within the kernel.h]hX&Queues an NMI on the thread’s vcpu. Note this is well defined only when KVM_CREATE_IRQCHIP has not been called, since this is an interface between the virtual cpu core and virtual local APIC. After KVM_CREATE_IRQCHIP has been called, this interface is completely emulated within the kernel.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubh)}(h\To use this to emulate the LINT1 input with KVM_CREATE_IRQCHIP, use the following algorithm:h]h\To use this to emulate the LINT1 input with KVM_CREATE_IRQCHIP, use the following algorithm:}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubj )}(h- pause the vcpu - read the local APIC's state (KVM_GET_LAPIC) - check whether changing LINT1 will queue an NMI (see the LVT entry for LINT1) - if so, issue KVM_NMI - resume the vcpu h]j)}(hhh](j)}(hpause the vcpuh]h)}(hj%Yh]hpause the vcpu}(hj'YhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#Yubah}(h]h ]h"]h$]h&]uh1jhj Yubj)}(h+read the local APIC's state (KVM_GET_LAPIC)h]h)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:Yubah}(h]h ]h"]h$]h&]uh1jhj Yubj)}(hLcheck whether changing LINT1 will queue an NMI (see the LVT entry for LINT1)h]h)}(hjSYh]hLcheck whether changing LINT1 will queue an NMI (see the LVT entry for LINT1)}(hjUYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQYubah}(h]h ]h"]h$]h&]uh1jhj Yubj)}(hif so, issue KVM_NMIh]h)}(hjjYh]hif so, issue KVM_NMI}(hjlYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhYubah}(h]h ]h"]h$]h&]uh1jhj Yubj)}(hresume the vcpu h]h)}(hresume the vcpuh]hresume the vcpu}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhj Yubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjYubah}(h]h ]h"]h$]h&]uh1j hhhMhjWhhubh)}(hPSome guests configure the LINT1 NMI input to cause a panic, aiding in debugging.h]hPSome guests configure the LINT1 NMI input to cause a panic, aiding in debugging.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWhhubeh}(h]kvm-nmiah ]h"] 4.64 kvm_nmiah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.65 KVM_S390_UCAS_MAPh]h4.65 KVM_S390_UCAS_MAP}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hKVM_CAP_S390_UCONTROLh]h)}(hjYh]hKVM_CAP_S390_UCONTROL}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjYhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hs390h]h)}(hjZh]hs390}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj Zubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjYhhubjx)}(hhh](j})}(hTypeh]hType}(hj,ZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)ZhhhKubj)}(h vcpu ioctlh]h)}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:Zubah}(h]h ]h"]h$]h&]uh1jhj)Zubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjYhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjZZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjWZhhhKubj)}(h!struct kvm_s390_ucas_mapping (in)h]h)}(hjjZh]h!struct kvm_s390_ucas_mapping (in)}(hjlZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhZubah}(h]h ]h"]h$]h&]uh1jhjWZubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjYhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjZhhhKubj)}(h0 in case of success h]h)}(h0 in case of successh]h0 in case of success}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjYhhubeh}(h]h ]h"]h$]h&]uh1jrhjYhhhhhMubh)}(h$The parameter is defined like this::h]h#The parameter is defined like this:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(histruct kvm_s390_ucas_mapping { __u64 user_addr; __u64 vcpu_addr; __u64 length; };h]histruct kvm_s390_ucas_mapping { __u64 user_addr; __u64 vcpu_addr; __u64 length; };}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hThis ioctl maps the memory at "user_addr" with the length "length" to the vcpu's address space starting at "vcpu_addr". All parameters need to be aligned by 1 megabyte.h]hThis ioctl maps the memory at “user_addr” with the length “length” to the vcpu’s address space starting at “vcpu_addr”. All parameters need to be aligned by 1 megabyte.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubeh}(h]kvm-s390-ucas-mapah ]h"]4.65 kvm_s390_ucas_mapah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.66 KVM_S390_UCAS_UNMAPh]h4.66 KVM_S390_UCAS_UNMAP}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj[hhhKubj)}(hKVM_CAP_S390_UCONTROLh]h)}(hj[h]hKVM_CAP_S390_UCONTROL}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj1[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.[hhhKubj)}(hs390h]h)}(hjA[h]hs390}(hjC[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj?[ubah}(h]h ]h"]h$]h&]uh1jhj.[ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZhhubjx)}(hhh](j})}(hTypeh]hType}(hj_[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj\[hhhKubj)}(h vcpu ioctlh]h)}(hjo[h]h vcpu ioctl}(hjq[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjm[ubah}(h]h ]h"]h$]h&]uh1jhj\[ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj[hhhKubj)}(h!struct kvm_s390_ucas_mapping (in)h]h)}(hj[h]h!struct kvm_s390_ucas_mapping (in)}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj[hhhKubj)}(h0 in case of success h]h)}(h0 in case of successh]h0 in case of success}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZhhubeh}(h]h ]h"]h$]h&]uh1jrhjZhhhhhMubh)}(h$The parameter is defined like this::h]h#The parameter is defined like this:}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZhhubj8)}(histruct kvm_s390_ucas_mapping { __u64 user_addr; __u64 vcpu_addr; __u64 length; };h]histruct kvm_s390_ucas_mapping { __u64 user_addr; __u64 vcpu_addr; __u64 length; };}hj[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjZhhubh)}(hThis ioctl unmaps the memory in the vcpu's address space starting at "vcpu_addr" with the length "length". The field "user_addr" is ignored. All parameters need to be aligned by 1 megabyte.h]hThis ioctl unmaps the memory in the vcpu’s address space starting at “vcpu_addr” with the length “length”. The field “user_addr” is ignored. All parameters need to be aligned by 1 megabyte.}(hj \hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjZhhubeh}(h]kvm-s390-ucas-unmapah ]h"]4.66 kvm_s390_ucas_unmapah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.67 KVM_S390_VCPU_FAULTh]h4.67 KVM_S390_VCPU_FAULT}(hj"\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj6\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj3\hhhKubj)}(hKVM_CAP_S390_UCONTROLh]h)}(hjF\h]hKVM_CAP_S390_UCONTROL}(hjH\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjD\ubah}(h]h ]h"]h$]h&]uh1jhj3\ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj0\hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjd\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hja\hhhKubj)}(hs390h]h)}(hjt\h]hs390}(hjv\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjr\ubah}(h]h ]h"]h$]h&]uh1jhja\ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj0\hhubjx)}(hhh](j})}(hTypeh]hType}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj\hhhKubj)}(h vcpu ioctlh]h)}(hj\h]h vcpu ioctl}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj0\hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj\hhhKubj)}(hvcpu absolute address (in)h]h)}(hj\h]hvcpu absolute address (in)}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj0\hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj\hhhKubj)}(h0 in case of success h]h)}(h0 in case of successh]h0 in case of success}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj0\hhubeh}(h]h ]h"]h$]h&]uh1jrhj\hhhhhMubh)}(hXThis call creates a page table entry on the virtual cpu's address space (for user controlled virtual machines) or the virtual machine's address space (for regular virtual machines). This only works for minor faults, thus it's recommended to access subject memory page via the user page table upfront. This is useful to handle validity intercepts for user controlled virtual machines to fault in the virtual cpu's lowcore pages prior to calling the KVM_RUN ioctl.h]hXThis call creates a page table entry on the virtual cpu’s address space (for user controlled virtual machines) or the virtual machine’s address space (for regular virtual machines). This only works for minor faults, thus it’s recommended to access subject memory page via the user page table upfront. This is useful to handle validity intercepts for user controlled virtual machines to fault in the virtual cpu’s lowcore pages prior to calling the KVM_RUN ioctl.}(hj ]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\hhubeh}(h]kvm-s390-vcpu-faultah ]h"]4.67 kvm_s390_vcpu_faultah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.68 KVM_SET_ONE_REGh]h4.68 KVM_SET_ONE_REG}(hj9]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6]hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjM]hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJ]hhhKubj)}(hKVM_CAP_ONE_REGh]h)}(hj]]h]hKVM_CAP_ONE_REG}(hj_]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj[]ubah}(h]h ]h"]h$]h&]uh1jhjJ]ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjG]hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj{]hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjx]hhhKubj)}(hallh]h)}(hj]h]hall}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubah}(h]h ]h"]h$]h&]uh1jhjx]ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjG]hhubjx)}(hhh](j})}(hTypeh]hType}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj]hhhKubj)}(h vcpu ioctlh]h)}(hj]h]h vcpu ioctl}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjG]hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj]hhhKubj)}(hstruct kvm_one_reg (in)h]h)}(hj]h]hstruct kvm_one_reg (in)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjG]hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^hhhKubj)}(h(0 on success, negative value on failure h]h)}(h'0 on success, negative value on failureh]h'0 on success, negative value on failure}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjG]hhubeh}(h]h ]h"]h$]h&]uh1jrhj6]hhhhhM ubh)}(hErrors:h]hErrors:}(hj7^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj )}(hX====== ============================================================ ENOENT no such register EINVAL invalid register ID, or no such register or used with VMs in protected virtualization mode on s390 EPERM (arm64) register access not allowed before vcpu finalization EBUSY (riscv) changing register value not allowed after the vcpu has run at least once ====== ============================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjL^ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK hjdubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]h)}(hKVM_REG_PPC_AMRh]hKVM_REG_PPC_AMR}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM> hjdubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]h)}(h64h]h64}(hj3dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM> hj0dubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjSdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM? hjPdubah}(h]h ]h"]h$]h&]uh1jhjMdubj)}(hhh]h)}(hKVM_REG_PPC_UAMORh]hKVM_REG_PPC_UAMOR}(hjjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM? hjgdubah}(h]h ]h"]h$]h&]uh1jhjMdubj)}(hhh]h)}(h64h]h64}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM? hj~dubah}(h]h ]h"]h$]h&]uh1jhjMdubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@ hjdubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(hKVM_REG_PPC_MMCR0h]hKVM_REG_PPC_MMCR0}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@ hjdubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(h64h]h64}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@ hjdubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMA hjdubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(hKVM_REG_PPC_MMCR1h]hKVM_REG_PPC_MMCR1}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMA hjeubah}(h]h ]h"]h$]h&]uh1jhjdubj)}(hhh]h)}(h64h]h64}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMA hjeubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj=ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMB hj:eubah}(h]h ]h"]h$]h&]uh1jhj7eubj)}(hhh]h)}(hKVM_REG_PPC_MMCRAh]hKVM_REG_PPC_MMCRA}(hjTehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMB hjQeubah}(h]h ]h"]h$]h&]uh1jhj7eubj)}(hhh]h)}(h64h]h64}(hjkehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMB hjheubah}(h]h ]h"]h$]h&]uh1jhj7eubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC hjeubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hKVM_REG_PPC_MMCR2h]hKVM_REG_PPC_MMCR2}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC hjeubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h64h]h64}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC hjeubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMD hjeubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hKVM_REG_PPC_MMCRSh]hKVM_REG_PPC_MMCRS}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMD hjeubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h64h]h64}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMD hjfubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj'fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhME hj$fubah}(h]h ]h"]h$]h&]uh1jhj!fubj)}(hhh]h)}(hKVM_REG_PPC_MMCR3h]hKVM_REG_PPC_MMCR3}(hj>fhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhME hj;fubah}(h]h ]h"]h$]h&]uh1jhj!fubj)}(hhh]h)}(h64h]h64}(hjUfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhME hjRfubah}(h]h ]h"]h$]h&]uh1jhj!fubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjufhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMF hjrfubah}(h]h ]h"]h$]h&]uh1jhjofubj)}(hhh]h)}(hKVM_REG_PPC_SIARh]hKVM_REG_PPC_SIAR}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMF hjfubah}(h]h ]h"]h$]h&]uh1jhjofubj)}(hhh]h)}(h64h]h64}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMF hjfubah}(h]h ]h"]h$]h&]uh1jhjofubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMG hjfubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(hKVM_REG_PPC_SDARh]hKVM_REG_PPC_SDAR}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMG hjfubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(h64h]h64}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMG hjfubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hjgubah}(h]h ]h"]h$]h&]uh1jhj gubj)}(hhh]h)}(hKVM_REG_PPC_SIERh]hKVM_REG_PPC_SIER}(hj(ghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hj%gubah}(h]h ]h"]h$]h&]uh1jhj gubj)}(hhh]h)}(h64h]h64}(hj?ghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj;{ubah}(h]h ]h"]h$]h&]uh1jhj!{ubj)}(hhh]h)}(h64h]h64}(hjU{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjR{ubah}(h]h ]h"]h$]h&]uh1jhj!{ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hju{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjr{ubah}(h]h ]h"]h$]h&]uh1jhjo{ubj)}(hhh]h)}(hKVM_REG_PPC_CSIGRh]hKVM_REG_PPC_CSIGR}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj{ubah}(h]h ]h"]h$]h&]uh1jhjo{ubj)}(hhh]h)}(h64h]h64}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj{ubah}(h]h ]h"]h$]h&]uh1jhjo{ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(hKVM_REG_PPC_TACRh]hKVM_REG_PPC_TACR}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(h64h]h64}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj{ubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhj |ubj)}(hhh]h)}(hKVM_REG_PPC_TCSCRh]hKVM_REG_PPC_TCSCR}(hj(|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj%|ubah}(h]h ]h"]h$]h&]uh1jhj |ubj)}(hhh]h)}(h64h]h64}(hj?|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<|ubah}(h]h ]h"]h$]h&]uh1jhj |ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj_|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj\|ubah}(h]h ]h"]h$]h&]uh1jhjY|ubj)}(hhh]h)}(hKVM_REG_PPC_PIDh]hKVM_REG_PPC_PID}(hjv|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjs|ubah}(h]h ]h"]h$]h&]uh1jhjY|ubj)}(hhh]h)}(h64h]h64}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhjY|ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hKVM_REG_PPC_ACOPh]hKVM_REG_PPC_ACOP}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(h64h]h64}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hKVM_REG_PPC_VRSAVEh]hKVM_REG_PPC_VRSAVE}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(h32h]h32}(hj)}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj&}ubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjI}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjF}ubah}(h]h ]h"]h$]h&]uh1jhjC}ubj)}(hhh]h)}(hKVM_REG_PPC_LPCRh]hKVM_REG_PPC_LPCR}(hj`}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]}ubah}(h]h ]h"]h$]h&]uh1jhjC}ubj)}(hhh]h)}(h32h]h32}(hjw}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjt}ubah}(h]h ]h"]h$]h&]uh1jhjC}ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hKVM_REG_PPC_LPCR_64h]hKVM_REG_PPC_LPCR_64}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(h64h]h64}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hKVM_REG_PPC_PPRh]hKVM_REG_PPC_PPR}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(h64h]h64}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj3~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj0~ubah}(h]h ]h"]h$]h&]uh1jhj-~ubj)}(hhh]h)}(hKVM_REG_PPC_ARCH_COMPATh]hKVM_REG_PPC_ARCH_COMPAT}(hjJ~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjG~ubah}(h]h ]h"]h$]h&]uh1jhj-~ubj)}(hhh]h)}(h32h]h32}(hja~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^~ubah}(h]h ]h"]h$]h&]uh1jhj-~ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~~ubah}(h]h ]h"]h$]h&]uh1jhj{~ubj)}(hhh]h)}(hKVM_REG_PPC_DABRXh]hKVM_REG_PPC_DABRX}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj{~ubj)}(hhh]h)}(h32h]h32}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj{~ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh]h)}(hKVM_REG_PPC_WORTh]hKVM_REG_PPC_WORT}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubj)}(hhh]h)}(h64h]h64}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_SPRG9h]hKVM_REG_PPC_SPRG9}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj1ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hKVM_REG_PPC_DBSRh]hKVM_REG_PPC_DBSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TIDRh]hKVM_REG_PPC_TIDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_PSSCRh]hKVM_REG_PPC_PSSCR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(hKVM_REG_PPC_DEC_EXPIRYh]hKVM_REG_PPC_DEC_EXPIRY}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjiubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_PTCRh]hKVM_REG_PPC_PTCR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjрhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj΀ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_HASHKEYRh]hKVM_REG_PPC_HASHKEYR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(hKVM_REG_PPC_HASHPKEYRh]hKVM_REG_PPC_HASHPKEYR}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjSubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(h64h]h64}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_DAWR1h]hKVM_REG_PPC_DAWR1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjہhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj؁ubah}(h]h ]h"]h$]h&]uh1jhjՁubj)}(hhh]h)}(hKVM_REG_PPC_DAWRX1h]hKVM_REG_PPC_DAWRX1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjՁubj)}(hhh]h)}(h64h]h64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjՁubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj&ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(hKVM_REG_PPC_DEXCRh]hKVM_REG_PPC_DEXCR}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(h64h]h64}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjTubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hKVM_REG_PPC_TM_GPR0h]hKVM_REG_PPC_TM_GPR0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjłhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj‚ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_GPR31h]hKVM_REG_PPC_TM_GPR31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(hKVM_REG_PPC_TM_VSR0h]hKVM_REG_PPC_TM_VSR0}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjYubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(h128h]h128}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjpubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjŃhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjƒubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_VSR63h]hKVM_REG_PPC_TM_VSR63}(hj܃hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjكubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h128h]h128}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hKVM_REG_PPC_TM_CRh]hKVM_REG_PPC_TM_CR}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj'ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h64h]h64}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj>ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hKVM_REG_PPC_TM_LRh]hKVM_REG_PPC_TM_LR}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjuubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_CTRh]hKVM_REG_PPC_TM_CTR}(hjƄhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjÄubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj݄hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjڄubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_FPSCRh]hKVM_REG_PPC_TM_FPSCR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hKVM_REG_PPC_TM_AMRh]hKVM_REG_PPC_TM_AMR}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj_ubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(h64h]h64}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjvubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_PPRh]hKVM_REG_PPC_TM_PPR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjDžhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjąubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_VRSAVEh]hKVM_REG_PPC_TM_VRSAVE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]h)}(hKVM_REG_PPC_TM_VSCRh]hKVM_REG_PPC_TM_VSCR}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjIubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]h)}(h32h]h32}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hKVM_REG_PPC_TM_DSCRh]hKVM_REG_PPC_TM_DSCR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjцhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjΆubah}(h]h ]h"]h$]h&]uh1jhjˆubj)}(hhh]h)}(hKVM_REG_PPC_TM_TARh]hKVM_REG_PPC_TM_TAR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjˆubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjˆubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hPPCh]hPPC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_PPC_TM_XERh]hKVM_REG_PPC_TM_XER}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj3ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(hKVM_REG_MIPS_R0h]hKVM_REG_MIPS_R0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_R31h]hKVM_REG_MIPS_R31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj8ubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(hKVM_REG_MIPS_HIh]hKVM_REG_MIPS_HI}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjOubah}(h]h ]h"]h$]h&]uh1jhj5ubj)}(hhh]h)}(h64h]h64}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjfubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_LOh]hKVM_REG_MIPS_LO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj׈hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjԈubah}(h]h ]h"]h$]h&]uh1jhjшubj)}(hhh]h)}(hKVM_REG_MIPS_PCh]hKVM_REG_MIPS_PC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjшubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjшubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_INDEXh]hKVM_REG_MIPS_CP0_INDEX}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj9ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjpubah}(h]h ]h"]h$]h&]uh1jhjmubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_ENTRYLO0h]hKVM_REG_MIPS_CP0_ENTRYLO0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjmubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjmubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_ENTRYLO1h]hKVM_REG_MIPS_CP0_ENTRYLO1}(hj؉hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjՉubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONTEXTh]hKVM_REG_MIPS_CP0_CONTEXT}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj#ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h64h]h64}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj:ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjZubah}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONTEXTCONFIGh]hKVM_REG_MIPS_CP0_CONTEXTCONFIG}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjqubah}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_USERLOCALh]hKVM_REG_MIPS_CP0_USERLOCAL}(hjŠhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjيhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj֊ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_XCONTEXTCONFIGh]hKVM_REG_MIPS_CP0_XCONTEXTCONFIG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjDubah}(h]h ]h"]h$]h&]uh1jhjAubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PAGEMASKh]hKVM_REG_MIPS_CP0_PAGEMASK}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj[ubah}(h]h ]h"]h$]h&]uh1jhjAubj)}(hhh]h)}(h32h]h32}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjrubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PAGEGRAINh]hKVM_REG_MIPS_CP0_PAGEGRAIN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjËhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj݋ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_SEGCTL0h]hKVM_REG_MIPS_CP0_SEGCTL0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj݋ubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj݋ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj.ubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_SEGCTL1h]hKVM_REG_MIPS_CP0_SEGCTL1}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjEubah}(h]h ]h"]h$]h&]uh1jhj+ubj)}(hhh]h)}(h64h]h64}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj\ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhjyubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_SEGCTL2h]hKVM_REG_MIPS_CP0_SEGCTL2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjyubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj͌hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjʌubah}(h]h ]h"]h$]h&]uh1jhjnjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PWBASEh]hKVM_REG_MIPS_CP0_PWBASE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjnjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjnjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PWFIELDh]hKVM_REG_MIPS_CP0_PWFIELD}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj/ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjFubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjfubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PWSIZEh]hKVM_REG_MIPS_CP0_PWSIZE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj}ubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_WIREDh]hKVM_REG_MIPS_CP0_WIRED}(hj΍hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjˍubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PWCTLh]hKVM_REG_MIPS_CP0_PWCTL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_HWRENAh]hKVM_REG_MIPS_CP0_HWRENA}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjgubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_BADVADDRh]hKVM_REG_MIPS_CP0_BADVADDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjώhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj̎ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_BADINSTRh]hKVM_REG_MIPS_CP0_BADINSTR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj:ubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_BADINSTRPh]hKVM_REG_MIPS_CP0_BADINSTRP}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjQubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]h)}(h32h]h32}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_COUNTh]hKVM_REG_MIPS_CP0_COUNT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjُhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj֏ubah}(h]h ]h"]h$]h&]uh1jhjӏubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_ENTRYHIh]hKVM_REG_MIPS_CP0_ENTRYHI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjӏubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjӏubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_COMPAREh]hKVM_REG_MIPS_CP0_COMPARE}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj;ubah}(h]h ]h"]h$]h&]uh1jhj!ubj)}(hhh]h)}(h32h]h32}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjrubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_STATUSh]hKVM_REG_MIPS_CP0_STATUS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjÐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_INTCTLh]hKVM_REG_MIPS_CP0_INTCTL}(hjڐhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjאubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CAUSEh]hKVM_REG_MIPS_CP0_CAUSE}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj%ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h32h]h32}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj\ubah}(h]h ]h"]h$]h&]uh1jhjYubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_EPCh]hKVM_REG_MIPS_CP0_EPC}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjsubah}(h]h ]h"]h$]h&]uh1jhjYubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_PRIDh]hKVM_REG_MIPS_CP0_PRID}(hjđhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjۑhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjؑubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_EBASEh]hKVM_REG_MIPS_CP0_EBASE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjFubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIGh]hKVM_REG_MIPS_CP0_CONFIG}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(h32h]h32}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjtubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG1h]hKVM_REG_MIPS_CP0_CONFIG1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjŒhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj’ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjߒubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG2h]hKVM_REG_MIPS_CP0_CONFIG2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjߒubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjߒubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj0ubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG3h]hKVM_REG_MIPS_CP0_CONFIG3}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjGubah}(h]h ]h"]h$]h&]uh1jhj-ubj)}(hhh]h)}(h32h]h32}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj-ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj~ubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG4h]hKVM_REG_MIPS_CP0_CONFIG4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj{ubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjϓhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj̓ubah}(h]h ]h"]h$]h&]uh1jhjɓubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG5h]hKVM_REG_MIPS_CP0_CONFIG5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjɓubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjɓubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_CONFIG7h]hKVM_REG_MIPS_CP0_CONFIG7}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj1ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_XCONTEXTh]hKVM_REG_MIPS_CP0_XCONTEXT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_ERROREPCh]hKVM_REG_MIPS_CP0_ERROREPC}(hjДhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj͔ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH1h]hKVM_REG_MIPS_CP0_KSCRATCH1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH2h]hKVM_REG_MIPS_CP0_KSCRATCH2}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjiubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH3h]hKVM_REG_MIPS_CP0_KSCRATCH3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjѕhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjΕubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH4h]hKVM_REG_MIPS_CP0_KSCRATCH4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH5h]hKVM_REG_MIPS_CP0_KSCRATCH5}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjSubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(h64h]h64}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_KSCRATCH6h]hKVM_REG_MIPS_CP0_KSCRATCH6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjۖhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjؖubah}(h]h ]h"]h$]h&]uh1jhjՖubj)}(hhh]h)}(hKVM_REG_MIPS_CP0_MAAR(0..63)h]hKVM_REG_MIPS_CP0_MAAR(0..63)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjՖubj)}(hhh]h)}(h64h]h64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjՖubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj&ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(hKVM_REG_MIPS_COUNT_CTLh]hKVM_REG_MIPS_COUNT_CTL}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(h64h]h64}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjTubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hKVM_REG_MIPS_COUNT_RESUMEh]hKVM_REG_MIPS_COUNT_RESUME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjŗhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj—ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_COUNT_HZh]hKVM_REG_MIPS_COUNT_HZ}(hjܗhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjٗubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hKVM_REG_MIPS_FPR_32(0..31)h]hKVM_REG_MIPS_FPR_32(0..31)}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj'ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(h32h]h32}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj>ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hKVM_REG_MIPS_FPR_64(0..31)h]hKVM_REG_MIPS_FPR_64(0..31)}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjuubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_VEC_128(0..31)h]hKVM_REG_MIPS_VEC_128(0..31)}(hjƘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjØubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h128h]h128}(hjݘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjژubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_FCR_IRh]hKVM_REG_MIPS_FCR_IR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hKVM_REG_MIPS_FCR_CSRh]hKVM_REG_MIPS_FCR_CSR}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj_ubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(h32h]h32}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjvubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_MSA_IRh]hKVM_REG_MIPS_MSA_IR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjǙhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjęubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubj)}(hhh](j)}(hhh]h)}(hMIPSh]hMIPS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hKVM_REG_MIPS_MSA_CSRh]hKVM_REG_MIPS_MSA_CSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj`ubeh}(h]h ]h"]h$]h&]uh1jyhj_ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj_ubah}(h]h ]h"]h$]h&]uh1jYhj_ubah}(h]h ]h"]h$]h&]uh1j hhhM. hj6]hhubh)}(hzARM registers are mapped using the lower 32 bits. The upper 16 of that is the register group type, or coprocessor number:h]hzARM registers are mapped using the lower 32 bits. The upper 16 of that is the register group type, or coprocessor number:}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(h7ARM core registers have the following id bit patterns::h]h6ARM core registers have the following id bit patterns:}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h40x4020 0000 0010 h]h40x4020 0000 0010 }hjdsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h>ARM 32-bit CP15 registers have the following id bit patterns::h]h=ARM 32-bit CP15 registers have the following id bit patterns:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h;0x4020 0000 000F h]h;0x4020 0000 000F }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h>ARM 64-bit CP15 registers have the following id bit patterns::h]h=ARM 64-bit CP15 registers have the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h<0x4030 0000 000F h]h<0x4030 0000 000F }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h8ARM CCSIDR registers are demultiplexed by CSSELR value::h]h7ARM CCSIDR registers are demultiplexed by CSSELR value:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x4020 0000 0011 00 h]h0x4020 0000 0011 00 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hEARM 32-bit VFP control registers have the following id bit patterns::h]hDARM 32-bit VFP control registers have the following id bit patterns:}(hjƚhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x4020 0000 0012 1 h]h0x4020 0000 0012 1 }hjԚsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hh]h0x4030 0000 0012 0 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h>ARM firmware pseudo-registers have the following bit pattern::h]h=ARM firmware pseudo-registers have the following bit pattern:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x4030 0000 0014 h]h0x4030 0000 0014 }hj sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h{arm64 registers are mapped using the lower 32 bits. The upper 16 of that is the register group type, or coprocessor number:h]h{arm64 registers are mapped using the lower 32 bits. The upper 16 of that is the register group type, or coprocessor number:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hXarm64 core/FP-SIMD registers have the following id bit patterns. Note that the size of the access is variable, as the kvm_regs structure contains elements ranging from 32 to 128 bits. The index is a 32bit value in the kvm_regs structure seen as a 32bit array::h]hXarm64 core/FP-SIMD registers have the following id bit patterns. Note that the size of the access is variable, as the kvm_regs structure contains elements ranging from 32 to 128 bits. The index is a 32bit value in the kvm_regs structure seen as a 32bit array:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h40x60x0 0000 0010 h]h40x60x0 0000 0010 }hj6sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h Specifically:h]h Specifically:}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjUubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjUubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjUubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK'uh1jchjUubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM" hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM" hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hBitsh]hBits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM" hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hkvm_regs memberh]hkvm_regs member}(hjΛhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM" hj˛ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1j_hjUubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0000h]h0x6030 0000 0010 0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hX0h]hX0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$ hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$ hj"ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h regs.regs[0]h]h regs.regs[0]}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$ hj9ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0002h]h0x6030 0000 0010 0002}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjYubah}(h]h ]h"]h$]h&]uh1jhjVubj)}(hhh]h)}(hX1h]hX1}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjpubah}(h]h ]h"]h$]h&]uh1jhjVubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjubah}(h]h ]h"]h$]h&]uh1jhjVubj)}(hhh]h)}(h regs.regs[1]h]h regs.regs[1]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM& hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 003ch]h0x6030 0000 0010 003c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hX30h]hX30}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hj'ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h regs.regs[30]h]h regs.regs[30]}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hj>ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 003eh]h0x6030 0000 0010 003e}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hSPh]hSP}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjuubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hregs.sph]hregs.sp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0040h]h0x6030 0000 0010 0040}(hjƝhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjÝubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hPCh]hPC}(hjݝhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjڝubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.pch]hregs.pc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0042h]h0x6030 0000 0010 0042}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hj(ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(hPSTATEh]hPSTATE}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hj?ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h64h]h64}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hjVubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h regs.pstateh]h regs.pstate}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hjmubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0044h]h0x6030 0000 0010 0044}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSP_EL1h]hSP_EL1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hsp_el1h]hsp_el1}(hj՞hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjҞubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0046h]h0x6030 0000 0010 0046}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hELR_EL1h]hELR_EL1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(helr_el1h]helr_el1}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0048h]h0x6030 0000 0010 0048}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjWubah}(h]h ]h"]h$]h&]uh1jhjTubj)}(hhh]h)}(hSPSR_EL1h]hSPSR_EL1}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjnubah}(h]h ]h"]h$]h&]uh1jhjTubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjubah}(h]h ]h"]h$]h&]uh1jhjTubj)}(hhh]h)}(h#spsr[KVM_SPSR_EL1] (alias SPSR_SVC)h]h#spsr[KVM_SPSR_EL1] (alias SPSR_SVC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 004ah]h0x6030 0000 0010 004a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM. hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSPSR_ABTh]hSPSR_ABT}(hj֟hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM. hjӟubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM. hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hspsr[KVM_SPSR_ABT]h]hspsr[KVM_SPSR_ABT]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM. hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 004ch]h0x6030 0000 0010 004c}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hj!ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSPSR_UNDh]hSPSR_UND}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hj8ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hjOubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hspsr[KVM_SPSR_UND]h]hspsr[KVM_SPSR_UND]}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hjfubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 004eh]h0x6030 0000 0010 004e}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSPSR_IRQh]hSPSR_IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hspsr[KVM_SPSR_IRQ]h]hspsr[KVM_SPSR_IRQ]}(hjΠhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjˠubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6030 0000 0010 0050h]h0x6030 0000 0010 0050}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSPSR_FIQh]hSPSR_FIQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h64h]h64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hspsr[KVM_SPSR_FIQ]h]hspsr[KVM_SPSR_FIQ]}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6040 0000 0010 0054h]h0x6040 0000 0010 0054}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2 hjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(hV0h]hV0}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2 hjgubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(h128h]h128}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2 hj~ubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]h)}(hfp_regs.vregs[0] [1]_h](hfp_regs.vregs[0] }(hjhhhNhNubhfootnote_reference)}(h[1]_h]h1}(hjhhhNhNubah}(h]id11ah ]h"]h$]h&]j_id14docnamejuh1jhjresolvedKubeh}(h]h ]h"]h$]h&]uh1hhhhM2 hjubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6040 0000 0010 0058h]h0x6040 0000 0010 0058}(hj̡hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3 hjɡubah}(h]h ]h"]h$]h&]uh1jhjơubj)}(hhh]h)}(hV1h]hV1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3 hjubah}(h]h ]h"]h$]h&]uh1jhjơubj)}(hhh]h)}(h128h]h128}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3 hjubah}(h]h ]h"]h$]h&]uh1jhjơubj)}(hhh]h)}(hfp_regs.vregs[1] [1]_h](hfp_regs.vregs[1] }(hjhhhNhNubj)}(h[1]_h]h1}(hjhhhNhNubah}(h]id12ah ]h"]h$]h&]j_jjjuh1jhjjKubeh}(h]h ]h"]h$]h&]uh1hhhhM3 hjubah}(h]h ]h"]h$]h&]uh1jhjơubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4 hj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6040 0000 0010 00d0h]h0x6040 0000 0010 00d0}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5 hjxubah}(h]h ]h"]h$]h&]uh1jhjuubj)}(hhh]h)}(hV31h]hV31}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5 hjubah}(h]h ]h"]h$]h&]uh1jhjuubj)}(hhh]h)}(h128h]h128}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5 hjubah}(h]h ]h"]h$]h&]uh1jhjuubj)}(hhh]h)}(hfp_regs.vregs[31] [1]_h](hfp_regs.vregs[31] }(hjhhhNhNubj)}(h[1]_h]h1}(hjȢhhhNhNubah}(h]id13ah ]h"]h$]h&]j_jjjuh1jhjjKubeh}(h]h ]h"]h$]h&]uh1hhhhM5 hjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6020 0000 0010 00d4h]h0x6020 0000 0010 00d4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFPSRh]hFPSR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h fp_regs.fpsrh]h fp_regs.fpsr}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hj1ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x6020 0000 0010 00d5h]h0x6020 0000 0010 00d5}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7 hjQubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(hFPCRh]hFPCR}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7 hjhubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(h32h]h32}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7 hjubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(h fp_regs.fpcrh]h fp_regs.fpcr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7 hjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjUubeh}(h]h ]h"]h$]h&]colsKuh1j^hjRubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubhfootnote)}(hThese encodings are not accepted for SVE-enabled vcpus. See :ref:`KVM_ARM_VCPU_INIT`. The equivalent register content can be accessed via bits [127:0] of the corresponding SVE Zn registers instead for vcpus that have SVE enabled (see below). h](hlabel)}(h1h]h1}(hjΣhhhNhNubah}(h]h ]h"]h$]h&]uh1j̣hjȣubh)}(hVThese encodings are not accepted for SVE-enabled vcpus. See :ref:`KVM_ARM_VCPU_INIT`.h](h=These encodings are not accepted for SVE-enabled vcpus. See }(hjܣhhhNhNubh)}(h:ref:`KVM_ARM_VCPU_INIT`h]j)}(hjh]hKVM_ARM_VCPU_INIT}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjkvm_arm_vcpu_inituh1hhhhM: hjܣubh.}(hjܣhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM: hjȣubh)}(hThe equivalent register content can be accessed via bits [127:0] of the corresponding SVE Zn registers instead for vcpus that have SVE enabled (see below).h]hThe equivalent register content can be accessed via bits [127:0] of the corresponding SVE Zn registers instead for vcpus that have SVE enabled (see below).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM= hjȣubeh}(h]jah ]h"]1ah$]h&](jj#jҢejjuh1jƣhhhM: hj6]hhjKubh)}(h:arm64 CCSIDR registers are demultiplexed by CSSELR value::h]h9arm64 CCSIDR registers are demultiplexed by CSSELR value:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMA hj6]hhubj8)}(h0x6020 0000 0011 00 h]h0x6020 0000 0011 00 }hj1sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMC hj6]hhubh)}(h;arm64 system registers have the following id bit patterns::h]h:arm64 system registers have the following id bit patterns:}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhME hj6]hhubj8)}(h80x6030 0000 0013 h]h80x6030 0000 0013 }hjMsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMG hj6]hhubj?)}(hXTwo system register IDs do not follow the specified pattern. These are KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT, which map to system registers CNTV_CVAL_EL0 and CNTVCT_EL0 respectively. These two had their values accidentally swapped, which means TIMER_CVAL is derived from the register encoding for CNTVCT_EL0 and TIMER_CNT is derived from the register encoding for CNTV_CVAL_EL0. As this is API, it must remain this way.h]h)}(hXTwo system register IDs do not follow the specified pattern. These are KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT, which map to system registers CNTV_CVAL_EL0 and CNTVCT_EL0 respectively. These two had their values accidentally swapped, which means TIMER_CVAL is derived from the register encoding for CNTVCT_EL0 and TIMER_CNT is derived from the register encoding for CNTV_CVAL_EL0. As this is API, it must remain this way.h]hXTwo system register IDs do not follow the specified pattern. These are KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT, which map to system registers CNTV_CVAL_EL0 and CNTVCT_EL0 respectively. These two had their values accidentally swapped, which means TIMER_CVAL is derived from the register encoding for CNTVCT_EL0 and TIMER_CNT is derived from the register encoding for CNTV_CVAL_EL0. As this is API, it must remain this way.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMK hj[ubah}(h]h ]h"]h$]h&]uh1j?hj6]hhhhhNubh)}(h@arm64 firmware pseudo-registers have the following bit pattern::h]h?arm64 firmware pseudo-registers have the following bit pattern:}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMS hj6]hhubj8)}(h0x6030 0000 0014 h]h0x6030 0000 0014 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMU hj6]hhubh)}(h5arm64 SVE registers have the following bit patterns::h]h4arm64 SVE registers have the following bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMW hj6]hhubj8)}(hX00x6080 0000 0015 00 Zn bits[2048*slice + 2047 : 2048*slice] 0x6050 0000 0015 04 Pn bits[256*slice + 255 : 256*slice] 0x6050 0000 0015 060 FFR bits[256*slice + 255 : 256*slice] 0x6060 0000 0015 ffff KVM_REG_ARM64_SVE_VLS pseudo-registerh]hX00x6080 0000 0015 00 Zn bits[2048*slice + 2047 : 2048*slice] 0x6050 0000 0015 04 Pn bits[256*slice + 255 : 256*slice] 0x6050 0000 0015 060 FFR bits[256*slice + 255 : 256*slice] 0x6060 0000 0015 ffff KVM_REG_ARM64_SVE_VLS pseudo-register}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMY hj6]hhubh)}(hAccess to register IDs where 2048 * slice >= 128 * max_vq will fail with ENOENT. max_vq is the vcpu's maximum supported vector length in 128-bit quadwords: see [2]_ below.h](hAccess to register IDs where 2048 * slice >= 128 * max_vq will fail with ENOENT. max_vq is the vcpu’s maximum supported vector length in 128-bit quadwords: see }(hjhhhNhNubj)}(h[2]_h]h2}(hjhhhNhNubah}(h]id15ah ]h"]h$]h&]j_id16jjuh1jhjjKubh below.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM^ hj6]hhubh)}(hiThese registers are only accessible on vcpus for which SVE is enabled. See KVM_ARM_VCPU_INIT for details.h]hiThese registers are only accessible on vcpus for which SVE is enabled. See KVM_ARM_VCPU_INIT for details.}(hjͤhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMb hj6]hhubh)}(hXIn addition, except for KVM_REG_ARM64_SVE_VLS, these registers are not accessible until the vcpu's SVE configuration has been finalized using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE). See KVM_ARM_VCPU_INIT and KVM_ARM_VCPU_FINALIZE for more information about this procedure.h]hXIn addition, except for KVM_REG_ARM64_SVE_VLS, these registers are not accessible until the vcpu’s SVE configuration has been finalized using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE). See KVM_ARM_VCPU_INIT and KVM_ARM_VCPU_FINALIZE for more information about this procedure.}(hjۤhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMe hj6]hhubh)}(hX^KVM_REG_ARM64_SVE_VLS is a pseudo-register that allows the set of vector lengths supported by the vcpu to be discovered and configured by userspace. When transferred to or from user memory via KVM_GET_ONE_REG or KVM_SET_ONE_REG, the value of this register is of type __u64[KVM_ARM64_SVE_VLS_WORDS], and encodes the set of vector lengths as follows::h]hX]KVM_REG_ARM64_SVE_VLS is a pseudo-register that allows the set of vector lengths supported by the vcpu to be discovered and configured by userspace. When transferred to or from user memory via KVM_GET_ONE_REG or KVM_SET_ONE_REG, the value of this register is of type __u64[KVM_ARM64_SVE_VLS_WORDS], and encodes the set of vector lengths as follows:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMj hj6]hhubj8)}(hX:__u64 vector_lengths[KVM_ARM64_SVE_VLS_WORDS]; if (vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX && ((vector_lengths[(vq - KVM_ARM64_SVE_VQ_MIN) / 64] >> ((vq - KVM_ARM64_SVE_VQ_MIN) % 64)) & 1)) /* Vector length vq * 16 bytes supported */ else /* Vector length vq * 16 bytes not supported */h]hX:__u64 vector_lengths[KVM_ARM64_SVE_VLS_WORDS]; if (vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX && ((vector_lengths[(vq - KVM_ARM64_SVE_VQ_MIN) / 64] >> ((vq - KVM_ARM64_SVE_VQ_MIN) % 64)) & 1)) /* Vector length vq * 16 bytes supported */ else /* Vector length vq * 16 bytes not supported */}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMq hj6]hhubjǣ)}(hThe maximum value vq for which the above condition is true is max_vq. This is the maximum vector length available to the guest on this vcpu, and determines which register slices are visible through this ioctl interface. h](jͣ)}(h2h]h2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j̣hjubh)}(hThe maximum value vq for which the above condition is true is max_vq. This is the maximum vector length available to the guest on this vcpu, and determines which register slices are visible through this ioctl interface.h]hThe maximum value vq for which the above condition is true is max_vq. This is the maximum vector length available to the guest on this vcpu, and determines which register slices are visible through this ioctl interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMz hjubeh}(h]j¤ah ]h"]2ah$]h&]jajjuh1jƣhhhMz hj6]hhjKubh)}(hS(See Documentation/arch/arm64/sve.rst for an explanation of the "vq" nomenclature.)h]hW(See Documentation/arch/arm64/sve.rst for an explanation of the “vq” nomenclature.)}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hKVM_REG_ARM64_SVE_VLS is only accessible after KVM_ARM_VCPU_INIT. KVM_ARM_VCPU_INIT initialises it to the best set of vector lengths that the host supports.h]hKVM_REG_ARM64_SVE_VLS is only accessible after KVM_ARM_VCPU_INIT. KVM_ARM_VCPU_INIT initialises it to the best set of vector lengths that the host supports.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hUserspace may subsequently modify it if desired until the vcpu's SVE configuration is finalized using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE).h]hUserspace may subsequently modify it if desired until the vcpu’s SVE configuration is finalized using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE).}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hX"Apart from simply removing all vector lengths from the host set that exceed some value, support for arbitrarily chosen sets of vector lengths is hardware-dependent and may not be available. Attempting to configure an invalid set of vector lengths via KVM_SET_ONE_REG will fail with EINVAL.h]hX"Apart from simply removing all vector lengths from the host set that exceed some value, support for arbitrarily chosen sets of vector lengths is hardware-dependent and may not be available. Attempting to configure an invalid set of vector lengths via KVM_SET_ONE_REG will fail with EINVAL.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hnAfter the vcpu's SVE configuration is finalized, further attempts to write this register will fail with EPERM.h]hpAfter the vcpu’s SVE configuration is finalized, further attempts to write this register will fail with EPERM.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hOarm64 bitmap feature firmware pseudo-registers have the following bit pattern::h]hNarm64 bitmap feature firmware pseudo-registers have the following bit pattern:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x6030 0000 0016 h]h0x6030 0000 0016 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hXThe bitmap feature firmware registers exposes the hypercall services that are available for userspace to configure. The set bits corresponds to the services that are available for the guests to access. By default, KVM sets all the supported bits during VM initialization. The userspace can discover the available services via KVM_GET_ONE_REG, and write back the bitmap corresponding to the features that it wishes guests to see via KVM_SET_ONE_REG.h]hXThe bitmap feature firmware registers exposes the hypercall services that are available for userspace to configure. The set bits corresponds to the services that are available for the guests to access. By default, KVM sets all the supported bits during VM initialization. The userspace can discover the available services via KVM_GET_ONE_REG, and write back the bitmap corresponding to the features that it wishes guests to see via KVM_SET_ONE_REG.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hNote: These registers are immutable once any of the vCPUs of the VM has run at least once. A KVM_SET_ONE_REG in such a scenario will return a -EBUSY to userspace.h]hNote: These registers are immutable once any of the vCPUs of the VM has run at least once. A KVM_SET_ONE_REG in such a scenario will return a -EBUSY to userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hA(See Documentation/virt/kvm/arm/hypercalls.rst for more details.)h]hA(See Documentation/virt/kvm/arm/hypercalls.rst for more details.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hdMIPS registers are mapped using the lower 32 bits. The upper 16 of that is the register group type:h]hdMIPS registers are mapped using the lower 32 bits. The upper 16 of that is the register group type:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hDMIPS core registers (see above) have the following id bit patterns::h]hCMIPS core registers (see above) have the following id bit patterns:}(hjƥhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x7030 0000 0000 h]h0x7030 0000 0000 }hjԥsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hMIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit patterns depending on whether they're 32-bit or 64-bit registers::h]hMIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit patterns depending on whether they’re 32-bit or 64-bit registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h]0x7020 0000 0001 00 (32-bit) 0x7030 0000 0001 00 (64-bit)h]h]0x7020 0000 0001 00 (32-bit) 0x7030 0000 0001 00 (64-bit)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hXQNote: KVM_REG_MIPS_CP0_ENTRYLO0 and KVM_REG_MIPS_CP0_ENTRYLO1 are the MIPS64 versions of the EntryLo registers regardless of the word size of the host hardware, host kernel, guest, and whether XPA is present in the guest, i.e. with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and the PFNX field starting at bit 30.h]hXQNote: KVM_REG_MIPS_CP0_ENTRYLO0 and KVM_REG_MIPS_CP0_ENTRYLO1 are the MIPS64 versions of the EntryLo registers regardless of the word size of the host hardware, host kernel, guest, and whether XPA is present in the guest, i.e. with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and the PFNX field starting at bit 30.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hTMIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit patterns::h]hSMIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit patterns:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x7030 0000 0001 01 h]h0x7030 0000 0001 01 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hKMIPS KVM control registers (see above) have the following id bit patterns::h]hJMIPS KVM control registers (see above) have the following id bit patterns:}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x7030 0000 0002 h]h0x7030 0000 0002 }hj6sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hXMIPS FPU registers (see KVM_REG_MIPS_FPR_{32,64}() above) have the following id bit patterns depending on the size of the register being accessed. They are always accessed according to the current guest FPU mode (Status.FR and Config5.FRE), i.e. as the guest would see them, and they become unpredictable if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector registers (see KVM_REG_MIPS_VEC_128() above) have similar patterns as they overlap the FPU registers::h]hXMIPS FPU registers (see KVM_REG_MIPS_FPR_{32,64}() above) have the following id bit patterns depending on the size of the register being accessed. They are always accessed according to the current guest FPU mode (Status.FR and Config5.FRE), i.e. as the guest would see them, and they become unpredictable if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector registers (see KVM_REG_MIPS_VEC_128() above) have similar patterns as they overlap the FPU registers:}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x7020 0000 0003 00 <0:3> (32-bit FPU registers) 0x7030 0000 0003 00 <0:3> (64-bit FPU registers) 0x7040 0000 0003 00 <0:3> (128-bit MSA vector registers)h]h0x7020 0000 0003 00 <0:3> (32-bit FPU registers) 0x7030 0000 0003 00 <0:3> (64-bit FPU registers) 0x7040 0000 0003 00 <0:3> (128-bit MSA vector registers)}hjRsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(heMIPS FPU control registers (see KVM_REG_MIPS_FCR_{IR,CSR} above) have the following id bit patterns::h]hdMIPS FPU control registers (see KVM_REG_MIPS_FCR_{IR,CSR} above) have the following id bit patterns:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h!0x7020 0000 0003 01 <0:3> h]h!0x7020 0000 0003 01 <0:3> }hjnsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(heMIPS MSA control registers (see KVM_REG_MIPS_MSA_{IR,CSR} above) have the following id bit patterns::h]hdMIPS MSA control registers (see KVM_REG_MIPS_MSA_{IR,CSR} above) have the following id bit patterns:}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h!0x7020 0000 0003 02 <0:3> h]h!0x7020 0000 0003 02 <0:3> }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(hiRISC-V registers are mapped using the lower 32 bits. The upper 8 bits of that is the register group type.h]hiRISC-V registers are mapped using the lower 32 bits. The upper 8 bits of that is the register group type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hiRISC-V config registers are meant for configuring a Guest VCPU and it has the following id bit patterns::h]hhRISC-V config registers are meant for configuring a Guest VCPU and it has the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x8020 0000 01 (32bit Host) 0x8030 0000 01 (64bit Host)h]h0x8020 0000 01 (32bit Host) 0x8030 0000 01 (64bit Host)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h*Following are the RISC-V config registers:h]h*Following are the RISC-V config registers:}(hj¦hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjӦubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjӦubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchjӦubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1j_hjӦubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0100 0000h]h0x80x0 0000 0100 0000}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjQubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(hisah]hisa}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhjNubj)}(hhh]h)}(h ISA feature bitmap of Guest VCPUh]h ISA feature bitmap of Guest VCPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1j~hjKubah}(h]h ]h"]h$]h&]uh1jyhjӦubeh}(h]h ]h"]h$]h&]colsKuh1j^hjЦubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hThe isa config register can be read anytime but can only be written before a Guest VCPU runs. It will have ISA feature bits matching underlying host set by default.h]hThe isa config register can be read anytime but can only be written before a Guest VCPU runs. It will have ISA feature bits matching underlying host set by default.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubh)}(hvRISC-V core registers represent the general execution state of a Guest VCPU and it has the following id bit patterns::h]huRISC-V core registers represent the general execution state of a Guest VCPU and it has the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x8020 0000 02 (32bit Host) 0x8030 0000 02 (64bit Host)h]h0x8020 0000 02 (32bit Host) 0x8030 0000 02 (64bit Host)}hj˧sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h(Following are the RISC-V core registers:h]h(Following are the RISC-V core registers:}(hj٧hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchjubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRegisterh]hRegister}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj ubah}(h]h ]h"]h$]h&]uh1j_hjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0000h]h0x80x0 0000 0200 0000}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hregs.pch]hregs.pc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhh]h)}(hProgram counterh]hProgram counter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0001h]h0x80x0 0000 0200 0001}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.rah]hregs.ra}(hjШhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjͨubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hReturn addressh]hReturn address}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0002h]h0x80x0 0000 0200 0002}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.sph]hregs.sp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Stack pointerh]h Stack pointer}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0003h]h0x80x0 0000 0200 0003}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(hregs.gph]hregs.gp}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjiubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(hGlobal pointerh]hGlobal pointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0004h]h0x80x0 0000 0200 0004}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.tph]hregs.tp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Task pointerh]h Task pointer}(hjѩhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjΩubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0005h]h0x80x0 0000 0200 0005}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.t0h]hregs.t0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCaller saved register 0h]hCaller saved register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0006h]h0x80x0 0000 0200 0006}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(hregs.t1h]hregs.t1}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjSubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(hCaller saved register 1h]hCaller saved register 1}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0007h]h0x80x0 0000 0200 0007}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.t2h]hregs.t2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCaller saved register 2h]hCaller saved register 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0008h]h0x80x0 0000 0200 0008}(hj۪hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjتubah}(h]h ]h"]h$]h&]uh1jhjժubj)}(hhh]h)}(hregs.s0h]hregs.s0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjժubj)}(hhh]h)}(hCallee saved register 0h]hCallee saved register 0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjժubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0009h]h0x80x0 0000 0200 0009}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj&ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(hregs.s1h]hregs.s1}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj=ubah}(h]h ]h"]h$]h&]uh1jhj#ubj)}(hhh]h)}(hCallee saved register 1h]hCallee saved register 1}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjTubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000ah]h0x80x0 0000 0200 000a}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hregs.a0h]hregs.a0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(h%Function argument (or return value) 0h]h%Function argument (or return value) 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000bh]h0x80x0 0000 0200 000b}(hjūhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj«ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.a1h]hregs.a1}(hjܫhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj٫ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%Function argument (or return value) 1h]h%Function argument (or return value) 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000ch]h0x80x0 0000 0200 000c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hregs.a2h]hregs.a2}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj'ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]h)}(hFunction argument 2h]hFunction argument 2}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj>ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000dh]h0x80x0 0000 0200 000d}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hregs.a3h]hregs.a3}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjuubah}(h]h ]h"]h$]h&]uh1jhj[ubj)}(hhh]h)}(hFunction argument 3h]hFunction argument 3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj[ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000eh]h0x80x0 0000 0200 000e}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.a4h]hregs.a4}(hjƬhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjìubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFunction argument 4h]hFunction argument 4}(hjݬhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjڬubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 000fh]h0x80x0 0000 0200 000f}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.a5h]hregs.a5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFunction argument 5h]hFunction argument 5}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0010h]h0x80x0 0000 0200 0010}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hregs.a6h]hregs.a6}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj_ubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hFunction argument 6h]hFunction argument 6}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjvubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0011h]h0x80x0 0000 0200 0011}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.a7h]hregs.a7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFunction argument 7h]hFunction argument 7}(hjǭhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjĭubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0012h]h0x80x0 0000 0200 0012}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.s2h]hregs.s2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCallee saved register 2h]hCallee saved register 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0013h]h0x80x0 0000 0200 0013}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj2ubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]h)}(hregs.s3h]hregs.s3}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjIubah}(h]h ]h"]h$]h&]uh1jhj/ubj)}(hhh]h)}(hCallee saved register 3h]hCallee saved register 3}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0014h]h0x80x0 0000 0200 0014}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hregs.s4h]hregs.s4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubj)}(hhh]h)}(hCallee saved register 4h]hCallee saved register 4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0015h]h0x80x0 0000 0200 0015}(hjѮhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjήubah}(h]h ]h"]h$]h&]uh1jhjˮubj)}(hhh]h)}(hregs.s5h]hregs.s5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjˮubj)}(hhh]h)}(hCallee saved register 5h]hCallee saved register 5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjˮubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0016h]h0x80x0 0000 0200 0016}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.s6h]hregs.s6}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj3ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCallee saved register 6h]hCallee saved register 6}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0017h]h0x80x0 0000 0200 0017}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(hregs.s7h]hregs.s7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(hCallee saved register 7h]hCallee saved register 7}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0018h]h0x80x0 0000 0200 0018}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.s8h]hregs.s8}(hjүhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjϯubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCallee saved register 8h]hCallee saved register 8}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0019h]h0x80x0 0000 0200 0019}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.s9h]hregs.s9}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCallee saved register 9h]hCallee saved register 9}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj4ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001ah]h0x80x0 0000 0200 001a}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjTubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hregs.s10h]hregs.s10}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjkubah}(h]h ]h"]h$]h&]uh1jhjQubj)}(hhh]h)}(hCallee saved register 10h]hCallee saved register 10}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001bh]h0x80x0 0000 0200 001b}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.s11h]hregs.s11}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCallee saved register 11h]hCallee saved register 11}(hjӰhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjаubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001ch]h0x80x0 0000 0200 001c}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.t3h]hregs.t3}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCaller saved register 3h]hCaller saved register 3}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001dh]h0x80x0 0000 0200 001d}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj>ubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(hregs.t4h]hregs.t4}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjUubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(hCaller saved register 4h]hCaller saved register 4}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjlubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001eh]h0x80x0 0000 0200 001e}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hregs.t5h]hregs.t5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hCaller saved register 5h]hCaller saved register 5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 001fh]h0x80x0 0000 0200 001f}(hjݱhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjڱubah}(h]h ]h"]h$]h&]uh1jhjױubj)}(hhh]h)}(hregs.t6h]hregs.t6}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjױubj)}(hhh]h)}(hCaller saved register 6h]hCaller saved register 6}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjױubeh}(h]h ]h"]h$]h&]uh1j~hjbubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0200 0020h]h0x80x0 0000 0200 0020}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(hmodeh]hmode}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]h)}(h)Privilege mode (1 = S-mode or 0 = U-mode)h]h)Privilege mode (1 = S-mode or 0 = U-mode)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjVubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1j~hjbubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hRISC-V csr registers represent the supervisor mode control/status registers of a Guest VCPU and it has the following id bit patterns::h]hRISC-V csr registers represent the supervisor mode control/status registers of a Guest VCPU and it has the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubj8)}(h0x8020 0000 03 (32bit Host) 0x8030 0000 03 (64bit Host)h]h0x8020 0000 03 (32bit Host) 0x8030 0000 03 (64bit Host)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj6]hhubh)}(h'Following are the RISC-V csr registers:h]h'Following are the RISC-V csr registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchjubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjݲhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM# hjڲubah}(h]h ]h"]h$]h&]uh1jhjײubj)}(hhh]h)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM# hjubah}(h]h ]h"]h$]h&]uh1jhjײubj)}(hhh]h)}(h Descriptionh]h Description}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM# hjubah}(h]h ]h"]h$]h&]uh1jhjײubeh}(h]h ]h"]h$]h&]uh1j~hjԲubah}(h]h ]h"]h$]h&]uh1j_hjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0000h]h0x80x0 0000 0300 0000}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hj1ubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh]h)}(hsstatush]hsstatus}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjHubah}(h]h ]h"]h$]h&]uh1jhj.ubj)}(hhh]h)}(hSupervisor statush]hSupervisor status}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hj_ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0001h]h0x80x0 0000 0300 0001}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM& hjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hsieh]hsie}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM& hjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hSupervisor interrupt enableh]hSupervisor interrupt enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM& hjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0002hQ]h0x80x0 0000 0300 0002}(hjгhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hjͳubah}(h]h ]h"]h$]h&]uh1jhjʳubj)}(hhh]h)}(hstvech]hstvec}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hjubah}(h]h ]h"]h$]h&]uh1jhjʳubj)}(hhh]h)}(hSupervisor trap vector baseh]hSupervisor trap vector base}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM' hjubah}(h]h ]h"]h$]h&]uh1jhjʳubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0003h]h0x80x0 0000 0300 0003}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hsscratchh]hsscratch}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hj2ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSupervisor scratch registerh]hSupervisor scratch register}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjIubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0004h]h0x80x0 0000 0300 0004}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjiubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(hsepch]hsepc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjubah}(h]h ]h"]h$]h&]uh1jhjfubj)}(hhh]h)}(h$Supervisor exception program counterh]h$Supervisor exception program counter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM) hjubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0005h]h0x80x0 0000 0300 0005}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hscauseh]hscause}(hjѴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hjδubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSupervisor trap causeh]hSupervisor trap cause}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM* hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0006h]h0x80x0 0000 0300 0006}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hstvalh]hstval}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h%Supervisor bad address or instructionh]h%Supervisor bad address or instruction}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0007h]h0x80x0 0000 0300 0007}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hjSubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(hsiph]hsip}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hjjubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(hSupervisor interrupt pendingh]hSupervisor interrupt pending}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hjubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j~hj+ubj)}(hhh](j)}(hhh]h)}(h0x80x0 0000 0300 0008h]h0x80x0 0000 0300 0008}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hsatph]hsatp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h-Supervisor address translation and protectionh]h-Supervisor address translation and protection}(hjҵhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjϵubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj+ubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hkRISC-V timer registers represent the timer state of a Guest VCPU and it has the following id bit patterns::h]hjRISC-V timer registers represent the timer state of a Guest VCPU and it has the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hj6]hhubj8)}(h90x8030 0000 04 h]h90x8030 0000 04 }hj sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM3 hj6]hhubh)}(h)Following are the RISC-V timer registers:h]h)Following are the RISC-V timer registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5 hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj,ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchj,ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchj,ubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8 hjSubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(hRegisterh]hRegister}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8 hjjubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8 hjubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j~hjMubah}(h]h ]h"]h$]h&]uh1j_hj,ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x8030 0000 0400 0000h]h0x8030 0000 0400 0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM: hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h frequencyh]h frequency}(hjĶhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM: hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTime base frequency (read-only)h]hTime base frequency (read-only)}(hj۶hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM: hjضubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x8030 0000 0400 0001h]h0x8030 0000 0400 0001}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM; hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htimeh]htime}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM; hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hTime value visible to Guesth]hTime value visible to Guest}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM; hj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x8030 0000 0400 0002h]h0x8030 0000 0400 0002}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM< hjFubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(hcompareh]hcompare}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM< hj]ubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(h Time compare programmed by Guesth]h Time compare programmed by Guest}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM< hjtubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x8030 0000 0400 0003h]h0x8030 0000 0400 0003}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM= hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hstateh]hstate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM= hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&Time compare state (1 = ON or 0 = OFF)h]h&Time compare state (1 = ON or 0 = OFF)}(hjŷhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM= hj·ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhj,ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj)ubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hRISC-V F-extension registers represent the single precision floating point state of a Guest VCPU and it has the following id bit patterns::h]hRISC-V F-extension registers represent the single precision floating point state of a Guest VCPU and it has the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@ hj6]hhubj8)}(h=0x8020 0000 05 h]h=0x8020 0000 05 }hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMC hj6]hhubh)}(h/Following are the RISC-V F-extension registers:h]h/Following are the RISC-V F-extension registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhME hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchjubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hjFubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(hRegisterh]hRegister}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hj]ubah}(h]h ]h"]h$]h&]uh1jhjCubj)}(hhh]h)}(h Descriptionh]h Description}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hjtubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1j~hj@ubah}(h]h ]h"]h$]h&]uh1j_hjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x8020 0000 0500 0000h]h0x8020 0000 0500 0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hf[0]h]hf[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJ hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFloating point register 0h]hFloating point register 0}(hjθhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJ hj˸ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x8020 0000 0500 001fh]h0x8020 0000 0500 001f}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhML hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hf[31]h]hf[31]}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhML hj4ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFloating point register 31h]hFloating point register 31}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhML hjKubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(h0x8020 0000 0500 0020h]h0x8020 0000 0500 0020}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMM hjkubah}(h]h ]h"]h$]h&]uh1jhjhubj)}(hhh]h)}(hfcsrh]hfcsr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMM hjubah}(h]h ]h"]h$]h&]uh1jhjhubj)}(hhh]h)}(h*Floating point control and status registerh]h*Floating point control and status register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMM hjubah}(h]h ]h"]h$]h&]uh1jhjhubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hRISC-V D-extension registers represent the double precision floating point state of a Guest VCPU and it has the following id bit patterns::h]hRISC-V D-extension registers represent the double precision floating point state of a Guest VCPU and it has the following id bit patterns:}(hjɹhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMP hj6]hhubj8)}(h0x8020 0000 06 (fcsr) 0x8030 0000 06 (non-fcsr)h]h0x8020 0000 06 (fcsr) 0x8030 0000 06 (non-fcsr)}hj׹sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMS hj6]hhubh)}(h/Following are the RISC-V D-extension registers:h]h/Following are the RISC-V D-extension registers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMV hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchjubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hRegisterh]hRegister}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY hj4ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h Descriptionh]h Description}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY hjKubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1j_hjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(h0x8030 0000 0600 0000h]h0x8030 0000 0600 0000}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hf[0]h]hf[0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hjubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hFloating point register 0h]hFloating point register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j~hjnubj)}(hhh](j)}(hhh]h)}(h...h]h...}(hjźhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\ hjºubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjnubj)}(hhh](j)}(hhh]h)}(h0x8030 0000 0600 001fh]h0x8030 0000 0600 001f}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM] hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hf[31]h]hf[31]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM] hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hFloating point register 31h]hFloating point register 31}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM] hj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjnubj)}(hhh](j)}(hhh]h)}(h0x8020 0000 0600 0020h]h0x8020 0000 0600 0020}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^ hjBubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(hfcsrh]hfcsr}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^ hjYubah}(h]h ]h"]h$]h&]uh1jhj?ubj)}(hhh]h)}(h*Floating point control and status registerh]h*Floating point control and status register}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^ hjpubah}(h]h ]h"]h$]h&]uh1jhj?ubeh}(h]h ]h"]h$]h&]uh1j~hjnubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubh)}(hmLoongArch registers are mapped using the lower 32 bits. The upper 16 bits of that is the register group type.h]hmLoongArch registers are mapped using the lower 32 bits. The upper 16 bits of that is the register group type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMa hj6]hhubh)}(hLoongArch csr registers are used to control guest cpu or get status of guest cpu, and they have the following id bit patterns::h]h~LoongArch csr registers are used to control guest cpu or get status of guest cpu, and they have the following id bit patterns:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd hj6]hhubj8)}(h.0x9030 0000 0001 00 (64-bit)h]h.0x9030 0000 0001 00 (64-bit)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMg hj6]hhubh)}(hLoongArch KVM control registers are used to implement some new defined functions such as set vcpu counter or reset vcpu, and they have the following id bit patterns::h]hLoongArch KVM control registers are used to implement some new defined functions such as set vcpu counter or reset vcpu, and they have the following id bit patterns:}(hjʻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMi hj6]hhubj8)}(h0x9030 0000 0002 h]h0x9030 0000 0002 }hjػsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMl hj6]hhubj )}(hhh]j)}(hSx86 MSR registers have the following id bit patterns:: 0x2030 0002 h](j)}(h6x86 MSR registers have the following id bit patterns::h]h6x86 MSR registers have the following id bit patterns::}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMo hjubj%)}(hhh]h)}(h0x2030 0002 h]h0x2030 0002 }(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMo hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMo hjubah}(h]h ]h"]h$]h&]uh1j hj6]hhhhhNubh)}(h0Following are the KVM-defined registers for x86:h]h0Following are the KVM-defined registers for x86:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMq hj6]hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj/ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchj/ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK-uh1jchj/ubj_)}(hhh]j)}(hhh](j)}(hhh]h)}(hEncodingh]hEncoding}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMt hjVubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hhh]h)}(hRegisterh]hRegister}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMt hjmubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMt hjubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1j~hjPubah}(h]h ]h"]h$]h&]uh1j_hj/ubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(h0x2030 0003 0000 0000h]h0x2030 0003 0000 0000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMv hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hSSPh]hSSP}(hjǼhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMv hjļubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hShadow Stack Pointerh]hShadow Stack Pointer}(hj޼hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMv hjۼubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1jyhj/ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj,ubah}(h]h ]h"]h$]h&]uh1jYhj6]hhhhhNubeh}(h]kvm-set-one-regah ]h"]4.68 kvm_set_one_regah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.69 KVM_GET_ONE_REGh]h4.69 KVM_GET_ONE_REG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMz ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj'hhhKubj)}(hKVM_CAP_ONE_REGh]h)}(hj:h]hKVM_CAP_ONE_REG}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM| hj8ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jwhhhM| hj$hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hallh]h)}(hjhh]hall}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM} hjfubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhM} hj$hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM~ hj$hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_one_reg (in and out)h]h)}(hjĽh]hstruct kvm_one_reg (in and out)}(hjƽhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj½ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj߽hhhKubj)}(h(0 on success, negative value on failure h]h)}(h'0 on success, negative value on failureh]h'0 on success, negative value on failure}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj߽ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM| ubh)}(hErrors include:h]hErrors include:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj )}(hXa======== ============================================================ ENOENT no such register EINVAL invalid register ID, or no such register or used with VMs in protected virtualization mode on s390 EPERM (arm64) register access not allowed before vcpu finalization ======== ============================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj)ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK0 on delivery, 0 if guest blocked the MSI, and -1 on error h]h)}(h;>0 on delivery, 0 if guest blocked the MSI, and -1 on errorh]h;>0 on delivery, 0 if guest blocked the MSI, and -1 on error}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj5ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjihhubeh}(h]h ]h"]h$]h&]uh1jrhjXhhhhhM ubh)}(h[Directly inject a MSI message. Only valid with in-kernel irqchip that handles MSI messages.h]h[Directly inject a MSI message. Only valid with in-kernel irqchip that handles MSI messages.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjXhhubj8)}(hstruct kvm_msi { __u32 address_lo; __u32 address_hi; __u32 data; __u32 flags; __u32 devid; __u8 pad[12]; };h]hstruct kvm_msi { __u32 address_lo; __u32 address_hi; __u32 data; __u32 flags; __u32 devid; __u8 pad[12]; };}hjgsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjXhhubj )}(hhh]j)}(hXflags: KVM_MSI_VALID_DEVID: devid contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail. h](j)}(hflags:h]hflags:}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjxubj%)}(hhh]h)}(hXKVM_MSI_VALID_DEVID: devid contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail.h]hXKVM_MSI_VALID_DEVID: devid contains a valid value. The per-VM KVM_CAP_MSI_DEVID capability advertises the requirement to provide the device ID. If this capability is not available, userspace should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjxubeh}(h]h ]h"]h$]h&]uh1jhhhM hjuubah}(h]h ]h"]h$]h&]uh1j hjXhhhhhNubh)}(hIf KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier for the device that wrote the MSI message. For PCI, this is usually a BDF identifier in the lower 16 bits.h]hIf KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier for the device that wrote the MSI message. For PCI, this is usually a BDF identifier in the lower 16 bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjXhhubh)}(hOn x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of address_hi must be zero.h]hOn x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of address_hi must be zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjXhhubeh}(h]kvm-signal-msiah ]h"]4.71 kvm_signal_msiah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.71 KVM_CREATE_PIT2h]h4.71 KVM_CREATE_PIT2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h KVM_CAP_PIT2h]h)}(hjh]h KVM_CAP_PIT2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hj&h]hx86}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hvm ioctlh]h)}(hjTh]hvm ioctl}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(hstruct kvm_pit_config (in)h]h)}(hjh]hstruct kvm_pit_config (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(hCreates an in-kernel device model for the i8254 PIT. This call is only valid after enabling in-kernel irqchip support via KVM_CREATE_IRQCHIP. The following parameters have to be passed::h]hCreates an in-kernel device model for the i8254 PIT. This call is only valid after enabling in-kernel irqchip support via KVM_CREATE_IRQCHIP. The following parameters have to be passed:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hBstruct kvm_pit_config { __u32 flags; __u32 pad[15]; };h]hBstruct kvm_pit_config { __u32 flags; __u32 pad[15]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjhhubh)}(hValid flags are::h]hValid flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hC#define KVM_PIT_SPEAKER_DUMMY 1 /* emulate speaker port stub */h]hC#define KVM_PIT_SPEAKER_DUMMY 1 /* emulate speaker port stub */}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjhhubh)}(hPIT timer interrupts may use a per-VM kernel thread for injection. If it exists, this thread will have a name of the following pattern::h]hPIT timer interrupts may use a per-VM kernel thread for injection. If it exists, this thread will have a name of the following pattern:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hkvm-pit/h]hkvm-pit/}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjhhubh)}(h|When running a guest with elevated priorities, the scheduling parameters of this thread may have to be adjusted accordingly.h]h|When running a guest with elevated priorities, the scheduling parameters of this thread may have to be adjusted accordingly.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h0This IOCTL replaces the obsolete KVM_CREATE_PIT.h]h0This IOCTL replaces the obsolete KVM_CREATE_PIT.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]kvm-create-pit2ah ]h"]4.71 kvm_create_pit2ah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.72 KVM_GET_PIT2h]h4.72 KVM_GET_PIT2}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^hhhKubj)}(hKVM_CAP_PIT_STATE2h]h)}(hjqh]hKVM_CAP_PIT_STATE2}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj[hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj[hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj[hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_pit_state2 (out)h]h)}(hjh]hstruct kvm_pit_state2 (out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj[hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj[hhubeh}(h]h ]h"]h$]h&]uh1jrhjJhhhhhM ubh)}(hRetrieves the state of the in-kernel PIT model. Only valid after KVM_CREATE_PIT2. The state is returned in the following structure::h]hRetrieves the state of the in-kernel PIT model. Only valid after KVM_CREATE_PIT2. The state is returned in the following structure:}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJhhubj8)}(hvstruct kvm_pit_state2 { struct kvm_pit_channel_state channels[3]; __u32 flags; __u32 reserved[9]; };h]hvstruct kvm_pit_state2 { struct kvm_pit_channel_state channels[3]; __u32 flags; __u32 reserved[9]; };}hjYsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjJhhubh)}(hValid flags are::h]hValid flags are:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJhhubj8)}(h/* disable PIT in HPET legacy mode */ #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 /* speaker port data bit enabled */ #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002h]h/* disable PIT in HPET legacy mode */ #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 /* speaker port data bit enabled */ #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002}hjusbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjJhhubh)}(h-This IOCTL replaces the obsolete KVM_GET_PIT.h]h-This IOCTL replaces the obsolete KVM_GET_PIT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjJhhubeh}(h] kvm-get-pit2ah ]h"]4.72 kvm_get_pit2ah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.73 KVM_SET_PIT2h]h4.73 KVM_SET_PIT2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_PIT_STATE2h]h)}(hjh]hKVM_CAP_PIT_STATE2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(hstruct kvm_pit_state2 (in)h]h)}(hjJh]hstruct kvm_pit_state2 (in)}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjHubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjehhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjvubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(hSets the state of the in-kernel PIT model. Only valid after KVM_CREATE_PIT2. See KVM_GET_PIT2 for details on struct kvm_pit_state2.h]hSets the state of the in-kernel PIT model. Only valid after KVM_CREATE_PIT2. See KVM_GET_PIT2 for details on struct kvm_pit_state2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubhtip)}(hX8``KVM_SET_PIT2`` strictly adheres to the spec of Intel 8254 PIT. For example, a ``count`` value of 0 in ``struct kvm_pit_channel_state`` is interpreted as 65536, which is the maximum count value. Refer to `Intel 8254 programmable interval timer `_.h]h)}(hX8``KVM_SET_PIT2`` strictly adheres to the spec of Intel 8254 PIT. For example, a ``count`` value of 0 in ``struct kvm_pit_channel_state`` is interpreted as 65536, which is the maximum count value. Refer to `Intel 8254 programmable interval timer `_.h](j)}(h``KVM_SET_PIT2``h]h KVM_SET_PIT2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhA strictly adheres to the spec of Intel 8254 PIT. For example, a }(hjhhhNhNubj)}(h ``count``h]hcount}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh value of 0 in }(hjhhhNhNubj)}(h ``struct kvm_pit_channel_state``h]hstruct kvm_pit_channel_state}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhE is interpreted as 65536, which is the maximum count value. Refer to }(hjhhhNhNubh reference)}(hi`Intel 8254 programmable interval timer `_h]h&Intel 8254 programmable interval timer}(hjhhhNhNubah}(h]h ]h"]h$]h&]name&Intel 8254 programmable interval timerrefuri=https://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdfuh1jhjubjT)}(h@ h]h}(h]&intel-8254-programmable-interval-timerah ]h"]&intel 8254 programmable interval timerah$]h&]refurijuh1jSjKhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubh)}(h-This IOCTL replaces the obsolete KVM_SET_PIT.h]h-This IOCTL replaces the obsolete KVM_SET_PIT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hjhhubeh}(h] kvm-set-pit2ah ]h"]4.73 kvm_set_pit2ah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.74 KVM_PPC_GET_SMMU_INFOh]h4.74 KVM_PPC_GET_SMMU_INFO}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhhhM) ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(hKVM_CAP_PPC_GET_SMMU_INFOh]h)}(hjVh]hKVM_CAP_PPC_GET_SMMU_INFO}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+ hjTubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM+ hj@hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(hpowerpch]h)}(hjh]hpowerpc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM, hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM, hj@hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM- hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM- hj@hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hNoneh]h)}(hjh]hNone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM. hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM. hj@hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM/ hj@hhubeh}(h]h ]h"]h$]h&]uh1jrhj/hhhhhM+ ubh)}(hThis populates and returns a structure describing the features of the "Server" class MMU emulation supported by KVM. This can in turn be used by userspace to generate the appropriate device-tree properties for the guest operating system.h]hThis populates and returns a structure describing the features of the “Server” class MMU emulation supported by KVM. This can in turn be used by userspace to generate the appropriate device-tree properties for the guest operating system.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hj/hhubh)}(hfThe structure contains some global information, followed by an array of supported segment page sizes::h]heThe structure contains some global information, followed by an array of supported segment page sizes:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hj/hhubj8)}(hstruct kvm_ppc_smmu_info { __u64 flags; __u32 slb_size; __u32 pad; struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ]; };h]hstruct kvm_ppc_smmu_info { __u64 flags; __u32 slb_size; __u32 pad; struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ]; };}hjLsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM9 hj/hhubh)}(hThe supported flags are:h]hThe supported flags are:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@ hj/hhubj )}(hX- KVM_PPC_PAGE_SIZES_REAL: When that flag is set, guest page sizes must "fit" the backing store page sizes. When not set, any page size in the list can be used regardless of how they are backed by userspace. - KVM_PPC_1T_SEGMENTS The emulated MMU supports 1T segments in addition to the standard 256M ones. - KVM_PPC_NO_HASH This flag indicates that HPT guests are not supported by KVM, thus all guests must use radix MMU mode. h]j)}(hhh](j)}(hKVM_PPC_PAGE_SIZES_REAL: When that flag is set, guest page sizes must "fit" the backing store page sizes. When not set, any page size in the list can be used regardless of how they are backed by userspace. h]j )}(hhh]j)}(hKVM_PPC_PAGE_SIZES_REAL: When that flag is set, guest page sizes must "fit" the backing store page sizes. When not set, any page size in the list can be used regardless of how they are backed by userspace. h](j)}(hKVM_PPC_PAGE_SIZES_REAL:h]hKVM_PPC_PAGE_SIZES_REAL:}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhME hjvubj%)}(hhh]h)}(hWhen that flag is set, guest page sizes must "fit" the backing store page sizes. When not set, any page size in the list can be used regardless of how they are backed by userspace.h]hWhen that flag is set, guest page sizes must “fit” the backing store page sizes. When not set, any page size in the list can be used regardless of how they are backed by userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC hjubah}(h]h ]h"]h$]h&]uh1j$hjvubeh}(h]h ]h"]h$]h&]uh1jhhhME hjsubah}(h]h ]h"]h$]h&]uh1j hjoubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(heKVM_PPC_1T_SEGMENTS The emulated MMU supports 1T segments in addition to the standard 256M ones. h]j )}(hhh]j)}(haKVM_PPC_1T_SEGMENTS The emulated MMU supports 1T segments in addition to the standard 256M ones. h](j)}(hKVM_PPC_1T_SEGMENTSh]hKVM_PPC_1T_SEGMENTS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMI hjubj%)}(hhh]h)}(hLThe emulated MMU supports 1T segments in addition to the standard 256M ones.h]hLThe emulated MMU supports 1T segments in addition to the standard 256M ones.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMI hjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhjlubj)}(h{KVM_PPC_NO_HASH This flag indicates that HPT guests are not supported by KVM, thus all guests must use radix MMU mode. h]j )}(hhh]j)}(hwKVM_PPC_NO_HASH This flag indicates that HPT guests are not supported by KVM, thus all guests must use radix MMU mode. h](j)}(hKVM_PPC_NO_HASHh]hKVM_PPC_NO_HASH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMM hjubj%)}(hhh]h)}(hfThis flag indicates that HPT guests are not supported by KVM, thus all guests must use radix MMU mode.h]hfThis flag indicates that HPT guests are not supported by KVM, thus all guests must use radix MMU mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhML hj ubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMM hjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhjlubeh}(h]h ]h"]h$]h&]jjuh1jhhhMB hjhubah}(h]h ]h"]h$]h&]uh1j hhhMB hj/hhubh)}(hAThe "slb_size" field indicates how many SLB entries are supportedh]hEThe “slb_size” field indicates how many SLB entries are supported}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMO hj/hhubh)}(hThe "sps" array contains 8 entries indicating the supported base page sizes for a segment in increasing order. Each entry is defined as follow::h]hThe “sps” array contains 8 entries indicating the supported base page sizes for a segment in increasing order. Each entry is defined as follow:}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQ hj/hhubj8)}(hstruct kvm_ppc_one_seg_page_size { __u32 page_shift; /* Base page shift of segment (or 0) */ __u32 slb_enc; /* SLB encoding for BookS */ struct kvm_ppc_one_page_size enc[KVM_PPC_PAGE_SIZES_MAX_SZ]; };h]hstruct kvm_ppc_one_seg_page_size { __u32 page_shift; /* Base page shift of segment (or 0) */ __u32 slb_enc; /* SLB encoding for BookS */ struct kvm_ppc_one_page_size enc[KVM_PPC_PAGE_SIZES_MAX_SZ]; };}hj]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMU hj/hhubh)}(hAn entry with a "page_shift" of 0 is unused. Because the array is organized in increasing order, a lookup can stop when encountering such an entry.h]hAn entry with a “page_shift” of 0 is unused. Because the array is organized in increasing order, a lookup can stop when encountering such an entry.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hj/hhubh)}(hThe "slb_enc" field provides the encoding to use in the SLB for the page size. The bits are in positions such as the value can directly be OR'ed into the "vsid" argument of the slbmte instruction.h]hThe “slb_enc” field provides the encoding to use in the SLB for the page size. The bits are in positions such as the value can directly be OR’ed into the “vsid” argument of the slbmte instruction.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_ hj/hhubh)}(hXkThe "enc" array is a list which for each of those segment base page size provides the list of supported actual page sizes (which can be only larger or equal to the base page size), along with the corresponding encoding in the hash PTE. Similarly, the array is 8 entries sorted by increasing sizes and an entry with a "0" shift is an empty entry and a terminator::h]hXrThe “enc” array is a list which for each of those segment base page size provides the list of supported actual page sizes (which can be only larger or equal to the base page size), along with the corresponding encoding in the hash PTE. Similarly, the array is 8 entries sorted by increasing sizes and an entry with a “0” shift is an empty entry and a terminator:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMc hj/hhubj8)}(hstruct kvm_ppc_one_page_size { __u32 page_shift; /* Page shift (or 0) */ __u32 pte_enc; /* Encoding in the HPTE (>>12) */ };h]hstruct kvm_ppc_one_page_size { __u32 page_shift; /* Page shift (or 0) */ __u32 pte_enc; /* Encoding in the HPTE (>>12) */ };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMj hj/hhubh)}(hThe "pte_enc" field provides a value that can OR'ed into the hash PTE's RPN field (ie, it needs to be shifted left by 12 to OR it into the hash PTE second double word).h]hThe “pte_enc” field provides a value that can OR’ed into the hash PTE’s RPN field (ie, it needs to be shifted left by 12 to OR it into the hash PTE second double word).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMo hj/hhubeh}(h]kvm-ppc-get-smmu-infoah ]h"]4.74 kvm_ppc_get_smmu_infoah$]h&]uh1hhjhhhhhM) ubh)}(hhh](h)}(h4.75 KVM_IRQFDh]h4.75 KVM_IRQFD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMt ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h KVM_CAP_IRQFDh]h)}(hjh]h KVM_CAP_IRQFD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMv hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMv hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86 s390 arm64h]h)}(hjh]hx86 s390 arm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMw hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMw hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(hvm ioctlh]h)}(hj<h]hvm ioctl}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMx hj:ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMx hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjWhhhKubj)}(hstruct kvm_irqfd (in)h]h)}(hjjh]hstruct kvm_irqfd (in)}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMy hjhubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jwhhhMy hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMz hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMz hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMv ubh)}(hXAllows setting an eventfd to directly trigger a guest interrupt. kvm_irqfd.fd specifies the file descriptor to use as the eventfd and kvm_irqfd.gsi specifies the irqchip pin toggled by this event. When an event is triggered on the eventfd, an interrupt is injected into the guest using the specified gsi pin. The irqfd is removed using the KVM_IRQFD_FLAG_DEASSIGN flag, specifying both kvm_irqfd.fd and kvm_irqfd.gsi.h]hXAllows setting an eventfd to directly trigger a guest interrupt. kvm_irqfd.fd specifies the file descriptor to use as the eventfd and kvm_irqfd.gsi specifies the irqchip pin toggled by this event. When an event is triggered on the eventfd, an interrupt is injected into the guest using the specified gsi pin. The irqfd is removed using the KVM_IRQFD_FLAG_DEASSIGN flag, specifying both kvm_irqfd.fd and kvm_irqfd.gsi.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM| hjhhubh)}(hX&With KVM_CAP_IRQFD_RESAMPLE, KVM_IRQFD supports a de-assert and notify mechanism allowing emulation of level-triggered, irqfd-based interrupts. When KVM_IRQFD_FLAG_RESAMPLE is set the user must pass an additional eventfd in the kvm_irqfd.resamplefd field. When operating in resample mode, posting of an interrupt through kvm_irq.fd asserts the specified gsi in the irqchip. When the irqchip is resampled, such as from an EOI, the gsi is de-asserted and the user is notified via kvm_irqfd.resamplefd. It is the user's responsibility to re-queue the interrupt if the device making use of it still requires service. Note that closing the resamplefd is not sufficient to disable the irqfd. The KVM_IRQFD_FLAG_RESAMPLE is only necessary on assignment and need not be specified with KVM_IRQFD_FLAG_DEASSIGN.h]hX(With KVM_CAP_IRQFD_RESAMPLE, KVM_IRQFD supports a de-assert and notify mechanism allowing emulation of level-triggered, irqfd-based interrupts. When KVM_IRQFD_FLAG_RESAMPLE is set the user must pass an additional eventfd in the kvm_irqfd.resamplefd field. When operating in resample mode, posting of an interrupt through kvm_irq.fd asserts the specified gsi in the irqchip. When the irqchip is resampled, such as from an EOI, the gsi is de-asserted and the user is notified via kvm_irqfd.resamplefd. It is the user’s responsibility to re-queue the interrupt if the device making use of it still requires service. Note that closing the resamplefd is not sufficient to disable the irqfd. The KVM_IRQFD_FLAG_RESAMPLE is only necessary on assignment and need not be specified with KVM_IRQFD_FLAG_DEASSIGN.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h@On arm64, gsi routing being supported, the following can happen:h]h@On arm64, gsi routing being supported, the following can happen:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj)}(hhh](j)}(hCin case no routing entry is associated to this gsi, injection failsh]h)}(hjh]hCin case no routing entry is associated to this gsi, injection fails}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hoin case the gsi is associated to an irqchip routing entry, irqchip.pin + 32 corresponds to the injected SPI ID.h]h)}(hoin case the gsi is associated to an irqchip routing entry, irqchip.pin + 32 corresponds to the injected SPI ID.h]hoin case the gsi is associated to an irqchip routing entry, irqchip.pin + 32 corresponds to the injected SPI ID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hin case the gsi is associated to an MSI routing entry, the MSI message and device ID are translated into an LPI (support restricted to GICv3 ITS in-kernel emulation). h]h)}(hin case the gsi is associated to an MSI routing entry, the MSI message and device ID are translated into an LPI (support restricted to GICv3 ITS in-kernel emulation).h]hin case the gsi is associated to an MSI routing entry, the MSI message and device ID are translated into an LPI (support restricted to GICv3 ITS in-kernel emulation).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hjhhubeh}(h] kvm-irqfdah ]h"]4.75 kvm_irqfdah$]h&]uh1hhjhhhhhMt ubh)}(hhh](h)}(h4.76 KVM_PPC_ALLOCATE_HTABh]h4.76 KVM_PPC_ALLOCATE_HTAB}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hKVM_CAP_PPC_ALLOC_HTABh]h)}(hjch]hKVM_CAP_PPC_ALLOC_HTAB}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjaubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjMhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(hpowerpch]h)}(hjh]hpowerpc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjMhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjMhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h3Pointer to u32 containing hash table order (in/out)h]h)}(hjh]h3Pointer to u32 containing hash table order (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjMhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjMhhubeh}(h]h ]h"]h$]h&]uh1jrhj<hhhhhM ubh)}(hXYThis requests the host kernel to allocate an MMU hash table for a guest using the PAPR paravirtualization interface. This only does anything if the kernel is configured to use the Book 3S HV style of virtualization. Otherwise the capability doesn't exist and the ioctl returns an ENOTTY error. The rest of this description assumes Book 3S HV.h]hX[This requests the host kernel to allocate an MMU hash table for a guest using the PAPR paravirtualization interface. This only does anything if the kernel is configured to use the Book 3S HV style of virtualization. Otherwise the capability doesn’t exist and the ioctl returns an ENOTTY error. The rest of this description assumes Book 3S HV.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<hhubh)}(huThere must be no vcpus running when this ioctl is called; if there are, it will do nothing and return an EBUSY error.h]huThere must be no vcpus running when this ioctl is called; if there are, it will do nothing and return an EBUSY error.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<hhubh)}(hThe parameter is a pointer to a 32-bit unsigned integer variable containing the order (log base 2) of the desired size of the hash table, which must be between 18 and 46. On successful return from the ioctl, the value will not be changed by the kernel.h]hThe parameter is a pointer to a 32-bit unsigned integer variable containing the order (log base 2) of the desired size of the hash table, which must be between 18 and 46. On successful return from the ioctl, the value will not be changed by the kernel.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<hhubh)}(hIf no hash table has been allocated when any vcpu is asked to run (with the KVM_RUN ioctl), the host kernel will allocate a default-sized hash table (16 MB).h]hIf no hash table has been allocated when any vcpu is asked to run (with the KVM_RUN ioctl), the host kernel will allocate a default-sized hash table (16 MB).}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<hhubh)}(hXIf this ioctl is called when a hash table has already been allocated, with a different order from the existing hash table, the existing hash table will be freed and a new one allocated. If this is ioctl is called when a hash table has already been allocated of the same order as specified, the kernel will clear out the existing hash table (zero all HPTEs). In either case, if the guest is using the virtualized real-mode area (VRMA) facility, the kernel will re-create the VMRA HPTEs on the next KVM_RUN of any vcpu.h]hXIf this ioctl is called when a hash table has already been allocated, with a different order from the existing hash table, the existing hash table will be freed and a new one allocated. If this is ioctl is called when a hash table has already been allocated of the same order as specified, the kernel will clear out the existing hash table (zero all HPTEs). In either case, if the guest is using the virtualized real-mode area (VRMA) facility, the kernel will re-create the VMRA HPTEs on the next KVM_RUN of any vcpu.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<hhubeh}(h]kvm-ppc-allocate-htabah ]h"]4.76 kvm_ppc_allocate_htabah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.77 KVM_S390_INTERRUPTh]h4.77 KVM_S390_INTERRUPT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctl, vcpu ioctlh]h)}(hjh]hvm ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(hstruct kvm_s390_interrupt (in)h]h)}(hj<h]hstruct kvm_s390_interrupt (in)}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj:ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjWhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(hAllows to inject an interrupt to the guest. Interrupts can be floating (vm ioctl) or per cpu (vcpu ioctl), depending on the interrupt type.h]hAllows to inject an interrupt to the guest. Interrupts can be floating (vm ioctl) or per cpu (vcpu ioctl), depending on the interrupt type.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h8Interrupt parameters are passed via kvm_s390_interrupt::h]h7Interrupt parameters are passed via kvm_s390_interrupt:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hVstruct kvm_s390_interrupt { __u32 type; __u32 parm; __u64 parm64; };h]hVstruct kvm_s390_interrupt { __u32 type; __u32 parm; __u64 parm64; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjhhubh)}(h!type can be one of the following:h]h!type can be one of the following:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj )}(hhh](j)}(h=KVM_S390_SIGP_STOP (vcpu) - sigp stop; optional flags in parmh](j)}(hKVM_S390_SIGP_STOP (vcpu)h]hKVM_S390_SIGP_STOP (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(h!sigp stop; optional flags in parmh]h)}(hjh]h!sigp stop; optional flags in parm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjubj)}(h9KVM_S390_PROGRAM_INT (vcpu) - program check; code in parmh](j)}(hKVM_S390_PROGRAM_INT (vcpu)h]hKVM_S390_PROGRAM_INT (vcpu)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(hprogram check; code in parmh]h)}(hj"h]hprogram check; code in parm}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hIKVM_S390_SIGP_SET_PREFIX (vcpu) - sigp set prefix; prefix address in parmh](j)}(hKVM_S390_SIGP_SET_PREFIX (vcpu)h]hKVM_S390_SIGP_SET_PREFIX (vcpu)}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjIubj%)}(hhh]j)}(hhh]j)}(h'sigp set prefix; prefix address in parmh]h)}(hjch]h'sigp set prefix; prefix address in parm}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjaubah}(h]h ]h"]h$]h&]uh1jhj^ubah}(h]h ]h"]h$]h&]jjuh1jhhhM hj[ubah}(h]h ]h"]h$]h&]uh1j$hjIubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(h!KVM_S390_RESTART (vcpu) - restarth](j)}(hKVM_S390_RESTART (vcpu)h]hKVM_S390_RESTART (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(hrestarth]h)}(hjh]hrestart}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(h;KVM_S390_INT_CLOCK_COMP (vcpu) - clock comparator interrupth](j)}(hKVM_S390_INT_CLOCK_COMP (vcpu)h]hKVM_S390_INT_CLOCK_COMP (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(hclock comparator interrupth]h)}(hjh]hclock comparator interrupt}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(h3KVM_S390_INT_CPU_TIMER (vcpu) - CPU timer interrupth](j)}(hKVM_S390_INT_CPU_TIMER (vcpu)h]hKVM_S390_INT_CPU_TIMER (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hj ubj%)}(hhh]j)}(hhh]j)}(hCPU timer interrupth]h)}(hj&h]hCPU timer interrupt}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj$ubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hj ubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hhKVM_S390_INT_VIRTIO (vm) - virtio external interrupt; external interrupt parameters in parm and parm64h](j)}(hKVM_S390_INT_VIRTIO (vm)h]hKVM_S390_INT_VIRTIO (vm)}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjMubj%)}(hhh]j)}(hhh]j)}(hKvirtio external interrupt; external interrupt parameters in parm and parm64h]h)}(hKvirtio external interrupt; external interrupt parameters in parm and parm64h]hKvirtio external interrupt; external interrupt parameters in parm and parm64}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjeubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]jjuh1jhhhM hj_ubah}(h]h ]h"]h$]h&]uh1j$hjMubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hKKVM_S390_INT_SERVICE (vm) - sclp external interrupt; sclp parameter in parmh](j)}(hKVM_S390_INT_SERVICE (vm)h]hKVM_S390_INT_SERVICE (vm)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(h/sclp external interrupt; sclp parameter in parmh]h)}(hjh]h/sclp external interrupt; sclp parameter in parm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hBKVM_S390_INT_EMERGENCY (vcpu) - sigp emergency; source cpu in parmh](j)}(hKVM_S390_INT_EMERGENCY (vcpu)h]hKVM_S390_INT_EMERGENCY (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(h"sigp emergency; source cpu in parmh]h)}(hjh]h"sigp emergency; source cpu in parm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hJKVM_S390_INT_EXTERNAL_CALL (vcpu) - sigp external call; source cpu in parmh](j)}(h!KVM_S390_INT_EXTERNAL_CALL (vcpu)h]h!KVM_S390_INT_EXTERNAL_CALL (vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(h&sigp external call; source cpu in parmh]h)}(hj+h]h&sigp external call; source cpu in parm}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj)ubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]jjuh1jhhhM hj#ubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hKVM_S390_INT_IO(ai,cssid,ssid,schid) (vm) - compound value to indicate an I/O interrupt (ai - adapter interrupt; cssid,ssid,schid - subchannel); I/O interruption parameters in parm (subchannel) and parm64 (intparm, interruption subclass)h](j)}(h)KVM_S390_INT_IO(ai,cssid,ssid,schid) (vm)h]h)KVM_S390_INT_IO(ai,cssid,ssid,schid) (vm)}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjRubj%)}(hhh]j)}(hhh]j)}(hcompound value to indicate an I/O interrupt (ai - adapter interrupt; cssid,ssid,schid - subchannel); I/O interruption parameters in parm (subchannel) and parm64 (intparm, interruption subclass)h]h)}(hcompound value to indicate an I/O interrupt (ai - adapter interrupt; cssid,ssid,schid - subchannel); I/O interruption parameters in parm (subchannel) and parm64 (intparm, interruption subclass)h]hcompound value to indicate an I/O interrupt (ai - adapter interrupt; cssid,ssid,schid - subchannel); I/O interruption parameters in parm (subchannel) and parm64 (intparm, interruption subclass)}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjdubah}(h]h ]h"]h$]h&]uh1j$hjRubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubj)}(hKVM_S390_MCHK (vm, vcpu) - machine check interrupt; cr 14 bits in parm, machine check interrupt code in parm64 (note that machine checks needing further payload are not supported by this ioctl) h](j)}(hKVM_S390_MCHK (vm, vcpu)h]hKVM_S390_MCHK (vm, vcpu)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh]j)}(hmachine check interrupt; cr 14 bits in parm, machine check interrupt code in parm64 (note that machine checks needing further payload are not supported by this ioctl) h]h)}(hmachine check interrupt; cr 14 bits in parm, machine check interrupt code in parm64 (note that machine checks needing further payload are not supported by this ioctl)h]hmachine check interrupt; cr 14 bits in parm, machine check interrupt code in parm64 (note that machine checks needing further payload are not supported by this ioctl)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.h]hFThis is an asynchronous vcpu ioctl and can be invoked from any thread.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]kvm-s390-interruptah ]h"]4.77 kvm_s390_interruptah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.78 KVM_PPC_GET_HTAB_FDh]h4.78 KVM_PPC_GET_HTAB_FD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_PPC_HTAB_FDh]h)}(hjh]hKVM_CAP_PPC_HTAB_FD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hpowerpch]h)}(hjGh]hpowerpc}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(hvm ioctlh]h)}(hjuh]hvm ioctl}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h&Pointer to struct kvm_get_htab_fd (in)h]h)}(hjh]h&Pointer to struct kvm_get_htab_fd (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h6file descriptor number (>= 0) on success, -1 on error h]h)}(h5file descriptor number (>= 0) on success, -1 on errorh]h5file descriptor number (>= 0) on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(hXdThis returns a file descriptor that can be used either to read out the entries in the guest's hashed page table (HPT), or to write entries to initialize the HPT. The returned fd can only be written to if the KVM_GET_HTAB_WRITE bit is set in the flags field of the argument, and can only be read if that bit is clear. The argument struct looks like this::h]hXeThis returns a file descriptor that can be used either to read out the entries in the guest’s hashed page table (HPT), or to write entries to initialize the HPT. The returned fd can only be written to if the KVM_GET_HTAB_WRITE bit is set in the flags field of the argument, and can only be read if that bit is clear. The argument struct looks like this:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hX/* For KVM_PPC_GET_HTAB_FD */ struct kvm_get_htab_fd { __u64 flags; __u64 start_index; __u64 reserved[2]; }; /* Values for kvm_get_htab_fd.flags */ #define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) #define KVM_GET_HTAB_WRITE ((__u64)0x2)h]hX/* For KVM_PPC_GET_HTAB_FD */ struct kvm_get_htab_fd { __u64 flags; __u64 start_index; __u64 reserved[2]; }; /* Values for kvm_get_htab_fd.flags */ #define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) #define KVM_GET_HTAB_WRITE ((__u64)0x2)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjhhubh)}(hwThe 'start_index' field gives the index in the HPT of the entry at which to start reading. It is ignored when writing.h]h{The ‘start_index’ field gives the index in the HPT of the entry at which to start reading. It is ignored when writing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hXReads on the fd will initially supply information about all "interesting" HPT entries. Interesting entries are those with the bolted bit set, if the KVM_GET_HTAB_BOLTED_ONLY bit is set, otherwise all entries. When the end of the HPT is reached, the read() will return. If read() is called again on the fd, it will start again from the beginning of the HPT, but will only return HPT entries that have changed since they were last read.h]hXReads on the fd will initially supply information about all “interesting” HPT entries. Interesting entries are those with the bolted bit set, if the KVM_GET_HTAB_BOLTED_ONLY bit is set, otherwise all entries. When the end of the HPT is reached, the read() will return. If read() is called again on the fd, it will start again from the beginning of the HPT, but will only return HPT entries that have changed since they were last read.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hX@Data read or written is structured as a header (8 bytes) followed by a series of valid HPT entries (16 bytes) each. The header indicates how many valid HPT entries there are and how many invalid entries follow the valid entries. The invalid entries are not represented explicitly in the stream. The header format is::h]hX?Data read or written is structured as a header (8 bytes) followed by a series of valid HPT entries (16 bytes) each. The header indicates how many valid HPT entries there are and how many invalid entries follow the valid entries. The invalid entries are not represented explicitly in the stream. The header format is:}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj8)}(hdstruct kvm_get_htab_header { __u32 index; __u16 n_valid; __u16 n_invalid; };h]hdstruct kvm_get_htab_header { __u32 index; __u16 n_valid; __u16 n_invalid; };}hj9sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM" hjhhubh)}(hWrites to the fd create HPT entries starting at the index given in the header; first 'n_valid' valid entries with contents from the data written, then 'n_invalid' invalid entries, invalidating any previously valid entries found.h]hWrites to the fd create HPT entries starting at the index given in the header; first ‘n_valid’ valid entries with contents from the data written, then ‘n_invalid’ invalid entries, invalidating any previously valid entries found.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjhhubeh}(h]kvm-ppc-get-htab-fdah ]h"]4.78 kvm_ppc_get_htab_fdah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.79 KVM_CREATE_DEVICEh]h4.79 KVM_CREATE_DEVICE}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hhhhhM. ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(hKVM_CAP_DEVICE_CTRLh]h)}(hjh]hKVM_CAP_DEVICE_CTRL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM0 hjnhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM1 hjnhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2 hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM2 hjnhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h!struct kvm_create_device (in/out)h]h)}(hjh]h!struct kvm_create_device (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3 hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM3 hjnhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4 hj:ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhM4 hjnhhubeh}(h]h ]h"]h$]h&]uh1jrhj]hhhhhM0 ubh)}(hErrors:h]hErrors:}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6 hj]hhubj )}(hX|====== ======================================================= ENODEV The device type is unknown or unsupported EEXIST Device already created, and this type of device may not be instantiated multiple times ====== ======================================================= Other error conditions may be defined by individual device types or have their standard meanings. h](jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjsubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK7uh1jchjsubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hENODEVh]hENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9 hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h)The device type is unknown or unsupportedh]h)The device type is unknown or unsupported}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9 hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEEXISTh]hEEXIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM: hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hVDevice already created, and this type of device may not be instantiated multiple timesh]hVDevice already created, and this type of device may not be instantiated multiple times}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM: hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjsubeh}(h]h ]h"]h$]h&]colsKuh1j^hjpubah}(h]h ]h"]h$]h&]uh1jYhjlubh)}(haOther error conditions may be defined by individual device types or have their standard meanings.h]haOther error conditions may be defined by individual device types or have their standard meanings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM> hjlubeh}(h]h ]h"]h$]h&]uh1j hhhM8 hj]hhubh)}(h{Creates an emulated device in the kernel. The file descriptor returned in fd can be used with KVM_SET/GET/HAS_DEVICE_ATTR.h]h{Creates an emulated device in the kernel. The file descriptor returned in fd can be used with KVM_SET/GET/HAS_DEVICE_ATTR.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMA hj]hhubh)}(hIf the KVM_CREATE_DEVICE_TEST flag is set, only test whether the device type is supported (not necessarily whether it can be created in the current vm).h]hIf the KVM_CREATE_DEVICE_TEST flag is set, only test whether the device type is supported (not necessarily whether it can be created in the current vm).}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMD hj]hhubh)}(hIndividual devices should not define flags. Attributes should be used for specifying any behavior that is not implied by the device type number.h]hIndividual devices should not define flags. Attributes should be used for specifying any behavior that is not implied by the device type number.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH hj]hhubj8)}(hstruct kvm_create_device { __u32 type; /* in: KVM_DEV_TYPE_xxx */ __u32 fd; /* out: device handle */ __u32 flags; /* in: KVM_CREATE_DEVICE_xxx */ };h]hstruct kvm_create_device { __u32 type; /* in: KVM_DEV_TYPE_xxx */ __u32 fd; /* out: device handle */ __u32 flags; /* in: KVM_CREATE_DEVICE_xxx */ };}hjLsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMN hj]hhubeh}(h]kvm-create-deviceah ]h"]4.79 kvm_create_deviceah$]h&]uh1hhjhhhhhM. ubh)}(hhh](h)}(h,4.80 KVM_SET_DEVICE_ATTR/KVM_GET_DEVICE_ATTRh]h,4.80 KVM_SET_DEVICE_ATTR/KVM_GET_DEVICE_ATTR}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhjbhhhhhMU ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjvhhhKubj)}(hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) device (no set)h]h)}(hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) device (no set)h]hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) device (no set)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMW hjubah}(h]h ]h"]h$]h&]uh1jhjvubeh}(h]h ]h"]h$]h&]uh1jwhhhMW hjshhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86, arm64, s390h]h)}(hjh]hx86, arm64, s390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMZ hjshhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h"device ioctl, vm ioctl, vcpu ioctlh]h)}(hjh]h"device ioctl, vm ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM[ hjshhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_device_attrh]h)}(hjh]hstruct kvm_device_attr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM\ hjshhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM] hj@ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhM] hjshhubeh}(h]h ]h"]h$]h&]uh1jrhjbhhhhhMW ubh)}(hErrors:h]hErrors:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_ hjbhhubj )}(hX===== ============================================================= ENXIO The group or attribute is unknown/unsupported for this device or hardware support is missing. EPERM The attribute cannot (currently) be accessed this way (e.g. read-only attribute, or attribute that only makes sense when the device is in a different state) ===== ============================================================= Other error conditions may be defined by individual device types. h](jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjyubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1jchjyubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hENXIOh]hENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMb hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h]The group or attribute is unknown/unsupported for this device or hardware support is missing.h]h]The group or attribute is unknown/unsupported for this device or hardware support is missing.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMb hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEPERMh]hEPERM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hThe attribute cannot (currently) be accessed this way (e.g. read-only attribute, or attribute that only makes sense when the device is in a different state)h]hThe attribute cannot (currently) be accessed this way (e.g. read-only attribute, or attribute that only makes sense when the device is in a different state)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjyubeh}(h]h ]h"]h$]h&]colsKuh1j^hjvubah}(h]h ]h"]h$]h&]uh1jYhjrubh)}(hAOther error conditions may be defined by individual device types.h]hAOther error conditions may be defined by individual device types.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMi hjrubeh}(h]h ]h"]h$]h&]uh1j hhhMa hjbhhubh)}(hXGets/sets a specified piece of device configuration and/or state. The semantics are device-specific. See individual device documentation in the "devices" directory. As with ONE_REG, the size of the data transferred is defined by the particular attribute.h]hXGets/sets a specified piece of device configuration and/or state. The semantics are device-specific. See individual device documentation in the “devices” directory. As with ONE_REG, the size of the data transferred is defined by the particular attribute.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMk hjbhhubj8)}(hXstruct kvm_device_attr { __u32 flags; /* no flags currently defined */ __u32 group; /* device-defined */ __u64 attr; /* group-defined */ __u64 addr; /* userspace address of attr data */ };h]hXstruct kvm_device_attr { __u32 flags; /* no flags currently defined */ __u32 group; /* device-defined */ __u64 attr; /* group-defined */ __u64 addr; /* userspace address of attr data */ };}hj6sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMr hjbhhubeh}(h]'kvm-set-device-attr-kvm-get-device-attrah ]h"],4.80 kvm_set_device_attr/kvm_get_device_attrah$]h&]uh1hhjhhhhhMU ubh)}(hhh](h)}(h4.81 KVM_HAS_DEVICE_ATTRh]h4.81 KVM_HAS_DEVICE_ATTR}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhMz ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj`hhhKubj)}(hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) deviceh]h)}(hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) deviceh]hKVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device, KVM_CAP_VCPU_ATTRIBUTES for vcpu device KVM_CAP_SYS_ATTRIBUTES for system (/dev/kvm) device}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM| hjqubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jwhhhM| hj]hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h"device ioctl, vm ioctl, vcpu ioctlh]h)}(hjh]h"device ioctl, vm ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj]hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_device_attrh]h)}(hjh]hstruct kvm_device_attr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj]hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj]hhubeh}(h]h ]h"]h$]h&]uh1jrhjLhhhhhM| ubh)}(hErrors:h]hErrors:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjLhhubj )}(h===== ============================================================= ENXIO The group or attribute is unknown/unsupported for this device or hardware support is missing. ===== ============================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj5ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1jchj5ubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(hENXIOh]hENXIO}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjRubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(h]The group or attribute is unknown/unsupported for this device or hardware support is missing.h]h]The group or attribute is unknown/unsupported for this device or hardware support is missing.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjiubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j~hjLubah}(h]h ]h"]h$]h&]uh1jyhj5ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj2ubah}(h]h ]h"]h$]h&]uh1jYhj.ubah}(h]h ]h"]h$]h&]uh1j hhhM hjLhhubh)}(hTests whether a device supports a particular attribute. A successful return indicates the attribute is implemented. It does not necessarily indicate that the attribute can be read or written in the device's current state. "addr" is ignored.h]hTests whether a device supports a particular attribute. A successful return indicates the attribute is implemented. It does not necessarily indicate that the attribute can be read or written in the device’s current state. “addr” is ignored.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjLhhubjT)}(h.. _KVM_ARM_VCPU_INIT:h]h}(h]h ]h"]h$]h&]j_kvm-arm-vcpu-inituh1jShM hjLhhhhubeh}(h]kvm-has-device-attrah ]h"]4.81 kvm_has_device_attrah$]h&]uh1hhjhhhhhMz ubh)}(hhh](h)}(h4.82 KVM_ARM_VCPU_INITh]h4.82 KVM_ARM_VCPU_INIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hjh]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj0hhhKubj)}(h vcpu ioctlh]h)}(hjCh]h vcpu ioctl}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjAubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^hhhKubj)}(hstruct kvm_vcpu_init (in)h]h)}(hjqh]hstruct kvm_vcpu_init (in)}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj )}(hX====== ================================================================= EINVAL the target is unknown, or the combination of features is invalid. ENOENT a features bit specified is unknown. ====== ================================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKAuh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAthe target is unknown, or the combination of features is invalid.h]hAthe target is unknown, or the combination of features is invalid.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hENOENTh]hENOENT}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj*ubah}(h]h ]h"]h$]h&]uh1jhj'ubj)}(hhh]h)}(h$a features bit specified is unknown.h]h$a features bit specified is unknown.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjAubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhM hjhhubh)}(hThis tells KVM what type of CPU to present to the guest, and what optional features it should have. This will cause a reset of the cpu registers to their initial values. If this is not called, KVM_RUN will return ENOEXEC for that vcpu.h]hThis tells KVM what type of CPU to present to the guest, and what optional features it should have. This will cause a reset of the cpu registers to their initial values. If this is not called, KVM_RUN will return ENOEXEC for that vcpu.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj )}(hhh]j)}(hXThe initial values are defined as: - Processor state: * AArch64: EL1h, D, A, I and F bits set. All other bits are cleared. * AArch32: SVC, A, I and F bits set. All other bits are cleared. - General Purpose registers, including PC and SP: set to 0 - FPSIMD/NEON registers: set to 0 - SVE registers: set to 0 - System registers: Reset to their architecturally defined values as for a warm reset to EL1 (resp. SVC) or EL2 (in the case of EL2 being enabled). h](j)}(h"The initial values are defined as:h]h"The initial values are defined as:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh](j)}(hProcessor state: * AArch64: EL1h, D, A, I and F bits set. All other bits are cleared. * AArch32: SVC, A, I and F bits set. All other bits are cleared.h]j )}(hhh]j)}(hProcessor state: * AArch64: EL1h, D, A, I and F bits set. All other bits are cleared. * AArch32: SVC, A, I and F bits set. All other bits are cleared.h](j)}(hProcessor state:h]hProcessor state:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM hjubj%)}(hhh]j)}(hhh](j)}(hBAArch64: EL1h, D, A, I and F bits set. All other bits are cleared.h]h)}(hBAArch64: EL1h, D, A, I and F bits set. All other bits are cleared.h]hBAArch64: EL1h, D, A, I and F bits set. All other bits are cleared.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h>AArch32: SVC, A, I and F bits set. All other bits are cleared.h]h)}(h>AArch32: SVC, A, I and F bits set. All other bits are cleared.h]h>AArch32: SVC, A, I and F bits set. All other bits are cleared.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]j*uh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h8General Purpose registers, including PC and SP: set to 0h]h)}(hjh]h8General Purpose registers, including PC and SP: set to 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hFPSIMD/NEON registers: set to 0h]h)}(hj'h]hFPSIMD/NEON registers: set to 0}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj%ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hSVE registers: set to 0h]h)}(hj>h]hSVE registers: set to 0}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj<ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hSystem registers: Reset to their architecturally defined values as for a warm reset to EL1 (resp. SVC) or EL2 (in the case of EL2 being enabled). h]h)}(hSystem registers: Reset to their architecturally defined values as for a warm reset to EL1 (resp. SVC) or EL2 (in the case of EL2 being enabled).h]hSystem registers: Reset to their architecturally defined values as for a warm reset to EL1 (resp. SVC) or EL2 (in the case of EL2 being enabled).}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjSubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(htNote that because some registers reflect machine topology, all vcpus should be created before this ioctl is invoked.h]htNote that because some registers reflect machine topology, all vcpus should be created before this ioctl is invoked.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hX$Userspace can call this function multiple times for a given vcpu, including after the vcpu has been run. This will reset the vcpu to its initial state. All calls to this function after the initial call must use the same target and same set of feature flags, otherwise EINVAL will be returned.h]hX$Userspace can call this function multiple times for a given vcpu, including after the vcpu has been run. This will reset the vcpu to its initial state. All calls to this function after the initial call must use the same target and same set of feature flags, otherwise EINVAL will be returned.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hPossible features:h]hPossible features:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj )}(hX& - KVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state. Depends on KVM_CAP_ARM_PSCI. If not set, the CPU will be powered on and execute guest code when KVM_RUN is called. - KVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode. Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only). - KVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision backward compatible with v0.2) for the CPU. Depends on KVM_CAP_ARM_PSCI_0_2. - KVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU. Depends on KVM_CAP_ARM_PMU_V3. - KVM_ARM_VCPU_PMU_V3_STRICT: Enable strict PMUv3 UAPI. Requires KVM_ARM_VCPU_PMU_V3. Depends on KVM_CAP_ARM_PMU_V3_STRICT. When enabled: * Userspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter * If the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementation * Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored - KVM_ARM_VCPU_PTRAUTH_ADDRESS: Enables Address Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_ADDRESS. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested. - KVM_ARM_VCPU_PTRAUTH_GENERIC: Enables Generic Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_GENERIC. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested. - KVM_ARM_VCPU_SVE: Enables SVE for the CPU (arm64 only). Depends on KVM_CAP_ARM_SVE. Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): * After KVM_ARM_VCPU_INIT: - KVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - KVM_RUN and KVM_GET_REG_LIST are not available; - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; - KVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. - KVM_ARM_VCPU_HAS_EL2: Enable Nested Virtualisation support, booting the guest from EL2 instead of EL1. Depends on KVM_CAP_ARM_EL2. The VM is running with HCR_EL2.E2H being RES1 (VHE) unless KVM_ARM_VCPU_HAS_EL2_E2H0 is also set. - KVM_ARM_VCPU_HAS_EL2_E2H0: Restrict Nested Virtualisation support to HCR_EL2.E2H being RES0 (non-VHE). Depends on KVM_CAP_ARM_EL2_E2H0. KVM_ARM_VCPU_HAS_EL2 must also be set. h]j)}(hhh](j)}(hKVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state. Depends on KVM_CAP_ARM_PSCI. If not set, the CPU will be powered on and execute guest code when KVM_RUN is called.h]h)}(hKVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state. Depends on KVM_CAP_ARM_PSCI. If not set, the CPU will be powered on and execute guest code when KVM_RUN is called.h]hKVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state. Depends on KVM_CAP_ARM_PSCI. If not set, the CPU will be powered on and execute guest code when KVM_RUN is called.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hfKVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode. Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).h]h)}(hfKVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode. Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).h]hfKVM_ARM_VCPU_EL1_32BIT: Starts the CPU in a 32bit mode. Depends on KVM_CAP_ARM_EL1_32BIT (arm64 only).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hKVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision backward compatible with v0.2) for the CPU. Depends on KVM_CAP_ARM_PSCI_0_2.h]h)}(hKVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision backward compatible with v0.2) for the CPU. Depends on KVM_CAP_ARM_PSCI_0_2.h]hKVM_ARM_VCPU_PSCI_0_2: Emulate PSCI v0.2 (or a future revision backward compatible with v0.2) for the CPU. Depends on KVM_CAP_ARM_PSCI_0_2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hNKVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU. Depends on KVM_CAP_ARM_PMU_V3.h]h)}(hNKVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU. Depends on KVM_CAP_ARM_PMU_V3.h]hNKVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU. Depends on KVM_CAP_ARM_PMU_V3.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hXKVM_ARM_VCPU_PMU_V3_STRICT: Enable strict PMUv3 UAPI. Requires KVM_ARM_VCPU_PMU_V3. Depends on KVM_CAP_ARM_PMU_V3_STRICT. When enabled: * Userspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter * If the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementation * Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored h](h)}(hKVM_ARM_VCPU_PMU_V3_STRICT: Enable strict PMUv3 UAPI. Requires KVM_ARM_VCPU_PMU_V3. Depends on KVM_CAP_ARM_PMU_V3_STRICT. When enabled:h]hKVM_ARM_VCPU_PMU_V3_STRICT: Enable strict PMUv3 UAPI. Requires KVM_ARM_VCPU_PMU_V3. Depends on KVM_CAP_ARM_PMU_V3_STRICT. When enabled:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj )}(hX&* Userspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter * If the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementation * Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored h]j)}(hhh](j)}(htUserspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter h]h)}(hsUserspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filterh]hsUserspace must explicitly select a PMU implementation before initializing the PMU or configuring a PMU event filter}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj-ubah}(h]h ]h"]h$]h&]uh1jhj*ubj)}(hqIf the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementation h]h)}(hpIf the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementationh]hpIf the PMU implements FEAT_PMUv3p4, PMMIR_EL1.SLOTS provides the hardware value of the underlying implementation}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjEubah}(h]h ]h"]h$]h&]uh1jhj*ubj)}(h5Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored h]h)}(h4Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignoredh]h4Writes to PMCR_EL0.N via KVM_SET_ONE_REG are ignored}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hj&ubah}(h]h ]h"]h$]h&]uh1j hhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hXFKVM_ARM_VCPU_PTRAUTH_ADDRESS: Enables Address Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_ADDRESS. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested. h]h)}(hXEKVM_ARM_VCPU_PTRAUTH_ADDRESS: Enables Address Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_ADDRESS. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested.h]hXEKVM_ARM_VCPU_PTRAUTH_ADDRESS: Enables Address Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_ADDRESS. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hXFKVM_ARM_VCPU_PTRAUTH_GENERIC: Enables Generic Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_GENERIC. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested. h]h)}(hXEKVM_ARM_VCPU_PTRAUTH_GENERIC: Enables Generic Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_GENERIC. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested.h]hXEKVM_ARM_VCPU_PTRAUTH_GENERIC: Enables Generic Pointer authentication for arm64 only. Depends on KVM_CAP_ARM_PTRAUTH_GENERIC. If KVM_CAP_ARM_PTRAUTH_ADDRESS and KVM_CAP_ARM_PTRAUTH_GENERIC are both present, then both KVM_ARM_VCPU_PTRAUTH_ADDRESS and KVM_ARM_VCPU_PTRAUTH_GENERIC must be requested or neither must be requested.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hXKVM_ARM_VCPU_SVE: Enables SVE for the CPU (arm64 only). Depends on KVM_CAP_ARM_SVE. Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): * After KVM_ARM_VCPU_INIT: - KVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - KVM_RUN and KVM_GET_REG_LIST are not available; - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; - KVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. h](h)}(hKVM_ARM_VCPU_SVE: Enables SVE for the CPU (arm64 only). Depends on KVM_CAP_ARM_SVE. Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):h]hKVM_ARM_VCPU_SVE: Enables SVE for the CPU (arm64 only). Depends on KVM_CAP_ARM_SVE. Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj )}(hXF* After KVM_ARM_VCPU_INIT: - KVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - KVM_RUN and KVM_GET_REG_LIST are not available; - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; - KVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. h]j)}(hhh](j)}(hAfter KVM_ARM_VCPU_INIT: - KVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. h](h)}(hAfter KVM_ARM_VCPU_INIT:h]hAfter KVM_ARM_VCPU_INIT:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj )}(h- KVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. h]j)}(hhh]j)}(hKVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. h]h)}(hKVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host.h]hKVM_REG_ARM64_SVE_VLS may be read using KVM_GET_ONE_REG: the initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hXBefore KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - KVM_RUN and KVM_GET_REG_LIST are not available; - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; - KVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. h](h)}(h/Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):h]h/Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj )}(hXx- KVM_RUN and KVM_GET_REG_LIST are not available; - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; - KVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. h]j)}(hhh](j)}(h0KVM_RUN and KVM_GET_REG_LIST are not available; h]h)}(h/KVM_RUN and KVM_GET_REG_LIST are not available;h]h/KVM_RUN and KVM_GET_REG_LIST are not available;}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj,ubah}(h]h ]h"]h$]h&]uh1jhj)ubj)}(hKVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR; h]h)}(hKVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR;h]hKVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access the scalable architectural SVE registers KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or KVM_REG_ARM64_SVE_FFR;}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjDubah}(h]h ]h"]h$]h&]uh1jhj)ubj)}(hKVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. h]h)}(hKVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu.h]hKVM_REG_ARM64_SVE_VLS may optionally be written using KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj\ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hj%ubah}(h]h ]h"]h$]h&]uh1j hhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hAfter KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): - the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. h](h)}(h.After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):h]h.After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE):}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj )}(hp- the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. h]j)}(hhh]j)}(hlthe KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. h]h)}(hkthe KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG.h]hkthe KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hKVM_ARM_VCPU_HAS_EL2: Enable Nested Virtualisation support, booting the guest from EL2 instead of EL1. Depends on KVM_CAP_ARM_EL2. The VM is running with HCR_EL2.E2H being RES1 (VHE) unless KVM_ARM_VCPU_HAS_EL2_E2H0 is also set. h]h)}(hKVM_ARM_VCPU_HAS_EL2: Enable Nested Virtualisation support, booting the guest from EL2 instead of EL1. Depends on KVM_CAP_ARM_EL2. The VM is running with HCR_EL2.E2H being RES1 (VHE) unless KVM_ARM_VCPU_HAS_EL2_E2H0 is also set.h]hKVM_ARM_VCPU_HAS_EL2: Enable Nested Virtualisation support, booting the guest from EL2 instead of EL1. Depends on KVM_CAP_ARM_EL2. The VM is running with HCR_EL2.E2H being RES1 (VHE) unless KVM_ARM_VCPU_HAS_EL2_E2H0 is also set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hKVM_ARM_VCPU_HAS_EL2_E2H0: Restrict Nested Virtualisation support to HCR_EL2.E2H being RES0 (non-VHE). Depends on KVM_CAP_ARM_EL2_E2H0. KVM_ARM_VCPU_HAS_EL2 must also be set. h]h)}(hKVM_ARM_VCPU_HAS_EL2_E2H0: Restrict Nested Virtualisation support to HCR_EL2.E2H being RES0 (non-VHE). Depends on KVM_CAP_ARM_EL2_E2H0. KVM_ARM_VCPU_HAS_EL2 must also be set.h]hKVM_ARM_VCPU_HAS_EL2_E2H0: Restrict Nested Virtualisation support to HCR_EL2.E2H being RES0 (non-VHE). Depends on KVM_CAP_ARM_EL2_E2H0. KVM_ARM_VCPU_HAS_EL2 must also be set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hhhM hjhhubeh}(h](jid17eh ]h"](4.82 kvm_arm_vcpu_initkvm_arm_vcpu_initeh$]h&]uh1hhjhhhhhM j}jjsj}jjsubh)}(hhh](h)}(h4.83 KVM_ARM_PREFERRED_TARGETh]h4.83 KVM_ARM_PREFERRED_TARGET}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj6hhhKubj)}(hbasich]h)}(hjIh]hbasic}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjGubah}(h]h ]h"]h$]h&]uh1jhj6ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj3hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjdhhhKubj)}(harm64h]h)}(hjwh]harm64}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjuubah}(h]h ]h"]h$]h&]uh1jhjdubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_vcpu_init (out)h]h)}(hjh]hstruct kvm_vcpu_init (out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubeh}(h]h ]h"]h$]h&]uh1jrhj"hhhhhM ubh)}(hErrors:h]hErrors:}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubj )}(h====== ========================================== ENODEV no preferred target available for the host ====== ========================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj8ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK*uh1jchj8ubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(hENODEVh]hENODEV}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjRubj)}(hhh]h)}(h*no preferred target available for the hosth]h*no preferred target available for the host}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjlubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1j~hjOubah}(h]h ]h"]h$]h&]uh1jyhj8ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj5ubah}(h]h ]h"]h$]h&]uh1jYhj1ubah}(h]h ]h"]h$]h&]uh1j hhhMhj"hhubh)}(h_This queries KVM for preferred CPU target type which can be emulated by KVM on underlying host.h]h_This queries KVM for preferred CPU target type which can be emulated by KVM on underlying host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubh)}(hX%The ioctl returns struct kvm_vcpu_init instance containing information about preferred CPU target type and recommended features for it. The kvm_vcpu_init->features bitmap returned will have feature bits set if the preferred target recommends setting these features, but this is not mandatory.h]hX%The ioctl returns struct kvm_vcpu_init instance containing information about preferred CPU target type and recommended features for it. The kvm_vcpu_init->features bitmap returned will have feature bits set if the preferred target recommends setting these features, but this is not mandatory.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubh)}(hThe information returned by this ioctl can be used to prepare an instance of struct kvm_vcpu_init for KVM_ARM_VCPU_INIT ioctl which will result in VCPU matching underlying host.h]hThe information returned by this ioctl can be used to prepare an instance of struct kvm_vcpu_init for KVM_ARM_VCPU_INIT ioctl which will result in VCPU matching underlying host.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj"hhubeh}(h]kvm-arm-preferred-targetah ]h"]4.83 kvm_arm_preferred_targetah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.84 KVM_GET_REG_LISTh]h4.84 KVM_GET_REG_LIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM(ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM*hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h,arm64, mips, riscv, x86 (if KVM_CAP_ONE_REG)h]h)}(hj)h]h,arm64, mips, riscv, x86 (if KVM_CAP_ONE_REG)}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM+hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDhhhKubj)}(h vcpu ioctlh]h)}(hjWh]h vcpu ioctl}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjUubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhM,hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjrhhhKubj)}(hstruct kvm_reg_list (in/out)h]h)}(hjh]hstruct kvm_reg_list (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jwhhhM-hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM.hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM*ubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjhhubj )}(hX ===== ============================================================== E2BIG the reg index list is too big to fit in the array specified by the user (the number required will be written into n). ===== ============================================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jchjubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(hE2BIGh]hE2BIG}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(huthe reg index list is too big to fit in the array specified by the user (the number required will be written into n).h]huthe reg index list is too big to fit in the array specified by the user (the number required will be written into n).}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhM2hjhhubj8)}(h^struct kvm_reg_list { __u64 n; /* number of registers in reg[] */ __u64 reg[0]; };h]h^struct kvm_reg_list { __u64 n; /* number of registers in reg[] */ __u64 reg[0]; };}hjTsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM9hjhhubh)}(hhThis ioctl returns the guest registers that are supported for the KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.h]hhThis ioctl returns the guest registers that are supported for the KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjhhubh)}(hNote that s390 does not support KVM_GET_REG_LIST for historical reasons (read: nobody cared). The set of registers in kernels 4.x and newer is:h]hNote that s390 does not support KVM_GET_REG_LIST for historical reasons (read: nobody cared). The set of registers in kernels 4.x and newer is:}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjhhubj)}(hhh](j)}(hKVM_REG_S390_TODPR h]h)}(hKVM_REG_S390_TODPRh]hKVM_REG_S390_TODPR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_EPOCHDIFF h]h)}(hKVM_REG_S390_EPOCHDIFFh]hKVM_REG_S390_EPOCHDIFF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_CPU_TIMER h]h)}(hKVM_REG_S390_CPU_TIMERh]hKVM_REG_S390_CPU_TIMER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_CLOCK_COMP h]h)}(hKVM_REG_S390_CLOCK_COMPh]hKVM_REG_S390_CLOCK_COMP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_PFTOKEN h]h)}(hKVM_REG_S390_PFTOKENh]hKVM_REG_S390_PFTOKEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_PFCOMPARE h]h)}(hKVM_REG_S390_PFCOMPAREh]hKVM_REG_S390_PFCOMPARE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_PFSELECT h]h)}(hKVM_REG_S390_PFSELECTh]hKVM_REG_S390_PFSELECT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_PP h]h)}(hKVM_REG_S390_PPh]hKVM_REG_S390_PP}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj)ubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubj)}(hKVM_REG_S390_GBEA h]h)}(hKVM_REG_S390_GBEAh]hKVM_REG_S390_GBEA}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjAubah}(h]h ]h"]h$]h&]uh1jhj~hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMDhjhhubh)}(hNote, for x86, all MSRs enumerated by KVM_GET_MSR_INDEX_LIST are supported as type KVM_X86_REG_TYPE_MSR, but are NOT enumerated via KVM_GET_REG_LIST.h]hNote, for x86, all MSRs enumerated by KVM_GET_MSR_INDEX_LIST are supported as type KVM_X86_REG_TYPE_MSR, but are NOT enumerated via KVM_GET_REG_LIST.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjhhubeh}(h]kvm-get-reg-listah ]h"]4.84 kvm_get_reg_listah$]h&]uh1hhjhhhhhM(ubh)}(hhh](h)}(h)4.85 KVM_ARM_SET_DEVICE_ADDR (deprecated)h]h)4.85 KVM_ARM_SET_DEVICE_ADDR (deprecated)}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhhhMZubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_ARM_SET_DEVICE_ADDRh]h)}(hjh]hKVM_CAP_ARM_SET_DEVICE_ADDR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM\hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hjh]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM]hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM^hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h"struct kvm_arm_device_address (in)h]h)}(hj&h]h"struct kvm_arm_device_address (in)}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM_hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjRubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhM`hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjuhhhhhM\ubh)}(hErrors:h]hErrors:}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhjuhhubj )}(hX<====== ============================================ ENODEV The device id is unknown ENXIO Device not supported on current system EEXIST Address already set E2BIG Address outside guest physical address space EBUSY Address overlaps with other device range ====== ============================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK,uh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hENODEVh]hENODEV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hThe device id is unknownh]hThe device id is unknown}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hENXIOh]hENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h&Device not supported on current systemh]h&Device not supported on current system}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEEXISTh]hEEXIST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hAddress already seth]hAddress already set}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hE2BIGh]hE2BIG}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjMubah}(h]h ]h"]h$]h&]uh1jhjJubj)}(hhh]h)}(h,Address outside guest physical address spaceh]h,Address outside guest physical address space}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjdubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEBUSYh]hEBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h(Address overlaps with other device rangeh]h(Address overlaps with other device range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhMdhjuhhubj8)}(hAstruct kvm_arm_device_addr { __u64 id; __u64 addr; };h]hAstruct kvm_arm_device_addr { __u64 id; __u64 addr; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMnhjuhhubh)}(hSpecify a device address in the guest's physical address space where guests can access emulated or directly exposed devices, which the host kernel needs to know about. The id field is an architecture specific identifier for a specific device.h]hSpecify a device address in the guest’s physical address space where guests can access emulated or directly exposed devices, which the host kernel needs to know about. The id field is an architecture specific identifier for a specific device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjuhhubh)}(hqarm64 divides the id field into two parts, a device id and an address type id specific to the individual device::h]hparm64 divides the id field into two parts, a device id and an address type id specific to the individual device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjuhhubj8)}(hbits: | 63 ... 32 | 31 ... 16 | 15 ... 0 | field: | 0x00000000 | device id | addr type id |h]hbits: | 63 ... 32 | 31 ... 16 | 15 ... 0 | field: | 0x00000000 | device id | addr type id |}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM{hjuhhubh)}(hXarm64 currently only require this when using the in-kernel GIC support for the hardware VGIC features, using KVM_ARM_DEVICE_VGIC_V2 as the device id. When setting the base address for the guest's mapping of the VGIC virtual CPU and distributor interface, the ioctl must be called after calling KVM_CREATE_IRQCHIP, but before calling KVM_RUN on any of the VCPUs. Calling this ioctl twice for any of the base addresses will return -EEXIST.h]hXarm64 currently only require this when using the in-kernel GIC support for the hardware VGIC features, using KVM_ARM_DEVICE_VGIC_V2 as the device id. When setting the base address for the guest’s mapping of the VGIC virtual CPU and distributor interface, the ioctl must be called after calling KVM_CREATE_IRQCHIP, but before calling KVM_RUN on any of the VCPUs. Calling this ioctl twice for any of the base addresses will return -EEXIST.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjuhhubh)}(hdNote, this IOCTL is deprecated and the more flexible SET/GET_DEVICE_ATTR API should be used instead.h]hdNote, this IOCTL is deprecated and the more flexible SET/GET_DEVICE_ATTR API should be used instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjuhhubeh}(h]"kvm-arm-set-device-addr-deprecatedah ]h"])4.85 kvm_arm_set_device_addr (deprecated)ah$]h&]uh1hhjhhhhhMZubh)}(hhh](h)}(h4.86 KVM_PPC_RTAS_DEFINE_TOKENh]h4.86 KVM_PPC_RTAS_DEFINE_TOKEN}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hKVM_CAP_PPC_RTASh]h)}(hjTh]hKVM_CAP_PPC_RTAS}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_rtas_token_argsh]h)}(hjh]hstruct kvm_rtas_token_args}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubeh}(h]h ]h"]h$]h&]uh1jrhj-hhhhhMubh)}(hXZDefines a token value for a RTAS (Run Time Abstraction Services) service in order to allow it to be handled in the kernel. The argument struct gives the name of the service, which must be the name of a service that has a kernel-side implementation. If the token value is non-zero, it will be associated with that service, and subsequent RTAS calls by the guest specifying that token will be handled by the kernel. If the token value is 0, then any token associated with the service will be forgotten, and subsequent RTAS calls by the guest for that service will be passed to userspace to be handled.h]hXZDefines a token value for a RTAS (Run Time Abstraction Services) service in order to allow it to be handled in the kernel. The argument struct gives the name of the service, which must be the name of a service that has a kernel-side implementation. If the token value is non-zero, it will be associated with that service, and subsequent RTAS calls by the guest specifying that token will be handled by the kernel. If the token value is 0, then any token associated with the service will be forgotten, and subsequent RTAS calls by the guest for that service will be passed to userspace to be handled.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubeh}(h]kvm-ppc-rtas-define-tokenah ]h"]4.86 kvm_ppc_rtas_define_tokenah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.87 KVM_SET_GUEST_DEBUGh]h4.87 KVM_SET_GUEST_DEBUG}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(hKVM_CAP_SET_GUEST_DEBUGh]h)}(hjkh]hKVM_CAP_SET_GUEST_DEBUG}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86, s390, ppc, arm64h]h)}(hjh]hx86, s390, ppc, arm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_guest_debug (in)h]h)}(hjh]hstruct kvm_guest_debug (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUhhubeh}(h]h ]h"]h$]h&]uh1jrhjDhhhhhMubj8)}(hfstruct kvm_guest_debug { __u32 control; __u32 pad; struct kvm_guest_debug_arch arch; };h]hfstruct kvm_guest_debug { __u32 control; __u32 pad; struct kvm_guest_debug_arch arch; };}hjEsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjDhhubh)}(hSet up the processor specific debug registers and configure vcpu for handling guest debug events. There are two parts to the structure, the first a control bitfield indicates the type of debug events to handle when running. Common control bits are:h]hSet up the processor specific debug registers and configure vcpu for handling guest debug events. There are two parts to the structure, the first a control bitfield indicates the type of debug events to handle when running. Common control bits are:}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDhhubj )}(hw- KVM_GUESTDBG_ENABLE: guest debugging is enabled - KVM_GUESTDBG_SINGLESTEP: the next run should single-step h]j)}(hhh](j)}(h6KVM_GUESTDBG_ENABLE: guest debugging is enabledh]h)}(hjjh]h6KVM_GUESTDBG_ENABLE: guest debugging is enabled}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhubah}(h]h ]h"]h$]h&]uh1jhjeubj)}(hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj:ubj%)}(hhh]h)}(h&the eax value used to obtain the entryh]h&the eax value used to obtain the entry}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubah}(h]h ]h"]h$]h&]uh1j$hj:ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj7ubj)}(hTindex: the ecx value used to obtain the entry (for entries that are affected by ecx)h](j)}(hindex:h]hindex:}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjiubj%)}(hhh]h)}(hMthe ecx value used to obtain the entry (for entries that are affected by ecx)h]hMthe ecx value used to obtain the entry (for entries that are affected by ecx)}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{ubah}(h]h ]h"]h$]h&]uh1j$hjiubeh}(h]h ]h"]h$]h&]uh1jhhhMhj7ubj)}(hflags: an OR of zero or more of the following: KVM_CPUID_FLAG_SIGNIFCANT_INDEX: if the index field is valid eax, ebx, ecx, edx: the values returned by the cpuid instruction for this function/index combination h](j)}(hflags:h]hflags:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM$hjubj%)}(hhh](j )}(hqan OR of zero or more of the following: KVM_CPUID_FLAG_SIGNIFCANT_INDEX: if the index field is valid h](h)}(h'an OR of zero or more of the following:h]h'an OR of zero or more of the following:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj )}(h@KVM_CPUID_FLAG_SIGNIFCANT_INDEX: if the index field is valid h]j )}(hhh]j)}(h=KVM_CPUID_FLAG_SIGNIFCANT_INDEX: if the index field is valid h](j)}(h KVM_CPUID_FLAG_SIGNIFCANT_INDEX:h]h KVM_CPUID_FLAG_SIGNIFCANT_INDEX:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj%)}(hhh]h)}(hif the index field is validh]hif the index field is valid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&]uh1j hhhMhjubeh}(h]h ]h"]h$]h&]uh1j hhhMhjubh)}(heax, ebx, ecx, edx:h]heax, ebx, ecx, edx:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjubj )}(hQthe values returned by the cpuid instruction for this function/index combination h]h)}(hPthe values returned by the cpuid instruction for this function/index combinationh]hPthe values returned by the cpuid instruction for this function/index combination}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1j hhhM#hjubeh}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM$hj7ubeh}(h]h ]h"]h$]h&]uh1j hj3ubah}(h]h ]h"]h$]h&]uh1j hhhMhjhhubeh}(h]kvm-get-emulated-cpuidah ]h"]4.88 kvm_get_emulated_cpuidah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.89 KVM_S390_MEM_OPh]h4.89 KVM_S390_MEM_OP}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjMhhhhhM'ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjahhhKubj)}(hJKVM_CAP_S390_MEM_OP, KVM_CAP_S390_PROTECTED, KVM_CAP_S390_MEM_OP_EXTENSIONh]h)}(hjth]hJKVM_CAP_S390_MEM_OP, KVM_CAP_S390_PROTECTED, KVM_CAP_S390_MEM_OP_EXTENSION}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjrubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jwhhhM)hj^hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM*hj^hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctl, vcpu ioctlh]h)}(hjh]hvm ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM+hj^hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_s390_mem_op (in)h]h)}(hjh]hstruct kvm_s390_mem_op (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM,hj^hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h= 0 on success, < 0 on generic error (e.g. -EFAULT or -ENOMEM), 16 bit program exception code if the access causes such an exception h]h)}(h= 0 on success, < 0 on generic error (e.g. -EFAULT or -ENOMEM), 16 bit program exception code if the access causes such an exceptionh]h= 0 on success, < 0 on generic error (e.g. -EFAULT or -ENOMEM), 16 bit program exception code if the access causes such an exception}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM-hj^hhubeh}(h]h ]h"]h$]h&]uh1jrhjMhhhhhM)ubh)}(hRead or write data from/to the VM's memory. The KVM_CAP_S390_MEM_OP_EXTENSION capability specifies what functionality is supported.h]hRead or write data from/to the VM’s memory. The KVM_CAP_S390_MEM_OP_EXTENSION capability specifies what functionality is supported.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjMhhubh)}(h6Parameters are specified via the following structure::h]h5Parameters are specified via the following structure:}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjMhhubj8)}(hXstruct kvm_s390_mem_op { __u64 gaddr; /* the guest address */ __u64 flags; /* flags */ __u32 size; /* amount of bytes */ __u32 op; /* type of operation */ __u64 buf; /* buffer in userspace */ union { struct { __u8 ar; /* the access register number */ __u8 key; /* access key, ignored if flag unset */ __u8 pad1[6]; /* ignored */ __u64 old_addr; /* ignored if flag unset */ }; __u32 sida_offset; /* offset into the sida */ __u8 reserved[32]; /* ignored */ }; };h]hXstruct kvm_s390_mem_op { __u64 gaddr; /* the guest address */ __u64 flags; /* flags */ __u32 size; /* amount of bytes */ __u32 op; /* type of operation */ __u64 buf; /* buffer in userspace */ union { struct { __u8 ar; /* the access register number */ __u8 key; /* access key, ignored if flag unset */ __u8 pad1[6]; /* ignored */ __u64 old_addr; /* ignored if flag unset */ }; __u32 sida_offset; /* offset into the sida */ __u8 reserved[32]; /* ignored */ }; };}hjjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM7hjMhhubh)}(hXLThe start address of the memory region has to be specified in the "gaddr" field, and the length of the region in the "size" field (which must not be 0). The maximum value for "size" can be obtained by checking the KVM_CAP_S390_MEM_OP capability. "buf" is the buffer supplied by the userspace application where the read data should be written to for a read access, or where the data that should be written is stored for a write access. The "reserved" field is meant for future extensions. Reserved and unused values are ignored. Future extension that add members must introduce new flags.h]hX`The start address of the memory region has to be specified in the “gaddr” field, and the length of the region in the “size” field (which must not be 0). The maximum value for “size” can be obtained by checking the KVM_CAP_S390_MEM_OP capability. “buf” is the buffer supplied by the userspace application where the read data should be written to for a read access, or where the data that should be written is stored for a write access. The “reserved” field is meant for future extensions. Reserved and unused values are ignored. Future extension that add members must introduce new flags.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhjMhhubh)}(hThe type of operation is specified in the "op" field. Flags modifying their behavior can be set in the "flags" field. Undefined flag bits must be set to 0.h]hThe type of operation is specified in the “op” field. Flags modifying their behavior can be set in the “flags” field. Undefined flag bits must be set to 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShjMhhubj )}(hhh]j)}(hX Possible operations are: * ``KVM_S390_MEMOP_LOGICAL_READ`` * ``KVM_S390_MEMOP_LOGICAL_WRITE`` * ``KVM_S390_MEMOP_ABSOLUTE_READ`` * ``KVM_S390_MEMOP_ABSOLUTE_WRITE`` * ``KVM_S390_MEMOP_SIDA_READ`` * ``KVM_S390_MEMOP_SIDA_WRITE`` * ``KVM_S390_MEMOP_ABSOLUTE_CMPXCHG`` h](j)}(hPossible operations are:h]hPossible operations are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM^hjubj%)}(hhh]j)}(hhh](j)}(h``KVM_S390_MEMOP_LOGICAL_READ``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_LOGICAL_READ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMXhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h ``KVM_S390_MEMOP_LOGICAL_WRITE``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_LOGICAL_WRITE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h ``KVM_S390_MEMOP_ABSOLUTE_READ``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_ABSOLUTE_READ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h!``KVM_S390_MEMOP_ABSOLUTE_WRITE``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_ABSOLUTE_WRITE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM[hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h``KVM_S390_MEMOP_SIDA_READ``h]h)}(hj1h]j)}(hj1h]hKVM_S390_MEMOP_SIDA_READ}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubah}(h]h ]h"]h$]h&]uh1hhhhM\hj/ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h``KVM_S390_MEMOP_SIDA_WRITE``h]h)}(hjQh]j)}(hjQh]hKVM_S390_MEMOP_SIDA_WRITE}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubah}(h]h ]h"]h$]h&]uh1hhhhM]hjOubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h$``KVM_S390_MEMOP_ABSOLUTE_CMPXCHG`` h]h)}(h#``KVM_S390_MEMOP_ABSOLUTE_CMPXCHG``h]j)}(hjuh]hKVM_S390_MEMOP_ABSOLUTE_CMPXCHG}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjsubah}(h]h ]h"]h$]h&]uh1hhhhM^hjoubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhMXhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhM^hjubah}(h]h ]h"]h$]h&]uh1j hjMhhhNhNubh)}(hhh](h)}(hLogical read/write:h]hLogical read/write:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMaubh)}(hXmAccess logical memory, i.e. translate the given guest address to an absolute address given the state of the VCPU and use the absolute address as target of the access. "ar" designates the access register number to be used; the valid range is 0..15. Logical accesses are permitted for the VCPU ioctl only. Logical accesses are permitted for non-protected guests only.h]hXqAccess logical memory, i.e. translate the given guest address to an absolute address given the state of the VCPU and use the absolute address as target of the access. “ar” designates the access register number to be used; the valid range is 0..15. Logical accesses are permitted for the VCPU ioctl only. Logical accesses are permitted for non-protected guests only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjhhubj )}(hhh]j)}(hSupported flags: * ``KVM_S390_MEMOP_F_CHECK_ONLY`` * ``KVM_S390_MEMOP_F_INJECT_EXCEPTION`` * ``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h](j)}(hSupported flags:h]hSupported flags:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMmhjubj%)}(hhh]j)}(hhh](j)}(h``KVM_S390_MEMOP_F_CHECK_ONLY``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_F_CHECK_ONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMkhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h%``KVM_S390_MEMOP_F_INJECT_EXCEPTION``h]h)}(hjh]j)}(hjh]h!KVM_S390_MEMOP_F_INJECT_EXCEPTION}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h%``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h]h)}(h$``KVM_S390_MEMOP_F_SKEY_PROTECTION``h]j)}(hj(h]h KVM_S390_MEMOP_F_SKEY_PROTECTION}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubah}(h]h ]h"]h$]h&]uh1hhhhMmhj"ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhMkhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMmhjubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(hXThe KVM_S390_MEMOP_F_CHECK_ONLY flag can be set to check whether the corresponding memory access would cause an access exception; however, no actual access to the data in memory at the destination is performed. In this case, "buf" is unused and can be NULL.h]hXThe KVM_S390_MEMOP_F_CHECK_ONLY flag can be set to check whether the corresponding memory access would cause an access exception; however, no actual access to the data in memory at the destination is performed. In this case, “buf” is unused and can be NULL.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjhhubh)}(hXIn case an access exception occurred during the access (or would occur in case of KVM_S390_MEMOP_F_CHECK_ONLY), the ioctl returns a positive error number indicating the type of exception. This exception is also raised directly at the corresponding VCPU if the flag KVM_S390_MEMOP_F_INJECT_EXCEPTION is set. On protection exceptions, unless specified otherwise, the injected translation-exception identifier (TEID) indicates suppression.h]hXIn case an access exception occurred during the access (or would occur in case of KVM_S390_MEMOP_F_CHECK_ONLY), the ioctl returns a positive error number indicating the type of exception. This exception is also raised directly at the corresponding VCPU if the flag KVM_S390_MEMOP_F_INJECT_EXCEPTION is set. On protection exceptions, unless specified otherwise, the injected translation-exception identifier (TEID) indicates suppression.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjhhubh)}(hX7If the KVM_S390_MEMOP_F_SKEY_PROTECTION flag is set, storage key protection is also in effect and may cause exceptions if accesses are prohibited given the access key designated by "key"; the valid range is 0..15. KVM_S390_MEMOP_F_SKEY_PROTECTION is available if KVM_CAP_S390_MEM_OP_EXTENSION is > 0. Since the accessed memory may span multiple pages and those pages might have different storage keys, it is possible that a protection exception occurs after memory has been modified. In this case, if the exception is injected, the TEID does not indicate suppression.h]hX;If the KVM_S390_MEMOP_F_SKEY_PROTECTION flag is set, storage key protection is also in effect and may cause exceptions if accesses are prohibited given the access key designated by “key”; the valid range is 0..15. KVM_S390_MEMOP_F_SKEY_PROTECTION is available if KVM_CAP_S390_MEM_OP_EXTENSION is > 0. Since the accessed memory may span multiple pages and those pages might have different storage keys, it is possible that a protection exception occurs after memory has been modified. In this case, if the exception is injected, the TEID does not indicate suppression.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjhhubeh}(h]logical-read-writeah ]h"]logical read/write:ah$]h&]uh1hhjMhhhhhMaubh)}(hhh](h)}(hAbsolute read/write:h]hAbsolute read/write:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX|Access absolute memory. This operation is intended to be used with the KVM_S390_MEMOP_F_SKEY_PROTECTION flag, to allow accessing memory and performing the checks required for storage key protection as one operation (as opposed to user space getting the storage keys, performing the checks, and accessing memory thereafter, which could lead to a delay between check and access). Absolute accesses are permitted for the VM ioctl if KVM_CAP_S390_MEM_OP_EXTENSION has the KVM_S390_MEMOP_EXTENSION_CAP_BASE bit set. Currently absolute accesses are not permitted for VCPU ioctls. Absolute accesses are permitted for non-protected guests only.h]hX|Access absolute memory. This operation is intended to be used with the KVM_S390_MEMOP_F_SKEY_PROTECTION flag, to allow accessing memory and performing the checks required for storage key protection as one operation (as opposed to user space getting the storage keys, performing the checks, and accessing memory thereafter, which could lead to a delay between check and access). Absolute accesses are permitted for the VM ioctl if KVM_CAP_S390_MEM_OP_EXTENSION has the KVM_S390_MEMOP_EXTENSION_CAP_BASE bit set. Currently absolute accesses are not permitted for VCPU ioctls. Absolute accesses are permitted for non-protected guests only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hhh]j)}(hZSupported flags: * ``KVM_S390_MEMOP_F_CHECK_ONLY`` * ``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h](j)}(hSupported flags:h]hSupported flags:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj%)}(hhh]j)}(hhh](j)}(h``KVM_S390_MEMOP_F_CHECK_ONLY``h]h)}(hjh]j)}(hjh]hKVM_S390_MEMOP_F_CHECK_ONLY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h%``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h]h)}(h$``KVM_S390_MEMOP_F_SKEY_PROTECTION``h]j)}(hjh]h KVM_S390_MEMOP_F_SKEY_PROTECTION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j$hjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjubah}(h]h ]h"]h$]h&]uh1j hjhhhNhNubh)}(hTThe semantics of the flags common with logical accesses are as for logical accesses.h]hTThe semantics of the flags common with logical accesses are as for logical accesses.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]absolute-read-writeah ]h"]absolute read/write:ah$]h&]uh1hhjMhhhhhMubh)}(hhh](h)}(hAbsolute cmpxchg:h]hAbsolute cmpxchg:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6hhhhhMubh)}(hXPerform cmpxchg on absolute guest memory. Intended for use with the KVM_S390_MEMOP_F_SKEY_PROTECTION flag. Instead of doing an unconditional write, the access occurs only if the target location contains the value pointed to by "old_addr". This is performed as an atomic cmpxchg with the length specified by the "size" parameter. "size" must be a power of two up to and including 16. If the exchange did not take place because the target value doesn't match the old value, the value "old_addr" points to is replaced by the target value. User space can tell if an exchange took place by checking if this replacement occurred. The cmpxchg op is permitted for the VM ioctl if KVM_CAP_S390_MEM_OP_EXTENSION has flag KVM_S390_MEMOP_EXTENSION_CAP_CMPXCHG set.h]hXPerform cmpxchg on absolute guest memory. Intended for use with the KVM_S390_MEMOP_F_SKEY_PROTECTION flag. Instead of doing an unconditional write, the access occurs only if the target location contains the value pointed to by “old_addr”. This is performed as an atomic cmpxchg with the length specified by the “size” parameter. “size” must be a power of two up to and including 16. If the exchange did not take place because the target value doesn’t match the old value, the value “old_addr” points to is replaced by the target value. User space can tell if an exchange took place by checking if this replacement occurred. The cmpxchg op is permitted for the VM ioctl if KVM_CAP_S390_MEM_OP_EXTENSION has flag KVM_S390_MEMOP_EXTENSION_CAP_CMPXCHG set.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6hhubj )}(hhh]j)}(h8Supported flags: * ``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h](j)}(hSupported flags:h]hSupported flags:}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjXubj%)}(hhh]j)}(hhh]j)}(h%``KVM_S390_MEMOP_F_SKEY_PROTECTION`` h]h)}(h$``KVM_S390_MEMOP_F_SKEY_PROTECTION``h]j)}(hjvh]h KVM_S390_MEMOP_F_SKEY_PROTECTION}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]jjuh1jhhhMhjjubah}(h]h ]h"]h$]h&]uh1j$hjXubeh}(h]h ]h"]h$]h&]uh1jhhhMhjUubah}(h]h ]h"]h$]h&]uh1j hj6hhhNhNubeh}(h]absolute-cmpxchgah ]h"]absolute cmpxchg:ah$]h&]uh1hhjMhhhhhMubh)}(hhh](h)}(hSIDA read/write:h]hSIDA read/write:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hX?Access the secure instruction data area which contains memory operands necessary for instruction emulation for protected guests. SIDA accesses are available if the KVM_CAP_S390_PROTECTED capability is available. SIDA accesses are permitted for the VCPU ioctl only. SIDA accesses are permitted for protected guests only.h]hX?Access the secure instruction data area which contains memory operands necessary for instruction emulation for protected guests. SIDA accesses are available if the KVM_CAP_S390_PROTECTED capability is available. SIDA accesses are permitted for the VCPU ioctl only. SIDA accesses are permitted for protected guests only.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hNo flags are supported.h]hNo flags are supported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]sida-read-writeah ]h"]sida read/write:ah$]h&]uh1hhjMhhhhhMubeh}(h]kvm-s390-mem-opah ]h"]4.89 kvm_s390_mem_opah$]h&]uh1hhjhhhhhM'ubh)}(hhh](h)}(h4.90 KVM_S390_GET_SKEYSh]h4.90 KVM_S390_GET_SKEYS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_S390_SKEYSh]h)}(hjh]hKVM_CAP_S390_SKEYS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj0hhhKubj)}(hs390h]h)}(hjCh]hs390}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1jhj0ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^hhhKubj)}(hvm ioctlh]h)}(hjqh]hvm ioctl}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_s390_skeysh]h)}(hjh]hstruct kvm_s390_skeys}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hb0 on success, KVM_S390_GET_SKEYS_NONE if guest is not using storage keys, negative value on error h]h)}(ha0 on success, KVM_S390_GET_SKEYS_NONE if guest is not using storage keys, negative value on errorh]ha0 on success, KVM_S390_GET_SKEYS_NONE if guest is not using storage keys, negative value on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hThis ioctl is used to get guest storage key values on the s390 architecture. The ioctl takes parameters via the kvm_s390_skeys struct::h]hThis ioctl is used to get guest storage key values on the s390 architecture. The ioctl takes parameters via the kvm_s390_skeys struct:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hstruct kvm_s390_skeys { __u64 start_gfn; __u64 count; __u64 skeydata_addr; __u32 flags; __u32 reserved[9]; };h]hstruct kvm_s390_skeys { __u64 start_gfn; __u64 count; __u64 skeydata_addr; __u32 flags; __u32 reserved[9]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(h^The start_gfn field is the number of the first guest frame whose storage keys you want to get.h]h^The start_gfn field is the number of the first guest frame whose storage keys you want to get.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hX The count field is the number of consecutive frames (starting from start_gfn) whose storage keys to get. The count field must be at least 1 and the maximum allowed value is defined as KVM_S390_SKEYS_MAX. Values outside this range will cause the ioctl to return -EINVAL.h]hX The count field is the number of consecutive frames (starting from start_gfn) whose storage keys to get. The count field must be at least 1 and the maximum allowed value is defined as KVM_S390_SKEYS_MAX. Values outside this range will cause the ioctl to return -EINVAL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hThe skeydata_addr field is the address to a buffer large enough to hold count bytes. This buffer will be filled with storage key data by the ioctl.h]hThe skeydata_addr field is the address to a buffer large enough to hold count bytes. This buffer will be filled with storage key data by the ioctl.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-s390-get-skeysah ]h"]4.90 kvm_s390_get_skeysah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.91 KVM_S390_SET_SKEYSh]h4.91 KVM_S390_SET_SKEYS}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQhhhKubj)}(hKVM_CAP_S390_SKEYSh]h)}(hjdh]hKVM_CAP_S390_SKEYS}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjbubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_s390_skeysh]h)}(hjh]hstruct kvm_s390_skeys}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h&0 on success, negative value on error h]h)}(h%0 on success, negative value on errorh]h%0 on success, negative value on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjNhhubeh}(h]h ]h"]h$]h&]uh1jrhj=hhhhhMubh)}(hThis ioctl is used to set guest storage key values on the s390 architecture. The ioctl takes parameters via the kvm_s390_skeys struct. See section on KVM_S390_GET_SKEYS for struct definition.h]hThis ioctl is used to set guest storage key values on the s390 architecture. The ioctl takes parameters via the kvm_s390_skeys struct. See section on KVM_S390_GET_SKEYS for struct definition.}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubh)}(h^The start_gfn field is the number of the first guest frame whose storage keys you want to set.h]h^The start_gfn field is the number of the first guest frame whose storage keys you want to set.}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubh)}(hX The count field is the number of consecutive frames (starting from start_gfn) whose storage keys to get. The count field must be at least 1 and the maximum allowed value is defined as KVM_S390_SKEYS_MAX. Values outside this range will cause the ioctl to return -EINVAL.h]hX The count field is the number of consecutive frames (starting from start_gfn) whose storage keys to get. The count field must be at least 1 and the maximum allowed value is defined as KVM_S390_SKEYS_MAX. Values outside this range will cause the ioctl to return -EINVAL.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubh)}(hThe skeydata_addr field is the address to a buffer containing count bytes of storage keys. Each byte in the buffer will be set as the storage key for a single frame starting at start_gfn for count frames.h]hThe skeydata_addr field is the address to a buffer containing count bytes of storage keys. Each byte in the buffer will be set as the storage key for a single frame starting at start_gfn for count frames.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubh)}(hmNote: If any architecturally invalid key value is found in the given data then the ioctl will return -EINVAL.h]hmNote: If any architecturally invalid key value is found in the given data then the ioctl will return -EINVAL.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=hhubeh}(h]kvm-s390-set-skeysah ]h"]4.91 kvm_s390_set_skeysah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.92 KVM_S390_IRQh]h4.92 KVM_S390_IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_S390_INJECT_IRQh]h)}(hjh]hKVM_CAP_S390_INJECT_IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj*hhhKubj)}(hstruct kvm_s390_irq (in)h]h)}(hj=h]hstruct kvm_s390_irq (in)}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hXK====== ================================================================= EINVAL interrupt type is invalid type is KVM_S390_SIGP_STOP and flag parameter is invalid value, type is KVM_S390_INT_EXTERNAL_CALL and code is bigger than the maximum of VCPUs EBUSY type is KVM_S390_SIGP_SET_PREFIX and vcpu is not stopped, type is KVM_S390_SIGP_STOP and a stop irq is already pending, type is KVM_S390_INT_EXTERNAL_CALL and an external call interrupt is already pending ====== ================================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKAuh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hinterrupt type is invalid type is KVM_S390_SIGP_STOP and flag parameter is invalid value, type is KVM_S390_INT_EXTERNAL_CALL and code is bigger than the maximum of VCPUsh]hinterrupt type is invalid type is KVM_S390_SIGP_STOP and flag parameter is invalid value, type is KVM_S390_INT_EXTERNAL_CALL and code is bigger than the maximum of VCPUs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEBUSYh]hEBUSY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(htype is KVM_S390_SIGP_SET_PREFIX and vcpu is not stopped, type is KVM_S390_SIGP_STOP and a stop irq is already pending, type is KVM_S390_INT_EXTERNAL_CALL and an external call interrupt is already pendingh]htype is KVM_S390_SIGP_SET_PREFIX and vcpu is not stopped, type is KVM_S390_SIGP_STOP and a stop irq is already pending, type is KVM_S390_INT_EXTERNAL_CALL and an external call interrupt is already pending}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhMhjhhubh)}(h+Allows to inject an interrupt to the guest.h]h+Allows to inject an interrupt to the guest.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hzUsing struct kvm_s390_irq as a parameter allows to inject additional payload which is not possible via KVM_S390_INTERRUPT.h]hzUsing struct kvm_s390_irq as a parameter allows to inject additional payload which is not possible via KVM_S390_INTERRUPT.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h2Interrupt parameters are passed via kvm_s390_irq::h]h1Interrupt parameters are passed via kvm_s390_irq:}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hXstruct kvm_s390_irq { __u64 type; union { struct kvm_s390_io_info io; struct kvm_s390_ext_info ext; struct kvm_s390_pgm_info pgm; struct kvm_s390_emerg_info emerg; struct kvm_s390_extcall_info extcall; struct kvm_s390_prefix_info prefix; struct kvm_s390_stop_info stop; struct kvm_s390_mchk_info mchk; char reserved[64]; } u; };h]hXstruct kvm_s390_irq { __u64 type; union { struct kvm_s390_io_info io; struct kvm_s390_ext_info ext; struct kvm_s390_pgm_info pgm; struct kvm_s390_emerg_info emerg; struct kvm_s390_extcall_info extcall; struct kvm_s390_prefix_info prefix; struct kvm_s390_stop_info stop; struct kvm_s390_mchk_info mchk; char reserved[64]; } u; };}hjmsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(h!type can be one of the following:h]h!type can be one of the following:}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjhhubj)}(hhh](j)}(h2KVM_S390_SIGP_STOP - sigp stop; parameter in .stoph]h)}(hjh]h2KVM_S390_SIGP_STOP - sigp stop; parameter in .stop}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h8KVM_S390_PROGRAM_INT - program check; parameters in .pgmh]h)}(hjh]h8KVM_S390_PROGRAM_INT - program check; parameters in .pgm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hAKVM_S390_SIGP_SET_PREFIX - sigp set prefix; parameters in .prefixh]h)}(hjh]hAKVM_S390_SIGP_SET_PREFIX - sigp set prefix; parameters in .prefix}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h)KVM_S390_RESTART - restart; no parametersh]h)}(hjh]h)KVM_S390_RESTART - restart; no parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hCKVM_S390_INT_CLOCK_COMP - clock comparator interrupt; no parametersh]h)}(hjh]hCKVM_S390_INT_CLOCK_COMP - clock comparator interrupt; no parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h;KVM_S390_INT_CPU_TIMER - CPU timer interrupt; no parametersh]h)}(hjh]h;KVM_S390_INT_CPU_TIMER - CPU timer interrupt; no parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h=KVM_S390_INT_EMERGENCY - sigp emergency; parameters in .emergh]h)}(hjh]h=KVM_S390_INT_EMERGENCY - sigp emergency; parameters in .emerg}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hGKVM_S390_INT_EXTERNAL_CALL - sigp external call; parameters in .extcallh]h)}(hj/h]hGKVM_S390_INT_EXTERNAL_CALL - sigp external call; parameters in .extcall}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hj-ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h=KVM_S390_MCHK - machine check interrupt; parameters in .mchk h]h)}(h= number of bytes copied into buffer, -EINVAL if buffer size is 0, -ENOBUFS if buffer size is too small to fit all pending interrupts, -EFAULT if the buffer address was invalid h]h)}(h>= number of bytes copied into buffer, -EINVAL if buffer size is 0, -ENOBUFS if buffer size is too small to fit all pending interrupts, -EFAULT if the buffer address was invalidh]h>= number of bytes copied into buffer, -EINVAL if buffer size is 0, -ENOBUFS if buffer size is too small to fit all pending interrupts, -EFAULT if the buffer address was invalid}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hjUubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjxhhhhhM2ubh)}(hThis ioctl allows userspace to retrieve the complete state of all currently pending interrupts in a single buffer. Use cases include migration and introspection. The parameter structure contains the address of a userspace buffer and its length::h]hThis ioctl allows userspace to retrieve the complete state of all currently pending interrupts in a single buffer. Use cases include migration and introspection. The parameter structure contains the address of a userspace buffer and its length:}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjxhhubj8)}(hstruct kvm_s390_irq_state { __u64 buf; __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; __u32 reserved[4]; /* will stay unused for compatibility reasons */ };h]hstruct kvm_s390_irq_state { __u64 buf; __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; __u32 reserved[4]; /* will stay unused for compatibility reasons */ };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM@hjxhhubh)}(h{Userspace passes in the above struct and for each pending interrupt a struct kvm_s390_irq is copied to the provided buffer.h]h{Userspace passes in the above struct and for each pending interrupt a struct kvm_s390_irq is copied to the provided buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjxhhubh)}(hThe structure contains a flags and a reserved field for future extensions. As the kernel never checked for flags == 0 and QEMU never pre-zeroed flags and reserved, these fields can not be used in the future without breaking compatibility.h]hThe structure contains a flags and a reserved field for future extensions. As the kernel never checked for flags == 0 and QEMU never pre-zeroed flags and reserved, these fields can not be used in the future without breaking compatibility.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjxhhubh)}(hgIf -ENOBUFS is returned the buffer provided was too small and userspace may retry with a bigger buffer.h]hgIf -ENOBUFS is returned the buffer provided was too small and userspace may retry with a bigger buffer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjxhhubeh}(h]kvm-s390-get-irq-stateah ]h"]4.94 kvm_s390_get_irq_stateah$]h&]uh1hhjhhhhhM0ubh)}(hhh](h)}(h4.95 KVM_S390_SET_IRQ_STATEh]h4.95 KVM_S390_SET_IRQ_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMSubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_S390_IRQ_STATEh]h)}(hjh]hKVM_CAP_S390_IRQ_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMUhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMVhjhhubjx)}(hhh](j})}(hTypeh]hType}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(h vcpu ioctlh]h)}(hjJh]h vcpu ioctl}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjHubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhMWhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjehhhKubj)}(hstruct kvm_s390_irq_state (in)h]h)}(hjxh]hstruct kvm_s390_irq_state (in)}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjvubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jwhhhMXhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EFAULT if the buffer address was invalid, -EINVAL for an invalid buffer length (see below), -EBUSY if there were already interrupts pending, errors occurring when actually injecting the interrupt. See KVM_S390_IRQ. h]h)}(h0 on success, -EFAULT if the buffer address was invalid, -EINVAL for an invalid buffer length (see below), -EBUSY if there were already interrupts pending, errors occurring when actually injecting the interrupt. See KVM_S390_IRQ.h]h0 on success, -EFAULT if the buffer address was invalid, -EINVAL for an invalid buffer length (see below), -EBUSY if there were already interrupts pending, errors occurring when actually injecting the interrupt. See KVM_S390_IRQ.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMYhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMUubh)}(hXThis ioctl allows userspace to set the complete state of all cpu-local interrupts currently pending for the vcpu. It is intended for restoring interrupt state after a migration. The input parameter is a userspace buffer containing a struct kvm_s390_irq_state::h]hXThis ioctl allows userspace to set the complete state of all cpu-local interrupts currently pending for the vcpu. It is intended for restoring interrupt state after a migration. The input parameter is a userspace buffer containing a struct kvm_s390_irq_state:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjhhubj8)}(hstruct kvm_s390_irq_state { __u64 buf; __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; __u32 reserved[4]; /* will stay unused for compatibility reasons */ };h]hstruct kvm_s390_irq_state { __u64 buf; __u32 flags; /* will stay unused for compatibility reasons */ __u32 len; __u32 reserved[4]; /* will stay unused for compatibility reasons */ };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMehjhhubh)}(hSThe restrictions for flags and reserved apply as well. (see KVM_S390_GET_IRQ_STATE)h]hSThe restrictions for flags and reserved apply as well. (see KVM_S390_GET_IRQ_STATE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjhhubh)}(hThe userspace memory referenced by buf contains a struct kvm_s390_irq for each interrupt to be injected into the guest. If one of the interrupts could not be injected for some reason the ioctl aborts.h]hThe userspace memory referenced by buf contains a struct kvm_s390_irq for each interrupt to be injected into the guest. If one of the interrupts could not be injected for some reason the ioctl aborts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjhhubh)}(hlen must be a multiple of sizeof(struct kvm_s390_irq). It must be > 0 and it must not exceed (max_vcpus + 32) * sizeof(struct kvm_s390_irq), which is the maximum number of possibly pending cpu-local interrupts.h]hlen must be a multiple of sizeof(struct kvm_s390_irq). It must be > 0 and it must not exceed (max_vcpus + 32) * sizeof(struct kvm_s390_irq), which is the maximum number of possibly pending cpu-local interrupts.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjhhubeh}(h]kvm-s390-set-irq-stateah ]h"]4.95 kvm_s390_set_irq_stateah$]h&]uh1hhjhhhhhMSubh)}(hhh](h)}(h 4.96 KVM_SMIh]h 4.96 KVM_SMI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMyubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj*hhhKubj)}(hKVM_CAP_X86_SMMh]h)}(hj=h]hKVM_CAP_X86_SMM}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj;ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jwhhhM{hj'hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXhhhKubj)}(hx86h]h)}(hjkh]hx86}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjiubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]uh1jwhhhM|hj'hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM}hj'hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM~hj'hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj'hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM{ubh)}(h#Queues an SMI on the thread's vcpu.h]h%Queues an SMI on the thread’s vcpu.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-smiah ]h"] 4.96 kvm_smiah$]h&]uh1hhjhhhhhMyubh)}(hhh](h)}(h4.97 KVM_X86_SET_MSR_FILTERh]h4.97 KVM_X86_SET_MSR_FILTER}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(hKVM_CAP_X86_MSR_FILTERh]h)}(hjTh]hKVM_CAP_X86_MSR_FILTER}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_msr_filterh]h)}(hjh]hstruct kvm_msr_filter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj>hhubeh}(h]h ]h"]h$]h&]uh1jrhj-hhhhhMubj8)}(hX)struct kvm_msr_filter_range { #define KVM_MSR_FILTER_READ (1 << 0) #define KVM_MSR_FILTER_WRITE (1 << 1) __u32 flags; __u32 nmsrs; /* number of msrs in bitmap */ __u32 base; /* MSR index the bitmap starts at */ __u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */ }; #define KVM_MSR_FILTER_MAX_RANGES 16 struct kvm_msr_filter { #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0) #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0) __u32 flags; struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES]; };h]hX)struct kvm_msr_filter_range { #define KVM_MSR_FILTER_READ (1 << 0) #define KVM_MSR_FILTER_WRITE (1 << 1) __u32 flags; __u32 nmsrs; /* number of msrs in bitmap */ __u32 base; /* MSR index the bitmap starts at */ __u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */ }; #define KVM_MSR_FILTER_MAX_RANGES 16 struct kvm_msr_filter { #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0) #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0) __u32 flags; struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES]; };}hj.sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj-hhubh)}(h1flags values for ``struct kvm_msr_filter_range``:h](hflags values for }(hj<hhhNhNubj)}(h``struct kvm_msr_filter_range``h]hstruct kvm_msr_filter_range}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh:}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(h``KVM_MSR_FILTER_READ``h]j)}(hj^h]hKVM_MSR_FILTER_READ}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubj )}(hFilter read accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that read accesses should be denied, while a 1 indicates that a read for a particular MSR should be allowed regardless of the default filter action. h]h)}(hFilter read accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that read accesses should be denied, while a 1 indicates that a read for a particular MSR should be allowed regardless of the default filter action.h]hFilter read accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that read accesses should be denied, while a 1 indicates that a read for a particular MSR should be allowed regardless of the default filter action.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1j hhhMhj-hhubh)}(h``KVM_MSR_FILTER_WRITE``h]j)}(hjh]hKVM_MSR_FILTER_WRITE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubj )}(hFilter write accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that write accesses should be denied, while a 1 indicates that a write for a particular MSR should be allowed regardless of the default filter action. h]h)}(hFilter write accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that write accesses should be denied, while a 1 indicates that a write for a particular MSR should be allowed regardless of the default filter action.h]hFilter write accesses to MSRs using the given bitmap. A 0 in the bitmap indicates that write accesses should be denied, while a 1 indicates that a write for a particular MSR should be allowed regardless of the default filter action.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hhhMhj-hhubh)}(h+flags values for ``struct kvm_msr_filter``:h](hflags values for }(hjhhhNhNubj)}(h``struct kvm_msr_filter``h]hstruct kvm_msr_filter}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(h ``KVM_MSR_FILTER_DEFAULT_ALLOW``h]j)}(hjh]hKVM_MSR_FILTER_DEFAULT_ALLOW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubj )}(hrIf no filter range matches an MSR index that is getting accessed, KVM will allow accesses to all MSRs by default. h]h)}(hqIf no filter range matches an MSR index that is getting accessed, KVM will allow accesses to all MSRs by default.h]hqIf no filter range matches an MSR index that is getting accessed, KVM will allow accesses to all MSRs by default.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j hhhMhj-hhubh)}(h``KVM_MSR_FILTER_DEFAULT_DENY``h]j)}(hj h]hKVM_MSR_FILTER_DEFAULT_DENY}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubj )}(hqIf no filter range matches an MSR index that is getting accessed, KVM will deny accesses to all MSRs by default. h]h)}(hpIf no filter range matches an MSR index that is getting accessed, KVM will deny accesses to all MSRs by default.h]hpIf no filter range matches an MSR index that is getting accessed, KVM will deny accesses to all MSRs by default.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj-hhubh)}(hXThis ioctl allows userspace to define up to 16 bitmaps of MSR ranges to deny guest MSR accesses that would normally be allowed by KVM. If an MSR is not covered by a specific range, the "default" filtering behavior applies. Each bitmap range covers MSRs from [base .. base+nmsrs).h]hXThis ioctl allows userspace to define up to 16 bitmaps of MSR ranges to deny guest MSR accesses that would normally be allowed by KVM. If an MSR is not covered by a specific range, the “default” filtering behavior applies. Each bitmap range covers MSRs from [base .. base+nmsrs).}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(hXGIf an MSR access is denied by userspace, the resulting KVM behavior depends on whether or not KVM_CAP_X86_USER_SPACE_MSR's KVM_MSR_EXIT_REASON_FILTER is enabled. If KVM_MSR_EXIT_REASON_FILTER is enabled, KVM will exit to userspace on denied accesses, i.e. userspace effectively intercepts the MSR access. If KVM_MSR_EXIT_REASON_FILTER is not enabled, KVM will inject a #GP into the guest on denied accesses. Note, if an MSR access is denied during emulation of MSR load/stores during VMX transitions, KVM ignores KVM_MSR_EXIT_REASON_FILTER. See the below warning for full details.h]hXIIf an MSR access is denied by userspace, the resulting KVM behavior depends on whether or not KVM_CAP_X86_USER_SPACE_MSR’s KVM_MSR_EXIT_REASON_FILTER is enabled. If KVM_MSR_EXIT_REASON_FILTER is enabled, KVM will exit to userspace on denied accesses, i.e. userspace effectively intercepts the MSR access. If KVM_MSR_EXIT_REASON_FILTER is not enabled, KVM will inject a #GP into the guest on denied accesses. Note, if an MSR access is denied during emulation of MSR load/stores during VMX transitions, KVM ignores KVM_MSR_EXIT_REASON_FILTER. See the below warning for full details.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(hX#If an MSR access is allowed by userspace, KVM will emulate and/or virtualize the access in accordance with the vCPU model. Note, KVM may still ultimately inject a #GP if an access is allowed by userspace, e.g. if KVM doesn't support the MSR, or to follow architectural behavior for the MSR.h]hX%If an MSR access is allowed by userspace, KVM will emulate and/or virtualize the access in accordance with the vCPU model. Note, KVM may still ultimately inject a #GP if an access is allowed by userspace, e.g. if KVM doesn’t support the MSR, or to follow architectural behavior for the MSR.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(hXBy default, KVM operates in KVM_MSR_FILTER_DEFAULT_ALLOW mode with no MSR range filters.h]hXBy default, KVM operates in KVM_MSR_FILTER_DEFAULT_ALLOW mode with no MSR range filters.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(hCalling this ioctl with an empty set of ranges (all nmsrs == 0) disables MSR filtering. In that mode, ``KVM_MSR_FILTER_DEFAULT_DENY`` is invalid and causes an error.h](hfCalling this ioctl with an empty set of ranges (all nmsrs == 0) disables MSR filtering. In that mode, }(hjphhhNhNubj)}(h``KVM_MSR_FILTER_DEFAULT_DENY``h]hKVM_MSR_FILTER_DEFAULT_DENY}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubh is invalid and causes an error.}(hjphhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubj?)}(hX MSR accesses that are side effects of instruction execution (emulated or native) are not filtered as hardware does not honor MSR bitmaps outside of RDMSR and WRMSR, and KVM mimics that behavior when emulating instructions to avoid pointless divergence from hardware. E.g. RDPID reads MSR_TSC_AUX, SYSENTER reads the SYSENTER MSRs, etc. MSRs that are loaded/stored via dedicated VMCS fields are not filtered as part of VM-Enter/VM-Exit emulation. MSRs that are loaded/store via VMX's load/store lists _are_ filtered as part of VM-Enter/VM-Exit emulation. If an MSR access is denied on VM-Enter, KVM synthesizes a consistency check VM-Exit(EXIT_REASON_MSR_LOAD_FAIL). If an MSR access is denied on VM-Exit, KVM synthesizes a VM-Abort. In short, KVM extends Intel's architectural list of MSRs that cannot be loaded/saved via the VM-Enter/VM-Exit MSR list. It is platform owner's responsibility to to communicate any such restrictions to their end users. x2APIC MSR accesses cannot be filtered (KVM silently ignores filters that cover any x2APIC MSRs).h](h)}(hXPMSR accesses that are side effects of instruction execution (emulated or native) are not filtered as hardware does not honor MSR bitmaps outside of RDMSR and WRMSR, and KVM mimics that behavior when emulating instructions to avoid pointless divergence from hardware. E.g. RDPID reads MSR_TSC_AUX, SYSENTER reads the SYSENTER MSRs, etc.h]hXPMSR accesses that are side effects of instruction execution (emulated or native) are not filtered as hardware does not honor MSR bitmaps outside of RDMSR and WRMSR, and KVM mimics that behavior when emulating instructions to avoid pointless divergence from hardware. E.g. RDPID reads MSR_TSC_AUX, SYSENTER reads the SYSENTER MSRs, etc.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hmMSRs that are loaded/stored via dedicated VMCS fields are not filtered as part of VM-Enter/VM-Exit emulation.h]hmMSRs that are loaded/stored via dedicated VMCS fields are not filtered as part of VM-Enter/VM-Exit emulation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hXMSRs that are loaded/store via VMX's load/store lists _are_ filtered as part of VM-Enter/VM-Exit emulation. If an MSR access is denied on VM-Enter, KVM synthesizes a consistency check VM-Exit(EXIT_REASON_MSR_LOAD_FAIL). If an MSR access is denied on VM-Exit, KVM synthesizes a VM-Abort. In short, KVM extends Intel's architectural list of MSRs that cannot be loaded/saved via the VM-Enter/VM-Exit MSR list. It is platform owner's responsibility to to communicate any such restrictions to their end users.h]hXMSRs that are loaded/store via VMX’s load/store lists _are_ filtered as part of VM-Enter/VM-Exit emulation. If an MSR access is denied on VM-Enter, KVM synthesizes a consistency check VM-Exit(EXIT_REASON_MSR_LOAD_FAIL). If an MSR access is denied on VM-Exit, KVM synthesizes a VM-Abort. In short, KVM extends Intel’s architectural list of MSRs that cannot be loaded/saved via the VM-Enter/VM-Exit MSR list. It is platform owner’s responsibility to to communicate any such restrictions to their end users.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(hax2APIC MSR accesses cannot be filtered (KVM silently ignores filters that cover any x2APIC MSRs).h]hax2APIC MSR accesses cannot be filtered (KVM silently ignores filters that cover any x2APIC MSRs).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1j?hj-hhhhhNubh)}(hXNote, invoking this ioctl while a vCPU is running is inherently racy. However, KVM does guarantee that vCPUs will see either the previous filter or the new filter, e.g. MSRs with identical settings in both the old and new filter will have deterministic behavior.h]hXNote, invoking this ioctl while a vCPU is running is inherently racy. However, KVM does guarantee that vCPUs will see either the previous filter or the new filter, e.g. MSRs with identical settings in both the old and new filter will have deterministic behavior.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubh)}(hXSimilarly, if userspace wishes to intercept on denied accesses, KVM_MSR_EXIT_REASON_FILTER must be enabled before activating any filters, and left enabled until after all filters are deactivated. Failure to do so may result in KVM injecting a #GP instead of exiting to userspace.h]hXSimilarly, if userspace wishes to intercept on denied accesses, KVM_MSR_EXIT_REASON_FILTER must be enabled before activating any filters, and left enabled until after all filters are deactivated. Failure to do so may result in KVM injecting a #GP instead of exiting to userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-hhubeh}(h]kvm-x86-set-msr-filterah ]h"]4.97 kvm_x86_set_msr_filterah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.98 KVM_CREATE_SPAPR_TCE_64h]h4.98 KVM_CREATE_SPAPR_TCE_64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hKVM_CAP_SPAPR_TCE_64h]h)}(hjh]hKVM_CAP_SPAPR_TCE_64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(hpowerpch]h)}(hjKh]hpowerpc}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjfhhhKubj)}(hvm ioctlh]h)}(hjyh]hvm ioctl}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwubah}(h]h ]h"]h$]h&]uh1jhjfubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h#struct kvm_create_spapr_tce_64 (in)h]h)}(hjh]h#struct kvm_create_spapr_tce_64 (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h7file descriptor for manipulating the created TCE table h]h)}(h6file descriptor for manipulating the created TCE tableh]h6file descriptor for manipulating the created TCE table}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(htThis is an extension for KVM_CAP_SPAPR_TCE which only supports 32bit windows, described in 4.62 KVM_CREATE_SPAPR_TCEh]htThis is an extension for KVM_CAP_SPAPR_TCE which only supports 32bit windows, described in 4.62 KVM_CREATE_SPAPR_TCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h9This capability uses extended struct in ioctl interface::h]h8This capability uses extended struct in ioctl interface:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(h/* for KVM_CAP_SPAPR_TCE_64 */ struct kvm_create_spapr_tce_64 { __u64 liobn; __u32 page_shift; __u32 flags; __u64 offset; /* in pages */ __u64 size; /* in pages */ };h]h/* for KVM_CAP_SPAPR_TCE_64 */ struct kvm_create_spapr_tce_64 { __u64 liobn; __u32 page_shift; __u32 flags; __u64 offset; /* in pages */ __u64 size; /* in pages */ };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(hXThe aim of extension is to support an additional bigger DMA window with a variable page size. KVM_CREATE_SPAPR_TCE_64 receives a 64bit window size, an IOMMU page shift and a bus offset of the corresponding DMA window, @size and @offset are numbers of IOMMU pages.h]hXThe aim of extension is to support an additional bigger DMA window with a variable page size. KVM_CREATE_SPAPR_TCE_64 receives a 64bit window size, an IOMMU page shift and a bus offset of the corresponding DMA window, @size and @offset are numbers of IOMMU pages.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(h"@flags are not used at the moment.h]h"@flags are not used at the moment.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h?The rest of functionality is identical to KVM_CREATE_SPAPR_TCE.h]h?The rest of functionality is identical to KVM_CREATE_SPAPR_TCE.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-create-spapr-tce-64ah ]h"]4.98 kvm_create_spapr_tce_64ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.99 KVM_REINJECT_CONTROLh]h4.99 KVM_REINJECT_CONTROL}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjghhhKubj)}(hKVM_CAP_REINJECT_CONTROLh]h)}(hjzh]hKVM_CAP_REINJECT_CONTROL}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjxubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h struct kvm_reinject_control (in)h]h)}(hjh]h struct kvm_reinject_control (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EFAULT if struct kvm_reinject_control cannot be read, -ENXIO if KVM_CREATE_PIT or KVM_CREATE_PIT2 didn't succeed earlier. h]h)}(h0 on success, -EFAULT if struct kvm_reinject_control cannot be read, -ENXIO if KVM_CREATE_PIT or KVM_CREATE_PIT2 didn't succeed earlier.h]h0 on success, -EFAULT if struct kvm_reinject_control cannot be read, -ENXIO if KVM_CREATE_PIT or KVM_CREATE_PIT2 didn’t succeed earlier.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubeh}(h]h ]h"]h$]h&]uh1jrhjShhhhhMubh)}(hXfi8254 (PIT) has two modes, reinject and !reinject. The default is reinject, where KVM queues elapsed i8254 ticks and monitors completion of interrupt from vector(s) that i8254 injects. Reinject mode dequeues a tick and injects its interrupt whenever there isn't a pending interrupt from i8254. !reinject mode injects an interrupt as soon as a tick arrives.h]hXhi8254 (PIT) has two modes, reinject and !reinject. The default is reinject, where KVM queues elapsed i8254 ticks and monitors completion of interrupt from vector(s) that i8254 injects. Reinject mode dequeues a tick and injects its interrupt whenever there isn’t a pending interrupt from i8254. !reinject mode injects an interrupt as soon as a tick arrives.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjShhubj8)}(hRstruct kvm_reinject_control { __u8 pit_reinject; __u8 reserved[31]; };h]hRstruct kvm_reinject_control { __u8 pit_reinject; __u8 reserved[31]; };}hjbsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM(hjShhubh)}(hpit_reinject = 0 (!reinject mode) is recommended, unless running an old operating system that uses the PIT for timing (e.g. Linux 2.4.x).h]hpit_reinject = 0 (!reinject mode) is recommended, unless running an old operating system that uses the PIT for timing (e.g. Linux 2.4.x).}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjShhubeh}(h]kvm-reinject-controlah ]h"]4.99 kvm_reinject_controlah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.100 KVM_PPC_CONFIGURE_V3_MMUh]h4.100 KVM_PPC_CONFIGURE_V3_MMU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM1ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0KVM_CAP_PPC_MMU_RADIX or KVM_CAP_PPC_MMU_HASH_V3h]h)}(hjh]h0KVM_CAP_PPC_MMU_RADIX or KVM_CAP_PPC_MMU_HASH_V3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM3hjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM4hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hj h]hvm ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM5hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(hstruct kvm_ppc_mmuv3_cfg (in)h]h)}(hj7h]hstruct kvm_ppc_mmuv3_cfg (in)}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj5ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hj0 on success, -EFAULT if struct kvm_ppc_mmuv3_cfg cannot be read, -EINVAL if the configuration is invalid h]h)}(hi0 on success, -EFAULT if struct kvm_ppc_mmuv3_cfg cannot be read, -EINVAL if the configuration is invalidh]hi0 on success, -EFAULT if struct kvm_ppc_mmuv3_cfg cannot be read, -EINVAL if the configuration is invalid}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjcubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhM7hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM3ubh)}(hThis ioctl controls whether the guest will use radix or HPT (hashed page table) translation, and sets the pointer to the process table for the guest.h]hThis ioctl controls whether the guest will use radix or HPT (hashed page table) translation, and sets the pointer to the process table for the guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjhhubj8)}(hOstruct kvm_ppc_mmuv3_cfg { __u64 flags; __u64 process_table; };h]hOstruct kvm_ppc_mmuv3_cfg { __u64 flags; __u64 process_table; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMAhjhhubh)}(hXThere are two bits that can be set in flags; KVM_PPC_MMUV3_RADIX and KVM_PPC_MMUV3_GTSE. KVM_PPC_MMUV3_RADIX, if set, configures the guest to use radix tree translation, and if clear, to use HPT translation. KVM_PPC_MMUV3_GTSE, if set and if KVM permits it, configures the guest to be able to use the global TLB and SLB invalidation instructions; if clear, the guest may not use these instructions.h]hXThere are two bits that can be set in flags; KVM_PPC_MMUV3_RADIX and KVM_PPC_MMUV3_GTSE. KVM_PPC_MMUV3_RADIX, if set, configures the guest to use radix tree translation, and if clear, to use HPT translation. KVM_PPC_MMUV3_GTSE, if set and if KVM permits it, configures the guest to be able to use the global TLB and SLB invalidation instructions; if clear, the guest may not use these instructions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjhhubh)}(hThe process_table field specifies the address and size of the guest process table, which is in the guest's space. This field is formatted as the second doubleword of the partition table entry, as defined in the Power ISA V3.00, Book III section 5.7.6.1.h]hXThe process_table field specifies the address and size of the guest process table, which is in the guest’s space. This field is formatted as the second doubleword of the partition table entry, as defined in the Power ISA V3.00, Book III section 5.7.6.1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjhhubeh}(h]kvm-ppc-configure-v3-mmuah ]h"]4.100 kvm_ppc_configure_v3_mmuah$]h&]uh1hhjhhhhhM1ubh)}(hhh](h)}(h4.101 KVM_PPC_GET_RMMU_INFOh]h4.101 KVM_PPC_GET_RMMU_INFO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMSubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_PPC_MMU_RADIXh]h)}(hjh]hKVM_CAP_PPC_MMU_RADIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMUhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMVhjhhubjx)}(hhh](j})}(hTypeh]hType}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(hvm ioctlh]h)}(hjJh]hvm ioctl}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjHubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhMWhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjehhhKubj)}(hstruct kvm_ppc_rmmu_info (out)h]h)}(hjxh]hstruct kvm_ppc_rmmu_info (out)}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjvubah}(h]h ]h"]h$]h&]uh1jhjeubeh}(h]h ]h"]h$]h&]uh1jwhhhMXhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hv0 on success, -EFAULT if struct kvm_ppc_rmmu_info cannot be written, -EINVAL if no useful information can be returned h]h)}(hu0 on success, -EFAULT if struct kvm_ppc_rmmu_info cannot be written, -EINVAL if no useful information can be returnedh]hu0 on success, -EFAULT if struct kvm_ppc_rmmu_info cannot be written, -EINVAL if no useful information can be returned}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMYhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMUubh)}(hThis ioctl returns a structure containing two things: (a) a list containing supported radix tree geometries, and (b) a list that maps page sizes to put in the "AP" (actual page size) field for the tlbie (TLB invalidate entry) instruction.h]hThis ioctl returns a structure containing two things: (a) a list containing supported radix tree geometries, and (b) a list that maps page sizes to put in the “AP” (actual page size) field for the tlbie (TLB invalidate entry) instruction.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjhhubj8)}(hstruct kvm_ppc_rmmu_info { struct kvm_ppc_radix_geom { __u8 page_shift; __u8 level_bits[4]; __u8 pad[3]; } geometries[8]; __u32 ap_encodings[8]; };h]hstruct kvm_ppc_rmmu_info { struct kvm_ppc_radix_geom { __u8 page_shift; __u8 level_bits[4]; __u8 pad[3]; } geometries[8]; __u32 ap_encodings[8]; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMdhjhhubh)}(hX2The geometries[] field gives up to 8 supported geometries for the radix page table, in terms of the log base 2 of the smallest page size, and the number of bits indexed at each level of the tree, from the PTE level up to the PGD level in that order. Any unused entries will have 0 in the page_shift field.h]hX2The geometries[] field gives up to 8 supported geometries for the radix page table, in terms of the log base 2 of the smallest page size, and the number of bits indexed at each level of the tree, from the PTE level up to the PGD level in that order. Any unused entries will have 0 in the page_shift field.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjhhubh)}(hThe ap_encodings gives the supported page sizes and their AP field encodings, encoded with the AP value in the top 3 bits and the log base 2 of the page size in the bottom 6 bits.h]hThe ap_encodings gives the supported page sizes and their AP field encodings, encoded with the AP value in the top 3 bits and the log base 2 of the page size in the bottom 6 bits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjhhubeh}(h]kvm-ppc-get-rmmu-infoah ]h"]4.101 kvm_ppc_get_rmmu_infoah$]h&]uh1hhjhhhhhMSubh)}(hhh](h)}(h 4.102 KVM_PPC_RESIZE_HPT_PREPAREh]h 4.102 KVM_PPC_RESIZE_HPT_PREPARE}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMxubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_SPAPR_RESIZE_HPTh]h)}(hj/h]hKVM_CAP_SPAPR_RESIZE_HPT}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMzhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJhhhKubj)}(hpowerpch]h)}(hj]h]hpowerpc}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj[ubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jwhhhM{hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM|hjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jwhhhM|hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_ppc_resize_hpt (in)h]h)}(hjh]hstruct kvm_ppc_resize_hpt (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM}hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hX%0 on successful completion, >0 if a new HPT is being prepared, the value is an estimated number of milliseconds until preparation is complete, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENOMEM if unable to allocate the new HPT, h]h)}(hX$0 on successful completion, >0 if a new HPT is being prepared, the value is an estimated number of milliseconds until preparation is complete, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENOMEM if unable to allocate the new HPT,h]hX$0 on successful completion, >0 if a new HPT is being prepared, the value is an estimated number of milliseconds until preparation is complete, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENOMEM if unable to allocate the new HPT,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM~hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMzubh)}(hUsed to implement the PAPR extension for runtime resizing of a guest's Hashed Page Table (HPT). Specifically this starts, stops or monitors the preparation of a new potential HPT for the guest, essentially implementing the H_RESIZE_HPT_PREPARE hypercall.h]hXUsed to implement the PAPR extension for runtime resizing of a guest’s Hashed Page Table (HPT). Specifically this starts, stops or monitors the preparation of a new potential HPT for the guest, essentially implementing the H_RESIZE_HPT_PREPARE hypercall.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hUstruct kvm_ppc_resize_hpt { __u64 flags; __u32 shift; __u32 pad; };h]hUstruct kvm_ppc_resize_hpt { __u64 flags; __u32 shift; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(hIf called with shift > 0 when there is no pending HPT for the guest, this begins preparation of a new pending HPT of size 2^(shift) bytes. It then returns a positive integer with the estimated number of milliseconds until preparation is complete.h]hIf called with shift > 0 when there is no pending HPT for the guest, this begins preparation of a new pending HPT of size 2^(shift) bytes. It then returns a positive integer with the estimated number of milliseconds until preparation is complete.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hIf called when there is a pending HPT whose size does not match that requested in the parameters, discards the existing pending HPT and creates a new one as above.h]hIf called when there is a pending HPT whose size does not match that requested in the parameters, discards the existing pending HPT and creates a new one as above.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hBIf called when there is a pending HPT of the size requested, will:h]hBIf called when there is a pending HPT of the size requested, will:}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj )}(hX.* If preparation of the pending HPT is already complete, return 0 * If preparation of the pending HPT has failed, return an error code, then discard the pending HPT. * If preparation of the pending HPT is still in progress, return an estimated number of milliseconds until preparation is complete. h]j)}(hhh](j)}(h?If preparation of the pending HPT is already complete, return 0h]h)}(hjXh]h?If preparation of the pending HPT is already complete, return 0}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(haIf preparation of the pending HPT has failed, return an error code, then discard the pending HPT.h]h)}(haIf preparation of the pending HPT has failed, return an error code, then discard the pending HPT.h]haIf preparation of the pending HPT has failed, return an error code, then discard the pending HPT.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjmubah}(h]h ]h"]h$]h&]uh1jhjSubj)}(hIf preparation of the pending HPT is still in progress, return an estimated number of milliseconds until preparation is complete. h]h)}(hIf preparation of the pending HPT is still in progress, return an estimated number of milliseconds until preparation is complete.h]hIf preparation of the pending HPT is still in progress, return an estimated number of milliseconds until preparation is complete.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjOubah}(h]h ]h"]h$]h&]uh1j hhhMhjhhubh)}(hwIf called with shift == 0, discards any currently pending HPT and returns 0 (i.e. cancels any in-progress preparation).h]hwIf called with shift == 0, discards any currently pending HPT and returns 0 (i.e. cancels any in-progress preparation).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hfflags is reserved for future expansion, currently setting any bits in flags will result in an -EINVAL.h]hfflags is reserved for future expansion, currently setting any bits in flags will result in an -EINVAL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hNormally this will be called repeatedly with the same parameters until it returns <= 0. The first call will initiate preparation, subsequent ones will monitor preparation until it completes or fails.h]hNormally this will be called repeatedly with the same parameters until it returns <= 0. The first call will initiate preparation, subsequent ones will monitor preparation until it completes or fails.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-ppc-resize-hpt-prepareah ]h"] 4.102 kvm_ppc_resize_hpt_prepareah$]h&]uh1hhjhhhhhMxubh)}(hhh](h)}(h4.103 KVM_PPC_RESIZE_HPT_COMMITh]h4.103 KVM_PPC_RESIZE_HPT_COMMIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_SPAPR_RESIZE_HPTh]h)}(hjh]hKVM_CAP_SPAPR_RESIZE_HPT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hpowerpch]h)}(hj0h]hpowerpc}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hvm ioctlh]h)}(hj^h]hvm ioctl}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hstruct kvm_ppc_resize_hpt (in)h]h)}(hjh]hstruct kvm_ppc_resize_hpt (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hX0 on successful completion, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENXIO is there is no pending HPT, or the pending HPT doesn't have the requested size, -EBUSY if the pending HPT is not fully prepared, -ENOSPC if there was a hash collision when moving existing HPT entries to the new HPT, -EIO on other error conditions h]h)}(hX0 on successful completion, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENXIO is there is no pending HPT, or the pending HPT doesn't have the requested size, -EBUSY if the pending HPT is not fully prepared, -ENOSPC if there was a hash collision when moving existing HPT entries to the new HPT, -EIO on other error conditionsh]hX0 on successful completion, -EFAULT if struct kvm_reinject_control cannot be read, -EINVAL if the supplied shift or flags are invalid, -ENXIO is there is no pending HPT, or the pending HPT doesn’t have the requested size, -EBUSY if the pending HPT is not fully prepared, -ENOSPC if there was a hash collision when moving existing HPT entries to the new HPT, -EIO on other error conditions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hUsed to implement the PAPR extension for runtime resizing of a guest's Hashed Page Table (HPT). Specifically this requests that the guest be transferred to working with the new HPT, essentially implementing the H_RESIZE_HPT_COMMIT hypercall.h]hUsed to implement the PAPR extension for runtime resizing of a guest’s Hashed Page Table (HPT). Specifically this requests that the guest be transferred to working with the new HPT, essentially implementing the H_RESIZE_HPT_COMMIT hypercall.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hUstruct kvm_ppc_resize_hpt { __u64 flags; __u32 shift; __u32 pad; };h]hUstruct kvm_ppc_resize_hpt { __u64 flags; __u32 shift; __u32 pad; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(hX This should only be called after KVM_PPC_RESIZE_HPT_PREPARE has returned 0 with the same parameters. In other cases KVM_PPC_RESIZE_HPT_COMMIT will return an error (usually -ENXIO or -EBUSY, though others may be possible if the preparation was started, but failed).h]hX This should only be called after KVM_PPC_RESIZE_HPT_PREPARE has returned 0 with the same parameters. In other cases KVM_PPC_RESIZE_HPT_COMMIT will return an error (usually -ENXIO or -EBUSY, though others may be possible if the preparation was started, but failed).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hThis will have undefined effects on the guest if it has not already placed itself in a quiescent state where no vcpu will make MMU enabled memory accesses.h]hThis will have undefined effects on the guest if it has not already placed itself in a quiescent state where no vcpu will make MMU enabled memory accesses.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(htOn successful completion, the pending HPT will become the guest's active HPT and the previous HPT will be discarded.h]hvOn successful completion, the pending HPT will become the guest’s active HPT and the previous HPT will be discarded.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hBOn failure, the guest will still be operating on its previous HPT.h]hBOn failure, the guest will still be operating on its previous HPT.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-ppc-resize-hpt-commitah ]h"]4.103 kvm_ppc_resize_hpt_commitah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h#4.104 KVM_X86_GET_MCE_CAP_SUPPORTEDh]h#4.104 KVM_X86_GET_MCE_CAP_SUPPORTED}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(h KVM_CAP_MCEh]h)}(hj_h]h KVM_CAP_MCE}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]ubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjzhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h system ioctlh]h)}(hjh]h system ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hu64 mce_cap (out)h]h)}(hjh]hu64 mce_cap (out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubeh}(h]h ]h"]h$]h&]uh1jrhj8hhhhhMubh)}(hReturns supported MCE capabilities. The u64 mce_cap parameter has the same format as the MSR_IA32_MCG_CAP register. Supported capabilities will have the corresponding bits set.h]hReturns supported MCE capabilities. The u64 mce_cap parameter has the same format as the MSR_IA32_MCG_CAP register. Supported capabilities will have the corresponding bits set.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8hhubeh}(h]kvm-x86-get-mce-cap-supportedah ]h"]#4.104 kvm_x86_get_mce_cap_supportedah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.105 KVM_X86_SETUP_MCEh]h4.105 KVM_X86_SETUP_MCE}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjOhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjchhhKubj)}(h KVM_CAP_MCEh]h)}(hjvh]h KVM_CAP_MCE}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjtubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj`hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj`hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj`hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hu64 mcg_cap (in)h]h)}(hjh]hu64 mcg_cap (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj`hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EFAULT if u64 mcg_cap cannot be read, -EINVAL if the requested number of banks is invalid, -EINVAL if requested MCE capability is not supported. h]h)}(h0 on success, -EFAULT if u64 mcg_cap cannot be read, -EINVAL if the requested number of banks is invalid, -EINVAL if requested MCE capability is not supported.h]h0 on success, -EFAULT if u64 mcg_cap cannot be read, -EINVAL if the requested number of banks is invalid, -EINVAL if requested MCE capability is not supported.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj`hhubeh}(h]h ]h"]h$]h&]uh1jrhjOhhhhhMubh)}(hXYInitializes MCE support for use. The u64 mcg_cap parameter has the same format as the MSR_IA32_MCG_CAP register and specifies which capabilities should be enabled. The maximum supported number of error-reporting banks can be retrieved when checking for KVM_CAP_MCE. The supported capabilities can be retrieved with KVM_X86_GET_MCE_CAP_SUPPORTED.h]hXYInitializes MCE support for use. The u64 mcg_cap parameter has the same format as the MSR_IA32_MCG_CAP register and specifies which capabilities should be enabled. The maximum supported number of error-reporting banks can be retrieved when checking for KVM_CAP_MCE. The supported capabilities can be retrieved with KVM_X86_GET_MCE_CAP_SUPPORTED.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjOhhubeh}(h]kvm-x86-setup-mceah ]h"]4.105 kvm_x86_setup_mceah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.106 KVM_X86_SET_MCEh]h4.106 KVM_X86_SET_MCE}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjzhhhKubj)}(h KVM_CAP_MCEh]h)}(hjh]h KVM_CAP_MCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hjh]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_x86_mce (in)h]h)}(hjh]hstruct kvm_x86_mce (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj2hhhKubj)}(h0 on success, -EFAULT if struct kvm_x86_mce cannot be read, -EINVAL if the bank number is invalid, -EINVAL if VAL bit is not set in status field. h]h)}(h0 on success, -EFAULT if struct kvm_x86_mce cannot be read, -EINVAL if the bank number is invalid, -EINVAL if VAL bit is not set in status field.h]h0 on success, -EFAULT if struct kvm_x86_mce cannot be read, -EINVAL if the bank number is invalid, -EINVAL if VAL bit is not set in status field.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjCubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubeh}(h]h ]h"]h$]h&]uh1jrhjfhhhhhMubh)}(hKInject a machine check error (MCE) into the guest. The input parameter is::h]hJInject a machine check error (MCE) into the guest. The input parameter is:}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfhhubj8)}(hstruct kvm_x86_mce { __u64 status; __u64 addr; __u64 misc; __u64 mcg_status; __u8 bank; __u8 pad1[7]; __u64 pad2[3]; };h]hstruct kvm_x86_mce { __u64 status; __u64 addr; __u64 misc; __u64 mcg_status; __u8 bank; __u8 pad1[7]; __u64 pad2[3]; };}hjusbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjfhhubh)}(hIf the MCE being reported is an uncorrected error, KVM will inject it as an MCE exception into the guest. If the guest MCG_STATUS register reports that an MCE is in progress, KVM causes an KVM_EXIT_SHUTDOWN vmexit.h]hIf the MCE being reported is an uncorrected error, KVM will inject it as an MCE exception into the guest. If the guest MCG_STATUS register reports that an MCE is in progress, KVM causes an KVM_EXIT_SHUTDOWN vmexit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfhhubh)}(hOtherwise, if the MCE is a corrected error, KVM will just store it in the corresponding bank (provided this bank is not holding a previously reported uncorrected error).h]hOtherwise, if the MCE is a corrected error, KVM will just store it in the corresponding bank (provided this bank is not holding a previously reported uncorrected error).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfhhubeh}(h]kvm-x86-set-mceah ]h"]4.106 kvm_x86_set_mceah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.107 KVM_S390_GET_CMMA_BITSh]h4.107 KVM_S390_GET_CMMA_BITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_S390_CMMA_MIGRATIONh]h)}(hjh]hKVM_CAP_S390_CMMA_MIGRATION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hj*h]hvm ioctl}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM!hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(h"struct kvm_s390_cmma_log (in, out)h]h)}(hjXh]h"struct kvm_s390_cmma_log (in, out)}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjVubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjshhhKubj)}(h(0 on success, a negative value on error h]h)}(h'0 on success, a negative value on errorh]h'0 on success, a negative value on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubj )}(hX_====== ============================================================= ENOMEM not enough memory can be allocated to complete the task ENXIO if CMMA is not enabled EINVAL if KVM_S390_CMMA_PEEK is not set but migration mode was not enabled EINVAL if KVM_S390_CMMA_PEEK is not set but dirty tracking has been disabled (and thus migration mode was automatically disabled) EFAULT if the userspace address is invalid or if no page table is present for the addresses (e.g. when using hugepages). ====== ============================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKCuh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hENOMEMh]hENOMEM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h7not enough memory can be allocated to complete the taskh]h7not enough memory can be allocated to complete the task}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hENXIOh]hENXIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hif CMMA is not enabledh]hif CMMA is not enabled}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj(ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hjHubah}(h]h ]h"]h$]h&]uh1jhjEubj)}(hhh]h)}(hCif KVM_S390_CMMA_PEEK is not set but migration mode was not enabledh]hCif KVM_S390_CMMA_PEEK is not set but migration mode was not enabled}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*hj_ubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjubah}(h]h ]h"]h$]h&]uh1jhj|ubj)}(hhh]h)}(hzif KVM_S390_CMMA_PEEK is not set but dirty tracking has been disabled (and thus migration mode was automatically disabled)h]hzif KVM_S390_CMMA_PEEK is not set but dirty tracking has been disabled (and thus migration mode was automatically disabled)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEFAULTh]hEFAULT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hqif the userspace address is invalid or if no page table is present for the addresses (e.g. when using hugepages).h]hqif the userspace address is invalid or if no page table is present for the addresses (e.g. when using hugepages).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhM'hjhhubh)}(hxThis ioctl is used to get the values of the CMMA bits on the s390 architecture. It is meant to be used in two scenarios:h]hxThis ioctl is used to get the values of the CMMA bits on the s390 architecture. It is meant to be used in two scenarios:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjhhubj)}(hhh](j)}(h~During live migration to save the CMMA values. Live migration needs to be enabled via the KVM_REQ_START_MIGRATION VM property.h]h)}(h~During live migration to save the CMMA values. Live migration needs to be enabled via the KVM_REQ_START_MIGRATION VM property.h]h~During live migration to save the CMMA values. Live migration needs to be enabled via the KVM_REQ_START_MIGRATION VM property.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hTTo non-destructively peek at the CMMA values, with the flag KVM_S390_CMMA_PEEK set. h]h)}(hSTo non-destructively peek at the CMMA values, with the flag KVM_S390_CMMA_PEEK set.h]hSTo non-destructively peek at the CMMA values, with the flag KVM_S390_CMMA_PEEK set.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj,ubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM4hjhhubh)}(hThe ioctl takes parameters via the kvm_s390_cmma_log struct. The desired values are written to a buffer whose location is indicated via the "values" member in the kvm_s390_cmma_log struct. The values in the input struct are also updated as needed.h]hThe ioctl takes parameters via the kvm_s390_cmma_log struct. The desired values are written to a buffer whose location is indicated via the “values” member in the kvm_s390_cmma_log struct. The values in the input struct are also updated as needed.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjhhubh)}(h"Each CMMA value takes up one byte.h]h"Each CMMA value takes up one byte.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjhhubj8)}(hstruct kvm_s390_cmma_log { __u64 start_gfn; __u32 count; __u32 flags; union { __u64 remaining; __u64 mask; }; __u64 values; };h]hstruct kvm_s390_cmma_log { __u64 start_gfn; __u32 count; __u32 flags; union { __u64 remaining; __u64 mask; }; __u64 values; };}hjfsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMBhjhhubh)}(hWstart_gfn is the number of the first guest frame whose CMMA values are to be retrieved,h]hWstart_gfn is the number of the first guest frame whose CMMA values are to be retrieved,}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjhhubh)}(h+count is the length of the buffer in bytes,h]h+count is the length of the buffer in bytes,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjhhubh)}(h@values points to the buffer where the result will be written to.h]h@values points to the buffer where the result will be written to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhjhhubh)}(hIf count is greater than KVM_S390_SKEYS_MAX, then it is considered to be KVM_S390_SKEYS_MAX. KVM_S390_SKEYS_MAX is re-used for consistency with other ioctls.h]hIf count is greater than KVM_S390_SKEYS_MAX, then it is considered to be KVM_S390_SKEYS_MAX. KVM_S390_SKEYS_MAX is re-used for consistency with other ioctls.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjhhubh)}(hThe result is written in the buffer pointed to by the field values, and the values of the input parameter are updated as follows.h]hThe result is written in the buffer pointed to by the field values, and the values of the input parameter are updated as follows.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjhhubh)}(hnDepending on the flags, different actions are performed. The only supported flag so far is KVM_S390_CMMA_PEEK.h]hnDepending on the flags, different actions are performed. The only supported flag so far is KVM_S390_CMMA_PEEK.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjhhubh)}(hThe default behaviour if KVM_S390_CMMA_PEEK is not set is: start_gfn will indicate the first page frame whose CMMA bits were dirty. It is not necessarily the same as the one passed as input, as clean pages are skipped.h]hThe default behaviour if KVM_S390_CMMA_PEEK is not set is: start_gfn will indicate the first page frame whose CMMA bits were dirty. It is not necessarily the same as the one passed as input, as clean pages are skipped.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hjhhubh)}(hXcount will indicate the number of bytes actually written in the buffer. It can (and very often will) be smaller than the input value, since the buffer is only filled until 16 bytes of clean values are found (which are then not copied in the buffer). Since a CMMA migration block needs the base address and the length, for a total of 16 bytes, we will send back some clean data if there is some dirty data afterwards, as long as the size of the clean data does not exceed the size of the header. This allows to minimize the amount of data to be saved or transferred over the network at the expense of more roundtrips to userspace. The next invocation of the ioctl will skip over all the clean values, saving potentially more than just the 16 bytes we found.h]hXcount will indicate the number of bytes actually written in the buffer. It can (and very often will) be smaller than the input value, since the buffer is only filled until 16 bytes of clean values are found (which are then not copied in the buffer). Since a CMMA migration block needs the base address and the length, for a total of 16 bytes, we will send back some clean data if there is some dirty data afterwards, as long as the size of the clean data does not exceed the size of the header. This allows to minimize the amount of data to be saved or transferred over the network at the expense of more roundtrips to userspace. The next invocation of the ioctl will skip over all the clean values, saving potentially more than just the 16 bytes we found.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjhhubh)}(hIf KVM_S390_CMMA_PEEK is set: the existing storage attributes are read even when not in migration mode, and no other action is performed;h]hIf KVM_S390_CMMA_PEEK is set: the existing storage attributes are read even when not in migration mode, and no other action is performed;}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjhhubh)}(h:the output start_gfn will be equal to the input start_gfn,h]h:the output start_gfn will be equal to the input start_gfn,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjhhubh)}(h`the output count will be equal to the input count, except if the end of memory has been reached.h]h`the output count will be equal to the input count, except if the end of memory has been reached.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjhhubh)}(hIn both cases: the field "remaining" will indicate the total number of dirty CMMA values still remaining, or 0 if KVM_S390_CMMA_PEEK is set and migration mode is not enabled.h]hIn both cases: the field “remaining” will indicate the total number of dirty CMMA values still remaining, or 0 if KVM_S390_CMMA_PEEK is set and migration mode is not enabled.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjhhubh)}(hmask is unused.h]hmask is unused.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hjhhubh)}(hFvalues points to the userspace buffer where the result will be stored.h]hFvalues points to the userspace buffer where the result will be stored.}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-s390-get-cmma-bitsah ]h"]4.107 kvm_s390_get_cmma_bitsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.108 KVM_S390_SET_CMMA_BITSh]h4.108 KVM_S390_SET_CMMA_BITS}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjT hhhKubj)}(hKVM_CAP_S390_CMMA_MIGRATIONh]h)}(hjg h]hKVM_CAP_S390_CMMA_MIGRATION}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhje ubah}(h]h ]h"]h$]h&]uh1jhjT ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjQ hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hs390h]h)}(hj h]hs390}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjQ hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvm ioctlh]h)}(hj h]hvm ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjQ hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hstruct kvm_s390_cmma_log (in)h]h)}(hj h]hstruct kvm_s390_cmma_log (in)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjQ hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h(0 on success, a negative value on error h]h)}(h'0 on success, a negative value on errorh]h'0 on success, a negative value on error}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjQ hhubeh}(h]h ]h"]h$]h&]uh1jrhj@ hhhhhMubh)}(hX%This ioctl is used to set the values of the CMMA bits on the s390 architecture. It is meant to be used during live migration to restore the CMMA values, but there are no restrictions on its use. The ioctl takes parameters via the kvm_s390_cmma_values struct. Each CMMA value takes up one byte.h]hX%This ioctl is used to set the values of the CMMA bits on the s390 architecture. It is meant to be used during live migration to restore the CMMA values, but there are no restrictions on its use. The ioctl takes parameters via the kvm_s390_cmma_values struct. Each CMMA value takes up one byte.}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubj8)}(hstruct kvm_s390_cmma_log { __u64 start_gfn; __u32 count; __u32 flags; union { __u64 remaining; __u64 mask; }; __u64 values; };h]hstruct kvm_s390_cmma_log { __u64 start_gfn; __u32 count; __u32 flags; union { __u64 remaining; __u64 mask; }; __u64 values; };}hjO sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj@ hhubh)}(h4start_gfn indicates the starting guest frame number,h]h4start_gfn indicates the starting guest frame number,}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(hCcount indicates how many values are to be considered in the buffer,h]hCcount indicates how many values are to be considered in the buffer,}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(h flags is not used and must be 0.h]h flags is not used and must be 0.}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(h5mask indicates which PGSTE bits are to be considered.h]h5mask indicates which PGSTE bits are to be considered.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(hremaining is not used.h]hremaining is not used.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(hCvalues points to the buffer in userspace where to store the values.h]hCvalues points to the buffer in userspace where to store the values.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubh)}(hXThis ioctl can fail with -ENOMEM if not enough memory can be allocated to complete the task, with -ENXIO if CMMA is not enabled, with -EINVAL if the count field is too large (e.g. more than KVM_S390_CMMA_SIZE_MAX) or if the flags field was not 0, with -EFAULT if the userspace address is invalid, if invalid pages are written to (e.g. after the end of memory) or if no page table is present for the addresses (e.g. when using hugepages).h]hXThis ioctl can fail with -ENOMEM if not enough memory can be allocated to complete the task, with -ENXIO if CMMA is not enabled, with -EINVAL if the count field is too large (e.g. more than KVM_S390_CMMA_SIZE_MAX) or if the flags field was not 0, with -EFAULT if the userspace address is invalid, if invalid pages are written to (e.g. after the end of memory) or if no page table is present for the addresses (e.g. when using hugepages).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ hhubeh}(h]kvm-s390-set-cmma-bitsah ]h"]4.108 kvm_s390_set_cmma_bitsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.109 KVM_PPC_GET_CPU_CHARh]h4.109 KVM_PPC_GET_CPU_CHAR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hKVM_CAP_PPC_GET_CPU_CHARh]h)}(hj h]hKVM_CAP_PPC_GET_CPU_CHAR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hpowerpch]h)}(hj h]hpowerpc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(hTypeh]hType}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7 hhhKubj)}(hvm ioctlh]h)}(hjJ h]hvm ioctl}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjH ubah}(h]h ]h"]h$]h&]uh1jhj7 ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjh hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hje hhhKubj)}(hstruct kvm_ppc_cpu_char (out)h]h)}(hjx h]hstruct kvm_ppc_cpu_char (out)}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjv ubah}(h]h ]h"]h$]h&]uh1jhje ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hQ0 on successful completion, -EFAULT if struct kvm_ppc_cpu_char cannot be written h]h)}(hP0 on successful completion, -EFAULT if struct kvm_ppc_cpu_char cannot be writtenh]hP0 on successful completion, -EFAULT if struct kvm_ppc_cpu_char cannot be written}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj hhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhMubh)}(hXNThis ioctl gives userspace information about certain characteristics of the CPU relating to speculative execution of instructions and possible information leakage resulting from speculative execution (see CVE-2017-5715, CVE-2017-5753 and CVE-2017-5754). The information is returned in struct kvm_ppc_cpu_char, which looks like this::h]hXMThis ioctl gives userspace information about certain characteristics of the CPU relating to speculative execution of instructions and possible information leakage resulting from speculative execution (see CVE-2017-5715, CVE-2017-5753 and CVE-2017-5754). The information is returned in struct kvm_ppc_cpu_char, which looks like this:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj8)}(hX6struct kvm_ppc_cpu_char { __u64 character; /* characteristics of the CPU */ __u64 behaviour; /* recommended software behaviour */ __u64 character_mask; /* valid bits in character */ __u64 behaviour_mask; /* valid bits in behaviour */ };h]hX6struct kvm_ppc_cpu_char { __u64 character; /* characteristics of the CPU */ __u64 behaviour; /* recommended software behaviour */ __u64 character_mask; /* valid bits in character */ __u64 behaviour_mask; /* valid bits in behaviour */ };}hj sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj hhubh)}(hX(For extensibility, the character_mask and behaviour_mask fields indicate which bits of character and behaviour have been filled in by the kernel. If the set of defined bits is extended in future then userspace will be able to tell whether it is running on a kernel that knows about the new bits.h]hX(For extensibility, the character_mask and behaviour_mask fields indicate which bits of character and behaviour have been filled in by the kernel. If the set of defined bits is extended in future then userspace will be able to tell whether it is running on a kernel that knows about the new bits.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hXThe character field describes attributes of the CPU which can help with preventing inadvertent information disclosure - specifically, whether there is an instruction to flash-invalidate the L1 data cache (ori 30,30,0 or mtspr SPRN_TRIG2,rN), whether the L1 data cache is set to a mode where entries can only be used by the thread that created them, whether the bcctr[l] instruction prevents speculation, and whether a speculation barrier instruction (ori 31,31,0) is provided.h]hXThe character field describes attributes of the CPU which can help with preventing inadvertent information disclosure - specifically, whether there is an instruction to flash-invalidate the L1 data cache (ori 30,30,0 or mtspr SPRN_TRIG2,rN), whether the L1 data cache is set to a mode where entries can only be used by the thread that created them, whether the bcctr[l] instruction prevents speculation, and whether a speculation barrier instruction (ori 31,31,0) is provided.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hXThe behaviour field describes actions that software should take to prevent inadvertent information disclosure, and thus describes which vulnerabilities the hardware is subject to; specifically whether the L1 data cache should be flushed when returning to user mode from the kernel, and whether a speculation barrier should be placed between an array bounds check and the array access.h]hXThe behaviour field describes actions that software should take to prevent inadvertent information disclosure, and thus describes which vulnerabilities the hardware is subject to; specifically whether the L1 data cache should be flushed when returning to user mode from the kernel, and whether a speculation barrier should be placed between an array bounds check and the array access.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hYThese fields use the same bit definitions as the new H_GET_CPU_CHARACTERISTICS hypercall.h]hYThese fields use the same bit definitions as the new H_GET_CPU_CHARACTERISTICS hypercall.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]kvm-ppc-get-cpu-charah ]h"]4.109 kvm_ppc_get_cpu_charah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.110 KVM_MEMORY_ENCRYPT_OPh]h4.110 KVM_MEMORY_ENCRYPT_OP}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8 hhhKubj)}(hbasich]h)}(hjK h]hbasic}(hjM hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI ubah}(h]h ]h"]h$]h&]uh1jhj8 ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5 hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjf hhhKubj)}(hx86h]h)}(hjy h]hx86}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjw ubah}(h]h ]h"]h$]h&]uh1jhjf ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5 hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvm ioctl, vcpu ioctlh]h)}(hj h]hvm ioctl, vcpu ioctl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5 hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h.an opaque platform specific structure (in/out)h]h)}(hj h]h.an opaque platform specific structure (in/out)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5 hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5 hhubeh}(h]h ]h"]h$]h&]uh1jrhj$ hhhhhMubh)}(hIf the platform supports creating encrypted VMs then this ioctl can be used for issuing platform-specific memory encryption commands to manage those encrypted VMs.h]hIf the platform supports creating encrypted VMs then this ioctl can be used for issuing platform-specific memory encryption commands to manage those encrypted VMs.}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ hhubh)}(hX:Currently, this ioctl is used for issuing both Secure Encrypted Virtualization (SEV) commands on AMD Processors and Trusted Domain Extensions (TDX) commands on Intel Processors. The detailed commands are defined in Documentation/virt/kvm/x86/amd-memory-encryption.rst and Documentation/virt/kvm/x86/intel-tdx.rst.;h]hX:Currently, this ioctl is used for issuing both Secure Encrypted Virtualization (SEV) commands on AMD Processors and Trusted Domain Extensions (TDX) commands on Intel Processors. The detailed commands are defined in Documentation/virt/kvm/x86/amd-memory-encryption.rst and Documentation/virt/kvm/x86/intel-tdx.rst.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ hhubeh}(h]kvm-memory-encrypt-opah ]h"]4.110 kvm_memory_encrypt_opah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h#4.111 KVM_MEMORY_ENCRYPT_REG_REGIONh]h#4.111 KVM_MEMORY_ENCRYPT_REG_REGION}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj] hhhKubj)}(hbasich]h)}(hjp h]hbasic}(hjr hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjn ubah}(h]h ]h"]h$]h&]uh1jhj] ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZ hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hx86h]h)}(hj h]hx86}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZ hhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hsystemh]h)}(hj h]hsystem}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZ hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hstruct kvm_enc_region (in)h]h)}(hj h]hstruct kvm_enc_region (in)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZ hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjZ hhubeh}(h]h ]h"]h$]h&]uh1jrhjI hhhhhMubh)}(hvThis ioctl can be used to register a guest memory region which may contain encrypted data (e.g. guest RAM, SMRAM etc).h]hvThis ioctl can be used to register a guest memory region which may contain encrypted data (e.g. guest RAM, SMRAM etc).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI hhubh)}(hXIt is used in the SEV-enabled guest. When encryption is enabled, a guest memory region may contain encrypted data. The SEV memory encryption engine uses a tweak such that two identical plaintext pages, each at different locations will have differing ciphertexts. So swapping or moving ciphertext of those pages will not result in plaintext being swapped. So relocating (or migrating) physical backing pages for the SEV guest will require some additional steps.h]hXIt is used in the SEV-enabled guest. When encryption is enabled, a guest memory region may contain encrypted data. The SEV memory encryption engine uses a tweak such that two identical plaintext pages, each at different locations will have differing ciphertexts. So swapping or moving ciphertext of those pages will not result in plaintext being swapped. So relocating (or migrating) physical backing pages for the SEV guest will require some additional steps.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI hhubh)}(hNote: The current SEV key management spec does not provide commands to swap or migrate (move) ciphertext pages. Hence, for now we pin the guest memory region registered with the ioctl.h]hNote: The current SEV key management spec does not provide commands to swap or migrate (move) ciphertext pages. Hence, for now we pin the guest memory region registered with the ioctl.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI hhubeh}(h]kvm-memory-encrypt-reg-regionah ]h"]#4.111 kvm_memory_encrypt_reg_regionah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h%4.112 KVM_MEMORY_ENCRYPT_UNREG_REGIONh]h%4.112 KVM_MEMORY_ENCRYPT_UNREG_REGION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hbasich]h)}(hjh]hbasic}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hsystemh]h)}(hjh]hsystem}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_enc_region (in)h]h)}(hj-h]hstruct kvm_enc_region (in)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjHhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhj|hhhhhMubh)}(hwThis ioctl can be used to unregister the guest memory region registered with KVM_MEMORY_ENCRYPT_REG_REGION ioctl above.h]hwThis ioctl can be used to unregister the guest memory region registered with KVM_MEMORY_ENCRYPT_REG_REGION ioctl above.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj|hhubeh}(h]kvm-memory-encrypt-unreg-regionah ]h"]%4.112 kvm_memory_encrypt_unreg_regionah$]h&]uh1hhjhhhhhM ubh)}(hhh](h)}(h4.113 KVM_HYPERV_EVENTFDh]h4.113 KVM_HYPERV_EVENTFD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_HYPERV_EVENTFDh]h)}(hjh]hKVM_CAP_HYPERV_EVENTFD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj1hhhKubj)}(hstruct kvm_hyperv_eventfd (in) h]h)}(hstruct kvm_hyperv_eventfd (in)h]hstruct kvm_hyperv_eventfd (in)}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hX*This ioctl (un)registers an eventfd to receive notifications from the guest on the specified Hyper-V connection id through the SIGNAL_EVENT hypercall, without causing a user exit. SIGNAL_EVENT hypercall with non-zero event flag number (bits 24-31) still triggers a KVM_EXIT_HYPERV_HCALL user exit.h]hX*This ioctl (un)registers an eventfd to receive notifications from the guest on the specified Hyper-V connection id through the SIGNAL_EVENT hypercall, without causing a user exit. SIGNAL_EVENT hypercall with non-zero event flag number (bits 24-31) still triggers a KVM_EXIT_HYPERV_HCALL user exit.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj8)}(hnstruct kvm_hyperv_eventfd { __u32 conn_id; __s32 fd; __u32 flags; __u32 padding[3]; };h]hnstruct kvm_hyperv_eventfd { __u32 conn_id; __s32 fd; __u32 flags; __u32 padding[3]; };}hjtsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM&hjhhubh)}(h-The conn_id field should fit within 24 bits::h]h,The conn_id field should fit within 24 bits:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjhhubj8)}(h8#define KVM_HYPERV_CONN_ID_MASK 0x00ffffffh]h8#define KVM_HYPERV_CONN_ID_MASK 0x00ffffff}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM/hjhhubh)}(h/The acceptable values for the flags field are::h]h.The acceptable values for the flags field are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjhhubj8)}(h.#define KVM_HYPERV_EVENTFD_DEASSIGN (1 << 0)h]h.#define KVM_HYPERV_EVENTFD_DEASSIGN (1 << 0)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM3hjhhubjs)}(hhh]jx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EINVAL if conn_id or flags is outside the allowed range, -ENOENT on deassign if the conn_id isn't registered, -EEXIST on assign if the conn_id is already registered h]h)}(h0 on success, -EINVAL if conn_id or flags is outside the allowed range, -ENOENT on deassign if the conn_id isn't registered, -EEXIST on assign if the conn_id is already registeredh]h0 on success, -EINVAL if conn_id or flags is outside the allowed range, -ENOENT on deassign if the conn_id isn’t registered, -EEXIST on assign if the conn_id is already registered}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM5hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM5ubeh}(h]kvm-hyperv-eventfdah ]h"]4.113 kvm_hyperv_eventfdah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.114 KVM_GET_NESTED_STATEh]h4.114 KVM_GET_NESTED_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM;ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_NESTED_STATEh]h)}(hj!h]hKVM_CAP_NESTED_STATE}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM=hj hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj<hhhKubj)}(hx86h]h)}(hjOh]hx86}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjMubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jwhhhM>hj hhubjx)}(hhh](j})}(hTypeh]hType}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjjhhhKubj)}(h vcpu ioctlh]h)}(hj}h]h vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj{ubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jwhhhM?hj hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h struct kvm_nested_state (in/out)h]h)}(hjh]h struct kvm_nested_state (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM@hj hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMAhj hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM=ubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjhhubj )}(hX===== ============================================================= E2BIG the total state size exceeds the value of 'size' specified by the user; the size required will be written into size. ===== ============================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1jchjubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(hE2BIGh]hE2BIG}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj-ubah}(h]h ]h"]h$]h&]uh1jhj*ubj)}(hhh]h)}(htthe total state size exceeds the value of 'size' specified by the user; the size required will be written into size.h]hxthe total state size exceeds the value of ‘size’ specified by the user; the size required will be written into size.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjDubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1j~hj'ubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hj ubah}(h]h ]h"]h$]h&]uh1jYhj ubah}(h]h ]h"]h$]h&]uh1j hhhMEhjhhubj8)}(hXstruct kvm_nested_state { __u16 flags; __u16 format; __u32 size; union { struct kvm_vmx_nested_state_hdr vmx; struct kvm_svm_nested_state_hdr svm; /* Pad the header to 128 bytes. */ __u8 pad[120]; } hdr; union { struct kvm_vmx_nested_state_data vmx[0]; struct kvm_svm_nested_state_data svm[0]; } data; }; #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 #define KVM_STATE_NESTED_EVMCS 0x00000004 #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000 #define KVM_STATE_NESTED_VMX_SMM_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_VMX_SMM_VMXON 0x00000002 #define KVM_STATE_NESTED_GIF_SET 0x00000100 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 struct kvm_vmx_nested_state_hdr { __u64 vmxon_pa; __u64 vmcs12_pa; struct { __u16 flags; } smm; __u32 flags; __u64 preemption_timer_deadline; }; struct kvm_svm_nested_state_hdr { __u64 vmcb_pa; __u64 gpat; }; struct kvm_vmx_nested_state_data { __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; }; struct kvm_svm_nested_state_data { __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE]; };h]hXstruct kvm_nested_state { __u16 flags; __u16 format; __u32 size; union { struct kvm_vmx_nested_state_hdr vmx; struct kvm_svm_nested_state_hdr svm; /* Pad the header to 128 bytes. */ __u8 pad[120]; } hdr; union { struct kvm_vmx_nested_state_data vmx[0]; struct kvm_svm_nested_state_data svm[0]; } data; }; #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 #define KVM_STATE_NESTED_EVMCS 0x00000004 #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000 #define KVM_STATE_NESTED_VMX_SMM_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_VMX_SMM_VMXON 0x00000002 #define KVM_STATE_NESTED_GIF_SET 0x00000100 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 struct kvm_vmx_nested_state_hdr { __u64 vmxon_pa; __u64 vmcs12_pa; struct { __u16 flags; } smm; __u32 flags; __u64 preemption_timer_deadline; }; struct kvm_svm_nested_state_hdr { __u64 vmcb_pa; __u64 gpat; }; struct kvm_vmx_nested_state_data { __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; }; struct kvm_svm_nested_state_data { __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE]; };}hjzsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMLhjhhubh)}(hVThis ioctl copies the vcpu's nested virtualization state from the kernel to userspace.h]hXThis ioctl copies the vcpu’s nested virtualization state from the kernel to userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hrThe maximum size of the state can be retrieved by passing KVM_CAP_NESTED_STATE to the KVM_CHECK_EXTENSION ioctl().h]hrThe maximum size of the state can be retrieved by passing KVM_CAP_NESTED_STATE to the KVM_CHECK_EXTENSION ioctl().}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-get-nested-stateah ]h"]4.114 kvm_get_nested_stateah$]h&]uh1hhjhhhhhM;ubh)}(hhh](h)}(h4.115 KVM_SET_NESTED_STATEh]h4.115 KVM_SET_NESTED_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_NESTED_STATEh]h)}(hjh]hKVM_CAP_NESTED_STATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h vcpu ioctlh]h)}(hj/h]h vcpu ioctl}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJhhhKubj)}(hstruct kvm_nested_state (in)h]h)}(hj]h]hstruct kvm_nested_state (in)}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hThis copies the vcpu's kvm_nested_state struct from userspace to the kernel. For the definition of struct kvm_nested_state, see KVM_GET_NESTED_STATE.h]hThis copies the vcpu’s kvm_nested_state struct from userspace to the kernel. For the definition of struct kvm_nested_state, see KVM_GET_NESTED_STATE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-set-nested-stateah ]h"]4.115 kvm_set_nested_stateah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h%4.116 KVM_(UN)REGISTER_COALESCED_MMIOh]h%4.116 KVM_(UN)REGISTER_COALESCED_MMIO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hUKVM_CAP_COALESCED_MMIO (for coalesced mmio) KVM_CAP_COALESCED_PIO (for coalesced pio)h]h)}(hUKVM_CAP_COALESCED_MMIO (for coalesced mmio) KVM_CAP_COALESCED_PIO (for coalesced pio)h]hUKVM_CAP_COALESCED_MMIO (for coalesced mmio) KVM_CAP_COALESCED_PIO (for coalesced pio)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hvm ioctlh]h)}(hjGh]hvm ioctl}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(hstruct kvm_coalesced_mmio_zoneh]h)}(hjuh]hstruct kvm_coalesced_mmio_zone}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hCoalesced I/O is a performance optimization that defers hardware register write emulation so that userspace exits are avoided. It is typically used to reduce the overhead of emulating frequently accessed hardware registers.h]hCoalesced I/O is a performance optimization that defers hardware register write emulation so that userspace exits are avoided. It is typically used to reduce the overhead of emulating frequently accessed hardware registers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hWhen a hardware register is configured for coalesced I/O, write accesses do not exit to userspace and their value is recorded in a ring buffer that is shared between kernel and userspace.h]hWhen a hardware register is configured for coalesced I/O, write accesses do not exit to userspace and their value is recorded in a ring buffer that is shared between kernel and userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXPCoalesced I/O is used if one or more write accesses to a hardware register can be deferred until a read or a write to another hardware register on the same device. This last access will cause a vmexit and userspace will process accesses from the ring buffer before emulating it. That will avoid exiting to userspace on repeated writes.h]hXPCoalesced I/O is used if one or more write accesses to a hardware register can be deferred until a read or a write to another hardware register on the same device. This last access will cause a vmexit and userspace will process accesses from the ring buffer before emulating it. That will avoid exiting to userspace on repeated writes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hCoalesced pio is based on coalesced mmio. There is little difference between coalesced mmio and pio except that coalesced pio records accesses to I/O ports.h]hCoalesced pio is based on coalesced mmio. There is little difference between coalesced mmio and pio except that coalesced pio records accesses to I/O ports.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-un-register-coalesced-mmioah ]h"]%4.116 kvm_(un)register_coalesced_mmioah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.117 KVM_CLEAR_DIRTY_LOGh]h4.117 KVM_CLEAR_DIRTY_LOG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h!KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2h]h)}(hj,h]h!KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(hx86, arm64, mipsh]h)}(hjZh]hx86, arm64, mips}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hTypeh]hType}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjuhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_clear_dirty_log (in)h]h)}(hjh]hstruct kvm_clear_dirty_log (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubj8)}(h/* for KVM_CLEAR_DIRTY_LOG */ struct kvm_clear_dirty_log { __u32 slot; __u32 num_pages; __u64 first_page; union { void __user *dirty_bitmap; /* one bit per page */ __u64 padding; }; };h]h/* for KVM_CLEAR_DIRTY_LOG */ struct kvm_clear_dirty_log { __u32 slot; __u32 num_pages; __u64 first_page; union { void __user *dirty_bitmap; /* one bit per page */ __u64 padding; }; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjhhubh)}(hXThe ioctl clears the dirty status of pages in a memory slot, according to the bitmap that is passed in struct kvm_clear_dirty_log's dirty_bitmap field. Bit 0 of the bitmap corresponds to page "first_page" in the memory slot, and num_pages is the size in bits of the input bitmap. first_page must be a multiple of 64; num_pages must also be a multiple of 64 unless first_page + num_pages is the size of the memory slot. For each bit that is set in the input bitmap, the corresponding page is marked "clean" in KVM's dirty bitmap, and dirty tracking is re-enabled for that page (for example via write-protection, or by clearing the dirty bit in a page table entry).h]hXThe ioctl clears the dirty status of pages in a memory slot, according to the bitmap that is passed in struct kvm_clear_dirty_log’s dirty_bitmap field. Bit 0 of the bitmap corresponds to page “first_page” in the memory slot, and num_pages is the size in bits of the input bitmap. first_page must be a multiple of 64; num_pages must also be a multiple of 64 unless first_page + num_pages is the size of the memory slot. For each bit that is set in the input bitmap, the corresponding page is marked “clean” in KVM’s dirty bitmap, and dirty tracking is re-enabled for that page (for example via write-protection, or by clearing the dirty bit in a page table entry).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of slot field specifies the address space for which you want to clear the dirty status. See KVM_SET_USER_MEMORY_REGION for details on the usage of slot field.h]hIf KVM_CAP_MULTI_ADDRESS_SPACE is available, bits 16-31 of slot field specifies the address space for which you want to clear the dirty status. See KVM_SET_USER_MEMORY_REGION for details on the usage of slot field.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hXThis ioctl is mostly useful when KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is enabled; for more information, see the description of the capability. However, it can always be used as long as KVM_CHECK_EXTENSION confirms that KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is present.h]hXThis ioctl is mostly useful when KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is enabled; for more information, see the description of the capability. However, it can always be used as long as KVM_CHECK_EXTENSION confirms that KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is present.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-clear-dirty-logah ]h"]4.117 kvm_clear_dirty_logah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h 4.118 KVM_GET_SUPPORTED_HV_CPUIDh]h 4.118 KVM_GET_SUPPORTED_HV_CPUID}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjZhhhKubj)}(h>KVM_CAP_HYPERV_CPUID (vcpu), KVM_CAP_SYS_HYPERV_CPUID (system)h]h)}(hjmh]h>KVM_CAP_HYPERV_CPUID (vcpu), KVM_CAP_SYS_HYPERV_CPUID (system)}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjWhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjWhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hsystem ioctl, vcpu ioctlh]h)}(hjh]hsystem ioctl, vcpu ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjWhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hstruct kvm_cpuid2 (in/out)h]h)}(hjh]hstruct kvm_cpuid2 (in/out)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjWhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjWhhubeh}(h]h ]h"]h$]h&]uh1jrhjFhhhhhMubj8)}(hXstruct kvm_cpuid2 { __u32 nent; __u32 padding; struct kvm_cpuid_entry2 entries[0]; }; struct kvm_cpuid_entry2 { __u32 function; __u32 index; __u32 flags; __u32 eax; __u32 ebx; __u32 ecx; __u32 edx; __u32 padding[3]; };h]hXstruct kvm_cpuid2 { __u32 nent; __u32 padding; struct kvm_cpuid_entry2 entries[0]; }; struct kvm_cpuid_entry2 { __u32 function; __u32 index; __u32 flags; __u32 eax; __u32 ebx; __u32 ecx; __u32 edx; __u32 padding[3]; };}hjGsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjFhhubh)}(hXThis ioctl returns x86 cpuid features leaves related to Hyper-V emulation in KVM. Userspace can use the information returned by this ioctl to construct cpuid information presented to guests consuming Hyper-V enlightenments (e.g. Windows or Hyper-V guests).h]hXThis ioctl returns x86 cpuid features leaves related to Hyper-V emulation in KVM. Userspace can use the information returned by this ioctl to construct cpuid information presented to guests consuming Hyper-V enlightenments (e.g. Windows or Hyper-V guests).}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFhhubh)}(hXCPUID feature leaves returned by this ioctl are defined by Hyper-V Top Level Functional Specification (TLFS). These leaves can't be obtained with KVM_GET_SUPPORTED_CPUID ioctl because some of them intersect with KVM feature leaves (0x40000000, 0x40000001).h]hXCPUID feature leaves returned by this ioctl are defined by Hyper-V Top Level Functional Specification (TLFS). These leaves can’t be obtained with KVM_GET_SUPPORTED_CPUID ioctl because some of them intersect with KVM feature leaves (0x40000000, 0x40000001).}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFhhubh)}(h;Currently, the following list of CPUID leaves are returned:h]h;Currently, the following list of CPUID leaves are returned:}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjFhhubj )}(hXJ- HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS - HYPERV_CPUID_INTERFACE - HYPERV_CPUID_VERSION - HYPERV_CPUID_FEATURES - HYPERV_CPUID_ENLIGHTMENT_INFO - HYPERV_CPUID_IMPLEMENT_LIMITS - HYPERV_CPUID_NESTED_FEATURES - HYPERV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS - HYPERV_CPUID_SYNDBG_INTERFACE - HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES h]j)}(hhh](j)}(h%HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONSh]h)}(hjh]h%HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_INTERFACEh]h)}(hjh]hHYPERV_CPUID_INTERFACE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_VERSIONh]h)}(hjh]hHYPERV_CPUID_VERSION}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_FEATURESh]h)}(hjh]hHYPERV_CPUID_FEATURES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_ENLIGHTMENT_INFOh]h)}(hjh]hHYPERV_CPUID_ENLIGHTMENT_INFO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_IMPLEMENT_LIMITSh]h)}(hjh]hHYPERV_CPUID_IMPLEMENT_LIMITS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_NESTED_FEATURESh]h)}(hjh]hHYPERV_CPUID_NESTED_FEATURES}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h,HYPERV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONSh]h)}(hj)h]h,HYPERV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hHYPERV_CPUID_SYNDBG_INTERFACEh]h)}(hj@h]hHYPERV_CPUID_SYNDBG_INTERFACE}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(h*HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES h]h)}(h)HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIESh]h)HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]jjuh1jhhhM hjubah}(h]h ]h"]h$]h&]uh1j hhhM hjFhhubh)}(hXUserspace invokes KVM_GET_SUPPORTED_HV_CPUID by passing a kvm_cpuid2 structure with the 'nent' field indicating the number of entries in the variable-size array 'entries'. If the number of entries is too low to describe all Hyper-V feature leaves, an error (E2BIG) is returned. If the number is more or equal to the number of Hyper-V feature leaves, the 'nent' field is adjusted to the number of valid entries in the 'entries' array, which is then filled.h]hXUserspace invokes KVM_GET_SUPPORTED_HV_CPUID by passing a kvm_cpuid2 structure with the ‘nent’ field indicating the number of entries in the variable-size array ‘entries’. If the number of entries is too low to describe all Hyper-V feature leaves, an error (E2BIG) is returned. If the number is more or equal to the number of Hyper-V feature leaves, the ‘nent’ field is adjusted to the number of valid entries in the ‘entries’ array, which is then filled.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFhhubh)}(h'index' and 'flags' fields in 'struct kvm_cpuid_entry2' are currently reserved, userspace should not expect to get any particular value there.h]h‘index’ and ‘flags’ fields in ‘struct kvm_cpuid_entry2’ are currently reserved, userspace should not expect to get any particular value there.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFhhubh)}(hNote, vcpu version of KVM_GET_SUPPORTED_HV_CPUID is currently deprecated. Unlike system ioctl which exposes all supported feature bits unconditionally, vcpu version has the following quirks:h]hNote, vcpu version of KVM_GET_SUPPORTED_HV_CPUID is currently deprecated. Unlike system ioctl which exposes all supported feature bits unconditionally, vcpu version has the following quirks:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjFhhubj)}(hhh](j)}(hHYPERV_CPUID_NESTED_FEATURES leaf and HV_X64_ENLIGHTENED_VMCS_RECOMMENDED feature bit are only exposed when Enlightened VMCS was previously enabled on the corresponding vCPU (KVM_CAP_HYPERV_ENLIGHTENED_VMCS).h]h)}(hHYPERV_CPUID_NESTED_FEATURES leaf and HV_X64_ENLIGHTENED_VMCS_RECOMMENDED feature bit are only exposed when Enlightened VMCS was previously enabled on the corresponding vCPU (KVM_CAP_HYPERV_ENLIGHTENED_VMCS).h]hHYPERV_CPUID_NESTED_FEATURES leaf and HV_X64_ENLIGHTENED_VMCS_RECOMMENDED feature bit are only exposed when Enlightened VMCS was previously enabled on the corresponding vCPU (KVM_CAP_HYPERV_ENLIGHTENED_VMCS).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hHV_STIMER_DIRECT_MODE_AVAILABLE bit is only exposed with in-kernel LAPIC. (presumes KVM_CREATE_IRQCHIP has already been called). h]h)}(hHV_STIMER_DIRECT_MODE_AVAILABLE bit is only exposed with in-kernel LAPIC. (presumes KVM_CREATE_IRQCHIP has already been called).h]hHV_STIMER_DIRECT_MODE_AVAILABLE bit is only exposed with in-kernel LAPIC. (presumes KVM_CREATE_IRQCHIP has already been called).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjubah}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM$hjFhhubeh}(h]kvm-get-supported-hv-cpuidah ]h"] 4.118 kvm_get_supported_hv_cpuidah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.119 KVM_ARM_VCPU_FINALIZEh]h4.119 KVM_ARM_VCPU_FINALIZE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM+ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hj h]harm64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM-hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj&hhhKubj)}(h vcpu ioctlh]h)}(hj9h]h vcpu ioctl}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hj7ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jwhhhM.hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjThhhKubj)}(hint feature (in)h]h)}(hjgh]hint feature (in)}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjeubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jwhhhM/hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM0hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM-ubh)}(hErrors:h]hErrors:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjhhubj )}(hX====== ============================================================== EPERM feature not enabled, needs configuration, or already finalized EINVAL feature unknown or not present ====== ============================================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEPERMh]hEPERM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h>feature not enabled, needs configuration, or already finalizedh]h>feature not enabled, needs configuration, or already finalized}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubj)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj ubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hfeature unknown or not presenth]hfeature unknown or not present}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj7ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjubah}(h]h ]h"]h$]h&]uh1j hhhM4hjhhubh)}(hRecognised values for feature:h]hRecognised values for feature:}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjhhubj )}(h===== =========================================== arm64 KVM_ARM_VCPU_SVE (requires KVM_CAP_ARM_SVE) ===== =========================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK+uh1jchjubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(harm64h]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h+KVM_ARM_VCPU_SVE (requires KVM_CAP_ARM_SVE)h]h+KVM_ARM_VCPU_SVE (requires KVM_CAP_ARM_SVE)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhj{ubah}(h]h ]h"]h$]h&]uh1j hhhM;hjhhubh)}(h:Finalizes the configuration of the specified vcpu feature.h]h:Finalizes the configuration of the specified vcpu feature.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hjhhubh)}(hThe vcpu must already have been initialised, enabling the affected feature, by means of a successful :ref:`KVM_ARM_VCPU_INIT ` call with the appropriate flag set in features[].h](heThe vcpu must already have been initialised, enabling the affected feature, by means of a successful }(hjhhhNhNubh)}(h,:ref:`KVM_ARM_VCPU_INIT `h]j)}(hjh]hKVM_ARM_VCPU_INIT}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjkvm_arm_vcpu_inituh1hhhhMAhjubh2 call with the appropriate flag set in features[].}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMAhjhhubh)}(hlFor affected vcpu features, this is a mandatory step that must be performed before the vcpu is fully usable.h]hlFor affected vcpu features, this is a mandatory step that must be performed before the vcpu is fully usable.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjhhubh)}(hBetween KVM_ARM_VCPU_INIT and KVM_ARM_VCPU_FINALIZE, the feature may be configured by use of ioctls such as KVM_SET_ONE_REG. The exact configuration that should be performed and how to do it are feature-dependent.h]hBetween KVM_ARM_VCPU_INIT and KVM_ARM_VCPU_FINALIZE, the feature may be configured by use of ioctls such as KVM_SET_ONE_REG. The exact configuration that should be performed and how to do it are feature-dependent.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjhhubh)}(hOther calls that depend on a particular feature being finalized, such as KVM_RUN, KVM_GET_REG_LIST, KVM_GET_ONE_REG and KVM_SET_ONE_REG, will fail with -EPERM unless the feature has already been finalized by means of a KVM_ARM_VCPU_FINALIZE call.h]hOther calls that depend on a particular feature being finalized, such as KVM_RUN, KVM_GET_REG_LIST, KVM_GET_ONE_REG and KVM_SET_ONE_REG, will fail with -EPERM unless the feature has already been finalized by means of a KVM_ARM_VCPU_FINALIZE call.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjhhubh)}(h^See KVM_ARM_VCPU_INIT for details of vcpu features that require finalization using this ioctl.h]h^See KVM_ARM_VCPU_INIT for details of vcpu features that require finalization using this ioctl.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjhhubeh}(h]kvm-arm-vcpu-finalizeah ]h"]4.119 kvm_arm_vcpu_finalizeah$]h&]uh1hhjhhhhhM+ubh)}(hhh](h)}(h4.120 KVM_SET_PMU_EVENT_FILTERh]h4.120 KVM_SET_PMU_EVENT_FILTER}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjlhhhhhMUubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hKVM_CAP_PMU_EVENT_FILTERh]h)}(hjh]hKVM_CAP_PMU_EVENT_FILTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMWhj}hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMXhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMXhj}hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm ioctlh]h)}(hjh]hvm ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMYhj}hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(h struct kvm_pmu_event_filter (in)h]h)}(hjh]h struct kvm_pmu_event_filter (in)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMZhj}hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjIubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhM[hj}hhubeh}(h]h ]h"]h$]h&]uh1jrhjlhhhhhMWubh)}(hErrors:h]hErrors:}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjlhhubj )}(hXR====== ============================================================ EFAULT args[0] cannot be accessed EINVAL args[0] contains invalid data in the filter or filter events E2BIG nevents is too large EBUSY not enough memory to allocate the filter ====== ============================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK#h]h vcpu ioctl}(hj@#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<#ubah}(h]h ]h"]h$]h&]uh1jhj+#ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj"hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj\#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjY#hhhKubj)}(hnoneh]h)}(hjl#h]hnone}(hjn#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjj#ubah}(h]h ]h"]h$]h&]uh1jhjY#ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj"hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(h0 h]h)}(hjh]h0}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj"hhubeh}(h]h ]h"]h$]h&]uh1jrhj"hhhhhMubh)}(hThis ioctl resets VCPU registers and control structures according to the initial cpu reset definition in the POP. However, the cpu is not put into ESA mode. This reset is a superset of the normal reset.h]hThis ioctl resets VCPU registers and control structures according to the initial cpu reset definition in the POP. However, the cpu is not put into ESA mode. This reset is a superset of the normal reset.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"hhubeh}(h]kvm-s390-initial-resetah ]h"]4.123 kvm_s390_initial_resetah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.124 KVM_S390_CLEAR_RESETh]h4.124 KVM_S390_CLEAR_RESET}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(hKVM_CAP_S390_VCPU_RESETSh]h)}(hj#h]hKVM_CAP_S390_VCPU_RESETS}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj#hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(hs390h]h)}(hj&$h]hs390}(hj($hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj#hhubjx)}(hhh](j})}(hTypeh]hType}(hjD$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjA$hhhKubj)}(h vcpu ioctlh]h)}(hjT$h]h vcpu ioctl}(hjV$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjR$ubah}(h]h ]h"]h$]h&]uh1jhjA$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj#hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjr$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjo$hhhKubj)}(hnoneh]h)}(hj$h]hnone}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhjo$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj#hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(h0 h]h)}(hjh]h0}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj#hhubeh}(h]h ]h"]h$]h&]uh1jrhj#hhhhhMubh)}(hThis ioctl resets VCPU registers and control structures according to the clear cpu reset definition in the POP. However, the cpu is not put into ESA mode. This reset is a superset of the initial reset.h]hThis ioctl resets VCPU registers and control structures according to the clear cpu reset definition in the POP. However, the cpu is not put into ESA mode. This reset is a superset of the initial reset.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubeh}(h]kvm-s390-clear-resetah ]h"]4.124 kvm_s390_clear_resetah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.125 KVM_S390_PV_COMMANDh]h4.125 KVM_S390_PV_COMMAND}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj$hhhKubj)}(hKVM_CAP_S390_PROTECTEDh]h)}(hj%h]hKVM_CAP_S390_PROTECTED}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj %ubah}(h]h ]h"]h$]h&]uh1jhj$ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj,%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)%hhhKubj)}(hs390h]h)}(hj<%h]hs390}(hj>%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj:%ubah}(h]h ]h"]h$]h&]uh1jhj)%ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubjx)}(hhh](j})}(hTypeh]hType}(hjZ%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjW%hhhKubj)}(hvm ioctlh]h)}(hjj%h]hvm ioctl}(hjl%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjh%ubah}(h]h ]h"]h$]h&]uh1jhjW%ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(hstruct kvm_pv_cmdh]h)}(hj%h]hstruct kvm_pv_cmd}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hj$hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj$hhubeh}(h]h ]h"]h$]h&]uh1jrhj$hhhhhM ubj8)}(hXFstruct kvm_pv_cmd { __u32 cmd; /* Command to be executed */ __u16 rc; /* Ultravisor return code */ __u16 rrc; /* Ultravisor return reason code */ __u64 data; /* Data or address */ __u32 flags; /* flags for future extensions. Must be 0 for now */ __u32 reserved[3]; };h]hXFstruct kvm_pv_cmd { __u32 cmd; /* Command to be executed */ __u16 rc; /* Ultravisor return code */ __u16 rrc; /* Ultravisor return reason code */ __u64 data; /* Data or address */ __u32 flags; /* flags for future extensions. Must be 0 for now */ __u32 reserved[3]; };}hj%sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj$hhubh)}(hX**Ultravisor return codes** The Ultravisor return (reason) codes are provided by the kernel if a Ultravisor call has been executed to achieve the results expected by the command. Therefore they are independent of the IOCTL return code. If KVM changes `rc`, its value will always be greater than 0 hence setting it to 0 before issuing a PV command is advised to be able to detect a change of `rc`.h](hstrong)}(h**Ultravisor return codes**h]hUltravisor return codes}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj%ubh The Ultravisor return (reason) codes are provided by the kernel if a Ultravisor call has been executed to achieve the results expected by the command. Therefore they are independent of the IOCTL return code. If KVM changes }(hj%hhhNhNubj,)}(h`rc`h]hrc}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj%ubh, its value will always be greater than 0 hence setting it to 0 before issuing a PV command is advised to be able to detect a change of }(hj%hhhNhNubj,)}(h`rc`h]hrc}(hj &hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj%ubh.}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubh)}(h**cmd values:**h]j%)}(hj:&h]h cmd values:}(hj<&hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj8&ubah}(h]h ]h"]h$]h&]uh1hhhhM#hj$hhubj )}(hhh](j)}(hXKVM_PV_ENABLE Allocate memory and register the VM with the Ultravisor, thereby donating memory to the Ultravisor that will become inaccessible to KVM. All existing CPUs are converted to protected ones. After this command has succeeded, any CPU added via hotplug will become protected during its creation as well. Errors: ===== ============================= EINTR an unmasked signal is pending ===== ============================= h](j)}(h KVM_PV_ENABLEh]h KVM_PV_ENABLE}(hjV&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM0hjR&ubj%)}(hhh](h)}(hX*Allocate memory and register the VM with the Ultravisor, thereby donating memory to the Ultravisor that will become inaccessible to KVM. All existing CPUs are converted to protected ones. After this command has succeeded, any CPU added via hotplug will become protected during its creation as well.h]hX*Allocate memory and register the VM with the Ultravisor, thereby donating memory to the Ultravisor that will become inaccessible to KVM. All existing CPUs are converted to protected ones. After this command has succeeded, any CPU added via hotplug will become protected during its creation as well.}(hjg&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjd&ubh)}(hErrors:h]hErrors:}(hju&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjd&ubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj&ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj&ubjz)}(hhh]j)}(hhh](j)}(hhh]h)}(hEINTRh]hEINTR}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubj)}(hhh]h)}(han unmasked signal is pendingh]han unmasked signal is pending}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj&ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1j~hj&ubah}(h]h ]h"]h$]h&]uh1jyhj&ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj&ubah}(h]h ]h"]h$]h&]uh1jYhjd&ubeh}(h]h ]h"]h$]h&]uh1j$hjR&ubeh}(h]h ]h"]h$]h&]uh1jhhhM0hjO&ubj)}(hXKVM_PV_DISABLE Deregister the VM from the Ultravisor and reclaim the memory that had been donated to the Ultravisor, making it usable by the kernel again. All registered VCPUs are converted back to non-protected ones. If a previous protected VM had been prepared for asynchronous teardown with KVM_PV_ASYNC_CLEANUP_PREPARE and not subsequently torn down with KVM_PV_ASYNC_CLEANUP_PERFORM, it will be torn down in this call together with the current protected VM. h](j)}(hKVM_PV_DISABLEh]hKVM_PV_DISABLE}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM9hj&ubj%)}(hhh]h)}(hXDeregister the VM from the Ultravisor and reclaim the memory that had been donated to the Ultravisor, making it usable by the kernel again. All registered VCPUs are converted back to non-protected ones. If a previous protected VM had been prepared for asynchronous teardown with KVM_PV_ASYNC_CLEANUP_PREPARE and not subsequently torn down with KVM_PV_ASYNC_CLEANUP_PERFORM, it will be torn down in this call together with the current protected VM.h]hXDeregister the VM from the Ultravisor and reclaim the memory that had been donated to the Ultravisor, making it usable by the kernel again. All registered VCPUs are converted back to non-protected ones. If a previous protected VM had been prepared for asynchronous teardown with KVM_PV_ASYNC_CLEANUP_PREPARE and not subsequently torn down with KVM_PV_ASYNC_CLEANUP_PERFORM, it will be torn down in this call together with the current protected VM.}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hj'ubah}(h]h ]h"]h$]h&]uh1j$hj&ubeh}(h]h ]h"]h$]h&]uh1jhhhM9hjO&hhubj)}(hKVM_PV_VM_SET_SEC_PARMS Pass the image header from VM memory to the Ultravisor in preparation of image unpacking and verification. h](j)}(hKVM_PV_VM_SET_SEC_PARMSh]hKVM_PV_VM_SET_SEC_PARMS}(hj)'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM=hj%'ubj%)}(hhh]h)}(hjPass the image header from VM memory to the Ultravisor in preparation of image unpacking and verification.h]hjPass the image header from VM memory to the Ultravisor in preparation of image unpacking and verification.}(hj:'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj7'ubah}(h]h ]h"]h$]h&]uh1j$hj%'ubeh}(h]h ]h"]h$]h&]uh1jhhhM=hjO&hhubj)}(hRKVM_PV_VM_UNPACK Unpack (protect and decrypt) a page of the encrypted boot image. h](j)}(hKVM_PV_VM_UNPACKh]hKVM_PV_VM_UNPACK}(hjX'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM@hjT'ubj%)}(hhh]h)}(h@Unpack (protect and decrypt) a page of the encrypted boot image.h]h@Unpack (protect and decrypt) a page of the encrypted boot image.}(hji'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hjf'ubah}(h]h ]h"]h$]h&]uh1j$hjT'ubeh}(h]h ]h"]h$]h&]uh1jhhhM@hjO&hhubj)}(h}KVM_PV_VM_VERIFY Verify the integrity of the unpacked image. Only if this succeeds, KVM is allowed to start protected VCPUs. h](j)}(hKVM_PV_VM_VERIFYh]hKVM_PV_VM_VERIFY}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMDhj'ubj%)}(hhh]h)}(hkVerify the integrity of the unpacked image. Only if this succeeds, KVM is allowed to start protected VCPUs.h]hkVerify the integrity of the unpacked image. Only if this succeeds, KVM is allowed to start protected VCPUs.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChj'ubah}(h]h ]h"]h$]h&]uh1j$hj'ubeh}(h]h ]h"]h$]h&]uh1jhhhMDhjO&hhubj)}(hXKVM_PV_INFO :Capability: KVM_CAP_S390_PROTECTED_DUMP Presents an API that provides Ultravisor related data to userspace via subcommands. len_max is the size of the user space buffer, len_written is KVM's indication of how much bytes of that buffer were actually written to. len_written can be used to determine the valid fields if more response fields are added in the future. :: enum pv_cmd_info_id { KVM_PV_INFO_VM, KVM_PV_INFO_DUMP, }; struct kvm_s390_pv_info_header { __u32 id; __u32 len_max; __u32 len_written; __u32 reserved; }; struct kvm_s390_pv_info { struct kvm_s390_pv_info_header header; struct kvm_s390_pv_info_dump dump; struct kvm_s390_pv_info_vm vm; }; h](j)}(h KVM_PV_INFOh]h KVM_PV_INFO}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMahj'ubj%)}(hhh](js)}(hhh]jx)}(hhh](j})}(h Capabilityh]h Capability}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj'hhhKubj)}(hKVM_CAP_S390_PROTECTED_DUMP h]h)}(hKVM_CAP_S390_PROTECTED_DUMPh]hKVM_CAP_S390_PROTECTED_DUMP}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhj'ubah}(h]h ]h"]h$]h&]uh1jhj'ubeh}(h]h ]h"]h$]h&]uh1jwhhhMGhj'ubah}(h]h ]h"]h$]h&]uh1jrhj'ubh)}(hXCPresents an API that provides Ultravisor related data to userspace via subcommands. len_max is the size of the user space buffer, len_written is KVM's indication of how much bytes of that buffer were actually written to. len_written can be used to determine the valid fields if more response fields are added in the future.h]hXEPresents an API that provides Ultravisor related data to userspace via subcommands. len_max is the size of the user space buffer, len_written is KVM’s indication of how much bytes of that buffer were actually written to. len_written can be used to determine the valid fields if more response fields are added in the future.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj'ubj8)}(hX=enum pv_cmd_info_id { KVM_PV_INFO_VM, KVM_PV_INFO_DUMP, }; struct kvm_s390_pv_info_header { __u32 id; __u32 len_max; __u32 len_written; __u32 reserved; }; struct kvm_s390_pv_info { struct kvm_s390_pv_info_header header; struct kvm_s390_pv_info_dump dump; struct kvm_s390_pv_info_vm vm; };h]hX=enum pv_cmd_info_id { KVM_PV_INFO_VM, KVM_PV_INFO_DUMP, }; struct kvm_s390_pv_info_header { __u32 id; __u32 len_max; __u32 len_written; __u32 reserved; }; struct kvm_s390_pv_info { struct kvm_s390_pv_info_header header; struct kvm_s390_pv_info_dump dump; struct kvm_s390_pv_info_vm vm; };}hj (sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMQhj'ubeh}(h]h ]h"]h$]h&]uh1j$hj'ubeh}(h]h ]h"]h$]h&]uh1jhhhMahjO&hhubeh}(h]h ]h"]h$]h&]uh1j hj$hhhhhNubh)}(h**subcommands:**h]j%)}(hj/(h]h subcommands:}(hj1(hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hj-(ubah}(h]h ]h"]h$]h&]uh1hhhhMchj$hhubj )}(hXKVM_PV_INFO_VM This subcommand provides basic Ultravisor information for PV hosts. These values are likely also exported as files in the sysfs firmware UV query interface but they are more easily available to programs in this API. The installed calls and feature_indication members provide the installed UV calls and the UV's other feature indications. The max_* members provide information about the maximum number of PV vcpus, PV guests and PV guest memory size. :: struct kvm_s390_pv_info_vm { __u64 inst_calls_list[4]; __u64 max_cpus; __u64 max_guests; __u64 max_guest_addr; __u64 feature_indication; }; KVM_PV_INFO_DUMP This subcommand provides information related to dumping PV guests. :: struct kvm_s390_pv_info_dump { __u64 dump_cpu_buffer_len; __u64 dump_config_mem_buffer_per_1m; __u64 dump_config_finalize_len; }; h]j )}(hhh](j)}(hX}KVM_PV_INFO_VM This subcommand provides basic Ultravisor information for PV hosts. These values are likely also exported as files in the sysfs firmware UV query interface but they are more easily available to programs in this API. The installed calls and feature_indication members provide the installed UV calls and the UV's other feature indications. The max_* members provide information about the maximum number of PV vcpus, PV guests and PV guest memory size. :: struct kvm_s390_pv_info_vm { __u64 inst_calls_list[4]; __u64 max_cpus; __u64 max_guests; __u64 max_guest_addr; __u64 feature_indication; }; h](j)}(hKVM_PV_INFO_VMh]hKVM_PV_INFO_VM}(hjO(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMzhjK(ubj%)}(hhh](h)}(hThis subcommand provides basic Ultravisor information for PV hosts. These values are likely also exported as files in the sysfs firmware UV query interface but they are more easily available to programs in this API.h]hThis subcommand provides basic Ultravisor information for PV hosts. These values are likely also exported as files in the sysfs firmware UV query interface but they are more easily available to programs in this API.}(hj`(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhj](ubh)}(hyThe installed calls and feature_indication members provide the installed UV calls and the UV's other feature indications.h]h{The installed calls and feature_indication members provide the installed UV calls and the UV’s other feature indications.}(hjn(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhj](ubh)}(hoThe max_* members provide information about the maximum number of PV vcpus, PV guests and PV guest memory size.h]hoThe max_* members provide information about the maximum number of PV vcpus, PV guests and PV guest memory size.}(hj|(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhj](ubj8)}(hstruct kvm_s390_pv_info_vm { __u64 inst_calls_list[4]; __u64 max_cpus; __u64 max_guests; __u64 max_guest_addr; __u64 feature_indication; };h]hstruct kvm_s390_pv_info_vm { __u64 inst_calls_list[4]; __u64 max_cpus; __u64 max_guests; __u64 max_guest_addr; __u64 feature_indication; };}hj(sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMshj](ubeh}(h]h ]h"]h$]h&]uh1j$hjK(ubeh}(h]h ]h"]h$]h&]uh1jhhhMzhjH(ubj)}(hKVM_PV_INFO_DUMP This subcommand provides information related to dumping PV guests. :: struct kvm_s390_pv_info_dump { __u64 dump_cpu_buffer_len; __u64 dump_config_mem_buffer_per_1m; __u64 dump_config_finalize_len; }; h](j)}(hKVM_PV_INFO_DUMPh]hKVM_PV_INFO_DUMP}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj(ubj%)}(hhh](h)}(hBThis subcommand provides information related to dumping PV guests.h]hBThis subcommand provides information related to dumping PV guests.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM}hj(ubj8)}(hstruct kvm_s390_pv_info_dump { __u64 dump_cpu_buffer_len; __u64 dump_config_mem_buffer_per_1m; __u64 dump_config_finalize_len; };h]hstruct kvm_s390_pv_info_dump { __u64 dump_cpu_buffer_len; __u64 dump_config_mem_buffer_per_1m; __u64 dump_config_finalize_len; };}hj(sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj(ubeh}(h]h ]h"]h$]h&]uh1j$hj(ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjH(ubeh}(h]h ]h"]h$]h&]uh1j hjD(ubah}(h]h ]h"]h$]h&]uh1j hhhMehj$hhubj )}(hhh](j)}(hXKVM_PV_DUMP :Capability: KVM_CAP_S390_PROTECTED_DUMP Presents an API that provides calls which facilitate dumping a protected VM. :: struct kvm_s390_pv_dmp { __u64 subcmd; __u64 buff_addr; __u64 buff_len; __u64 gaddr; /* For dump storage state */ }; **subcommands:** KVM_PV_DUMP_INIT Initializes the dump process of a protected VM. If this call does not succeed all other subcommands will fail with -EINVAL. This subcommand will return -EINVAL if a dump process has not yet been completed. Not all PV vms can be dumped, the owner needs to set `dump allowed` PCF bit 34 in the SE header to allow dumping. KVM_PV_DUMP_CONFIG_STOR_STATE Stores `buff_len` bytes of tweak component values starting with the 1MB block specified by the absolute guest address (`gaddr`). `buff_len` needs to be `conf_dump_storage_state_len` aligned and at least >= the `conf_dump_storage_state_len` value provided by the dump uv_info data. buff_user might be written to even if an error rc is returned. For instance if we encounter a fault after writing the first page of data. KVM_PV_DUMP_COMPLETE If the subcommand succeeds it completes the dump process and lets KVM_PV_DUMP_INIT be called again. On success `conf_dump_finalize_len` bytes of completion data will be stored to the `buff_addr`. The completion data contains a key derivation seed, IV, tweak nonce and encryption keys as well as an authentication tag all of which are needed to decrypt the dump at a later time. h](j)}(h KVM_PV_DUMPh]h KVM_PV_DUMP}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj(ubj%)}(hhh](js)}(hhh]jx)}(hhh](j})}(h Capabilityh]h Capability}(hj )hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj)hhhKubj)}(hKVM_CAP_S390_PROTECTED_DUMP h]h)}(hKVM_CAP_S390_PROTECTED_DUMPh]hKVM_CAP_S390_PROTECTED_DUMP}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jhj)ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj)ubah}(h]h ]h"]h$]h&]uh1jrhj)ubh)}(hLPresents an API that provides calls which facilitate dumping a protected VM.h]hLPresents an API that provides calls which facilitate dumping a protected VM.}(hj=)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubj8)}(hstruct kvm_s390_pv_dmp { __u64 subcmd; __u64 buff_addr; __u64 buff_len; __u64 gaddr; /* For dump storage state */ };h]hstruct kvm_s390_pv_dmp { __u64 subcmd; __u64 buff_addr; __u64 buff_len; __u64 gaddr; /* For dump storage state */ };}hjK)sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj)ubh)}(h**subcommands:**h]j%)}(hj[)h]h subcommands:}(hj])hhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjY)ubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubj )}(hhh](j)}(hXRKVM_PV_DUMP_INIT Initializes the dump process of a protected VM. If this call does not succeed all other subcommands will fail with -EINVAL. This subcommand will return -EINVAL if a dump process has not yet been completed. Not all PV vms can be dumped, the owner needs to set `dump allowed` PCF bit 34 in the SE header to allow dumping. h](j)}(hKVM_PV_DUMP_INITh]hKVM_PV_DUMP_INIT}(hjw)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjs)ubj%)}(hhh](h)}(hInitializes the dump process of a protected VM. If this call does not succeed all other subcommands will fail with -EINVAL. This subcommand will return -EINVAL if a dump process has not yet been completed.h]hInitializes the dump process of a protected VM. If this call does not succeed all other subcommands will fail with -EINVAL. This subcommand will return -EINVAL if a dump process has not yet been completed.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubh)}(hqNot all PV vms can be dumped, the owner needs to set `dump allowed` PCF bit 34 in the SE header to allow dumping.h](h5Not all PV vms can be dumped, the owner needs to set }(hj)hhhNhNubj,)}(h`dump allowed`h]h dump allowed}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubh. PCF bit 34 in the SE header to allow dumping.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj)ubeh}(h]h ]h"]h$]h&]uh1j$hjs)ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjp)ubj)}(hXKVM_PV_DUMP_CONFIG_STOR_STATE Stores `buff_len` bytes of tweak component values starting with the 1MB block specified by the absolute guest address (`gaddr`). `buff_len` needs to be `conf_dump_storage_state_len` aligned and at least >= the `conf_dump_storage_state_len` value provided by the dump uv_info data. buff_user might be written to even if an error rc is returned. For instance if we encounter a fault after writing the first page of data. h](j)}(hKVM_PV_DUMP_CONFIG_STOR_STATEh]hKVM_PV_DUMP_CONFIG_STOR_STATE}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj)ubj%)}(hhh]h)}(hXStores `buff_len` bytes of tweak component values starting with the 1MB block specified by the absolute guest address (`gaddr`). `buff_len` needs to be `conf_dump_storage_state_len` aligned and at least >= the `conf_dump_storage_state_len` value provided by the dump uv_info data. buff_user might be written to even if an error rc is returned. For instance if we encounter a fault after writing the first page of data.h](hStores }(hj)hhhNhNubj,)}(h `buff_len`h]hbuff_len}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubhf bytes of tweak component values starting with the 1MB block specified by the absolute guest address (}(hj)hhhNhNubj,)}(h`gaddr`h]hgaddr}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubh). }(hj)hhhNhNubj,)}(h `buff_len`h]hbuff_len}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubh needs to be }(hj)hhhNhNubj,)}(h`conf_dump_storage_state_len`h]hconf_dump_storage_state_len}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubh aligned and at least >= the }(hj)hhhNhNubj,)}(h`conf_dump_storage_state_len`h]hconf_dump_storage_state_len}(hj'*hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj)ubh value provided by the dump uv_info data. buff_user might be written to even if an error rc is returned. For instance if we encounter a fault after writing the first page of data.}(hj)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1j$hj)ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjp)ubj)}(hXKVM_PV_DUMP_COMPLETE If the subcommand succeeds it completes the dump process and lets KVM_PV_DUMP_INIT be called again. On success `conf_dump_finalize_len` bytes of completion data will be stored to the `buff_addr`. The completion data contains a key derivation seed, IV, tweak nonce and encryption keys as well as an authentication tag all of which are needed to decrypt the dump at a later time. h](j)}(hKVM_PV_DUMP_COMPLETEh]hKVM_PV_DUMP_COMPLETE}(hjO*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjK*ubj%)}(hhh](h)}(hcIf the subcommand succeeds it completes the dump process and lets KVM_PV_DUMP_INIT be called again.h]hcIf the subcommand succeeds it completes the dump process and lets KVM_PV_DUMP_INIT be called again.}(hj`*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]*ubh)}(hXOn success `conf_dump_finalize_len` bytes of completion data will be stored to the `buff_addr`. The completion data contains a key derivation seed, IV, tweak nonce and encryption keys as well as an authentication tag all of which are needed to decrypt the dump at a later time.h](h On success }(hjn*hhhNhNubj,)}(h`conf_dump_finalize_len`h]hconf_dump_finalize_len}(hjv*hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjn*ubh0 bytes of completion data will be stored to the }(hjn*hhhNhNubj,)}(h `buff_addr`h]h buff_addr}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjn*ubh. The completion data contains a key derivation seed, IV, tweak nonce and encryption keys as well as an authentication tag all of which are needed to decrypt the dump at a later time.}(hjn*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj]*ubeh}(h]h ]h"]h$]h&]uh1j$hjK*ubeh}(h]h ]h"]h$]h&]uh1jhhhMhjp)ubeh}(h]h ]h"]h$]h&]uh1j hj)ubeh}(h]h ]h"]h$]h&]uh1j$hj(ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj(ubj)}(hXKVM_PV_ASYNC_CLEANUP_PREPARE :Capability: KVM_CAP_S390_PROTECTED_ASYNC_DISABLE Prepare the current protected VM for asynchronous teardown. Most resources used by the current protected VM will be set aside for a subsequent asynchronous teardown. The current protected VM will then resume execution immediately as non-protected. There can be at most one protected VM prepared for asynchronous teardown at any time. If a protected VM had already been prepared for teardown without subsequently calling KVM_PV_ASYNC_CLEANUP_PERFORM, this call will fail. In that case, the userspace process should issue a normal KVM_PV_DISABLE. The resources set aside with this call will need to be cleaned up with a subsequent call to KVM_PV_ASYNC_CLEANUP_PERFORM or KVM_PV_DISABLE, otherwise they will be cleaned up when KVM terminates. KVM_PV_ASYNC_CLEANUP_PREPARE can be called again as soon as cleanup starts, i.e. before KVM_PV_ASYNC_CLEANUP_PERFORM finishes. h](j)}(hKVM_PV_ASYNC_CLEANUP_PREPAREh]hKVM_PV_ASYNC_CLEANUP_PREPARE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj*ubj%)}(hhh](js)}(hhh]jx)}(hhh](j})}(h Capabilityh]h Capability}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj*hhhKubj)}(h%KVM_CAP_S390_PROTECTED_ASYNC_DISABLE h]h)}(h$KVM_CAP_S390_PROTECTED_ASYNC_DISABLEh]h$KVM_CAP_S390_PROTECTED_ASYNC_DISABLE}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jhj*ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj*ubah}(h]h ]h"]h$]h&]uh1jrhj*ubh)}(hXbPrepare the current protected VM for asynchronous teardown. Most resources used by the current protected VM will be set aside for a subsequent asynchronous teardown. The current protected VM will then resume execution immediately as non-protected. There can be at most one protected VM prepared for asynchronous teardown at any time. If a protected VM had already been prepared for teardown without subsequently calling KVM_PV_ASYNC_CLEANUP_PERFORM, this call will fail. In that case, the userspace process should issue a normal KVM_PV_DISABLE. The resources set aside with this call will need to be cleaned up with a subsequent call to KVM_PV_ASYNC_CLEANUP_PERFORM or KVM_PV_DISABLE, otherwise they will be cleaned up when KVM terminates. KVM_PV_ASYNC_CLEANUP_PREPARE can be called again as soon as cleanup starts, i.e. before KVM_PV_ASYNC_CLEANUP_PERFORM finishes.h]hXbPrepare the current protected VM for asynchronous teardown. Most resources used by the current protected VM will be set aside for a subsequent asynchronous teardown. The current protected VM will then resume execution immediately as non-protected. There can be at most one protected VM prepared for asynchronous teardown at any time. If a protected VM had already been prepared for teardown without subsequently calling KVM_PV_ASYNC_CLEANUP_PERFORM, this call will fail. In that case, the userspace process should issue a normal KVM_PV_DISABLE. The resources set aside with this call will need to be cleaned up with a subsequent call to KVM_PV_ASYNC_CLEANUP_PERFORM or KVM_PV_DISABLE, otherwise they will be cleaned up when KVM terminates. KVM_PV_ASYNC_CLEANUP_PREPARE can be called again as soon as cleanup starts, i.e. before KVM_PV_ASYNC_CLEANUP_PERFORM finishes.}(hj +hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubeh}(h]h ]h"]h$]h&]uh1j$hj*ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj(hhubj)}(hXKVM_PV_ASYNC_CLEANUP_PERFORM :Capability: KVM_CAP_S390_PROTECTED_ASYNC_DISABLE Tear down the protected VM previously prepared for teardown with KVM_PV_ASYNC_CLEANUP_PREPARE. The resources that had been set aside will be freed during the execution of this command. This PV command should ideally be issued by userspace from a separate thread. If a fatal signal is received (or the process terminates naturally), the command will terminate immediately without completing, and the normal KVM shutdown procedure will take care of cleaning up all remaining protected VMs, including the ones whose teardown was interrupted by process termination. h](j)}(hKVM_PV_ASYNC_CLEANUP_PERFORMh]hKVM_PV_ASYNC_CLEANUP_PERFORM}(hj)+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj%+ubj%)}(hhh](js)}(hhh]jx)}(hhh](j})}(h Capabilityh]h Capability}(hj@+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj=+hhhKubj)}(h%KVM_CAP_S390_PROTECTED_ASYNC_DISABLE h]h)}(h$KVM_CAP_S390_PROTECTED_ASYNC_DISABLEh]h$KVM_CAP_S390_PROTECTED_ASYNC_DISABLE}(hjR+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjN+ubah}(h]h ]h"]h$]h&]uh1jhj=+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj:+ubah}(h]h ]h"]h$]h&]uh1jrhj7+ubh)}(hX1Tear down the protected VM previously prepared for teardown with KVM_PV_ASYNC_CLEANUP_PREPARE. The resources that had been set aside will be freed during the execution of this command. This PV command should ideally be issued by userspace from a separate thread. If a fatal signal is received (or the process terminates naturally), the command will terminate immediately without completing, and the normal KVM shutdown procedure will take care of cleaning up all remaining protected VMs, including the ones whose teardown was interrupted by process termination.h]hX1Tear down the protected VM previously prepared for teardown with KVM_PV_ASYNC_CLEANUP_PREPARE. The resources that had been set aside will be freed during the execution of this command. This PV command should ideally be issued by userspace from a separate thread. If a fatal signal is received (or the process terminates naturally), the command will terminate immediately without completing, and the normal KVM shutdown procedure will take care of cleaning up all remaining protected VMs, including the ones whose teardown was interrupted by process termination.}(hjr+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7+ubeh}(h]h ]h"]h$]h&]uh1j$hj%+ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj(hhubeh}(h]h ]h"]h$]h&]uh1j hj$hhhNhNubeh}(h]kvm-s390-pv-commandah ]h"]4.125 kvm_s390_pv_commandah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.126 KVM_XEN_HVM_SET_ATTRh]h4.126 KVM_XEN_HVM_SET_ATTR}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFOh]h)}(hj+h]h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj+hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj+hhhKubj)}(hx86h]h)}(hj+h]hx86}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj+hhubjx)}(hhh](j})}(hTypeh]hType}(hj ,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj ,hhhKubj)}(hvm ioctlh]h)}(hj,h]hvm ioctl}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1jhj ,ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj+hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj;,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8,hhhKubj)}(hstruct kvm_xen_hvm_attrh]h)}(hjK,h]hstruct kvm_xen_hvm_attr}(hjM,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjI,ubah}(h]h ]h"]h$]h&]uh1jhj8,ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj+hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hji,hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjf,hhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hj{,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjw,ubah}(h]h ]h"]h$]h&]uh1jhjf,ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj+hhubeh}(h]h ]h"]h$]h&]uh1jrhj+hhhhhMubj8)}(hXWstruct kvm_xen_hvm_attr { __u16 type; __u16 pad[3]; union { __u8 long_mode; __u8 vector; __u8 runstate_update_flag; union { __u64 gfn; __u64 hva; } shared_info; struct { __u32 send_port; __u32 type; /* EVTCHNSTAT_ipi / EVTCHNSTAT_interdomain */ __u32 flags; union { struct { __u32 port; __u32 vcpu; __u32 priority; } port; struct { __u32 port; /* Zero for eventfd */ __s32 fd; } eventfd; __u32 padding[4]; } deliver; } evtchn; __u32 xen_version; __u64 pad[8]; } u; };h]hXWstruct kvm_xen_hvm_attr { __u16 type; __u16 pad[3]; union { __u8 long_mode; __u8 vector; __u8 runstate_update_flag; union { __u64 gfn; __u64 hva; } shared_info; struct { __u32 send_port; __u32 type; /* EVTCHNSTAT_ipi / EVTCHNSTAT_interdomain */ __u32 flags; union { struct { __u32 port; __u32 vcpu; __u32 priority; } port; struct { __u32 port; /* Zero for eventfd */ __s32 fd; } eventfd; __u32 padding[4]; } deliver; } evtchn; __u32 xen_version; __u64 pad[8]; } u; };}hj,sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj+hhubh)}(h type values:h]h type values:}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+hhubj )}(hhh](j)}(hKVM_XEN_ATTR_TYPE_LONG_MODE Sets the ABI mode of the VM to 32-bit or 64-bit (long mode). This determines the layout of the shared_info page exposed to the VM. h](j)}(hKVM_XEN_ATTR_TYPE_LONG_MODEh]hKVM_XEN_ATTR_TYPE_LONG_MODE}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj,ubj%)}(hhh]h)}(hSets the ABI mode of the VM to 32-bit or 64-bit (long mode). This determines the layout of the shared_info page exposed to the VM.h]hSets the ABI mode of the VM to 32-bit or 64-bit (long mode). This determines the layout of the shared_info page exposed to the VM.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1j$hj,ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj,ubj)}(hXKVM_XEN_ATTR_TYPE_SHARED_INFO Sets the guest physical frame number at which the Xen shared_info page resides. Note that although Xen places vcpu_info for the first 32 vCPUs in the shared_info page, KVM does not automatically do so and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO or KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA be used explicitly even when the vcpu_info for a given vCPU resides at the "default" location in the shared_info page. This is because KVM may not be aware of the Xen CPU id which is used as the index into the vcpu_info[] array, so may know the correct default location. Note that the shared_info page may be constantly written to by KVM; it contains the event channel bitmap used to deliver interrupts to a Xen guest, amongst other things. It is exempt from dirty tracking mechanisms — KVM will not explicitly mark the page as dirty each time an event channel interrupt is delivered to the guest! Thus, userspace should always assume that the designated GFN is dirty if any vCPU has been running or any event channel interrupts can be routed to the guest. Setting the gfn to KVM_XEN_INVALID_GFN will disable the shared_info page. h](j)}(hKVM_XEN_ATTR_TYPE_SHARED_INFOh]hKVM_XEN_ATTR_TYPE_SHARED_INFO}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj,ubj%)}(hhh](h)}(hX:Sets the guest physical frame number at which the Xen shared_info page resides. Note that although Xen places vcpu_info for the first 32 vCPUs in the shared_info page, KVM does not automatically do so and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO or KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA be used explicitly even when the vcpu_info for a given vCPU resides at the "default" location in the shared_info page. This is because KVM may not be aware of the Xen CPU id which is used as the index into the vcpu_info[] array, so may know the correct default location.h]hX>Sets the guest physical frame number at which the Xen shared_info page resides. Note that although Xen places vcpu_info for the first 32 vCPUs in the shared_info page, KVM does not automatically do so and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO or KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA be used explicitly even when the vcpu_info for a given vCPU resides at the “default” location in the shared_info page. This is because KVM may not be aware of the Xen CPU id which is used as the index into the vcpu_info[] array, so may know the correct default location.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubh)}(hXNote that the shared_info page may be constantly written to by KVM; it contains the event channel bitmap used to deliver interrupts to a Xen guest, amongst other things. It is exempt from dirty tracking mechanisms — KVM will not explicitly mark the page as dirty each time an event channel interrupt is delivered to the guest! Thus, userspace should always assume that the designated GFN is dirty if any vCPU has been running or any event channel interrupts can be routed to the guest.h]hXNote that the shared_info page may be constantly written to by KVM; it contains the event channel bitmap used to deliver interrupts to a Xen guest, amongst other things. It is exempt from dirty tracking mechanisms — KVM will not explicitly mark the page as dirty each time an event channel interrupt is delivered to the guest! Thus, userspace should always assume that the designated GFN is dirty if any vCPU has been running or any event channel interrupts can be routed to the guest.}(hj -hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubh)}(hISetting the gfn to KVM_XEN_INVALID_GFN will disable the shared_info page.h]hISetting the gfn to KVM_XEN_INVALID_GFN will disable the shared_info page.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubeh}(h]h ]h"]h$]h&]uh1j$hj,ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj,hhubj)}(hXBKVM_XEN_ATTR_TYPE_SHARED_INFO_HVA If the KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA flag is also set in the Xen capabilities, then this attribute may be used to set the userspace address at which the shared_info page resides, which will always be fixed in the VMM regardless of where it is mapped in guest physical address space. This attribute should be used in preference to KVM_XEN_ATTR_TYPE_SHARED_INFO as it avoids unnecessary invalidation of an internal cache when the page is re-mapped in guest physical address space. Setting the hva to zero will disable the shared_info page. h](j)}(h!KVM_XEN_ATTR_TYPE_SHARED_INFO_HVAh]h!KVM_XEN_ATTR_TYPE_SHARED_INFO_HVA}(hj8-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM%hj4-ubj%)}(hhh](h)}(hXIf the KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA flag is also set in the Xen capabilities, then this attribute may be used to set the userspace address at which the shared_info page resides, which will always be fixed in the VMM regardless of where it is mapped in guest physical address space. This attribute should be used in preference to KVM_XEN_ATTR_TYPE_SHARED_INFO as it avoids unnecessary invalidation of an internal cache when the page is re-mapped in guest physical address space.h]hXIf the KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA flag is also set in the Xen capabilities, then this attribute may be used to set the userspace address at which the shared_info page resides, which will always be fixed in the VMM regardless of where it is mapped in guest physical address space. This attribute should be used in preference to KVM_XEN_ATTR_TYPE_SHARED_INFO as it avoids unnecessary invalidation of an internal cache when the page is re-mapped in guest physical address space.}(hjI-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjF-ubh)}(h:Setting the hva to zero will disable the shared_info page.h]h:Setting the hva to zero will disable the shared_info page.}(hjW-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjF-ubeh}(h]h ]h"]h$]h&]uh1j$hj4-ubeh}(h]h ]h"]h$]h&]uh1jhhhM%hj,hhubj)}(hXVKVM_XEN_ATTR_TYPE_UPCALL_VECTOR Sets the exception vector used to deliver Xen event channel upcalls. This is the HVM-wide vector injected directly by the hypervisor (not through the local APIC), typically configured by a guest via HVM_PARAM_CALLBACK_IRQ. This can be disabled again (e.g. for guest SHUTDOWN_soft_reset) by setting it to zero. h](j)}(hKVM_XEN_ATTR_TYPE_UPCALL_VECTORh]hKVM_XEN_ATTR_TYPE_UPCALL_VECTOR}(hju-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM,hjq-ubj%)}(hhh]h)}(hX5Sets the exception vector used to deliver Xen event channel upcalls. This is the HVM-wide vector injected directly by the hypervisor (not through the local APIC), typically configured by a guest via HVM_PARAM_CALLBACK_IRQ. This can be disabled again (e.g. for guest SHUTDOWN_soft_reset) by setting it to zero.h]hX5Sets the exception vector used to deliver Xen event channel upcalls. This is the HVM-wide vector injected directly by the hypervisor (not through the local APIC), typically configured by a guest via HVM_PARAM_CALLBACK_IRQ. This can be disabled again (e.g. for guest SHUTDOWN_soft_reset) by setting it to zero.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj-ubah}(h]h ]h"]h$]h&]uh1j$hjq-ubeh}(h]h ]h"]h$]h&]uh1jhhhM,hj,hhubj)}(hX-KVM_XEN_ATTR_TYPE_EVTCHN This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures an outbound port number for interception of EVTCHNOP_send requests from the guest. A given sending port number may be directed back to a specified vCPU (by APIC ID) / port / priority on the guest, or to trigger events on an eventfd. The vCPU and priority can be changed by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but other fields cannot change for a given sending port. A port mapping is removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags field. Passing KVM_XEN_EVTCHN_RESET in the flags field removes all interception of outbound event channels. The values of the flags field are mutually exclusive and cannot be combined as a bitmask. h](j)}(hKVM_XEN_ATTR_TYPE_EVTCHNh]hKVM_XEN_ATTR_TYPE_EVTCHN}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM:hj-ubj%)}(hhh]h)}(hXThis attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures an outbound port number for interception of EVTCHNOP_send requests from the guest. A given sending port number may be directed back to a specified vCPU (by APIC ID) / port / priority on the guest, or to trigger events on an eventfd. The vCPU and priority can be changed by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but other fields cannot change for a given sending port. A port mapping is removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags field. Passing KVM_XEN_EVTCHN_RESET in the flags field removes all interception of outbound event channels. The values of the flags field are mutually exclusive and cannot be combined as a bitmask.h]hXThis attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures an outbound port number for interception of EVTCHNOP_send requests from the guest. A given sending port number may be directed back to a specified vCPU (by APIC ID) / port / priority on the guest, or to trigger events on an eventfd. The vCPU and priority can be changed by setting KVM_XEN_EVTCHN_UPDATE in a subsequent call, but other fields cannot change for a given sending port. A port mapping is removed by using KVM_XEN_EVTCHN_DEASSIGN in the flags field. Passing KVM_XEN_EVTCHN_RESET in the flags field removes all interception of outbound event channels. The values of the flags field are mutually exclusive and cannot be combined as a bitmask.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj-ubah}(h]h ]h"]h$]h&]uh1j$hj-ubeh}(h]h ]h"]h$]h&]uh1jhhhM:hj,hhubj)}(hXKVM_XEN_ATTR_TYPE_XEN_VERSION This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures the 32-bit version code returned to the guest when it invokes the XENVER_version call; typically (XEN_MAJOR << 16 | XEN_MINOR). PV Xen guests will often use this to as a dummy hypercall to trigger event channel delivery, so responding within the kernel without exiting to userspace is beneficial. h](j)}(hKVM_XEN_ATTR_TYPE_XEN_VERSIONh]hKVM_XEN_ATTR_TYPE_XEN_VERSION}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMChj-ubj%)}(hhh]h)}(hXThis attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures the 32-bit version code returned to the guest when it invokes the XENVER_version call; typically (XEN_MAJOR << 16 | XEN_MINOR). PV Xen guests will often use this to as a dummy hypercall to trigger event channel delivery, so responding within the kernel without exiting to userspace is beneficial.h]hXThis attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_EVTCHN_SEND features. It configures the 32-bit version code returned to the guest when it invokes the XENVER_version call; typically (XEN_MAJOR << 16 | XEN_MINOR). PV Xen guests will often use this to as a dummy hypercall to trigger event channel delivery, so responding within the kernel without exiting to userspace is beneficial.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=hj-ubah}(h]h ]h"]h$]h&]uh1j$hj-ubeh}(h]h ]h"]h$]h&]uh1jhhhMChj,hhubj)}(hXKVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG. It enables the XEN_RUNSTATE_UPDATE flag which allows guest vCPUs to safely read other vCPUs' vcpu_runstate_info. Xen guests enable this feature via the VMASST_TYPE_runstate_update_flag of the HYPERVISOR_vm_assist hypercall. h](j)}(h&KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAGh]h&KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMKhj-ubj%)}(hhh]h)}(hXYThis attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG. It enables the XEN_RUNSTATE_UPDATE flag which allows guest vCPUs to safely read other vCPUs' vcpu_runstate_info. Xen guests enable this feature via the VMASST_TYPE_runstate_update_flag of the HYPERVISOR_vm_assist hypercall.h]hX[This attribute is available when the KVM_CAP_XEN_HVM ioctl indicates support for KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG. It enables the XEN_RUNSTATE_UPDATE flag which allows guest vCPUs to safely read other vCPUs’ vcpu_runstate_info. Xen guests enable this feature via the VMASST_TYPE_runstate_update_flag of the HYPERVISOR_vm_assist hypercall.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj.ubah}(h]h ]h"]h$]h&]uh1j$hj-ubeh}(h]h ]h"]h$]h&]uh1jhhhMKhj,hhubeh}(h]h ]h"]h$]h&]uh1j hj+hhhhhNubeh}(h]kvm-xen-hvm-set-attrah ]h"]4.126 kvm_xen_hvm_set_attrah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.127 KVM_XEN_HVM_GET_ATTRh]h4.127 KVM_XEN_HVM_GET_ATTR}(hj>.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;.hhhhhMNubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjR.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjO.hhhKubj)}(h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFOh]h)}(hjb.h]h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO}(hjd.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhj`.ubah}(h]h ]h"]h$]h&]uh1jhjO.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMPhjL.hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj}.hhhKubj)}(hx86h]h)}(hj.h]hx86}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhj.ubah}(h]h ]h"]h$]h&]uh1jhj}.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMQhjL.hhubjx)}(hhh](j})}(hTypeh]hType}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.hhhKubj)}(hvm ioctlh]h)}(hj.h]hvm ioctl}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMRhjL.hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.hhhKubj)}(hstruct kvm_xen_hvm_attrh]h)}(hj.h]hstruct kvm_xen_hvm_attr}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj.ubah}(h]h ]h"]h$]h&]uh1jhj.ubeh}(h]h ]h"]h$]h&]uh1jwhhhMShjL.hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj /hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj/hhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj/ubah}(h]h ]h"]h$]h&]uh1jhj/ubeh}(h]h ]h"]h$]h&]uh1jwhhhMThjL.hhubeh}(h]h ]h"]h$]h&]uh1jrhj;.hhhhhMPubh)}(hAllows Xen VM attributes to be read. For the structure and types, see KVM_XEN_HVM_SET_ATTR above. The KVM_XEN_ATTR_TYPE_EVTCHN attribute cannot be read.h]hAllows Xen VM attributes to be read. For the structure and types, see KVM_XEN_HVM_SET_ATTR above. The KVM_XEN_ATTR_TYPE_EVTCHN attribute cannot be read.}(hj4h]hstruct kvm_arm_copy_mte_tags}(hj@4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<4ubah}(h]h ]h"]h$]h&]uh1jhj+4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj\4hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjY4hhhKubj)}(hnnumber of bytes copied, < 0 on error (-EINVAL for incorrect arguments, -EFAULT if memory cannot be accessed). h]h)}(hmnumber of bytes copied, < 0 on error (-EINVAL for incorrect arguments, -EFAULT if memory cannot be accessed).h]hmnumber of bytes copied, < 0 on error (-EINVAL for incorrect arguments, -EFAULT if memory cannot be accessed).}(hjn4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjj4ubah}(h]h ]h"]h$]h&]uh1jhjY4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj3hhubeh}(h]h ]h"]h$]h&]uh1jrhj3hhhhhMubj8)}(hstruct kvm_arm_copy_mte_tags { __u64 guest_ipa; __u64 length; void __user *addr; __u64 flags; __u64 reserved[2]; };h]hstruct kvm_arm_copy_mte_tags { __u64 guest_ipa; __u64 length; void __user *addr; __u64 flags; __u64 reserved[2]; };}hj4sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj3hhubh)}(hXCopies Memory Tagging Extension (MTE) tags to/from guest tag memory. The ``guest_ipa`` and ``length`` fields must be ``PAGE_SIZE`` aligned. ``length`` must not be bigger than 2^31 - PAGE_SIZE bytes. The ``addr`` field must point to a buffer which the tags will be copied to or from.h](hICopies Memory Tagging Extension (MTE) tags to/from guest tag memory. The }(hj4hhhNhNubj)}(h ``guest_ipa``h]h guest_ipa}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh and }(hj4hhhNhNubj)}(h ``length``h]hlength}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh fields must be }(hj4hhhNhNubj)}(h ``PAGE_SIZE``h]h PAGE_SIZE}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh aligned. }(hj4hhhNhNubj)}(h ``length``h]hlength}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubh5 must not be bigger than 2^31 - PAGE_SIZE bytes. The }(hj4hhhNhNubj)}(h``addr``h]haddr}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj4ubhG field must point to a buffer which the tags will be copied to or from.}(hj4hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hk``flags`` specifies the direction of copy, either ``KVM_ARM_TAGS_TO_GUEST`` or ``KVM_ARM_TAGS_FROM_GUEST``.h](j)}(h ``flags``h]hflags}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh) specifies the direction of copy, either }(hj5hhhNhNubj)}(h``KVM_ARM_TAGS_TO_GUEST``h]hKVM_ARM_TAGS_TO_GUEST}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh or }(hj5hhhNhNubj)}(h``KVM_ARM_TAGS_FROM_GUEST``h]hKVM_ARM_TAGS_FROM_GUEST}(hj,5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hThe size of the buffer to store the tags is ``(length / 16)`` bytes (granules in MTE are 16 bytes long). Each byte contains a single tag value. This matches the format of ``PTRACE_PEEKMTETAGS`` and ``PTRACE_POKEMTETAGS``.h](h,The size of the buffer to store the tags is }(hjD5hhhNhNubj)}(h``(length / 16)``h]h (length / 16)}(hjL5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD5ubhn bytes (granules in MTE are 16 bytes long). Each byte contains a single tag value. This matches the format of }(hjD5hhhNhNubj)}(h``PTRACE_PEEKMTETAGS``h]hPTRACE_PEEKMTETAGS}(hj^5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD5ubh and }(hjD5hhhNhNubj)}(h``PTRACE_POKEMTETAGS``h]hPTRACE_POKEMTETAGS}(hjp5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjD5ubh.}(hjD5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubh)}(hXIf an error occurs before any data is copied then a negative error code is returned. If some tags have been copied before an error occurs then the number of bytes successfully copied is returned. If the call completes successfully then ``length`` is returned.h](hIf an error occurs before any data is copied then a negative error code is returned. If some tags have been copied before an error occurs then the number of bytes successfully copied is returned. If the call completes successfully then }(hj5hhhNhNubj)}(h ``length``h]hlength}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh is returned.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj3hhubeh}(h]kvm-arm-mte-copy-tagsah ]h"]4.130 kvm_arm_mte_copy_tagsah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.131 KVM_GET_SREGS2h]h4.131 KVM_GET_SREGS2}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(hKVM_CAP_SREGS2h]h)}(hj5h]hKVM_CAP_SREGS2}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj5hhhKubj)}(hx86h]h)}(hj6h]hx86}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1jhj5ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5hhubjx)}(hhh](j})}(hTypeh]hType}(hj#6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj 6hhhKubj)}(h vcpu ioctlh]h)}(hj36h]h vcpu ioctl}(hj56hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj16ubah}(h]h ]h"]h$]h&]uh1jhj 6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjQ6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjN6hhhKubj)}(hstruct kvm_sregs2 (out)h]h)}(hja6h]hstruct kvm_sregs2 (out)}(hjc6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_6ubah}(h]h ]h"]h$]h&]uh1jhjN6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj|6hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1jhj|6ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj5hhubeh}(h]h ]h"]h$]h&]uh1jrhj5hhhhhMubh)}(h^Reads special registers from the vcpu. This ioctl (when supported) replaces the KVM_GET_SREGS.h]h^Reads special registers from the vcpu. This ioctl (when supported) replaces the KVM_GET_SREGS.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj5hhubj8)}(hXLstruct kvm_sregs2 { /* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */ struct kvm_segment cs, ds, es, fs, gs, ss; struct kvm_segment tr, ldt; struct kvm_dtable gdt, idt; __u64 cr0, cr2, cr3, cr4, cr8; __u64 efer; __u64 apic_base; __u64 flags; __u64 pdptrs[4]; };h]hXLstruct kvm_sregs2 { /* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */ struct kvm_segment cs, ds, es, fs, gs, ss; struct kvm_segment tr, ldt; struct kvm_dtable gdt, idt; __u64 cr0, cr2, cr3, cr4, cr8; __u64 efer; __u64 apic_base; __u64 flags; __u64 pdptrs[4]; };}hj6sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj5hhubh)}(h flags values for ``kvm_sregs2``:h](hflags values for }(hj6hhhNhNubj)}(h``kvm_sregs2``h]h kvm_sregs2}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubh:}(hj6hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubh)}(h!``KVM_SREGS2_FLAGS_PDPTRS_VALID``h]j)}(hj6h]hKVM_SREGS2_FLAGS_PDPTRS_VALID}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhhhMhj5hhubj )}(h8Indicates that the struct contains valid PDPTR values. h]h)}(h6Indicates that the struct contains valid PDPTR values.h]h6Indicates that the struct contains valid PDPTR values.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7ubah}(h]h ]h"]h$]h&]uh1j hhhMhj5hhubeh}(h]kvm-get-sregs2ah ]h"]4.131 kvm_get_sregs2ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.132 KVM_SET_SREGS2h]h4.132 KVM_SET_SREGS2}(hj'7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$7hhhhhM#ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj;7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj87hhhKubj)}(hKVM_CAP_SREGS2h]h)}(hjK7h]hKVM_CAP_SREGS2}(hjM7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjI7ubah}(h]h ]h"]h$]h&]uh1jhj87ubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hj57hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hji7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjf7hhhKubj)}(hx86h]h)}(hjy7h]hx86}(hj{7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjw7ubah}(h]h ]h"]h$]h&]uh1jhjf7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM&hj57hhubjx)}(hhh](j})}(hTypeh]hType}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(h vcpu ioctlh]h)}(hj7h]h vcpu ioctl}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM'hj57hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(hstruct kvm_sregs2 (in)h]h)}(hj7h]hstruct kvm_sregs2 (in)}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hj7ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM(hj57hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj7hhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj8ubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jwhhhM)hj57hhubeh}(h]h ]h"]h$]h&]uh1jrhj$7hhhhhM%ubh)}(hWrites special registers into the vcpu. See KVM_GET_SREGS2 for the data structures. This ioctl (when supported) replaces the KVM_SET_SREGS.h]hWrites special registers into the vcpu. See KVM_GET_SREGS2 for the data structures. This ioctl (when supported) replaces the KVM_SET_SREGS.}(hj%8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj$7hhubeh}(h]kvm-set-sregs2ah ]h"]4.132 kvm_set_sregs2ah$]h&]uh1hhjhhhhhM#ubh)}(hhh](h)}(h4.133 KVM_GET_STATS_FDh]h4.133 KVM_GET_STATS_FD}(hj>8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj;8hhhhhM0ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjR8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjO8hhhKubj)}(hKVM_CAP_STATS_BINARY_FDh]h)}(hjb8h]hKVM_CAP_STATS_BINARY_FD}(hjd8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hj`8ubah}(h]h ]h"]h$]h&]uh1jhjO8ubeh}(h]h ]h"]h$]h&]uh1jwhhhM2hjL8hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj}8hhhKubj)}(hallh]h)}(hj8h]hall}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hj8ubah}(h]h ]h"]h$]h&]uh1jhj}8ubeh}(h]h ]h"]h$]h&]uh1jwhhhM3hjL8hhubjx)}(hhh](j})}(hTypeh]hType}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(hvm ioctl, vcpu ioctlh]h)}(hj8h]hvm ioctl, vcpu ioctl}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhM4hjL8hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj8hhhKubj)}(hnoneh]h)}(hj8h]hnone}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj8ubah}(h]h ]h"]h$]h&]uh1jhj8ubeh}(h]h ]h"]h$]h&]uh1jwhhhM5hjL8hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj 9hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj9hhhKubj)}(h4statistics file descriptor on success, < 0 on error h]h)}(h3statistics file descriptor on success, < 0 on errorh]h3statistics file descriptor on success, < 0 on error}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6hj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jwhhhM6hjL8hhubeh}(h]h ]h"]h$]h&]uh1jrhj;8hhhhhM2ubh)}(hErrors:h]hErrors:}(hj<9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj;8hhubj )}(h====== ====================================================== ENOMEM if the fd could not be created due to lack of memory EMFILE if the number of opened files exceeds the limit ====== ====================================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjQ9ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK6uh1jchjQ9ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hENOMEMh]hENOMEM}(hjq9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjn9ubah}(h]h ]h"]h$]h&]uh1jhjk9ubj)}(hhh]h)}(h4if the fd could not be created due to lack of memoryh]h4if the fd could not be created due to lack of memory}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj9ubah}(h]h ]h"]h$]h&]uh1jhjk9ubeh}(h]h ]h"]h$]h&]uh1j~hjh9ubj)}(hhh](j)}(hhh]h)}(hEMFILEh]hEMFILE}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubj)}(hhh]h)}(h/if the number of opened files exceeds the limith]h/if the number of opened files exceeds the limit}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj9ubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1j~hjh9ubeh}(h]h ]h"]h$]h&]uh1jyhjQ9ubeh}(h]h ]h"]h$]h&]colsKuh1j^hjN9ubah}(h]h ]h"]h$]h&]uh1jYhjJ9ubah}(h]h ]h"]h$]h&]uh1j hhhM:hj;8hhubh)}(hThe returned file descriptor can be used to read VM/vCPU statistics data in binary format. The data in the file descriptor consists of four blocks organized as follows:h]hThe returned file descriptor can be used to read VM/vCPU statistics data in binary format. The data in the file descriptor consists of four blocks organized as follows:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj;8hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchj:ubjz)}(hhh](j)}(hhh]j)}(hhh]h)}(hHeaderh]hHeader}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhj:ubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1j~hj:ubj)}(hhh]j)}(hhh]h)}(h id stringh]h id string}(hj9:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj6:ubah}(h]h ]h"]h$]h&]uh1jhj3:ubah}(h]h ]h"]h$]h&]uh1j~hj:ubj)}(hhh]j)}(hhh]h)}(h Descriptorsh]h Descriptors}(hjY:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjV:ubah}(h]h ]h"]h$]h&]uh1jhjS:ubah}(h]h ]h"]h$]h&]uh1j~hj:ubj)}(hhh]j)}(hhh]h)}(h Stats Datah]h Stats Data}(hjy:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjv:ubah}(h]h ]h"]h$]h&]uh1jhjs:ubah}(h]h ]h"]h$]h&]uh1j~hj:ubeh}(h]h ]h"]h$]h&]uh1jyhj:ubeh}(h]h ]h"]h$]h&]colsKuh1j^hj:ubah}(h]h ]h"]h$]h&]uh1jYhj;8hhhhhNubh)}(hX7Apart from the header starting at offset 0, please be aware that it is not guaranteed that the four blocks are adjacent or in the above order; the offsets of the id, descriptors and data blocks are found in the header. However, all four blocks are aligned to 64 bit offsets in the file and they do not overlap.h]hX7Apart from the header starting at offset 0, please be aware that it is not guaranteed that the four blocks are adjacent or in the above order; the offsets of the id, descriptors and data blocks are found in the header. However, all four blocks are aligned to 64 bit offsets in the file and they do not overlap.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj;8hhubh)}(hAll blocks except the data block are immutable. Userspace can read them only one time after retrieving the file descriptor, and then use ``pread`` or ``lseek`` to read the statistics repeatedly.h](hAll blocks except the data block are immutable. Userspace can read them only one time after retrieving the file descriptor, and then use }(hj:hhhNhNubj)}(h ``pread``h]hpread}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubh or }(hj:hhhNhNubj)}(h ``lseek``h]hlseek}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubh# to read the statistics repeatedly.}(hj:hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMShj;8hhubh)}(h!All data is in system endianness.h]h!All data is in system endianness.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhj;8hhubh)}(h(The format of the header is as follows::h]h'The format of the header is as follows:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhj;8hhubj8)}(hstruct kvm_stats_header { __u32 flags; __u32 name_size; __u32 num_desc; __u32 id_offset; __u32 desc_offset; __u32 data_offset; };h]hstruct kvm_stats_header { __u32 flags; __u32 name_size; __u32 num_desc; __u32 id_offset; __u32 desc_offset; __u32 data_offset; };}hj;sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM[hj;8hhubh)}(hFThe ``flags`` field is not used at the moment. It is always read as 0.h](hThe }(hj;hhhNhNubj)}(h ``flags``h]hflags}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh9 field is not used at the moment. It is always read as 0.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMdhj;8hhubh)}(hThe ``name_size`` field is the size (in byte) of the statistics name string (including trailing '\0') which is contained in the "id string" block and appended at the end of every descriptor.h](hThe }(hj0;hhhNhNubj)}(h ``name_size``h]h name_size}(hj8;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0;ubh field is the size (in byte) of the statistics name string (including trailing ‘0’) which is contained in the “id string” block and appended at the end of every descriptor.}(hj0;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMfhj;8hhubh)}(hThe ``num_desc`` field is the number of descriptors that are included in the descriptor block. (The actual number of values in the data block may be larger, since each descriptor may comprise more than one value).h](hThe }(hjP;hhhNhNubj)}(h ``num_desc``h]hnum_desc}(hjX;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjP;ubh field is the number of descriptors that are included in the descriptor block. (The actual number of values in the data block may be larger, since each descriptor may comprise more than one value).}(hjP;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMjhj;8hhubh)}(hThe ``id_offset`` field is the offset of the id string from the start of the file indicated by the file descriptor. It is a multiple of 8.h](hThe }(hjp;hhhNhNubj)}(h ``id_offset``h]h id_offset}(hjx;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjp;ubhy field is the offset of the id string from the start of the file indicated by the file descriptor. It is a multiple of 8.}(hjp;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMnhj;8hhubh)}(hThe ``desc_offset`` field is the offset of the Descriptors block from the start of the file indicated by the file descriptor. It is a multiple of 8.h](hThe }(hj;hhhNhNubj)}(h``desc_offset``h]h desc_offset}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh field is the offset of the Descriptors block from the start of the file indicated by the file descriptor. It is a multiple of 8.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMqhj;8hhubh)}(hThe ``data_offset`` field is the offset of the Stats Data block from the start of the file indicated by the file descriptor. It is a multiple of 8.h](hThe }(hj;hhhNhNubj)}(h``data_offset``h]h data_offset}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh field is the offset of the Stats Data block from the start of the file indicated by the file descriptor. It is a multiple of 8.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMthj;8hhubh)}(hThe id string block contains a string which identifies the file descriptor on which KVM_GET_STATS_FD was invoked. The size of the block, including the trailing ``'\0'``, is indicated by the ``name_size`` field in the header.h](hThe id string block contains a string which identifies the file descriptor on which KVM_GET_STATS_FD was invoked. The size of the block, including the trailing }(hj;hhhNhNubj)}(h``'\0'``h]h'\0'}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh, is indicated by the }(hj;hhhNhNubj)}(h ``name_size``h]h name_size}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj;ubh field in the header.}(hj;hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMwhj;8hhubh)}(hThe descriptors block is only needed to be read once for the lifetime of the file descriptor contains a sequence of ``struct kvm_stats_desc``, each followed by a string of size ``name_size``. ::h](htThe descriptors block is only needed to be read once for the lifetime of the file descriptor contains a sequence of }(hj<hhhNhNubj)}(h``struct kvm_stats_desc``h]hstruct kvm_stats_desc}(hj <hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh$, each followed by a string of size }(hj<hhhNhNubj)}(h ``name_size``h]h name_size}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM{hj;8hhubj8)}(hX#define KVM_STATS_TYPE_SHIFT 0 #define KVM_STATS_TYPE_MASK (0xF << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_CUMULATIVE (0x0 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_INSTANT (0x1 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_PEAK (0x2 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_LINEAR_HIST (0x3 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_LOG_HIST (0x4 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_LOG_HIST #define KVM_STATS_UNIT_SHIFT 4 #define KVM_STATS_UNIT_MASK (0xF << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_NONE (0x0 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_BYTES (0x1 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_SECONDS (0x2 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_BOOLEAN (0x4 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_MAX KVM_STATS_UNIT_BOOLEAN #define KVM_STATS_BASE_SHIFT 8 #define KVM_STATS_BASE_MASK (0xF << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_POW10 (0x0 << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_POW2 (0x1 << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_MAX KVM_STATS_BASE_POW2 struct kvm_stats_desc { __u32 flags; __s16 exponent; __u16 size; __u32 offset; __u32 bucket_size; char name[]; };h]hX#define KVM_STATS_TYPE_SHIFT 0 #define KVM_STATS_TYPE_MASK (0xF << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_CUMULATIVE (0x0 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_INSTANT (0x1 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_PEAK (0x2 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_LINEAR_HIST (0x3 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_LOG_HIST (0x4 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_LOG_HIST #define KVM_STATS_UNIT_SHIFT 4 #define KVM_STATS_UNIT_MASK (0xF << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_NONE (0x0 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_BYTES (0x1 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_SECONDS (0x2 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_BOOLEAN (0x4 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_MAX KVM_STATS_UNIT_BOOLEAN #define KVM_STATS_BASE_SHIFT 8 #define KVM_STATS_BASE_MASK (0xF << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_POW10 (0x0 << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_POW2 (0x1 << KVM_STATS_BASE_SHIFT) #define KVM_STATS_BASE_MAX KVM_STATS_BASE_POW2 struct kvm_stats_desc { __u32 flags; __s16 exponent; __u16 size; __u32 offset; __u32 bucket_size; char name[]; };}hj4<sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj;8hhubh)}(hThe ``flags`` field contains the type and unit of the statistics data described by this descriptor. Its endianness is CPU native. The following flags are supported:h](hThe }(hjB<hhhNhNubj)}(h ``flags``h]hflags}(hjJ<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjB<ubh field contains the type and unit of the statistics data described by this descriptor. Its endianness is CPU native. The following flags are supported:}(hjB<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(h&Bits 0-3 of ``flags`` encode the type:h](h Bits 0-3 of }(hjb<hhhNhNubj)}(h ``flags``h]hflags}(hjj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjb<ubh encode the type:}(hjb<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubj )}(hX* ``KVM_STATS_TYPE_CUMULATIVE`` The statistics reports a cumulative count. The value of data can only be increased. Most of the counters used in KVM are of this type. The corresponding ``size`` field for this type is always 1. All cumulative statistics data are read/write. * ``KVM_STATS_TYPE_INSTANT`` The statistics reports an instantaneous value. Its value can be increased or decreased. This type is usually used as a measurement of some resources, like the number of dirty pages, the number of large pages, etc. All instant statistics are read only. The corresponding ``size`` field for this type is always 1. * ``KVM_STATS_TYPE_PEAK`` The statistics data reports a peak value, for example the maximum number of items in a hash table bucket, the longest time waited and so on. The value of data can only be increased. The corresponding ``size`` field for this type is always 1. * ``KVM_STATS_TYPE_LINEAR_HIST`` The statistic is reported as a linear histogram. The number of buckets is specified by the ``size`` field. The size of buckets is specified by the ``hist_param`` field. The range of the Nth bucket (1 <= N < ``size``) is [``hist_param``*(N-1), ``hist_param``*N), while the range of the last bucket is [``hist_param``*(``size``-1), +INF). (+INF means positive infinity value.) * ``KVM_STATS_TYPE_LOG_HIST`` The statistic is reported as a logarithmic histogram. The number of buckets is specified by the ``size`` field. The range of the first bucket is [0, 1), while the range of the last bucket is [pow(2, ``size``-2), +INF). Otherwise, The Nth bucket (1 < N < ``size``) covers [pow(2, N-2), pow(2, N-1)). h]j)}(hhh](j)}(hX``KVM_STATS_TYPE_CUMULATIVE`` The statistics reports a cumulative count. The value of data can only be increased. Most of the counters used in KVM are of this type. The corresponding ``size`` field for this type is always 1. All cumulative statistics data are read/write.h]h)}(hX``KVM_STATS_TYPE_CUMULATIVE`` The statistics reports a cumulative count. The value of data can only be increased. Most of the counters used in KVM are of this type. The corresponding ``size`` field for this type is always 1. All cumulative statistics data are read/write.h](j)}(h``KVM_STATS_TYPE_CUMULATIVE``h]hKVM_STATS_TYPE_CUMULATIVE}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh The statistics reports a cumulative count. The value of data can only be increased. Most of the counters used in KVM are of this type. The corresponding }(hj<hhhNhNubj)}(h``size``h]hsize}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubhP field for this type is always 1. All cumulative statistics data are read/write.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hXR``KVM_STATS_TYPE_INSTANT`` The statistics reports an instantaneous value. Its value can be increased or decreased. This type is usually used as a measurement of some resources, like the number of dirty pages, the number of large pages, etc. All instant statistics are read only. The corresponding ``size`` field for this type is always 1.h]h)}(hXR``KVM_STATS_TYPE_INSTANT`` The statistics reports an instantaneous value. Its value can be increased or decreased. This type is usually used as a measurement of some resources, like the number of dirty pages, the number of large pages, etc. All instant statistics are read only. The corresponding ``size`` field for this type is always 1.h](j)}(h``KVM_STATS_TYPE_INSTANT``h]hKVM_STATS_TYPE_INSTANT}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubhX The statistics reports an instantaneous value. Its value can be increased or decreased. This type is usually used as a measurement of some resources, like the number of dirty pages, the number of large pages, etc. All instant statistics are read only. The corresponding }(hj<hhhNhNubj)}(h``size``h]hsize}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh! field for this type is always 1.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hX ``KVM_STATS_TYPE_PEAK`` The statistics data reports a peak value, for example the maximum number of items in a hash table bucket, the longest time waited and so on. The value of data can only be increased. The corresponding ``size`` field for this type is always 1.h]h)}(hX ``KVM_STATS_TYPE_PEAK`` The statistics data reports a peak value, for example the maximum number of items in a hash table bucket, the longest time waited and so on. The value of data can only be increased. The corresponding ``size`` field for this type is always 1.h](j)}(h``KVM_STATS_TYPE_PEAK``h]hKVM_STATS_TYPE_PEAK}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh The statistics data reports a peak value, for example the maximum number of items in a hash table bucket, the longest time waited and so on. The value of data can only be increased. The corresponding }(hj<hhhNhNubj)}(h``size``h]hsize}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj<ubh! field for this type is always 1.}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hX``KVM_STATS_TYPE_LINEAR_HIST`` The statistic is reported as a linear histogram. The number of buckets is specified by the ``size`` field. The size of buckets is specified by the ``hist_param`` field. The range of the Nth bucket (1 <= N < ``size``) is [``hist_param``*(N-1), ``hist_param``*N), while the range of the last bucket is [``hist_param``*(``size``-1), +INF). (+INF means positive infinity value.)h]h)}(hX``KVM_STATS_TYPE_LINEAR_HIST`` The statistic is reported as a linear histogram. The number of buckets is specified by the ``size`` field. The size of buckets is specified by the ``hist_param`` field. The range of the Nth bucket (1 <= N < ``size``) is [``hist_param``*(N-1), ``hist_param``*N), while the range of the last bucket is [``hist_param``*(``size``-1), +INF). (+INF means positive infinity value.)h](j)}(h``KVM_STATS_TYPE_LINEAR_HIST``h]hKVM_STATS_TYPE_LINEAR_HIST}(hj9=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5=ubh\ The statistic is reported as a linear histogram. The number of buckets is specified by the }(hj5=hhhNhNubj)}(h``size``h]hsize}(hjK=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5=ubh0 field. The size of buckets is specified by the }(hj5=hhhNhNubj)}(h``hist_param``h]h hist_param}(hj]=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5=ubh. field. The range of the Nth bucket (1 <= N < }(hj5=hhhNhNubj)}(h``size``h]hsize}(hjo=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5=ubh) is [}(hj5=hhhNhNubj)}(hh``hist_param``*(N-1), ``hist_param``*N), while the range of the last bucket is [``hist_param``*(``size``h]hdhist_param``*(N-1), ``hist_param``*N), while the range of the last bucket is [``hist_param``*(``size}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5=ubh1-1), +INF). (+INF means positive infinity value.)}(hj5=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj1=ubah}(h]h ]h"]h$]h&]uh1jhj<ubj)}(hXG``KVM_STATS_TYPE_LOG_HIST`` The statistic is reported as a logarithmic histogram. The number of buckets is specified by the ``size`` field. The range of the first bucket is [0, 1), while the range of the last bucket is [pow(2, ``size``-2), +INF). Otherwise, The Nth bucket (1 < N < ``size``) covers [pow(2, N-2), pow(2, N-1)). h]h)}(hXF``KVM_STATS_TYPE_LOG_HIST`` The statistic is reported as a logarithmic histogram. The number of buckets is specified by the ``size`` field. The range of the first bucket is [0, 1), while the range of the last bucket is [pow(2, ``size``-2), +INF). Otherwise, The Nth bucket (1 < N < ``size``) covers [pow(2, N-2), pow(2, N-1)).h](j)}(h``KVM_STATS_TYPE_LOG_HIST``h]hKVM_STATS_TYPE_LOG_HIST}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubha The statistic is reported as a logarithmic histogram. The number of buckets is specified by the }(hj=hhhNhNubj)}(h``size``h]hsize}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh_ field. The range of the first bucket is [0, 1), while the range of the last bucket is [pow(2, }(hj=hhhNhNubj)}(h``size``h]hsize}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh/-2), +INF). Otherwise, The Nth bucket (1 < N < }(hj=hhhNhNubj)}(h``size``h]hsize}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh$) covers [pow(2, N-2), pow(2, N-1)).}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj=ubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj<ubah}(h]h ]h"]h$]h&]uh1j hhhMhj;8hhubh)}(h&Bits 4-7 of ``flags`` encode the unit:h](h Bits 4-7 of }(hj>hhhNhNubj)}(h ``flags``h]hflags}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh encode the unit:}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubj )}(hXU* ``KVM_STATS_UNIT_NONE`` There is no unit for the value of statistics data. This usually means that the value is a simple counter of an event. * ``KVM_STATS_UNIT_BYTES`` It indicates that the statistics data is used to measure memory size, in the unit of Byte, KiByte, MiByte, GiByte, etc. The unit of the data is determined by the ``exponent`` field in the descriptor. * ``KVM_STATS_UNIT_SECONDS`` It indicates that the statistics data is used to measure time or latency. * ``KVM_STATS_UNIT_CYCLES`` It indicates that the statistics data is used to measure CPU clock cycles. * ``KVM_STATS_UNIT_BOOLEAN`` It indicates that the statistic will always be either 0 or 1. Boolean statistics of "peak" type will never go back from 1 to 0. Boolean statistics can be linear histograms (with two buckets) but not logarithmic histograms. h]j)}(hhh](j)}(h``KVM_STATS_UNIT_NONE`` There is no unit for the value of statistics data. This usually means that the value is a simple counter of an event.h]h)}(h``KVM_STATS_UNIT_NONE`` There is no unit for the value of statistics data. This usually means that the value is a simple counter of an event.h](j)}(h``KVM_STATS_UNIT_NONE``h]hKVM_STATS_UNIT_NONE}(hj6>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2>ubhv There is no unit for the value of statistics data. This usually means that the value is a simple counter of an event.}(hj2>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj.>ubah}(h]h ]h"]h$]h&]uh1jhj+>ubj)}(h``KVM_STATS_UNIT_BYTES`` It indicates that the statistics data is used to measure memory size, in the unit of Byte, KiByte, MiByte, GiByte, etc. The unit of the data is determined by the ``exponent`` field in the descriptor.h]h)}(h``KVM_STATS_UNIT_BYTES`` It indicates that the statistics data is used to measure memory size, in the unit of Byte, KiByte, MiByte, GiByte, etc. The unit of the data is determined by the ``exponent`` field in the descriptor.h](j)}(h``KVM_STATS_UNIT_BYTES``h]hKVM_STATS_UNIT_BYTES}(hj\>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX>ubh It indicates that the statistics data is used to measure memory size, in the unit of Byte, KiByte, MiByte, GiByte, etc. The unit of the data is determined by the }(hjX>hhhNhNubj)}(h ``exponent``h]hexponent}(hjn>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjX>ubh field in the descriptor.}(hjX>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjT>ubah}(h]h ]h"]h$]h&]uh1jhj+>ubj)}(hd``KVM_STATS_UNIT_SECONDS`` It indicates that the statistics data is used to measure time or latency.h]h)}(hd``KVM_STATS_UNIT_SECONDS`` It indicates that the statistics data is used to measure time or latency.h](j)}(h``KVM_STATS_UNIT_SECONDS``h]hKVM_STATS_UNIT_SECONDS}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhJ It indicates that the statistics data is used to measure time or latency.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj+>ubj)}(hd``KVM_STATS_UNIT_CYCLES`` It indicates that the statistics data is used to measure CPU clock cycles.h]h)}(hd``KVM_STATS_UNIT_CYCLES`` It indicates that the statistics data is used to measure CPU clock cycles.h](j)}(h``KVM_STATS_UNIT_CYCLES``h]hKVM_STATS_UNIT_CYCLES}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubhK It indicates that the statistics data is used to measure CPU clock cycles.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj+>ubj)}(h``KVM_STATS_UNIT_BOOLEAN`` It indicates that the statistic will always be either 0 or 1. Boolean statistics of "peak" type will never go back from 1 to 0. Boolean statistics can be linear histograms (with two buckets) but not logarithmic histograms. h]h)}(h``KVM_STATS_UNIT_BOOLEAN`` It indicates that the statistic will always be either 0 or 1. Boolean statistics of "peak" type will never go back from 1 to 0. Boolean statistics can be linear histograms (with two buckets) but not logarithmic histograms.h](j)}(h``KVM_STATS_UNIT_BOOLEAN``h]hKVM_STATS_UNIT_BOOLEAN}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj>ubh It indicates that the statistic will always be either 0 or 1. Boolean statistics of “peak” type will never go back from 1 to 0. Boolean statistics can be linear histograms (with two buckets) but not logarithmic histograms.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj>ubah}(h]h ]h"]h$]h&]uh1jhj+>ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj'>ubah}(h]h ]h"]h$]h&]uh1j hhhMhj;8hhubh)}(hNote that, in the case of histograms, the unit applies to the bucket ranges, while the bucket value indicates how many samples fell in the bucket's range.h]hNote that, in the case of histograms, the unit applies to the bucket ranges, while the bucket value indicates how many samples fell in the bucket’s range.}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(hQBits 8-11 of ``flags``, together with ``exponent``, encode the scale of the unit:h](h Bits 8-11 of }(hj?hhhNhNubj)}(h ``flags``h]hflags}(hj ?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh, together with }(hj?hhhNhNubj)}(h ``exponent``h]hexponent}(hj2?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh, encode the scale of the unit:}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubj )}(hX* ``KVM_STATS_BASE_POW10`` The scale is based on power of 10. It is used for measurement of time and CPU clock cycles. For example, an exponent of -9 can be used with ``KVM_STATS_UNIT_SECONDS`` to express that the unit is nanoseconds. * ``KVM_STATS_BASE_POW2`` The scale is based on power of 2. It is used for measurement of memory size. For example, an exponent of 20 can be used with ``KVM_STATS_UNIT_BYTES`` to express that the unit is MiB. h]j)}(hhh](j)}(h``KVM_STATS_BASE_POW10`` The scale is based on power of 10. It is used for measurement of time and CPU clock cycles. For example, an exponent of -9 can be used with ``KVM_STATS_UNIT_SECONDS`` to express that the unit is nanoseconds.h]h)}(h``KVM_STATS_BASE_POW10`` The scale is based on power of 10. It is used for measurement of time and CPU clock cycles. For example, an exponent of -9 can be used with ``KVM_STATS_UNIT_SECONDS`` to express that the unit is nanoseconds.h](j)}(h``KVM_STATS_BASE_POW10``h]hKVM_STATS_BASE_POW10}(hjY?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU?ubh The scale is based on power of 10. It is used for measurement of time and CPU clock cycles. For example, an exponent of -9 can be used with }(hjU?hhhNhNubj)}(h``KVM_STATS_UNIT_SECONDS``h]hKVM_STATS_UNIT_SECONDS}(hjk?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjU?ubh) to express that the unit is nanoseconds.}(hjU?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjQ?ubah}(h]h ]h"]h$]h&]uh1jhjN?ubj)}(h``KVM_STATS_BASE_POW2`` The scale is based on power of 2. It is used for measurement of memory size. For example, an exponent of 20 can be used with ``KVM_STATS_UNIT_BYTES`` to express that the unit is MiB. h]h)}(h``KVM_STATS_BASE_POW2`` The scale is based on power of 2. It is used for measurement of memory size. For example, an exponent of 20 can be used with ``KVM_STATS_UNIT_BYTES`` to express that the unit is MiB.h](j)}(h``KVM_STATS_BASE_POW2``h]hKVM_STATS_BASE_POW2}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh~ The scale is based on power of 2. It is used for measurement of memory size. For example, an exponent of 20 can be used with }(hj?hhhNhNubj)}(h``KVM_STATS_UNIT_BYTES``h]hKVM_STATS_UNIT_BYTES}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh! to express that the unit is MiB.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj?ubah}(h]h ]h"]h$]h&]uh1jhjN?ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjJ?ubah}(h]h ]h"]h$]h&]uh1j hhhMhj;8hhubh)}(hThe ``size`` field is the number of values of this statistics data. Its value is usually 1 for most of simple statistics. 1 means it contains an unsigned 64bit data.h](hThe }(hj?hhhNhNubj)}(h``size``h]hsize}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubh field is the number of values of this statistics data. Its value is usually 1 for most of simple statistics. 1 means it contains an unsigned 64bit data.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(hrThe ``offset`` field is the offset from the start of Data Block to the start of the corresponding statistics data.h](hThe }(hj?hhhNhNubj)}(h ``offset``h]hoffset}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?ubhd field is the offset from the start of Data Block to the start of the corresponding statistics data.}(hj?hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(hThe ``bucket_size`` field is used as a parameter for histogram statistics data. It is only used by linear histogram statistics data, specifying the size of a bucket in the unit expressed by bits 4-11 of ``flags`` together with ``exponent``.h](hThe }(hj @hhhNhNubj)}(h``bucket_size``h]h bucket_size}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj @ubh field is used as a parameter for histogram statistics data. It is only used by linear histogram statistics data, specifying the size of a bucket in the unit expressed by bits 4-11 of }(hj @hhhNhNubj)}(h ``flags``h]hflags}(hj'@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj @ubh together with }(hj @hhhNhNubj)}(h ``exponent``h]hexponent}(hj9@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj @ubh.}(hj @hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(hThe ``name`` field is the name string of the statistics data. The name string starts at the end of ``struct kvm_stats_desc``. The maximum length including the trailing ``'\0'``, is indicated by ``name_size`` in the header.h](hThe }(hjQ@hhhNhNubj)}(h``name``h]hname}(hjY@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ@ubhW field is the name string of the statistics data. The name string starts at the end of }(hjQ@hhhNhNubj)}(h``struct kvm_stats_desc``h]hstruct kvm_stats_desc}(hjk@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ@ubh-. The maximum length including the trailing }(hjQ@hhhNhNubj)}(h``'\0'``h]h'\0'}(hj}@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ@ubh, is indicated by }(hjQ@hhhNhNubj)}(h ``name_size``h]h name_size}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ@ubh in the header.}(hjQ@hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubh)}(hrThe Stats Data block contains an array of 64-bit values in the same order as the descriptors in Descriptors block.h]hrThe Stats Data block contains an array of 64-bit values in the same order as the descriptors in Descriptors block.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;8hhubeh}(h]kvm-get-stats-fdah ]h"]4.133 kvm_get_stats_fdah$]h&]uh1hhjhhhhhM0ubh)}(hhh](h)}(h4.134 KVM_GET_XSAVE2h]h4.134 KVM_GET_XSAVE2}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@hhhKubj)}(hKVM_CAP_XSAVE2h]h)}(hj@h]hKVM_CAP_XSAVE2}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@ubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj@hhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj@hhhKubj)}(hx86h]h)}(hjAh]hx86}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj@hhubjx)}(hhh](j})}(hTypeh]hType}(hj0AhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj-AhhhKubj)}(h vcpu ioctlh]h)}(hj@Ah]h vcpu ioctl}(hjBAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>Aubah}(h]h ]h"]h$]h&]uh1jhj-Aubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj@hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj^AhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj[AhhhKubj)}(hstruct kvm_xsave (out)h]h)}(hjnAh]hstruct kvm_xsave (out)}(hjpAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjlAubah}(h]h ]h"]h$]h&]uh1jhj[Aubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj@hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjAhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1jhjAubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj@hhubeh}(h]h ]h"]h$]h&]uh1jrhj@hhhhhMubj8)}(hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };h]hEstruct kvm_xsave { __u32 region[1024]; __u32 extra[0]; };}hjAsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj@hhubh)}(hXThis ioctl would copy current vcpu's xsave struct to the userspace. It copies as many bytes as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) when invoked on the vm file descriptor. The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) will always be at least 4096. Currently, it is only greater than 4096 if a dynamic feature has been enabled with ``arch_prctl()``, but this may change in the future.h](hXmThis ioctl would copy current vcpu’s xsave struct to the userspace. It copies as many bytes as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) when invoked on the vm file descriptor. The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) will always be at least 4096. Currently, it is only greater than 4096 if a dynamic feature has been enabled with }(hjAhhhNhNubj)}(h``arch_prctl()``h]h arch_prctl()}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjAubh$, but this may change in the future.}(hjAhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hj@hhubh)}(hjThe offsets of the state save areas in struct kvm_xsave follow the contents of CPUID leaf 0xD on the host.h]hjThe offsets of the state save areas in struct kvm_xsave follow the contents of CPUID leaf 0xD on the host.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj@hhubeh}(h]kvm-get-xsave2ah ]h"]4.134 kvm_get_xsave2ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.135 KVM_XEN_HVM_EVTCHN_SENDh]h4.135 KVM_XEN_HVM_EVTCHN_SEND}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBhhhKubj)}(h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SENDh]h)}(hj)Bh]h0KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND}(hj+BhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'Bubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjBhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjGBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDBhhhKubj)}(hx86h]h)}(hjWBh]hx86}(hjYBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUBubah}(h]h ]h"]h$]h&]uh1jhjDBubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjBhhubjx)}(hhh](j})}(hTypeh]hType}(hjuBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjrBhhhKubj)}(hvm ioctlh]h)}(hjBh]hvm ioctl}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBubah}(h]h ]h"]h$]h&]uh1jhjrBubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjBhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBhhhKubj)}(h!struct kvm_irq_routing_xen_evtchnh]h)}(hjBh]h!struct kvm_irq_routing_xen_evtchn}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjBhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBhhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjBhhubeh}(h]h ]h"]h$]h&]uh1jrhjBhhhhhMubj8)}(h]struct kvm_irq_routing_xen_evtchn { __u32 port; __u32 vcpu; __u32 priority; };h]h]struct kvm_irq_routing_xen_evtchn { __u32 port; __u32 vcpu; __u32 priority; };}hjCsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM!hjBhhubh)}(hIThis ioctl injects an event channel interrupt directly to the guest vCPU.h]hIThis ioctl injects an event channel interrupt directly to the guest vCPU.}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjBhhubeh}(h]kvm-xen-hvm-evtchn-sendah ]h"]4.135 kvm_xen_hvm_evtchn_sendah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.136 KVM_S390_PV_CPU_COMMANDh]h4.136 KVM_S390_PV_CPU_COMMAND}(hj*ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'ChhhhhM*ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj>ChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj;ChhhKubj)}(hKVM_CAP_S390_PROTECTED_DUMPh]h)}(hjNCh]hKVM_CAP_S390_PROTECTED_DUMP}(hjPChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjLCubah}(h]h ]h"]h$]h&]uh1jhj;Cubeh}(h]h ]h"]h$]h&]uh1jwhhhM,hj8Chhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjlChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjiChhhKubj)}(hs390h]h)}(hj|Ch]hs390}(hj~ChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjzCubah}(h]h ]h"]h$]h&]uh1jhjiCubeh}(h]h ]h"]h$]h&]uh1jwhhhM-hj8Chhubjx)}(hhh](j})}(hTypeh]hType}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(h vcpu ioctlh]h)}(hjCh]h vcpu ioctl}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM.hjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM.hj8Chhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(hnoneh]h)}(hjCh]hnone}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjCubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM/hj8Chhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjDubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM0hj8Chhubeh}(h]h ]h"]h$]h&]uh1jrhj'ChhhhhM,ubh)}(hThis ioctl closely mirrors `KVM_S390_PV_COMMAND` but handles requests for vcpus. It re-uses the kvm_s390_pv_dmp struct and hence also shares the command ids.h](hThis ioctl closely mirrors }(hj(DhhhNhNubj,)}(h`KVM_S390_PV_COMMAND`h]hKVM_S390_PV_COMMAND}(hj0DhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj(Dubhm but handles requests for vcpus. It re-uses the kvm_s390_pv_dmp struct and hence also shares the command ids.}(hj(DhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM2hj'Chhubh)}(h **command:**h]j%)}(hjJDh]hcommand:}(hjLDhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjHDubah}(h]h ]h"]h$]h&]uh1hhhhM6hj'Chhubj )}(hhh]j)}(hcKVM_PV_DUMP Presents an API that provides calls which facilitate dumping a vcpu of a protected VM. h](j)}(h KVM_PV_DUMPh]h KVM_PV_DUMP}(hjfDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM:hjbDubj%)}(hhh]h)}(hVPresents an API that provides calls which facilitate dumping a vcpu of a protected VM.h]hVPresents an API that provides calls which facilitate dumping a vcpu of a protected VM.}(hjwDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjtDubah}(h]h ]h"]h$]h&]uh1j$hjbDubeh}(h]h ]h"]h$]h&]uh1jhhhM:hj_Dubah}(h]h ]h"]h$]h&]uh1j hj'ChhhhhNubh)}(h**subcommand:**h]j%)}(hjDh]h subcommand:}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1j%hjDubah}(h]h ]h"]h$]h&]uh1hhhhM<hj'Chhubj )}(hhh]j)}(hKVM_PV_DUMP_CPU Provides encrypted dump data like register values. The length of the returned data is provided by uv_info.guest_cpu_stor_len. h](j)}(hKVM_PV_DUMP_CPUh]hKVM_PV_DUMP_CPU}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM@hjDubj%)}(hhh]h)}(h}Provides encrypted dump data like register values. The length of the returned data is provided by uv_info.guest_cpu_stor_len.h]h}Provides encrypted dump data like register values. The length of the returned data is provided by uv_info.guest_cpu_stor_len.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hjDubah}(h]h ]h"]h$]h&]uh1j$hjDubeh}(h]h ]h"]h$]h&]uh1jhhhM@hjDubah}(h]h ]h"]h$]h&]uh1j hj'ChhhhhNubeh}(h]kvm-s390-pv-cpu-commandah ]h"]4.136 kvm_s390_pv_cpu_commandah$]h&]uh1hhjhhhhhM*ubh)}(hhh](h)}(h4.137 KVM_S390_ZPCI_OPh]h4.137 KVM_S390_ZPCI_OP}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhMCubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(hKVM_CAP_S390_ZPCI_OPh]h)}(hjEh]hKVM_CAP_S390_ZPCI_OP}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhMEhjDhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj3EhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj0EhhhKubj)}(hs390h]h)}(hjCEh]hs390}(hjEEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhjAEubah}(h]h ]h"]h$]h&]uh1jhj0Eubeh}(h]h ]h"]h$]h&]uh1jwhhhMFhjDhhubjx)}(hhh](j})}(hTypeh]hType}(hjaEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^EhhhKubj)}(hvm ioctlh]h)}(hjqEh]hvm ioctl}(hjsEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjoEubah}(h]h ]h"]h$]h&]uh1jhj^Eubeh}(h]h ]h"]h$]h&]uh1jwhhhMGhjDhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(hstruct kvm_s390_zpci_op (in)h]h)}(hjEh]hstruct kvm_s390_zpci_op (in)}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhMHhjDhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjEhhhKubj)}(h0 on success, <0 on error h]h)}(h0 on success, <0 on errorh]h0 on success, <0 on error}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhjEubah}(h]h ]h"]h$]h&]uh1jhjEubeh}(h]h ]h"]h$]h&]uh1jwhhhMIhjDhhubeh}(h]h ]h"]h$]h&]uh1jrhjDhhhhhMEubh)}(hJUsed to manage hardware-assisted virtualization features for zPCI devices.h]hJUsed to manage hardware-assisted virtualization features for zPCI devices.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMKhjDhhubh)}(h6Parameters are specified via the following structure::h]h5Parameters are specified via the following structure:}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjDhhubj8)}(hXstruct kvm_s390_zpci_op { /* in */ __u32 fh; /* target device */ __u8 op; /* operation to perform */ __u8 pad[3]; union { /* for KVM_S390_ZPCIOP_REG_AEN */ struct { __u64 ibv; /* Guest addr of interrupt bit vector */ __u64 sb; /* Guest addr of summary bit */ __u32 flags; __u32 noi; /* Number of interrupts */ __u8 isc; /* Guest interrupt subclass */ __u8 sbo; /* Offset of guest summary bit vector */ __u16 pad; } reg_aen; __u64 reserved[8]; } u; };h]hXstruct kvm_s390_zpci_op { /* in */ __u32 fh; /* target device */ __u8 op; /* operation to perform */ __u8 pad[3]; union { /* for KVM_S390_ZPCIOP_REG_AEN */ struct { __u64 ibv; /* Guest addr of interrupt bit vector */ __u64 sb; /* Guest addr of summary bit */ __u32 flags; __u32 noi; /* Number of interrupts */ __u8 isc; /* Guest interrupt subclass */ __u8 sbo; /* Offset of guest summary bit vector */ __u16 pad; } reg_aen; __u64 reserved[8]; } u; };}hj Fsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMOhjDhhubh)}(hXyThe type of operation is specified in the "op" field. KVM_S390_ZPCIOP_REG_AEN is used to register the VM for adapter event notification interpretation, which will allow firmware delivery of adapter events directly to the vm, with KVM providing a backup delivery mechanism; KVM_S390_ZPCIOP_DEREG_AEN is used to subsequently disable interpretation of adapter event notifications.h]hX}The type of operation is specified in the “op” field. KVM_S390_ZPCIOP_REG_AEN is used to register the VM for adapter event notification interpretation, which will allow firmware delivery of adapter events directly to the vm, with KVM providing a backup delivery mechanism; KVM_S390_ZPCIOP_DEREG_AEN is used to subsequently disable interpretation of adapter event notifications.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjDhhubh)}(hThe target zPCI function must also be specified via the "fh" field. For the KVM_S390_ZPCIOP_REG_AEN operation, additional information to establish firmware delivery must be provided via the "reg_aen" struct.h]hThe target zPCI function must also be specified via the “fh” field. For the KVM_S390_ZPCIOP_REG_AEN operation, additional information to establish firmware delivery must be provided via the “reg_aen” struct.}(hj'FhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjDhhubh)}(hgThe "pad" and "reserved" fields may be used for future extensions and should be set to 0s by userspace.h]hoThe “pad” and “reserved” fields may be used for future extensions and should be set to 0s by userspace.}(hj5FhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjDhhubeh}(h]kvm-s390-zpci-opah ]h"]4.137 kvm_s390_zpci_opah$]h&]uh1hhjhhhhhMCubh)}(hhh](h)}(h 4.138 KVM_ARM_SET_COUNTER_OFFSETh]h 4.138 KVM_ARM_SET_COUNTER_OFFSET}(hjNFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKFhhhhhMrubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjbFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj_FhhhKubj)}(hKVM_CAP_COUNTER_OFFSETh]h)}(hjrFh]hKVM_CAP_COUNTER_OFFSET}(hjtFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjpFubah}(h]h ]h"]h$]h&]uh1jhj_Fubeh}(h]h ]h"]h$]h&]uh1jwhhhMthj\Fhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(harm64h]h)}(hjFh]harm64}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMuhj\Fhhubjx)}(hhh](j})}(hTypeh]hType}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(hvm ioctlh]h)}(hjFh]hvm ioctl}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMvhj\Fhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(h"struct kvm_arm_counter_offset (in)h]h)}(hjFh]h"struct kvm_arm_counter_offset (in)}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjFubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMwhj\Fhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hj,GhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj(Gubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMxhj\Fhhubeh}(h]h ]h"]h$]h&]uh1jrhjKFhhhhhMtubh)}(hThis capability indicates that userspace is able to apply a single VM-wide offset to both the virtual and physical counters as viewed by the guest using the KVM_ARM_SET_CNT_OFFSET ioctl and the following data structure:h]hThis capability indicates that userspace is able to apply a single VM-wide offset to both the virtual and physical counters as viewed by the guest using the KVM_ARM_SET_CNT_OFFSET ioctl and the following data structure:}(hjLGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhjKFhhubj8)}(hXstruct kvm_arm_counter_offset { __u64 counter_offset; __u64 reserved; };h]hXstruct kvm_arm_counter_offset { __u64 counter_offset; __u64 reserved; };}hjZGsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjKFhhubh)}(hX1The offset describes a number of counter cycles that are subtracted from both virtual and physical counter views (similar to the effects of the CNTVOFF_EL2 and CNTPOFF_EL2 system registers, but only global). The offset always applies to all vcpus (already created or created after this ioctl) for this VM.h]hX1The offset describes a number of counter cycles that are subtracted from both virtual and physical counter views (similar to the effects of the CNTVOFF_EL2 and CNTPOFF_EL2 system registers, but only global). The offset always applies to all vcpus (already created or created after this ioctl) for this VM.}(hjhGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKFhhubh)}(htIt is userspace's responsibility to compute the offset based, for example, on previous values of the guest counters.h]hvIt is userspace’s responsibility to compute the offset based, for example, on previous values of the guest counters.}(hjvGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKFhhubh)}(hAny value other than 0 for the "reserved" field may result in an error (-EINVAL) being returned. This ioctl can also return -EBUSY if any vcpu ioctl is issued concurrently.h]hAny value other than 0 for the “reserved” field may result in an error (-EINVAL) being returned. This ioctl can also return -EBUSY if any vcpu ioctl is issued concurrently.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKFhhubh)}(hNote that using this ioctl results in KVM ignoring subsequent userspace writes to the CNTVCT_EL0 and CNTPCT_EL0 registers using the SET_ONE_REG interface. No error will be returned, but the resulting offset will not be applied.h]hNote that using this ioctl results in KVM ignoring subsequent userspace writes to the CNTVCT_EL0 and CNTPCT_EL0 registers using the SET_ONE_REG interface. No error will be returned, but the resulting offset will not be applied.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKFhhubjT)}(h#.. _KVM_ARM_GET_REG_WRITABLE_MASKS:h]h}(h]h ]h"]h$]h&]j_kvm-arm-get-reg-writable-masksuh1jShMhjKFhhhhubeh}(h]kvm-arm-set-counter-offsetah ]h"] 4.138 kvm_arm_set_counter_offsetah$]h&]uh1hhjhhhhhMrubh)}(hhh](h)}(h$4.139 KVM_ARM_GET_REG_WRITABLE_MASKSh]h$4.139 KVM_ARM_GET_REG_WRITABLE_MASKS}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjGhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(h%KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGESh]h)}(hjGh]h%KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjGhhhKubj)}(harm64h]h)}(hjHh]harm64}(hj HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhjGubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hTypeh]hType}(hj&HhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#HhhhKubj)}(hvm ioctlh]h)}(hj6Hh]hvm ioctl}(hj8HhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4Hubah}(h]h ]h"]h$]h&]uh1jhj#Hubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjTHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjQHhhhKubj)}(hstruct reg_mask_range (in/out)h]h)}(hjdHh]hstruct reg_mask_range (in/out)}(hjfHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjbHubah}(h]h ]h"]h$]h&]uh1jhjQHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjHhhhKubj)}(h0 on success, < 0 on error h]h)}(h0 on success, < 0 on errorh]h0 on success, < 0 on error}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jhjHubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjGhhubeh}(h]h ]h"]h$]h&]uh1jrhjGhhhhhMubj8)}(hX#define KVM_ARM_FEATURE_ID_RANGE 0 #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) struct reg_mask_range { __u64 addr; /* Pointer to mask array */ __u32 range; /* Requested range */ __u32 reserved[13]; };h]hX#define KVM_ARM_FEATURE_ID_RANGE 0 #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) struct reg_mask_range { __u64 addr; /* Pointer to mask array */ __u32 range; /* Requested range */ __u32 reserved[13]; };}hjHsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjGhhubh)}(hTThis ioctl copies the writable masks for a selected range of registers to userspace.h]hTThis ioctl copies the writable masks for a selected range of registers to userspace.}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjGhhubh)}(h]The ``addr`` field is a pointer to the destination array where KVM copies the writable masks.h](hThe }(hjHhhhNhNubj)}(h``addr``h]haddr}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubhQ field is a pointer to the destination array where KVM copies the writable masks.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjGhhubh)}(hXdThe ``range`` field indicates the requested range of registers. ``KVM_CHECK_EXTENSION`` for the ``KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES`` capability returns the supported ranges, expressed as a set of flags. Each flag's bit index represents a possible value for the ``range`` field. All other values are reserved for future use and KVM may return an error.h](hThe }(hjHhhhNhNubj)}(h ``range``h]hrange}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh3 field indicates the requested range of registers. }(hjHhhhNhNubj)}(h``KVM_CHECK_EXTENSION``h]hKVM_CHECK_EXTENSION}(hj IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh for the }(hjHhhhNhNubj)}(h)``KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES``h]h%KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubh capability returns the supported ranges, expressed as a set of flags. Each flag’s bit index represents a possible value for the }(hjHhhhNhNubj)}(h ``range``h]hrange}(hj.IhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjHubhQ field. All other values are reserved for future use and KVM may return an error.}(hjHhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjGhhubh)}(hbThe ``reserved[13]`` array is reserved for future use and should be 0, or KVM may return an error.h](hThe }(hjFIhhhNhNubj)}(h``reserved[13]``h]h reserved[13]}(hjNIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjFIubhN array is reserved for future use and should be 0, or KVM may return an error.}(hjFIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjGhhubh)}(hhh](h)}(hKVM_ARM_FEATURE_ID_RANGE (0)h]hKVM_ARM_FEATURE_ID_RANGE (0)}(hjiIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfIhhhhhMubh)}(hThe Feature ID range is defined as the AArch64 System register space with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.h]hThe Feature ID range is defined as the AArch64 System register space with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.}(hjwIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfIhhubh)}(hXXThe mask returned array pointed to by ``addr`` is indexed by the macro ``ARM64_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)``, allowing userspace to know what fields can be changed for the system register described by ``op0, op1, crn, crm, op2``. KVM rejects ID register values that describe a superset of the features supported by the system.h](h&The mask returned array pointed to by }(hjIhhhNhNubj)}(h``addr``h]haddr}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh is indexed by the macro }(hjIhhhNhNubj)}(h7``ARM64_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)``h]h3ARM64_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubh], allowing userspace to know what fields can be changed for the system register described by }(hjIhhhNhNubj)}(h``op0, op1, crn, crm, op2``h]hop0, op1, crn, crm, op2}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjIubhb. KVM rejects ID register values that describe a superset of the features supported by the system.}(hjIhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjfIhhubeh}(h]kvm-arm-feature-id-range-0ah ]h"]kvm_arm_feature_id_range (0)ah$]h&]uh1hhjGhhhhhMubeh}(h](jGid18eh ]h"]($4.139 kvm_arm_get_reg_writable_maskskvm_arm_get_reg_writable_maskseh$]h&]uh1hhjhhhhhMj}jIjGsj}jGjGsubh)}(hhh](h)}(h!4.140 KVM_SET_USER_MEMORY_REGION2h]h!4.140 KVM_SET_USER_MEMORY_REGION2}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjIhhhKubj)}(hKVM_CAP_USER_MEMORY2h]h)}(hjJh]hKVM_CAP_USER_MEMORY2}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJubah}(h]h ]h"]h$]h&]uh1jhjIubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hj!JhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJhhhKubj)}(hallh]h)}(hj1Jh]hall}(hj3JhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj/Jubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(hTypeh]hType}(hjOJhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLJhhhKubj)}(hvm ioctlh]h)}(hj_Jh]hvm ioctl}(hjaJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj]Jubah}(h]h ]h"]h$]h&]uh1jhjLJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj}JhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjzJhhhKubj)}(h(struct kvm_userspace_memory_region2 (in)h]h)}(hjJh]h(struct kvm_userspace_memory_region2 (in)}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJubah}(h]h ]h"]h$]h&]uh1jhjzJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjJubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjIhhubeh}(h]h ]h"]h$]h&]uh1jrhjIhhhhhMubh)}(hXEKVM_SET_USER_MEMORY_REGION2 is an extension to KVM_SET_USER_MEMORY_REGION that allows mapping guest_memfd memory into a guest. All fields shared with KVM_SET_USER_MEMORY_REGION identically. Userspace can set KVM_MEM_GUEST_MEMFD in flags to have KVM bind the memory region to a given guest_memfd range of [guest_memfd_offset, guest_memfd_offset + memory_size]. The target guest_memfd must point at a file created via KVM_CREATE_GUEST_MEMFD on the current VM, and the target range must not be bound to any other memory region. All standard bounds checks apply (use common sense).h]hXEKVM_SET_USER_MEMORY_REGION2 is an extension to KVM_SET_USER_MEMORY_REGION that allows mapping guest_memfd memory into a guest. All fields shared with KVM_SET_USER_MEMORY_REGION identically. Userspace can set KVM_MEM_GUEST_MEMFD in flags to have KVM bind the memory region to a given guest_memfd range of [guest_memfd_offset, guest_memfd_offset + memory_size]. The target guest_memfd must point at a file created via KVM_CREATE_GUEST_MEMFD on the current VM, and the target range must not be bound to any other memory region. All standard bounds checks apply (use common sense).}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIhhubj8)}(hX:struct kvm_userspace_memory_region2 { __u32 slot; __u32 flags; __u64 guest_phys_addr; __u64 memory_size; /* bytes */ __u64 userspace_addr; /* start of the userspace allocated memory */ __u64 guest_memfd_offset; __u32 guest_memfd; __u32 pad1; __u64 pad2[14]; };h]hX:struct kvm_userspace_memory_region2 { __u32 slot; __u32 flags; __u64 guest_phys_addr; __u64 memory_size; /* bytes */ __u64 userspace_addr; /* start of the userspace allocated memory */ __u64 guest_memfd_offset; __u32 guest_memfd; __u32 pad1; __u64 pad2[14]; };}hjJsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjIhhubh)}(hXA KVM_MEM_GUEST_MEMFD region _must_ have a valid guest_memfd (private memory) and userspace_addr (shared memory). However, "valid" for userspace_addr simply means that the address itself must be a legal userspace address. The backing mapping for userspace_addr is not required to be valid/populated at the time of KVM_SET_USER_MEMORY_REGION2, e.g. shared memory can be lazily mapped/allocated on-demand.h]hXA KVM_MEM_GUEST_MEMFD region _must_ have a valid guest_memfd (private memory) and userspace_addr (shared memory). However, “valid” for userspace_addr simply means that the address itself must be a legal userspace address. The backing mapping for userspace_addr is not required to be valid/populated at the time of KVM_SET_USER_MEMORY_REGION2, e.g. shared memory can be lazily mapped/allocated on-demand.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIhhubh)}(hXWhen mapping a gfn into the guest, KVM selects shared vs. private, i.e consumes userspace_addr vs. guest_memfd, based on the gfn's KVM_MEMORY_ATTRIBUTE_PRIVATE state. At VM creation time, all memory is shared, i.e. the PRIVATE attribute is '0' for all gfns. Userspace can control whether memory is shared/private by toggling KVM_MEMORY_ATTRIBUTE_PRIVATE via KVM_SET_MEMORY_ATTRIBUTES as needed.h]hXWhen mapping a gfn into the guest, KVM selects shared vs. private, i.e consumes userspace_addr vs. guest_memfd, based on the gfn’s KVM_MEMORY_ATTRIBUTE_PRIVATE state. At VM creation time, all memory is shared, i.e. the PRIVATE attribute is ‘0’ for all gfns. Userspace can control whether memory is shared/private by toggling KVM_MEMORY_ATTRIBUTE_PRIVATE via KVM_SET_MEMORY_ATTRIBUTES as needed.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjIhhubh)}(hhh](h)}(hS390:h]hS390:}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhhhhhMubh)}(hmReturns -EINVAL if the VM has the KVM_VM_S390_UCONTROL flag set. Returns -EINVAL if called on a protected VM.h]hmReturns -EINVAL if the VM has the KVM_VM_S390_UCONTROL flag set. Returns -EINVAL if called on a protected VM.}(hj&KhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKhhubeh}(h]id19ah ]h"]h$]s390:ah&]uh1hhjIhhhhhMjKubeh}(h]kvm-set-user-memory-region2ah ]h"]!4.140 kvm_set_user_memory_region2ah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.141 KVM_SET_MEMORY_ATTRIBUTESh]h4.141 KVM_SET_MEMORY_ATTRIBUTES}(hjGKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDKhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hj[KhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjXKhhhKubj)}(hKVM_CAP_MEMORY_ATTRIBUTESh]h)}(hjkKh]hKVM_CAP_MEMORY_ATTRIBUTES}(hjmKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiKubah}(h]h ]h"]h$]h&]uh1jhjXKubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUKhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hx86h]h)}(hjKh]hx86}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUKhhubjx)}(hhh](j})}(hTypeh]hType}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hvm ioctlh]h)}(hjKh]hvm ioctl}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUKhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(h!struct kvm_memory_attributes (in)h]h)}(hjKh]h!struct kvm_memory_attributes (in)}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjKubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUKhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(h0 on success, <0 on error h]h)}(h0 on success, <0 on errorh]h0 on success, <0 on error}(hj%LhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!Lubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjUKhhubeh}(h]h ]h"]h$]h&]uh1jrhjDKhhhhhMubh)}(hiKVM_SET_MEMORY_ATTRIBUTES allows userspace to set memory attributes for a range of guest physical memory.h]hiKVM_SET_MEMORY_ATTRIBUTES allows userspace to set memory attributes for a range of guest physical memory.}(hjELhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDKhhubj8)}(hstruct kvm_memory_attributes { __u64 address; __u64 size; __u64 attributes; __u64 flags; }; #define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3)h]hstruct kvm_memory_attributes { __u64 address; __u64 size; __u64 attributes; __u64 flags; }; #define KVM_MEMORY_ATTRIBUTE_PRIVATE (1ULL << 3)}hjSLsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjDKhhubh)}(hXThe address and size must be page aligned. The supported attributes can be retrieved via ioctl(KVM_CHECK_EXTENSION) on KVM_CAP_MEMORY_ATTRIBUTES. If executed on a VM, KVM_CAP_MEMORY_ATTRIBUTES precisely returns the attributes supported by that VM. If executed at system scope, KVM_CAP_MEMORY_ATTRIBUTES returns all attributes supported by KVM. The only attribute defined at this time is KVM_MEMORY_ATTRIBUTE_PRIVATE, which marks the associated gfn as being guest private memory.h]hXThe address and size must be page aligned. The supported attributes can be retrieved via ioctl(KVM_CHECK_EXTENSION) on KVM_CAP_MEMORY_ATTRIBUTES. If executed on a VM, KVM_CAP_MEMORY_ATTRIBUTES precisely returns the attributes supported by that VM. If executed at system scope, KVM_CAP_MEMORY_ATTRIBUTES returns all attributes supported by KVM. The only attribute defined at this time is KVM_MEMORY_ATTRIBUTE_PRIVATE, which marks the associated gfn as being guest private memory.}(hjaLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDKhhubh)}(hqNote, there is no "get" API. Userspace is responsible for explicitly tracking the state of a gfn/page as needed.h]huNote, there is no “get” API. Userspace is responsible for explicitly tracking the state of a gfn/page as needed.}(hjoLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDKhhubh)}(hDThe "flags" field is reserved for future extensions and must be '0'.h]hLThe “flags” field is reserved for future extensions and must be ‘0’.}(hj}LhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDKhhubeh}(h]kvm-set-memory-attributesah ]h"]4.141 kvm_set_memory_attributesah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.142 KVM_CREATE_GUEST_MEMFDh]h4.142 KVM_CREATE_GUEST_MEMFD}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhhhM!ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(hKVM_CAP_GUEST_MEMFDh]h)}(hjLh]hKVM_CAP_GUEST_MEMFD}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjLhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(hnoneh]h)}(hjLh]hnone}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjLubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjLhhubjx)}(hhh](j})}(hTypeh]hType}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hvm ioctlh]h)}(hjMh]hvm ioctl}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjMubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hjLhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj4MhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj1MhhhKubj)}(h!struct kvm_create_guest_memfd(in)h]h)}(hjDMh]h!struct kvm_create_guest_memfd(in)}(hjFMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjBMubah}(h]h ]h"]h$]h&]uh1jhj1Mubeh}(h]h ]h"]h$]h&]uh1jwhhhM&hjLhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjbMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj_MhhhKubj)}(h*A file descriptor on success, <0 on error h]h)}(h)A file descriptor on success, <0 on errorh]h)A file descriptor on success, <0 on error}(hjtMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hjpMubah}(h]h ]h"]h$]h&]uh1jhj_Mubeh}(h]h ]h"]h$]h&]uh1jwhhhM'hjLhhubeh}(h]h ]h"]h$]h&]uh1jrhjLhhhhhM#ubh)}(hXKVM_CREATE_GUEST_MEMFD creates an anonymous file and returns a file descriptor that refers to it. guest_memfd files are roughly analogous to files created via memfd_create(), e.g. guest_memfd files live in RAM, have volatile storage, and are automatically released when the last reference is dropped. Unlike "regular" memfd_create() files, guest_memfd files are bound to their owning virtual machine (see below), cannot be mapped, read, or written by userspace, and cannot be resized (guest_memfd files do however support PUNCH_HOLE).h]hXKVM_CREATE_GUEST_MEMFD creates an anonymous file and returns a file descriptor that refers to it. guest_memfd files are roughly analogous to files created via memfd_create(), e.g. guest_memfd files live in RAM, have volatile storage, and are automatically released when the last reference is dropped. Unlike “regular” memfd_create() files, guest_memfd files are bound to their owning virtual machine (see below), cannot be mapped, read, or written by userspace, and cannot be resized (guest_memfd files do however support PUNCH_HOLE).}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjLhhubj8)}(h`struct kvm_create_guest_memfd { __u64 size; __u64 flags; __u64 reserved[6]; };h]h`struct kvm_create_guest_memfd { __u64 size; __u64 flags; __u64 reserved[6]; };}hjMsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM3hjLhhubh)}(hXConceptually, the inode backing a guest_memfd file represents physical memory, i.e. is coupled to the virtual machine as a thing, not to a "struct kvm". The file itself, which is bound to a "struct kvm", is that instance's view of the underlying memory, e.g. effectively provides the translation of guest addresses to host memory. This allows for use cases where multiple KVM structures are used to manage a single virtual machine, e.g. when performing intrahost migration of a virtual machine.h]hXConceptually, the inode backing a guest_memfd file represents physical memory, i.e. is coupled to the virtual machine as a thing, not to a “struct kvm”. The file itself, which is bound to a “struct kvm”, is that instance’s view of the underlying memory, e.g. effectively provides the translation of guest addresses to host memory. This allows for use cases where multiple KVM structures are used to manage a single virtual machine, e.g. when performing intrahost migration of a virtual machine.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjLhhubh)}(hXKVM currently only supports mapping guest_memfd via KVM_SET_USER_MEMORY_REGION2, and more specifically via the guest_memfd and guest_memfd_offset fields in "struct kvm_userspace_memory_region2", where guest_memfd_offset is the offset into the guest_memfd instance. For a given guest_memfd file, there can be at most one mapping per page, i.e. binding multiple memory regions to a single guest_memfd range is not allowed (any number of memory regions can be bound to a single guest_memfd file, but the bound ranges must not overlap).h]hXKVM currently only supports mapping guest_memfd via KVM_SET_USER_MEMORY_REGION2, and more specifically via the guest_memfd and guest_memfd_offset fields in “struct kvm_userspace_memory_region2”, where guest_memfd_offset is the offset into the guest_memfd instance. For a given guest_memfd file, there can be at most one mapping per page, i.e. binding multiple memory regions to a single guest_memfd range is not allowed (any number of memory regions can be bound to a single guest_memfd file, but the bound ranges must not overlap).}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjLhhubh)}(hThe capability KVM_CAP_GUEST_MEMFD_FLAGS enumerates the `flags` that can be specified via KVM_CREATE_GUEST_MEMFD. Currently defined flags:h](h8The capability KVM_CAP_GUEST_MEMFD_FLAGS enumerates the }(hjMhhhNhNubj,)}(h`flags`h]hflags}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjMubhL that can be specified via KVM_CREATE_GUEST_MEMFD. Currently defined flags:}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMIhjLhhubj )}(hXx============================ ================================================ GUEST_MEMFD_FLAG_MMAP Enable using mmap() on the guest_memfd file descriptor. GUEST_MEMFD_FLAG_INIT_SHARED Make all memory in the file shared during KVM_CREATE_GUEST_MEMFD (memory files created without INIT_SHARED will be marked private). Shared memory can be faulted into host userspace page tables. Private memory cannot. ============================ ================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjMubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK0uh1jchjMubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hGUEST_MEMFD_FLAG_MMAPh]hGUEST_MEMFD_FLAG_MMAP}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjNubah}(h]h ]h"]h$]h&]uh1jhj Nubj)}(hhh]h)}(h7Enable using mmap() on the guest_memfd file descriptor.h]h7Enable using mmap() on the guest_memfd file descriptor.}(hj*NhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj'Nubah}(h]h ]h"]h$]h&]uh1jhj Nubeh}(h]h ]h"]h$]h&]uh1j~hj Nubj)}(hhh](j)}(hhh]h)}(hGUEST_MEMFD_FLAG_INIT_SHAREDh]hGUEST_MEMFD_FLAG_INIT_SHARED}(hjJNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjGNubah}(h]h ]h"]h$]h&]uh1jhjDNubj)}(hhh]h)}(hMake all memory in the file shared during KVM_CREATE_GUEST_MEMFD (memory files created without INIT_SHARED will be marked private). Shared memory can be faulted into host userspace page tables. Private memory cannot.h]hMake all memory in the file shared during KVM_CREATE_GUEST_MEMFD (memory files created without INIT_SHARED will be marked private). Shared memory can be faulted into host userspace page tables. Private memory cannot.}(hjaNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj^Nubah}(h]h ]h"]h$]h&]uh1jhjDNubeh}(h]h ]h"]h$]h&]uh1j~hj Nubeh}(h]h ]h"]h$]h&]uh1jyhjMubeh}(h]h ]h"]h$]h&]colsKuh1j^hjMubah}(h]h ]h"]h$]h&]uh1jYhjMubah}(h]h ]h"]h$]h&]uh1j hhhMLhjLhhubh)}(hWhen the KVM MMU performs a PFN lookup to service a guest fault and the backing guest_memfd has the GUEST_MEMFD_FLAG_MMAP set, then the fault will always be consumed from guest_memfd, regardless of whether it is a shared or a private fault.h]hWhen the KVM MMU performs a PFN lookup to service a guest fault and the backing guest_memfd has the GUEST_MEMFD_FLAG_MMAP set, then the fault will always be consumed from guest_memfd, regardless of whether it is a shared or a private fault.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjLhhubh)}(h7See KVM_SET_USER_MEMORY_REGION2 for additional details.h]h7See KVM_SET_USER_MEMORY_REGION2 for additional details.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjLhhubeh}(h]kvm-create-guest-memfdah ]h"]4.142 kvm_create_guest_memfdah$]h&]uh1hhjhhhhhM!ubh)}(hhh](h)}(h4.143 KVM_PRE_FAULT_MEMORYh]h4.143 KVM_PRE_FAULT_MEMORY}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhM^ubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjNhhhKubj)}(hKVM_CAP_PRE_FAULT_MEMORYh]h)}(hjNh]hKVM_CAP_PRE_FAULT_MEMORY}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hjNubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jwhhhM`hjNhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjNhhhKubj)}(hnoneh]h)}(hj Oh]hnone}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj Oubah}(h]h ]h"]h$]h&]uh1jhjNubeh}(h]h ]h"]h$]h&]uh1jwhhhMahjNhhubjx)}(hhh](j})}(hTypeh]hType}(hj+OhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj(OhhhKubj)}(h vcpu ioctlh]h)}(hj;Oh]h vcpu ioctl}(hj=OhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj9Oubah}(h]h ]h"]h$]h&]uh1jhj(Oubeh}(h]h ]h"]h$]h&]uh1jwhhhMbhjNhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjYOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjVOhhhKubj)}(h$struct kvm_pre_fault_memory (in/out)h]h)}(hjiOh]h$struct kvm_pre_fault_memory (in/out)}(hjkOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjgOubah}(h]h ]h"]h$]h&]uh1jhjVOubeh}(h]h ]h"]h$]h&]uh1jwhhhMchjNhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjOhhhKubj)}(h20 if at least one page is processed, < 0 on error h]h)}(h10 if at least one page is processed, < 0 on errorh]h10 if at least one page is processed, < 0 on error}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhjOubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jwhhhMdhjNhhubeh}(h]h ]h"]h$]h&]uh1jrhjNhhhhhM`ubh)}(hErrors:h]hErrors:}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMfhjNhhubj )}(hX========== =============================================================== EINVAL The specified `gpa` and `size` were invalid (e.g. not page aligned, causes an overflow, or size is zero), or the VM is UCONTROL (s390). ENOENT The specified `gpa` is outside defined memslots. EINTR An unmasked signal is pending and no page was processed. EFAULT The parameter address was invalid. EOPNOTSUPP Mapping memory for a GPA is unsupported by the hypervisor, and/or for the current vCPU state/mode. EIO unexpected error conditions (also causes a WARN) ========== =============================================================== h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK uh1jchjOubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK?uh1jchjOubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjOubah}(h]h ]h"]h$]h&]uh1jhjOubj)}(hhh]h)}(hThe specified `gpa` and `size` were invalid (e.g. not page aligned, causes an overflow, or size is zero), or the VM is UCONTROL (s390).h](hThe specified }(hjPhhhNhNubj,)}(h`gpa`h]hgpa}(hj PhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjPubh and }(hjPhhhNhNubj,)}(h`size`h]hsize}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjPubhi were invalid (e.g. not page aligned, causes an overflow, or size is zero), or the VM is UCONTROL (s390).}(hjPhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMihjPubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1j~hjOubj)}(hhh](j)}(hhh]h)}(hENOENTh]hENOENT}(hjIPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjFPubah}(h]h ]h"]h$]h&]uh1jhjCPubj)}(hhh]h)}(h0The specified `gpa` is outside defined memslots.h](hThe specified }(hj`PhhhNhNubj,)}(h`gpa`h]hgpa}(hjhPhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj`Pubh is outside defined memslots.}(hj`PhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMlhj]Pubah}(h]h ]h"]h$]h&]uh1jhjCPubeh}(h]h ]h"]h$]h&]uh1j~hjOubj)}(hhh](j)}(hhh]h)}(hEINTRh]hEINTR}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjPubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(h8An unmasked signal is pending and no page was processed.h]h8An unmasked signal is pending and no page was processed.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j~hjOubj)}(hhh](j)}(hhh]h)}(hEFAULTh]hEFAULT}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjPubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(h"The parameter address was invalid.h]h"The parameter address was invalid.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjPubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j~hjOubj)}(hhh](j)}(hhh]h)}(h EOPNOTSUPPh]h EOPNOTSUPP}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjPubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]h)}(hbMapping memory for a GPA is unsupported by the hypervisor, and/or for the current vCPU state/mode.h]hbMapping memory for a GPA is unsupported by the hypervisor, and/or for the current vCPU state/mode.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohjQubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1j~hjOubj)}(hhh](j)}(hhh]h)}(hEIOh]hEIO}(hj7QhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj4Qubah}(h]h ]h"]h$]h&]uh1jhj1Qubj)}(hhh]h)}(h0unexpected error conditions (also causes a WARN)h]h0unexpected error conditions (also causes a WARN)}(hjNQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhjKQubah}(h]h ]h"]h$]h&]uh1jhj1Qubeh}(h]h ]h"]h$]h&]uh1j~hjOubeh}(h]h ]h"]h$]h&]uh1jyhjOubeh}(h]h ]h"]h$]h&]colsKuh1j^hjOubah}(h]h ]h"]h$]h&]uh1jYhjOubah}(h]h ]h"]h$]h&]uh1j hhhMhhjNhhubj8)}(hstruct kvm_pre_fault_memory { /* in/out */ __u64 gpa; __u64 size; /* in */ __u64 flags; __u64 padding[5]; };h]hstruct kvm_pre_fault_memory { /* in/out */ __u64 gpa; __u64 size; /* in */ __u64 flags; __u64 padding[5]; };}hjQsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMvhjNhhubh)}(hX*KVM_PRE_FAULT_MEMORY populates KVM's stage-2 page tables used to map memory for the current vCPU state. KVM maps memory as if the vCPU generated a stage-2 read page fault, e.g. faults in memory as needed, but doesn't break CoW. On x86, KVM does not mark any newly created stage-2 PTE as Accessed.h]hX.KVM_PRE_FAULT_MEMORY populates KVM’s stage-2 page tables used to map memory for the current vCPU state. KVM maps memory as if the vCPU generated a stage-2 read page fault, e.g. faults in memory as needed, but doesn’t break CoW. On x86, KVM does not mark any newly created stage-2 PTE as Accessed.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hX0In the case of confidential VM types where there is an initial set up of private guest memory before the guest is 'finalized'/measured, this ioctl should only be issued after completing all the necessary setup to put the guest into a 'finalized' state so that the above semantics can be reliably ensured.h]hX8In the case of confidential VM types where there is an initial set up of private guest memory before the guest is ‘finalized’/measured, this ioctl should only be issued after completing all the necessary setup to put the guest into a ‘finalized’ state so that the above semantics can be reliably ensured.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hnIn some cases, multiple vCPUs might share the page tables. In this case, the ioctl can be called in parallel.h]hnIn some cases, multiple vCPUs might share the page tables. In this case, the ioctl can be called in parallel.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hWhen the ioctl returns, the input values are updated to point to the remaining range. If `size` > 0 on return, the caller can just issue the ioctl again with the same `struct kvm_map_memory` argument.h](hZWhen the ioctl returns, the input values are updated to point to the remaining range. If }(hjQhhhNhNubj,)}(h`size`h]hsize}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjQubhH > 0 on return, the caller can just issue the ioctl again with the same }(hjQhhhNhNubj,)}(h`struct kvm_map_memory`h]hstruct kvm_map_memory}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjQubh argument.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(hXcShadow page tables cannot support this ioctl because they are indexed by virtual address or nested guest physical address. Calling this ioctl when the guest is using shadow page tables (for example because it is running a nested guest with nested page tables) will fail with `EOPNOTSUPP` even if `KVM_CHECK_EXTENSION` reports the capability to be present.h](hXShadow page tables cannot support this ioctl because they are indexed by virtual address or nested guest physical address. Calling this ioctl when the guest is using shadow page tables (for example because it is running a nested guest with nested page tables) will fail with }(hjQhhhNhNubj,)}(h `EOPNOTSUPP`h]h EOPNOTSUPP}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjQubh even if }(hjQhhhNhNubj,)}(h`KVM_CHECK_EXTENSION`h]hKVM_CHECK_EXTENSION}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjQubh& reports the capability to be present.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubh)}(h`flags` must currently be zero.h](j,)}(h`flags`h]hflags}(hj!RhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjRubh must currently be zero.}(hjRhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjNhhubeh}(h]kvm-pre-fault-memoryah ]h"]4.143 kvm_pre_fault_memoryah$]h&]uh1hhjhhhhhM^ubh)}(hhh](h)}(h4.144 KVM_S390_KEYOPh]h4.144 KVM_S390_KEYOP}(hjDRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjARhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjXRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjURhhhKubj)}(hKVM_CAP_S390_KEYOPh]h)}(hjhRh]hKVM_CAP_S390_KEYOP}(hjjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfRubah}(h]h ]h"]h$]h&]uh1jhjURubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRRhhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hs390h]h)}(hjRh]hs390}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRRhhubjx)}(hhh](j})}(hTypeh]hType}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hvm ioctlh]h)}(hjRh]hvm ioctl}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRRhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjRhhhKubj)}(hstruct kvm_s390_keyop (in/out)h]h)}(hjRh]hstruct kvm_s390_keyop (in/out)}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjRubah}(h]h ]h"]h$]h&]uh1jhjRubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRRhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj ShhhKubj)}(h#0 in case of success, < 0 on error h]h)}(h"0 in case of success, < 0 on errorh]h"0 in case of success, < 0 on error}(hj"ShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjSubah}(h]h ]h"]h$]h&]uh1jhj Subeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRRhhubeh}(h]h ]h"]h$]h&]uh1jrhjARhhhhhMubh)}(hThe specified key operation is performed on the given guest address. The previous storage key (or the relevant part thereof) will be returned in `key`.h](hThe specified key operation is performed on the given guest address. The previous storage key (or the relevant part thereof) will be returned in }(hjBShhhNhNubj,)}(h`key`h]hkey}(hjJShhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjBSubh.}(hjBShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjARhhubj8)}(hZstruct kvm_s390_keyop { __u64 guest_addr; __u8 key; __u8 operation; };h]hZstruct kvm_s390_keyop { __u64 guest_addr; __u8 key; __u8 operation; };}hjbSsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjARhhubh)}(h-Currently supported values for ``operation``:h](hCurrently supported values for }(hjpShhhNhNubj)}(h ``operation``h]h operation}(hjxShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpSubh:}(hjpShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjARhhubj )}(hhh](j)}(h]KVM_S390_KEYOP_ISKE Returns the storage key for the guest address ``guest_addr`` in ``key``. h](j)}(hKVM_S390_KEYOP_ISKEh]hKVM_S390_KEYOP_ISKE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjSubj%)}(hhh]h)}(hHReturns the storage key for the guest address ``guest_addr`` in ``key``.h](h.Returns the storage key for the guest address }(hjShhhNhNubj)}(h``guest_addr``h]h guest_addr}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh in }(hjShhhNhNubj)}(h``key``h]hkey}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjSubah}(h]h ]h"]h$]h&]uh1j$hjSubeh}(h]h ]h"]h$]h&]uh1jhhhMhjSubj)}(hKVM_S390_KEYOP_RRBE Resets the reference bit for the guest address ``guest_addr``, returning the R and C bits of the old storage key in ``key``; the remaining fields of the storage key will be set to 0. h](j)}(hKVM_S390_KEYOP_RRBEh]hKVM_S390_KEYOP_RRBE}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjSubj%)}(hhh]h)}(hResets the reference bit for the guest address ``guest_addr``, returning the R and C bits of the old storage key in ``key``; the remaining fields of the storage key will be set to 0.h](h/Resets the reference bit for the guest address }(hjShhhNhNubj)}(h``guest_addr``h]h guest_addr}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh7, returning the R and C bits of the old storage key in }(hjShhhNhNubj)}(h``key``h]hkey}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSubh;; the remaining fields of the storage key will be set to 0.}(hjShhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjSubah}(h]h ]h"]h$]h&]uh1j$hjSubeh}(h]h ]h"]h$]h&]uh1jhhhMhjShhubj)}(hKVM_S390_KEYOP_SSKE Sets the storage key for the guest address ``guest_addr`` to the key specified in ``key``, returning the previous value in ``key``. h](j)}(hKVM_S390_KEYOP_SSKEh]hKVM_S390_KEYOP_SSKE}(hj=ThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj9Tubj%)}(hhh]h)}(hSets the storage key for the guest address ``guest_addr`` to the key specified in ``key``, returning the previous value in ``key``.h](h+Sets the storage key for the guest address }(hjNThhhNhNubj)}(h``guest_addr``h]h guest_addr}(hjVThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNTubh to the key specified in }(hjNThhhNhNubj)}(h``key``h]hkey}(hjhThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNTubh", returning the previous value in }(hjNThhhNhNubj)}(h``key``h]hkey}(hjzThhhNhNubah}(h]h ]h"]h$]h&]uh1jhjNTubh.}(hjNThhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjKTubah}(h]h ]h"]h$]h&]uh1j$hj9Tubeh}(h]h ]h"]h$]h&]uh1jhhhMhjShhubeh}(h]h ]h"]h$]h&]uh1j hjARhhhhhNubeh}(h]kvm-s390-keyopah ]h"]4.144 kvm_s390_keyopah$]h&]uh1hhjhhhhhMubh)}(hhh](h)}(h4.145 KVM_PPC_GET_COMPAT_CAPSh]h4.145 KVM_PPC_GET_COMPAT_CAPS}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjThhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Capabilityh]h Capability}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjThhhKubj)}(hKVM_CAP_PPC_COMPAT_CAPSh]h)}(hjTh]hKVM_CAP_PPC_COMPAT_CAPS}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjThhubjx)}(hhh](j})}(h Architecturesh]h Architectures}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjThhhKubj)}(hpowerpch]h)}(hjUh]hpowerpc}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTubah}(h]h ]h"]h$]h&]uh1jhjTubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjThhubjx)}(hhh](j})}(hTypeh]hType}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hvm ioctlh]h)}(hj/Uh]hvm ioctl}(hj1UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj-Uubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjThhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjMUhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjJUhhhKubj)}(h#struct kvm_ppc_compat_caps (in/out)h]h)}(hj]Uh]h#struct kvm_ppc_compat_caps (in/out)}(hj_UhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[Uubah}(h]h ]h"]h$]h&]uh1jhjJUubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjThhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj{UhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxUhhhKubj)}(h(0 on success, negative value on failure h]h)}(h'0 on success, negative value on failureh]h'0 on success, negative value on failure}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjxUubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjThhubeh}(h]h ]h"]h$]h&]uh1jrhjThhhhhMubh)}(hErrors include:h]hErrors include:}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjThhubj )}(hX======== ============================================================ EFAULT if ``struct kvm_ppc_compat_caps`` cannot be read from or written to userspace EINVAL if the ``size`` field is smaller than ``KVM_PPC_COMPAT_CAPS_SIZE_VER0``, if the ``flags`` field is non-zero, or if the backend fails to retrieve or map CPU compatibility capabilities E2BIG if ``size`` exceeds ``PAGE_SIZE`` (pathological input guard), or if ``size`` is larger than the kernel's struct size and the unknown trailing bytes are non-zero (new userspace on old kernel with non-default fields set); in the latter case the kernel writes back its own struct size into the ``size`` field so userspace can retry with the correct size ENOTTY if the backend does not implement the ``get_compat_caps`` operation (e.g., on non-HV KVM implementations where the required KVM operations are not available) ======== ============================================================ h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjUubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK=uh1jchjUubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hEFAULTh]hEFAULT}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubj)}(hhh]h)}(hMif ``struct kvm_ppc_compat_caps`` cannot be read from or written to userspaceh](hif }(hjUhhhNhNubj)}(h``struct kvm_ppc_compat_caps``h]hstruct kvm_ppc_compat_caps}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjUubh, cannot be read from or written to userspace}(hjUhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjUubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1j~hjUubj)}(hhh](j)}(hhh]h)}(hEINVALh]hEINVAL}(hj+VhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(Vubah}(h]h ]h"]h$]h&]uh1jhj%Vubj)}(hhh]h)}(hif the ``size`` field is smaller than ``KVM_PPC_COMPAT_CAPS_SIZE_VER0``, if the ``flags`` field is non-zero, or if the backend fails to retrieve or map CPU compatibility capabilitiesh](hif the }(hjBVhhhNhNubj)}(h``size``h]hsize}(hjJVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBVubh field is smaller than }(hjBVhhhNhNubj)}(h!``KVM_PPC_COMPAT_CAPS_SIZE_VER0``h]hKVM_PPC_COMPAT_CAPS_SIZE_VER0}(hj\VhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBVubh , if the }(hjBVhhhNhNubj)}(h ``flags``h]hflags}(hjnVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjBVubh] field is non-zero, or if the backend fails to retrieve or map CPU compatibility capabilities}(hjBVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj?Vubah}(h]h ]h"]h$]h&]uh1jhj%Vubeh}(h]h ]h"]h$]h&]uh1j~hjUubj)}(hhh](j)}(hhh]h)}(hE2BIGh]hE2BIG}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1jhjVubj)}(hhh]h)}(hX^if ``size`` exceeds ``PAGE_SIZE`` (pathological input guard), or if ``size`` is larger than the kernel's struct size and the unknown trailing bytes are non-zero (new userspace on old kernel with non-default fields set); in the latter case the kernel writes back its own struct size into the ``size`` field so userspace can retry with the correct sizeh](hif }(hjVhhhNhNubj)}(h``size``h]hsize}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh exceeds }(hjVhhhNhNubj)}(h ``PAGE_SIZE``h]h PAGE_SIZE}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh# (pathological input guard), or if }(hjVhhhNhNubj)}(h``size``h]hsize}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh is larger than the kernel’s struct size and the unknown trailing bytes are non-zero (new userspace on old kernel with non-default fields set); in the latter case the kernel writes back its own struct size into the }(hjVhhhNhNubj)}(h``size``h]hsize}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjVubh3 field so userspace can retry with the correct size}(hjVhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjVubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1j~hjUubj)}(hhh](j)}(hhh]h)}(hENOTTYh]hENOTTY}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjWubah}(h]h ]h"]h$]h&]uh1jhjWubj)}(hhh]h)}(hif the backend does not implement the ``get_compat_caps`` operation (e.g., on non-HV KVM implementations where the required KVM operations are not available)h](h&if the backend does not implement the }(hj.WhhhNhNubj)}(h``get_compat_caps``h]hget_compat_caps}(hj6WhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.Wubhd operation (e.g., on non-HV KVM implementations where the required KVM operations are not available)}(hj.WhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+Wubah}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]uh1j~hjUubeh}(h]h ]h"]h$]h&]uh1jyhjUubeh}(h]h ]h"]h$]h&]colsKuh1j^hjUubah}(h]h ]h"]h$]h&]uh1jYhjUubah}(h]h ]h"]h$]h&]uh1j hhhMhjThhubh)}(hIBM POWER system server-based processors provide a compatibility mode feature where an Nth generation processor can operate in modes consistent with earlier generations such as (N-1) and (N-2).h]hIBM POWER system server-based processors provide a compatibility mode feature where an Nth generation processor can operate in modes consistent with earlier generations such as (N-1) and (N-2).}(hjsWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjThhubh)}(hThis ioctl provides userspace with information about the CPU compatibility modes supported by the current host processor for booting the nested KVM guests on KVM on PowerNV (nested API v1) and KVM on PowerVM (nested API v2) platforms.h]hThis ioctl provides userspace with information about the CPU compatibility modes supported by the current host processor for booting the nested KVM guests on KVM on PowerNV (nested API v1) and KVM on PowerVM (nested API v2) platforms.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjThhubj8)}(hXstruct kvm_ppc_compat_caps { __u64 size; /* Size of this structure */ __u64 flags; /* Reserved for future use, must be 0 */ __u64 compat_capabilities; /* Capabilities supported by the host */ };h]hXstruct kvm_ppc_compat_caps { __u64 size; /* Size of this structure */ __u64 flags; /* Reserved for future use, must be 0 */ __u64 compat_capabilities; /* Capabilities supported by the host */ };}hjWsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjThhubh)}(hXEBefore calling this ioctl, userspace must set the ``size`` field to ``sizeof(struct kvm_ppc_compat_caps)`` and zero the ``flags`` field. The kernel rejects non-zero ``flags`` with ``-EINVAL`` to prevent uninitialized stack values from being silently accepted, keeping the field available for future use without ABI ambiguity.h](h2Before calling this ioctl, userspace must set the }(hjWhhhNhNubj)}(h``size``h]hsize}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh field to }(hjWhhhNhNubj)}(h&``sizeof(struct kvm_ppc_compat_caps)``h]h"sizeof(struct kvm_ppc_compat_caps)}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh and zero the }(hjWhhhNhNubj)}(h ``flags``h]hflags}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh$ field. The kernel rejects non-zero }(hjWhhhNhNubj)}(h ``flags``h]hflags}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh with }(hjWhhhNhNubj)}(h ``-EINVAL``h]h-EINVAL}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjWubh to prevent uninitialized stack values from being silently accepted, keeping the field available for future use without ABI ambiguity.}(hjWhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjThhubh)}(hjThe ioctl uses ``copy_struct_from_user()`` and ``copy_struct_to_user()`` to support extensible versioning.h](hThe ioctl uses }(hjXhhhNhNubj)}(h``copy_struct_from_user()``h]hcopy_struct_from_user()}(hj XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh and }(hjXhhhNhNubj)}(h``copy_struct_to_user()``h]hcopy_struct_to_user()}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh" to support extensible versioning.}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjThhubh)}(hk``KVM_PPC_COMPAT_CAPS_SIZE_VER0`` (24) is a frozen constant marking the size of the initial struct version.h](j)}(h!``KVM_PPC_COMPAT_CAPS_SIZE_VER0``h]hKVM_PPC_COMPAT_CAPS_SIZE_VER0}(hj;XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj7XubhJ (24) is a frozen constant marking the size of the initial struct version.}(hj7XhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjThhubh)}(hThe ``compat_capabilities`` bit field describes the processor compatibility modes supported by the host. The following bits indicate support for specific processor modes (using IBM's MSB-0 convention where bit 0 is the most significant bit):h](hThe }(hjSXhhhNhNubj)}(h``compat_capabilities``h]hcompat_capabilities}(hj[XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjSXubh bit field describes the processor compatibility modes supported by the host. The following bits indicate support for specific processor modes (using IBM’s MSB-0 convention where bit 0 is the most significant bit):}(hjSXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjThhubj)}(hhh](j)}(hU``KVM_PPC_COMPAT_CAP_POWER9`` (bit 1) -- KVM guests can run in Power9 processor modeh]h)}(hjxXh](j)}(h``KVM_PPC_COMPAT_CAP_POWER9``h]hKVM_PPC_COMPAT_CAP_POWER9}(hj}XhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjzXubh8 (bit 1) -- KVM guests can run in Power9 processor mode}(hjzXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjvXubah}(h]h ]h"]h$]h&]uh1jhjsXhhhhhNubj)}(hV``KVM_PPC_COMPAT_CAP_POWER10`` (bit 2) -- KVM guests can run in Power10 processor modeh]h)}(hjXh](j)}(h``KVM_PPC_COMPAT_CAP_POWER10``h]hKVM_PPC_COMPAT_CAP_POWER10}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh8 (bit 2) -- KVM guests can run in Power10 processor mode}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjsXhhhhhNubj)}(hW``KVM_PPC_COMPAT_CAP_POWER11`` (bit 3) -- KVM guests can run in Power11 processor mode h]h)}(hV``KVM_PPC_COMPAT_CAP_POWER11`` (bit 3) -- KVM guests can run in Power11 processor modeh](j)}(h``KVM_PPC_COMPAT_CAP_POWER11``h]hKVM_PPC_COMPAT_CAP_POWER11}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh8 (bit 3) -- KVM guests can run in Power11 processor mode}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjXubah}(h]h ]h"]h$]h&]uh1jhjsXhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjThhubj;)}(hXThe bit numbering above uses IBM's MSB-0 convention (bit 0 is the most significant bit). In the actual implementation, these are defined as: - ``KVM_PPC_COMPAT_CAP_POWER9`` = ``(1ULL << 62)`` - ``KVM_PPC_COMPAT_CAP_POWER10`` = ``(1ULL << 61)`` - ``KVM_PPC_COMPAT_CAP_POWER11`` = ``(1ULL << 60)`` Userspace should use the defined constants from ```` rather than hardcoding bit positions.h](h)}(hThe bit numbering above uses IBM's MSB-0 convention (bit 0 is the most significant bit). In the actual implementation, these are defined as:h]hThe bit numbering above uses IBM’s MSB-0 convention (bit 0 is the most significant bit). In the actual implementation, these are defined as:}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjXubj)}(hhh](j)}(h1``KVM_PPC_COMPAT_CAP_POWER9`` = ``(1ULL << 62)``h]h)}(hjYh](j)}(h``KVM_PPC_COMPAT_CAP_POWER9``h]hKVM_PPC_COMPAT_CAP_POWER9}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh = }(hjYhhhNhNubj)}(h``(1ULL << 62)``h]h (1ULL << 62)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1jhjXubj)}(h1``KVM_PPC_COMPAT_CAP_POWER10`` = ``(1ULL << 61)``h]h)}(hj6Yh](j)}(h``KVM_PPC_COMPAT_CAP_POWER10``h]hKVM_PPC_COMPAT_CAP_POWER10}(hj;YhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8Yubh = }(hj8YhhhNhNubj)}(h``(1ULL << 61)``h]h (1ULL << 61)}(hjMYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8Yubeh}(h]h ]h"]h$]h&]uh1hhhhMhj4Yubah}(h]h ]h"]h$]h&]uh1jhjXubj)}(h2``KVM_PPC_COMPAT_CAP_POWER11`` = ``(1ULL << 60)`` h]h)}(h1``KVM_PPC_COMPAT_CAP_POWER11`` = ``(1ULL << 60)``h](j)}(h``KVM_PPC_COMPAT_CAP_POWER11``h]hKVM_PPC_COMPAT_CAP_POWER11}(hjoYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkYubh = }(hjkYhhhNhNubj)}(h``(1ULL << 60)``h]h (1ULL << 60)}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjkYubeh}(h]h ]h"]h$]h&]uh1hhhhMhjgYubah}(h]h ]h"]h$]h&]uh1jhjXubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjXubh)}(hgUserspace should use the defined constants from ```` rather than hardcoding bit positions.h](h0Userspace should use the defined constants from }(hjYhhhNhNubj)}(h````h]h }(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjYubh& rather than hardcoding bit positions.}(hjYhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjXubeh}(h]h ]h"]h$]h&]uh1j;hjThhhhhNubjT)}(h .. _kvm_run:h]h}(h]h ]h"]h$]h&]j_id20uh1jShM hjThhhhubeh}(h]kvm-ppc-get-compat-capsah ]h"]4.145 kvm_ppc_get_compat_capsah$]h&]uh1hhjhhhhhMubeh}(h]api-descriptionah ]h"]4. api descriptionah$]h&]uh1hhhhhhhhKfubh)}(hhh](h)}(h5. The kvm_run structureh]h5. The kvm_run structure}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhhhM ubh)}(hX(Application code obtains a pointer to the kvm_run structure by mmap()ing a vcpu fd. From that point, application code can control execution by changing fields in kvm_run prior to calling the KVM_RUN ioctl, and obtain information about the reason KVM_RUN returned by looking up structure members.h]hX(Application code obtains a pointer to the kvm_run structure by mmap()ing a vcpu fd. From that point, application code can control execution by changing fields in kvm_run prior to calling the KVM_RUN ioctl, and obtain information about the reason KVM_RUN returned by looking up structure members.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(hDstruct kvm_run { /* in */ __u8 request_interrupt_window;h]hDstruct kvm_run { /* in */ __u8 request_interrupt_window;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hRequest that KVM_RUN return when it becomes possible to inject external interrupts into the guest. Useful in conjunction with KVM_INTERRUPT.h]hRequest that KVM_RUN return when it becomes possible to inject external interrupts into the guest. Useful in conjunction with KVM_INTERRUPT.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(h__u8 immediate_exit;h]h__u8 immediate_exit;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hjYhhubh)}(hXThis field is polled once when KVM_RUN starts; if non-zero, KVM_RUN exits immediately, returning -EINTR. In the common scenario where a signal is used to "kick" a VCPU out of KVM_RUN, this field can be used to avoid usage of KVM_SET_SIGNAL_MASK, which has worse scalability. Rather than blocking the signal outside KVM_RUN, userspace can set up a signal handler that sets run->immediate_exit to a non-zero value.h]hXThis field is polled once when KVM_RUN starts; if non-zero, KVM_RUN exits immediately, returning -EINTR. In the common scenario where a signal is used to “kick” a VCPU out of KVM_RUN, this field can be used to avoid usage of KVM_SET_SIGNAL_MASK, which has worse scalability. Rather than blocking the signal outside KVM_RUN, userspace can set up a signal handler that sets run->immediate_exit to a non-zero value.}(hj+ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjYhhubh)}(hAThis field is ignored if KVM_CAP_IMMEDIATE_EXIT is not available.h]hAThis field is ignored if KVM_CAP_IMMEDIATE_EXIT is not available.}(hj9ZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjYhhubj8)}(h/__u8 padding1[6]; /* out */ __u32 exit_reason;h]h/__u8 padding1[6]; /* out */ __u32 exit_reason;}hjGZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM-hjYhhubh)}(hWhen KVM_RUN has returned successfully (return value 0), this informs application code why KVM_RUN has returned. Allowable values for this field are detailed below.h]hWhen KVM_RUN has returned successfully (return value 0), this informs application code why KVM_RUN has returned. Allowable values for this field are detailed below.}(hjUZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjYhhubj8)}(h#__u8 ready_for_interrupt_injection;h]h#__u8 ready_for_interrupt_injection;}hjcZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM8hjYhhubh)}(hyIf request_interrupt_window has been specified, this field indicates an interrupt can be injected now with KVM_INTERRUPT.h]hyIf request_interrupt_window has been specified, this field indicates an interrupt can be injected now with KVM_INTERRUPT.}(hjqZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjYhhubj8)}(h __u8 if_flag;h]h __u8 if_flag;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM?hjYhhubh)}(hYThe value of the current interrupt flag. Only valid if in-kernel local APIC is not used.h]hYThe value of the current interrupt flag. Only valid if in-kernel local APIC is not used.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjYhhubj8)}(h __u16 flags;h]h __u16 flags;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMFhjYhhubh)}(h{More architecture-specific flags detailing state of the VCPU that may affect the device's behavior. Current defined flags::h]h|More architecture-specific flags detailing state of the VCPU that may affect the device’s behavior. Current defined flags:}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjYhhubj8)}(hXp/* x86, set if the VCPU is in system management mode */ #define KVM_RUN_X86_SMM (1 << 0) /* x86, set if bus lock detected in VM */ #define KVM_RUN_X86_BUS_LOCK (1 << 1) /* x86, set if the VCPU is executing a nested (L2) guest */ #define KVM_RUN_X86_GUEST_MODE (1 << 2) /* arm64, set for KVM_EXIT_DEBUG */ #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0)h]hXp/* x86, set if the VCPU is in system management mode */ #define KVM_RUN_X86_SMM (1 << 0) /* x86, set if bus lock detected in VM */ #define KVM_RUN_X86_BUS_LOCK (1 << 1) /* x86, set if the VCPU is executing a nested (L2) guest */ #define KVM_RUN_X86_GUEST_MODE (1 << 2) /* arm64, set for KVM_EXIT_DEBUG */ #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0)}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMKhjYhhubj8)}(h5/* in (pre_kvm_run), out (post_kvm_run) */ __u64 cr8;h]h5/* in (pre_kvm_run), out (post_kvm_run) */ __u64 cr8;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMWhjYhhubh)}(hgThe value of the cr8 register. Only valid if in-kernel local APIC is not used. Both input and output.h]hgThe value of the cr8 register. Only valid if in-kernel local APIC is not used. Both input and output.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjYhhubj8)}(h__u64 apic_base;h]h__u64 apic_base;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM_hjYhhubh)}(hhThe value of the APIC BASE msr. Only valid if in-kernel local APIC is not used. Both input and output.h]hhThe value of the APIC BASE msr. Only valid if in-kernel local APIC is not used. Both input and output.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjYhhubj8)}(hqunion { /* KVM_EXIT_UNKNOWN */ struct { __u64 hardware_exit_reason; } hw;h]hqunion { /* KVM_EXIT_UNKNOWN */ struct { __u64 hardware_exit_reason; } hw;}hjZsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMfhjYhhubh)}(hIf exit_reason is KVM_EXIT_UNKNOWN, the vcpu has exited due to unknown reasons. Further architecture-specific information is available in hardware_exit_reason.h]hIf exit_reason is KVM_EXIT_UNKNOWN, the vcpu has exited due to unknown reasons. Further architecture-specific information is available in hardware_exit_reason.}(hj [hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjYhhubj8)}(h/* KVM_EXIT_FAIL_ENTRY */ struct { __u64 hardware_entry_failure_reason; __u32 cpu; /* if KVM_LAST_CPU */ } fail_entry;h]h/* KVM_EXIT_FAIL_ENTRY */ struct { __u64 hardware_entry_failure_reason; __u32 cpu; /* if KVM_LAST_CPU */ } fail_entry;}hj[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMrhjYhhubh)}(hIf exit_reason is KVM_EXIT_FAIL_ENTRY, the vcpu could not be run due to unknown reasons. Further architecture-specific information is available in hardware_entry_failure_reason.h]hIf exit_reason is KVM_EXIT_FAIL_ENTRY, the vcpu could not be run due to unknown reasons. Further architecture-specific information is available in hardware_entry_failure_reason.}(hj'[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjYhhubj8)}(hZ/* KVM_EXIT_EXCEPTION */ struct { __u32 exception; __u32 error_code; } ex;h]hZ/* KVM_EXIT_EXCEPTION */ struct { __u32 exception; __u32 error_code; } ex;}hj5[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM~hjYhhubh)}(hUnused.h]hUnused.}(hjC[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(hX_ /* KVM_EXIT_IO */ struct { #define KVM_EXIT_IO_IN 0 #define KVM_EXIT_IO_OUT 1 __u8 direction; __u8 size; /* bytes */ __u16 port; __u32 count; __u64 data_offset; /* relative to kvm_run start */ } io;h]hX_ /* KVM_EXIT_IO */ struct { #define KVM_EXIT_IO_IN 0 #define KVM_EXIT_IO_OUT 1 __u8 direction; __u8 size; /* bytes */ __u16 port; __u32 count; __u64 data_offset; /* relative to kvm_run start */ } io;}hjQ[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hXAIf exit_reason is KVM_EXIT_IO, then the vcpu has executed a port I/O instruction which could not be satisfied by kvm. data_offset describes where the data is located (KVM_EXIT_IO_OUT) or where kvm expects application code to place the data for the next KVM_RUN invocation (KVM_EXIT_IO_IN). Data format is a packed array.h]hXAIf exit_reason is KVM_EXIT_IO, then the vcpu has executed a port I/O instruction which could not be satisfied by kvm. data_offset describes where the data is located (KVM_EXIT_IO_OUT) or where kvm expects application code to place the data for the next KVM_RUN invocation (KVM_EXIT_IO_IN). Data format is a packed array.}(hj_[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(hO/* KVM_EXIT_DEBUG */ struct { struct kvm_debug_exit_arch arch; } debug;h]hO/* KVM_EXIT_DEBUG */ struct { struct kvm_debug_exit_arch arch; } debug;}hjm[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hIf the exit_reason is KVM_EXIT_DEBUG, then a vcpu is processing a debug event for which architecture specific information is returned.h]hIf the exit_reason is KVM_EXIT_DEBUG, then a vcpu is processing a debug event for which architecture specific information is returned.}(hj{[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj8)}(h/* KVM_EXIT_MMIO */ struct { __u64 phys_addr; __u8 data[8]; __u32 len; __u8 is_write; } mmio;h]h/* KVM_EXIT_MMIO */ struct { __u64 phys_addr; __u8 data[8]; __u32 len; __u8 is_write; } mmio;}hj[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hIf exit_reason is KVM_EXIT_MMIO, then the vcpu has executed a memory-mapped I/O instruction which could not be satisfied by kvm. The 'data' member contains the written data if 'is_write' is true, and should be filled by application code otherwise.h]hXIf exit_reason is KVM_EXIT_MMIO, then the vcpu has executed a memory-mapped I/O instruction which could not be satisfied by kvm. The ‘data’ member contains the written data if ‘is_write’ is true, and should be filled by application code otherwise.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubh)}(hThe 'data' member contains, in its first 'len' bytes, the value as it would appear if the VCPU performed a load or store of the appropriate width directly to the byte array.h]hThe ‘data’ member contains, in its first ‘len’ bytes, the value as it would appear if the VCPU performed a load or store of the appropriate width directly to the byte array.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj;)}(hXFor KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_PAPR, KVM_EXIT_XEN, KVM_EXIT_EPR, KVM_EXIT_HYPERCALL, KVM_EXIT_TDX, KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR the corresponding operations are complete (and guest state is consistent) only after userspace has re-entered the kernel with KVM_RUN. The kernel side will first finish incomplete operations and then check for pending signals. The pending state of the operation is not preserved in state which is visible to userspace, thus userspace should ensure that the operation is completed before performing a live migration. Userspace can re-enter the guest with an unmasked signal pending or with the immediate_exit field set to complete pending operations without allowing any further instructions to be executed.h](h)}(hXFor KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_PAPR, KVM_EXIT_XEN, KVM_EXIT_EPR, KVM_EXIT_HYPERCALL, KVM_EXIT_TDX, KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR the corresponding operations are complete (and guest state is consistent) only after userspace has re-entered the kernel with KVM_RUN. The kernel side will first finish incomplete operations and then check for pending signals.h]hXFor KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_PAPR, KVM_EXIT_XEN, KVM_EXIT_EPR, KVM_EXIT_HYPERCALL, KVM_EXIT_TDX, KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR the corresponding operations are complete (and guest state is consistent) only after userspace has re-entered the kernel with KVM_RUN. The kernel side will first finish incomplete operations and then check for pending signals.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubh)}(hX|The pending state of the operation is not preserved in state which is visible to userspace, thus userspace should ensure that the operation is completed before performing a live migration. Userspace can re-enter the guest with an unmasked signal pending or with the immediate_exit field set to complete pending operations without allowing any further instructions to be executed.h]hX|The pending state of the operation is not preserved in state which is visible to userspace, thus userspace should ensure that the operation is completed before performing a live migration. Userspace can re-enter the guest with an unmasked signal pending or with the immediate_exit field set to complete pending operations without allowing any further instructions to be executed.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ubeh}(h]h ]h"]h$]h&]uh1j;hjYhhhhhNubj8)}(h/* KVM_EXIT_HYPERCALL */ struct { __u64 nr; __u64 args[6]; __u64 ret; __u64 flags; } hypercall;h]h/* KVM_EXIT_HYPERCALL */ struct { __u64 nr; __u64 args[6]; __u64 ret; __u64 flags; } hypercall;}hj[sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjYhhubh)}(hIt is strongly recommended that userspace use ``KVM_EXIT_IO`` (x86) or ``KVM_EXIT_MMIO`` (all except s390) to implement functionality that requires a guest to interact with host userspace.h](h.It is strongly recommended that userspace use }(hj[hhhNhNubj)}(h``KVM_EXIT_IO``h]h KVM_EXIT_IO}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubh (x86) or }(hj[hhhNhNubj)}(h``KVM_EXIT_MMIO``h]h KVM_EXIT_MMIO}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[ubhd (all except s390) to implement functionality that requires a guest to interact with host userspace.}(hj[hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjYhhubj;)}(h7KVM_EXIT_IO is significantly faster than KVM_EXIT_MMIO.h]h)}(hj\h]h7KVM_EXIT_IO is significantly faster than KVM_EXIT_MMIO.}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1j;hjYhhhhhNubh)}(hhh](h)}(h For arm64:h]h For arm64:}(hj3\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0\hhhhhMubh)}(hSMCCC exits can be enabled depending on the configuration of the SMCCC filter. See the Documentation/virt/kvm/devices/vm.rst ``KVM_ARM_SMCCC_FILTER`` for more details.h](h}SMCCC exits can be enabled depending on the configuration of the SMCCC filter. See the Documentation/virt/kvm/devices/vm.rst }(hjA\hhhNhNubj)}(h``KVM_ARM_SMCCC_FILTER``h]hKVM_ARM_SMCCC_FILTER}(hjI\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjA\ubh for more details.}(hjA\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubh)}(h``nr`` contains the function ID of the guest's SMCCC call. Userspace is expected to use the ``KVM_GET_ONE_REG`` ioctl to retrieve the call parameters from the vCPU's GPRs.h](j)}(h``nr``h]hnr}(hje\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja\ubhX contains the function ID of the guest’s SMCCC call. Userspace is expected to use the }(hja\hhhNhNubj)}(h``KVM_GET_ONE_REG``h]hKVM_GET_ONE_REG}(hjw\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja\ubh> ioctl to retrieve the call parameters from the vCPU’s GPRs.}(hja\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj )}(hhh]j)}(hXDefinition of ``flags``: - ``KVM_HYPERCALL_EXIT_SMC``: Indicates that the guest used the SMC conduit to initiate the SMCCC call. If this bit is 0 then the guest used the HVC conduit for the SMCCC call. - ``KVM_HYPERCALL_EXIT_16BIT``: Indicates that the guest used a 16bit instruction to initiate the SMCCC call. If this bit is 0 then the guest used a 32bit instruction. An AArch64 guest always has this bit set to 0. h](j)}(hDefinition of ``flags``:h](hDefinition of }(hj\hhhNhNubj)}(h ``flags``h]hflags}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh:}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1jhhhMhj\ubj%)}(hhh]j)}(hhh](j)}(h``KVM_HYPERCALL_EXIT_SMC``: Indicates that the guest used the SMC conduit to initiate the SMCCC call. If this bit is 0 then the guest used the HVC conduit for the SMCCC call. h]h)}(h``KVM_HYPERCALL_EXIT_SMC``: Indicates that the guest used the SMC conduit to initiate the SMCCC call. If this bit is 0 then the guest used the HVC conduit for the SMCCC call.h](j)}(h``KVM_HYPERCALL_EXIT_SMC``h]hKVM_HYPERCALL_EXIT_SMC}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh: Indicates that the guest used the SMC conduit to initiate the SMCCC call. If this bit is 0 then the guest used the HVC conduit for the SMCCC call.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubj)}(h``KVM_HYPERCALL_EXIT_16BIT``: Indicates that the guest used a 16bit instruction to initiate the SMCCC call. If this bit is 0 then the guest used a 32bit instruction. An AArch64 guest always has this bit set to 0. h]h)}(h``KVM_HYPERCALL_EXIT_16BIT``: Indicates that the guest used a 16bit instruction to initiate the SMCCC call. If this bit is 0 then the guest used a 32bit instruction. An AArch64 guest always has this bit set to 0.h](j)}(h``KVM_HYPERCALL_EXIT_16BIT``h]hKVM_HYPERCALL_EXIT_16BIT}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj\ubh: Indicates that the guest used a 16bit instruction to initiate the SMCCC call. If this bit is 0 then the guest used a 32bit instruction. An AArch64 guest always has this bit set to 0.}(hj\hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1jhj\ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj\ubah}(h]h ]h"]h$]h&]uh1j$hj\ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj\ubah}(h]h ]h"]h$]h&]uh1j hj0\hhhNhNubh)}(hbAt the point of exit, PC points to the instruction immediately following the trapping instruction.h]hbAt the point of exit, PC points to the instruction immediately following the trapping instruction.}(hj ]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj8)}(hn/* KVM_EXIT_TPR_ACCESS */ struct { __u64 rip; __u32 is_write; __u32 pad; } tpr_access;h]hn/* KVM_EXIT_TPR_ACCESS */ struct { __u64 rip; __u32 is_write; __u32 pad; } tpr_access;}hj.]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj0\hhubh)}(h,To be documented (KVM_TPR_ACCESS_REPORTING).h]h,To be documented (KVM_TPR_ACCESS_REPORTING).}(hj<]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj8)}(h/* KVM_EXIT_S390_SIEIC */ struct { __u8 icptcode; __u64 mask; /* psw upper half */ __u64 addr; /* psw lower half */ __u16 ipa; __u32 ipb; } s390_sieic;h]h/* KVM_EXIT_S390_SIEIC */ struct { __u8 icptcode; __u64 mask; /* psw upper half */ __u64 addr; /* psw lower half */ __u16 ipa; __u32 ipb; } s390_sieic;}hjJ]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj0\hhubh)}(hs390 specific.h]hs390 specific.}(hjX]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj8)}(h /* KVM_EXIT_S390_RESET */ #define KVM_S390_RESET_POR 1 #define KVM_S390_RESET_CLEAR 2 #define KVM_S390_RESET_SUBSYSTEM 4 #define KVM_S390_RESET_CPU_INIT 8 #define KVM_S390_RESET_IPL 16 __u64 s390_reset_flags;h]h /* KVM_EXIT_S390_RESET */ #define KVM_S390_RESET_POR 1 #define KVM_S390_RESET_CLEAR 2 #define KVM_S390_RESET_SUBSYSTEM 4 #define KVM_S390_RESET_CPU_INIT 8 #define KVM_S390_RESET_IPL 16 __u64 s390_reset_flags;}hjf]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj0\hhubh)}(hs390 specific.h]hs390 specific.}(hjt]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj8)}(hl/* KVM_EXIT_S390_UCONTROL */ struct { __u64 trans_exc_code; __u32 pgm_code; } s390_ucontrol;h]hl/* KVM_EXIT_S390_UCONTROL */ struct { __u64 trans_exc_code; __u32 pgm_code; } s390_ucontrol;}hj]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj0\hhubh)}(hXs390 specific. A page fault has occurred for a user controlled virtual machine (KVM_VM_S390_UCONTROL) on its host page table that cannot be resolved by the kernel. The program code and the translation exception code that were placed in the cpu's lowcore are presented here as defined by the z Architecture Principles of Operation Book in the Chapter for Dynamic Address Translation (DAT)h]hXs390 specific. A page fault has occurred for a user controlled virtual machine (KVM_VM_S390_UCONTROL) on its host page table that cannot be resolved by the kernel. The program code and the translation exception code that were placed in the cpu’s lowcore are presented here as defined by the z Architecture Principles of Operation Book in the Chapter for Dynamic Address Translation (DAT)}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj8)}(hb/* KVM_EXIT_DCR */ struct { __u32 dcrn; __u32 data; __u8 is_write; } dcr;h]hb/* KVM_EXIT_DCR */ struct { __u32 dcrn; __u32 data; __u8 is_write; } dcr;}hj]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM%hj0\hhubh)}(h"Deprecated - was used for 440 KVM.h]h"Deprecated - was used for 440 KVM.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj0\hhubj8)}(h:/* KVM_EXIT_OSI */ struct { __u64 gprs[32]; } osi;h]h:/* KVM_EXIT_OSI */ struct { __u64 gprs[32]; } osi;}hj]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM0hj0\hhubh)}(hMOL uses a special hypercall interface it calls 'OSI'. To enable it, we catch hypercalls and exit with this exit struct that contains all the guest gprs.h]hMOL uses a special hypercall interface it calls ‘OSI’. To enable it, we catch hypercalls and exit with this exit struct that contains all the guest gprs.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj0\hhubh)}(hIf exit_reason is KVM_EXIT_OSI, then the vcpu has triggered such a hypercall. Userspace can now handle the hypercall and when it's done modify the gprs as necessary. Upon guest entry all guest GPRs will then be replaced by the values in this struct.h]hIf exit_reason is KVM_EXIT_OSI, then the vcpu has triggered such a hypercall. Userspace can now handle the hypercall and when it’s done modify the gprs as necessary. Upon guest entry all guest GPRs will then be replaced by the values in this struct.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj0\hhubj8)}(hl/* KVM_EXIT_PAPR_HCALL */ struct { __u64 nr; __u64 ret; __u64 args[9]; } papr_hcall;h]hl/* KVM_EXIT_PAPR_HCALL */ struct { __u64 nr; __u64 ret; __u64 args[9]; } papr_hcall;}hj]sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM?hj0\hhubh)}(hXGThis is used on 64-bit PowerPC when emulating a pSeries partition, e.g. with the 'pseries' machine type in qemu. It occurs when the guest does a hypercall using the 'sc 1' instruction. The 'nr' field contains the hypercall number (from the guest R3), and 'args' contains the arguments (from the guest R4 - R12). Userspace should put the return code in 'ret' and any extra returned values in args[]. The possible hypercalls are defined in the Power Architecture Platform Requirements (PAPR) document available from www.power.org (free developer registration required to access it).h]hX[This is used on 64-bit PowerPC when emulating a pSeries partition, e.g. with the ‘pseries’ machine type in qemu. It occurs when the guest does a hypercall using the ‘sc 1’ instruction. The ‘nr’ field contains the hypercall number (from the guest R3), and ‘args’ contains the arguments (from the guest R4 - R12). Userspace should put the return code in ‘ret’ and any extra returned values in args[]. The possible hypercalls are defined in the Power Architecture Platform Requirements (PAPR) document available from www.power.org (free developer registration required to access it).}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj0\hhubj8)}(h/* KVM_EXIT_S390_TSCH */ struct { __u16 subchannel_id; __u16 subchannel_nr; __u32 io_int_parm; __u32 io_int_word; __u32 ipb; __u8 dequeued; } s390_tsch;h]h/* KVM_EXIT_S390_TSCH */ struct { __u16 subchannel_id; __u16 subchannel_nr; __u32 io_int_parm; __u32 io_int_word; __u32 ipb; __u8 dequeued; } s390_tsch;}hj^sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMRhj0\hhubh)}(hXfs390 specific. This exit occurs when KVM_CAP_S390_CSS_SUPPORT has been enabled and TEST SUBCHANNEL was intercepted. If dequeued is set, a pending I/O interrupt for the target subchannel has been dequeued and subchannel_id, subchannel_nr, io_int_parm and io_int_word contain the parameters for that interrupt. ipb is needed for instruction parameter decoding.h]hXfs390 specific. This exit occurs when KVM_CAP_S390_CSS_SUPPORT has been enabled and TEST SUBCHANNEL was intercepted. If dequeued is set, a pending I/O interrupt for the target subchannel has been dequeued and subchannel_id, subchannel_nr, io_int_parm and io_int_word contain the parameters for that interrupt. ipb is needed for instruction parameter decoding.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj0\hhubj8)}(h5/* KVM_EXIT_EPR */ struct { __u32 epr; } epr;h]h5/* KVM_EXIT_EPR */ struct { __u32 epr; } epr;}hj^sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMdhj0\hhubh)}(hX,On FSL BookE PowerPC chips, the interrupt controller has a fast patch interrupt acknowledge path to the core. When the core successfully delivers an interrupt, it automatically populates the EPR register with the interrupt vector number and acknowledges the interrupt inside the interrupt controller.h]hX,On FSL BookE PowerPC chips, the interrupt controller has a fast patch interrupt acknowledge path to the core. When the core successfully delivers an interrupt, it automatically populates the EPR register with the interrupt vector number and acknowledges the interrupt inside the interrupt controller.}(hj*^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj0\hhubh)}(hIn case the interrupt controller lives in user space, we need to do the interrupt acknowledge cycle through it to fetch the next to be delivered interrupt vector using this exit.h]hIn case the interrupt controller lives in user space, we need to do the interrupt acknowledge cycle through it to fetch the next to be delivered interrupt vector using this exit.}(hj8^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMohj0\hhubh)}(hIt gets triggered whenever both KVM_CAP_PPC_EPR are enabled and an external interrupt has just been delivered into the guest. User space should put the acknowledged interrupt vector into the 'epr' field.h]hIt gets triggered whenever both KVM_CAP_PPC_EPR are enabled and an external interrupt has just been delivered into the guest. User space should put the acknowledged interrupt vector into the ‘epr’ field.}(hjF^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj0\hhubj8)}(hX /* KVM_EXIT_SYSTEM_EVENT */ struct { #define KVM_SYSTEM_EVENT_SHUTDOWN 1 #define KVM_SYSTEM_EVENT_RESET 2 #define KVM_SYSTEM_EVENT_CRASH 3 #define KVM_SYSTEM_EVENT_WAKEUP 4 #define KVM_SYSTEM_EVENT_SUSPEND 5 #define KVM_SYSTEM_EVENT_SEV_TERM 6 #define KVM_SYSTEM_EVENT_TDX_FATAL 7 __u32 type; __u32 ndata; __u64 data[16]; } system_event;h]hX /* KVM_EXIT_SYSTEM_EVENT */ struct { #define KVM_SYSTEM_EVENT_SHUTDOWN 1 #define KVM_SYSTEM_EVENT_RESET 2 #define KVM_SYSTEM_EVENT_CRASH 3 #define KVM_SYSTEM_EVENT_WAKEUP 4 #define KVM_SYSTEM_EVENT_SUSPEND 5 #define KVM_SYSTEM_EVENT_SEV_TERM 6 #define KVM_SYSTEM_EVENT_TDX_FATAL 7 __u32 type; __u32 ndata; __u64 data[16]; } system_event;}hjT^sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMyhj0\hhubh)}(hXIf exit_reason is KVM_EXIT_SYSTEM_EVENT then the vcpu has triggered a system-level event using some architecture specific mechanism (hypercall or some special instruction). In case of ARM64, this is triggered using HVC instruction based PSCI call from the vcpu.h]hXIf exit_reason is KVM_EXIT_SYSTEM_EVENT then the vcpu has triggered a system-level event using some architecture specific mechanism (hypercall or some special instruction). In case of ARM64, this is triggered using HVC instruction based PSCI call from the vcpu.}(hjb^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubh)}(hTThe 'type' field describes the system-level event type. Valid values for 'type' are:h]h\The ‘type’ field describes the system-level event type. Valid values for ‘type’ are:}(hjp^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj )}(hX- KVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the VM. Userspace is not obliged to honour this, and if it does honour this does not need to destroy the VM synchronously (ie it may call KVM_RUN again before shutdown finally occurs). - KVM_SYSTEM_EVENT_RESET -- the guest has requested a reset of the VM. As with SHUTDOWN, userspace can choose to ignore the request, or to schedule the reset to occur in the future and may call KVM_RUN again. - KVM_SYSTEM_EVENT_CRASH -- the guest crash occurred and the guest has requested a crash condition maintenance. Userspace can choose to ignore the request, or to gather VM memory core dump and/or reset/shutdown of the VM. - KVM_SYSTEM_EVENT_SEV_TERM -- an AMD SEV guest requested termination. The guest physical address of the guest's GHCB is stored in `data[0]`. - KVM_SYSTEM_EVENT_TDX_FATAL -- a TDX guest reported a fatal error state. KVM doesn't do any parsing or conversion, it just dumps 16 general-purpose registers to userspace, in ascending order of the 4-bit indices for x86-64 general-purpose registers in instruction encoding, as defined in the Intel SDM. - KVM_SYSTEM_EVENT_WAKEUP -- the exiting vCPU is in a suspended state and KVM has recognized a wakeup event. Userspace may honor this event by marking the exiting vCPU as runnable, or deny it and call KVM_RUN again. - KVM_SYSTEM_EVENT_SUSPEND -- the guest has requested a suspension of the VM. h]j)}(hhh](j)}(hKVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the VM. Userspace is not obliged to honour this, and if it does honour this does not need to destroy the VM synchronously (ie it may call KVM_RUN again before shutdown finally occurs).h]h)}(hKVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the VM. Userspace is not obliged to honour this, and if it does honour this does not need to destroy the VM synchronously (ie it may call KVM_RUN again before shutdown finally occurs).h]hKVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the VM. Userspace is not obliged to honour this, and if it does honour this does not need to destroy the VM synchronously (ie it may call KVM_RUN again before shutdown finally occurs).}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hKVM_SYSTEM_EVENT_RESET -- the guest has requested a reset of the VM. As with SHUTDOWN, userspace can choose to ignore the request, or to schedule the reset to occur in the future and may call KVM_RUN again.h]h)}(hKVM_SYSTEM_EVENT_RESET -- the guest has requested a reset of the VM. As with SHUTDOWN, userspace can choose to ignore the request, or to schedule the reset to occur in the future and may call KVM_RUN again.h]hKVM_SYSTEM_EVENT_RESET -- the guest has requested a reset of the VM. As with SHUTDOWN, userspace can choose to ignore the request, or to schedule the reset to occur in the future and may call KVM_RUN again.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hKVM_SYSTEM_EVENT_CRASH -- the guest crash occurred and the guest has requested a crash condition maintenance. Userspace can choose to ignore the request, or to gather VM memory core dump and/or reset/shutdown of the VM.h]h)}(hKVM_SYSTEM_EVENT_CRASH -- the guest crash occurred and the guest has requested a crash condition maintenance. Userspace can choose to ignore the request, or to gather VM memory core dump and/or reset/shutdown of the VM.h]hKVM_SYSTEM_EVENT_CRASH -- the guest crash occurred and the guest has requested a crash condition maintenance. Userspace can choose to ignore the request, or to gather VM memory core dump and/or reset/shutdown of the VM.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hKVM_SYSTEM_EVENT_SEV_TERM -- an AMD SEV guest requested termination. The guest physical address of the guest's GHCB is stored in `data[0]`.h]h)}(hKVM_SYSTEM_EVENT_SEV_TERM -- an AMD SEV guest requested termination. The guest physical address of the guest's GHCB is stored in `data[0]`.h](hKVM_SYSTEM_EVENT_SEV_TERM -- an AMD SEV guest requested termination. The guest physical address of the guest’s GHCB is stored in }(hj^hhhNhNubj,)}(h `data[0]`h]hdata[0]}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj^ubh.}(hj^hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hX-KVM_SYSTEM_EVENT_TDX_FATAL -- a TDX guest reported a fatal error state. KVM doesn't do any parsing or conversion, it just dumps 16 general-purpose registers to userspace, in ascending order of the 4-bit indices for x86-64 general-purpose registers in instruction encoding, as defined in the Intel SDM.h]h)}(hX-KVM_SYSTEM_EVENT_TDX_FATAL -- a TDX guest reported a fatal error state. KVM doesn't do any parsing or conversion, it just dumps 16 general-purpose registers to userspace, in ascending order of the 4-bit indices for x86-64 general-purpose registers in instruction encoding, as defined in the Intel SDM.h]hX/KVM_SYSTEM_EVENT_TDX_FATAL -- a TDX guest reported a fatal error state. KVM doesn’t do any parsing or conversion, it just dumps 16 general-purpose registers to userspace, in ascending order of the 4-bit indices for x86-64 general-purpose registers in instruction encoding, as defined in the Intel SDM.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hKVM_SYSTEM_EVENT_WAKEUP -- the exiting vCPU is in a suspended state and KVM has recognized a wakeup event. Userspace may honor this event by marking the exiting vCPU as runnable, or deny it and call KVM_RUN again.h]h)}(hKVM_SYSTEM_EVENT_WAKEUP -- the exiting vCPU is in a suspended state and KVM has recognized a wakeup event. Userspace may honor this event by marking the exiting vCPU as runnable, or deny it and call KVM_RUN again.h]hKVM_SYSTEM_EVENT_WAKEUP -- the exiting vCPU is in a suspended state and KVM has recognized a wakeup event. Userspace may honor this event by marking the exiting vCPU as runnable, or deny it and call KVM_RUN again.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_ubah}(h]h ]h"]h$]h&]uh1jhj^ubj)}(hLKVM_SYSTEM_EVENT_SUSPEND -- the guest has requested a suspension of the VM. h]h)}(hKKVM_SYSTEM_EVENT_SUSPEND -- the guest has requested a suspension of the VM.h]hKKVM_SYSTEM_EVENT_SUSPEND -- the guest has requested a suspension of the VM.}(hj+_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'_ubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj~^ubah}(h]h ]h"]h$]h&]uh1j hhhMhj0\hhubh)}(hIf KVM_CAP_SYSTEM_EVENT_DATA is present, the 'data' field can contain architecture specific information for the system-level event. Only the first `ndata` items (possibly zero) of the data array are valid.h](hIf KVM_CAP_SYSTEM_EVENT_DATA is present, the ‘data’ field can contain architecture specific information for the system-level event. Only the first }(hjK_hhhNhNubj,)}(h`ndata`h]hndata}(hjS_hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hjK_ubh3 items (possibly zero) of the data array are valid.}(hjK_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubj )}(hX- for arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI specification. - for arm64, data[0] is set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 if the guest issued a SYSTEM_OFF2 call according to v1.3 of the PSCI specification. - for RISC-V, data[0] is set to the value of the second argument of the ``sbi_system_reset`` call. h]j)}(hhh](j)}(hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI specification. h]h)}(hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI specification.h]hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI specification.}(hjv_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjr_ubah}(h]h ]h"]h$]h&]uh1jhjo_ubj)}(hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 if the guest issued a SYSTEM_OFF2 call according to v1.3 of the PSCI specification. h]h)}(hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 if the guest issued a SYSTEM_OFF2 call according to v1.3 of the PSCI specification.h]hfor arm64, data[0] is set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 if the guest issued a SYSTEM_OFF2 call according to v1.3 of the PSCI specification.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj_ubah}(h]h ]h"]h$]h&]uh1jhjo_ubj)}(hafor RISC-V, data[0] is set to the value of the second argument of the ``sbi_system_reset`` call. h]h)}(h`for RISC-V, data[0] is set to the value of the second argument of the ``sbi_system_reset`` call.h](hFfor RISC-V, data[0] is set to the value of the second argument of the }(hj_hhhNhNubj)}(h``sbi_system_reset``h]hsbi_system_reset}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ubh call.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj_ubah}(h]h ]h"]h$]h&]uh1jhjo_ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjk_ubah}(h]h ]h"]h$]h&]uh1j hhhMhj0\hhubh)}(hPrevious versions of Linux defined a `flags` member in this struct. The field is now aliased to `data[0]`. Userspace can assume that it is only written if ndata is greater than 0.h](h%Previous versions of Linux defined a }(hj_hhhNhNubj,)}(h`flags`h]hflags}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj_ubh5 member in this struct. The field is now aliased to }(hj_hhhNhNubj,)}(h `data[0]`h]hdata[0]}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj_ubhK. Userspace can assume that it is only written if ndata is greater than 0.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj0\hhubeh}(h]id21ah ]h"]h$]j$@ah&]uh1hhjYhhhhhMjKubh)}(hhh](h)}(hFor arm/arm64:h]hFor arm/arm64:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhMubh)}(hKVM_SYSTEM_EVENT_SUSPEND exits are enabled with the KVM_CAP_ARM_SYSTEM_SUSPEND VM capability. If a guest invokes the PSCI SYSTEM_SUSPEND function, KVM will exit to userspace with this event type.h]hKVM_SYSTEM_EVENT_SUSPEND exits are enabled with the KVM_CAP_ARM_SYSTEM_SUSPEND VM capability. If a guest invokes the PSCI SYSTEM_SUSPEND function, KVM will exit to userspace with this event type.}(hj"`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hX It is the sole responsibility of userspace to implement the PSCI SYSTEM_SUSPEND call according to ARM DEN0022D.b 5.19 "SYSTEM_SUSPEND". KVM does not change the vCPU's state before exiting to userspace, so the call parameters are left in-place in the vCPU registers.h]hXIt is the sole responsibility of userspace to implement the PSCI SYSTEM_SUSPEND call according to ARM DEN0022D.b 5.19 “SYSTEM_SUSPEND”. KVM does not change the vCPU’s state before exiting to userspace, so the call parameters are left in-place in the vCPU registers.}(hj0`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hHUserspace is _required_ to take action for such an exit. It must either:h]hHUserspace is _required_ to take action for such an exit. It must either:}(hj>`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(hX- Honor the guest request to suspend the VM. Userspace can request in-kernel emulation of suspension by setting the calling vCPU's state to KVM_MP_STATE_SUSPENDED. Userspace must configure the vCPU's state according to the parameters passed to the PSCI function when the calling vCPU is resumed. See ARM DEN0022D.b 5.19.1 "Intended use" for details on the function parameters. - Deny the guest request to suspend the VM. See ARM DEN0022D.b 5.19.2 "Caller responsibilities" for possible return values. h]j)}(hhh](j)}(hXwHonor the guest request to suspend the VM. Userspace can request in-kernel emulation of suspension by setting the calling vCPU's state to KVM_MP_STATE_SUSPENDED. Userspace must configure the vCPU's state according to the parameters passed to the PSCI function when the calling vCPU is resumed. See ARM DEN0022D.b 5.19.1 "Intended use" for details on the function parameters. h]h)}(hXvHonor the guest request to suspend the VM. Userspace can request in-kernel emulation of suspension by setting the calling vCPU's state to KVM_MP_STATE_SUSPENDED. Userspace must configure the vCPU's state according to the parameters passed to the PSCI function when the calling vCPU is resumed. See ARM DEN0022D.b 5.19.1 "Intended use" for details on the function parameters.h]hX~Honor the guest request to suspend the VM. Userspace can request in-kernel emulation of suspension by setting the calling vCPU’s state to KVM_MP_STATE_SUSPENDED. Userspace must configure the vCPU’s state according to the parameters passed to the PSCI function when the calling vCPU is resumed. See ARM DEN0022D.b 5.19.1 “Intended use” for details on the function parameters.}(hjW`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjS`ubah}(h]h ]h"]h$]h&]uh1jhjP`ubj)}(hzDeny the guest request to suspend the VM. See ARM DEN0022D.b 5.19.2 "Caller responsibilities" for possible return values. h]h)}(hyDeny the guest request to suspend the VM. See ARM DEN0022D.b 5.19.2 "Caller responsibilities" for possible return values.h]h}Deny the guest request to suspend the VM. See ARM DEN0022D.b 5.19.2 “Caller responsibilities” for possible return values.}(hjo`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjk`ubah}(h]h ]h"]h$]h&]uh1jhjP`ubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjL`ubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubh)}(hX_Hibernation using the PSCI SYSTEM_OFF2 call is enabled when PSCI v1.3 is enabled. If a guest invokes the PSCI SYSTEM_OFF2 function, KVM will exit to userspace with the KVM_SYSTEM_EVENT_SHUTDOWN event type and with data[0] set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2. The only supported hibernate type for the SYSTEM_OFF2 function is HIBERNATE_OFF.h]hX_Hibernation using the PSCI SYSTEM_OFF2 call is enabled when PSCI v1.3 is enabled. If a guest invokes the PSCI SYSTEM_OFF2 function, KVM will exit to userspace with the KVM_SYSTEM_EVENT_SHUTDOWN event type and with data[0] set to KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2. The only supported hibernate type for the SYSTEM_OFF2 function is HIBERNATE_OFF.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(h>/* KVM_EXIT_IOAPIC_EOI */ struct { __u8 vector; } eoi;h]h>/* KVM_EXIT_IOAPIC_EOI */ struct { __u8 vector; } eoi;}hj`sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(hX{Indicates that the VCPU's in-kernel local APIC received an EOI for a level-triggered IOAPIC interrupt. This exit only triggers when the IOAPIC is implemented in userspace (i.e. KVM_CAP_SPLIT_IRQCHIP is enabled); the userspace IOAPIC should process the EOI and retrigger the interrupt if it is still asserted. Vector is the LAPIC interrupt vector for which the EOI was received.h]hX}Indicates that the VCPU’s in-kernel local APIC received an EOI for a level-triggered IOAPIC interrupt. This exit only triggers when the IOAPIC is implemented in userspace (i.e. KVM_CAP_SPLIT_IRQCHIP is enabled); the userspace IOAPIC should process the EOI and retrigger the interrupt if it is still asserted. Vector is the LAPIC interrupt vector for which the EOI was received.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(hX struct kvm_hyperv_exit { #define KVM_EXIT_HYPERV_SYNIC 1 #define KVM_EXIT_HYPERV_HCALL 2 #define KVM_EXIT_HYPERV_SYNDBG 3 __u32 type; __u32 pad1; union { struct { __u32 msr; __u32 pad2; __u64 control; __u64 evt_page; __u64 msg_page; } synic; struct { __u64 input; __u64 result; __u64 params[2]; } hcall; struct { __u32 msr; __u32 pad2; __u64 control; __u64 status; __u64 send_page; __u64 recv_page; __u64 pending_page; } syndbg; } u; }; /* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv;h]hX struct kvm_hyperv_exit { #define KVM_EXIT_HYPERV_SYNIC 1 #define KVM_EXIT_HYPERV_HCALL 2 #define KVM_EXIT_HYPERV_SYNDBG 3 __u32 type; __u32 pad1; union { struct { __u32 msr; __u32 pad2; __u64 control; __u64 evt_page; __u64 msg_page; } synic; struct { __u64 input; __u64 result; __u64 params[2]; } hcall; struct { __u32 msr; __u32 pad2; __u64 control; __u64 status; __u64 send_page; __u64 recv_page; __u64 pending_page; } syndbg; } u; }; /* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv;}hj`sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(h`Indicates that the VCPU exits into userspace to process some tasks related to Hyper-V emulation.h]h`Indicates that the VCPU exits into userspace to process some tasks related to Hyper-V emulation.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`hhubh)}(hValid values for 'type' are:h]h Valid values for ‘type’ are:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(hA- KVM_EXIT_HYPERV_SYNIC -- synchronously notify user-space about h]j)}(hhh]j)}(h?KVM_EXIT_HYPERV_SYNIC -- synchronously notify user-space about h]h)}(h>KVM_EXIT_HYPERV_SYNIC -- synchronously notify user-space abouth]h>KVM_EXIT_HYPERV_SYNIC -- synchronously notify user-space about}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`ubah}(h]h ]h"]h$]h&]uh1jhj`ubah}(h]h ]h"]h$]h&]jjuh1jhhhMhj`ubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubh)}(hHyper-V SynIC state change. Notification is used to remap SynIC event/message pages and to enable/disable SynIC messages/events processing in userspace.h]hHyper-V SynIC state change. Notification is used to remap SynIC event/message pages and to enable/disable SynIC messages/events processing in userspace.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(hB- KVM_EXIT_HYPERV_SYNDBG -- synchronously notify user-space about h]j)}(hhh]j)}(h@KVM_EXIT_HYPERV_SYNDBG -- synchronously notify user-space about h]h)}(h?KVM_EXIT_HYPERV_SYNDBG -- synchronously notify user-space abouth]h?KVM_EXIT_HYPERV_SYNDBG -- synchronously notify user-space about}(hj'ahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#aubah}(h]h ]h"]h$]h&]uh1jhj aubah}(h]h ]h"]h$]h&]jjuh1jhhhMhjaubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubh)}(hHyper-V Synthetic debugger state change. Notification is used to either update the pending_page location or to send a control command (send the buffer located in send_page or recv a buffer to recv_page).h]hHyper-V Synthetic debugger state change. Notification is used to either update the pending_page location or to send a control command (send the buffer located in send_page or recv a buffer to recv_page).}(hjGahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(hs/* KVM_EXIT_ARM_NISV / KVM_EXIT_ARM_LDST64B */ struct { __u64 esr_iss; __u64 fault_ipa; } arm_nisv;h]hs/* KVM_EXIT_ARM_NISV / KVM_EXIT_ARM_LDST64B */ struct { __u64 esr_iss; __u64 fault_ipa; } arm_nisv;}hjUasbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubj)}(hhh]j)}(hKVM_EXIT_ARM_NISV: h]h)}(hKVM_EXIT_ARM_NISV:h]hKVM_EXIT_ARM_NISV:}(hjjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjfaubah}(h]h ]h"]h$]h&]uh1jhjcahhhhhNubah}(h]h ]h"]h$]h&]jjuh1jhhhM$hj`hhubh)}(hXrUsed on arm64 systems. If a guest accesses memory not in a memslot, KVM will typically return to userspace and ask it to do MMIO emulation on its behalf. However, for certain classes of instructions, no instruction decode (direction, length of memory access) is provided, and fetching and decoding the instruction from the VM is overly complicated to live in the kernel.h]hXrUsed on arm64 systems. If a guest accesses memory not in a memslot, KVM will typically return to userspace and ask it to do MMIO emulation on its behalf. However, for certain classes of instructions, no instruction decode (direction, length of memory access) is provided, and fetching and decoding the instruction from the VM is overly complicated to live in the kernel.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hj`hhubh)}(hXHistorically, when this situation occurred, KVM would print a warning and kill the VM. KVM assumed that if the guest accessed non-memslot memory, it was trying to do I/O, which just couldn't be emulated, and the warning message was phrased accordingly. However, what happened more often was that a guest bug caused access outside the guest memory areas which should lead to a more meaningful warning message and an external abort in the guest, if the access did not fall within an I/O window.h]hXHistorically, when this situation occurred, KVM would print a warning and kill the VM. KVM assumed that if the guest accessed non-memslot memory, it was trying to do I/O, which just couldn’t be emulated, and the warning message was phrased accordingly. However, what happened more often was that a guest bug caused access outside the guest memory areas which should lead to a more meaningful warning message and an external abort in the guest, if the access did not fall within an I/O window.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hj`hhubh)}(hXUserspace implementations can query for KVM_CAP_ARM_NISV_TO_USER, and enable this capability at VM creation. Once this is done, these types of errors will instead return to userspace with KVM_EXIT_ARM_NISV, with the valid bits from the ESR_EL2 in the esr_iss field, and the faulting IPA in the fault_ipa field. Userspace can either fix up the access if it's actually an I/O access by decoding the instruction from guest memory (if it's very brave) and continue executing the guest, or it can decide to suspend, dump, or restart the guest.h]hXUserspace implementations can query for KVM_CAP_ARM_NISV_TO_USER, and enable this capability at VM creation. Once this is done, these types of errors will instead return to userspace with KVM_EXIT_ARM_NISV, with the valid bits from the ESR_EL2 in the esr_iss field, and the faulting IPA in the fault_ipa field. Userspace can either fix up the access if it’s actually an I/O access by decoding the instruction from guest memory (if it’s very brave) and continue executing the guest, or it can decide to suspend, dump, or restart the guest.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hj`hhubh)}(hNote that KVM does not skip the faulting instruction as it does for KVM_EXIT_MMIO, but userspace has to emulate any change to the processing state if it decides to decode and emulate the instruction.h]hNote that KVM does not skip the faulting instruction as it does for KVM_EXIT_MMIO, but userspace has to emulate any change to the processing state if it decides to decode and emulate the instruction.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hj`hhubh)}(hXThis feature isn't available to protected VMs, as userspace does not have access to the state that is required to perform the emulation. Instead, a data abort exception is directly injected in the guest. Note that although KVM_CAP_ARM_NISV_TO_USER will be reported if queried outside of a protected VM context, the feature will not be exposed if queried on a protected VM file descriptor.h]hXThis feature isn’t available to protected VMs, as userspace does not have access to the state that is required to perform the emulation. Instead, a data abort exception is directly injected in the guest. Note that although KVM_CAP_ARM_NISV_TO_USER will be reported if queried outside of a protected VM context, the feature will not be exposed if queried on a protected VM file descriptor.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM@hj`hhubj)}(hhh]j)}(hKVM_EXIT_ARM_LDST64B: h]h)}(hKVM_EXIT_ARM_LDST64B:h]hKVM_EXIT_ARM_LDST64B:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjaubah}(h]h ]h"]h$]h&]uh1jhjahhhhhNubah}(h]h ]h"]h$]h&]jjuh1jhhhMGhj`hhubh)}(hUsed on arm64 systems. When a guest using a LD64B, ST64B, ST64BV, ST64BV0, outside of a memslot, KVM will return to userspace with KVM_EXIT_ARM_LDST64B, exposing the relevant ESR_EL2 information and faulting IPA, similarly to KVM_EXIT_ARM_NISV.h]hUsed on arm64 systems. When a guest using a LD64B, ST64B, ST64BV, ST64BV0, outside of a memslot, KVM will return to userspace with KVM_EXIT_ARM_LDST64B, exposing the relevant ESR_EL2 information and faulting IPA, similarly to KVM_EXIT_ARM_NISV.}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj`hhubh)}(hHUserspace is supposed to fully emulate the instructions, which includes:h]hHUserspace is supposed to fully emulate the instructions, which includes:}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj`hhubj )}(hX- fetch of the operands for a store, including ACCDATA_EL1 in the case of a ST64BV0 instruction - deal with the endianness if the guest is big-endian - emulate the access, including the delivery of an exception if the access didn't succeed - provide a return value in the case of ST64BV/ST64BV0 - return the data in the case of a load - increment PC if the instruction was successfully executed h]j)}(hhh](j)}(h]fetch of the operands for a store, including ACCDATA_EL1 in the case of a ST64BV0 instructionh]h)}(h]fetch of the operands for a store, including ACCDATA_EL1 in the case of a ST64BV0 instructionh]h]fetch of the operands for a store, including ACCDATA_EL1 in the case of a ST64BV0 instruction}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjbubah}(h]h ]h"]h$]h&]uh1jhj bubj)}(h3deal with the endianness if the guest is big-endianh]h)}(hj(bh]h3deal with the endianness if the guest is big-endian}(hj*bhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj&bubah}(h]h ]h"]h$]h&]uh1jhj bubj)}(hWemulate the access, including the delivery of an exception if the access didn't succeedh]h)}(hWemulate the access, including the delivery of an exception if the access didn't succeedh]hYemulate the access, including the delivery of an exception if the access didn’t succeed}(hjAbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj=bubah}(h]h ]h"]h$]h&]uh1jhj bubj)}(h4provide a return value in the case of ST64BV/ST64BV0h]h)}(hjWbh]h4provide a return value in the case of ST64BV/ST64BV0}(hjYbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjUbubah}(h]h ]h"]h$]h&]uh1jhj bubj)}(h%return the data in the case of a loadh]h)}(hjnbh]h%return the data in the case of a load}(hjpbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhjlbubah}(h]h ]h"]h$]h&]uh1jhj bubj)}(h:increment PC if the instruction was successfully executed h]h)}(h9increment PC if the instruction was successfully executedh]h9increment PC if the instruction was successfully executed}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjbubah}(h]h ]h"]h$]h&]uh1jhj bubeh}(h]h ]h"]h$]h&]jjuh1jhhhMPhjbubah}(h]h ]h"]h$]h&]uh1j hhhMPhj`hhubh)}(hXNote that there is no expectation of performance for this emulation, as it involves a large number of interaction with the guest state. It is, however, expected that the instruction's semantics are preserved, specially the single-copy atomicity property of the 64 byte access.h]hXNote that there is no expectation of performance for this emulation, as it involves a large number of interaction with the guest state. It is, however, expected that the instruction’s semantics are preserved, specially the single-copy atomicity property of the 64 byte access.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhj`hhubh)}(hThis exit reason must be handled if userspace sets ID_AA64ISAR1_EL1.LS64 to a non-zero value, indicating that FEAT_LS64* is enabled.h]hThis exit reason must be handled if userspace sets ID_AA64ISAR1_EL1.LS64 to a non-zero value, indicating that FEAT_LS64* is enabled.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hj`hhubj8)}(h/* KVM_EXIT_X86_RDMSR / KVM_EXIT_X86_WRMSR */ struct { __u8 error; /* user -> kernel */ __u8 pad[7]; __u32 reason; /* kernel -> user */ __u32 index; /* kernel -> user */ __u64 data; /* kernel <-> user */ } msr;h]h/* KVM_EXIT_X86_RDMSR / KVM_EXIT_X86_WRMSR */ struct { __u8 error; /* user -> kernel */ __u8 pad[7]; __u32 reason; /* kernel -> user */ __u32 index; /* kernel -> user */ __u64 data; /* kernel <-> user */ } msr;}hjbsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMchj`hhubh)}(hUsed on x86 systems. When the VM capability KVM_CAP_X86_USER_SPACE_MSR is enabled, MSR accesses to registers that would invoke a #GP by KVM kernel code may instead trigger a KVM_EXIT_X86_RDMSR exit for reads and KVM_EXIT_X86_WRMSR exit for writes.h]hUsed on x86 systems. When the VM capability KVM_CAP_X86_USER_SPACE_MSR is enabled, MSR accesses to registers that would invoke a #GP by KVM kernel code may instead trigger a KVM_EXIT_X86_RDMSR exit for reads and KVM_EXIT_X86_WRMSR exit for writes.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj`hhubh)}(hThe "reason" field specifies why the MSR interception occurred. Userspace will only receive MSR exits when a particular reason was requested during through ENABLE_CAP. Currently valid exit reasons are:h]hThe “reason” field specifies why the MSR interception occurred. Userspace will only receive MSR exits when a particular reason was requested during through ENABLE_CAP. Currently valid exit reasons are:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMqhj`hhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjbubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK(uh1jchjbubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_UNKNOWNh]hKVM_MSR_EXIT_REASON_UNKNOWN}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhj cubah}(h]h ]h"]h$]h&]uh1jhj cubj)}(hhh]h)}(h$access to MSR that is unknown to KVMh]h$access to MSR that is unknown to KVM}(hj'chhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhj$cubah}(h]h ]h"]h$]h&]uh1jhj cubeh}(h]h ]h"]h$]h&]uh1j~hjcubj)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_INVALh]hKVM_MSR_EXIT_REASON_INVAL}(hjGchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjDcubah}(h]h ]h"]h$]h&]uh1jhjAcubj)}(hhh]h)}(h'access to invalid MSRs or reserved bitsh]h'access to invalid MSRs or reserved bits}(hj^chhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhj[cubah}(h]h ]h"]h$]h&]uh1jhjAcubeh}(h]h ]h"]h$]h&]uh1j~hjcubj)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_FILTERh]hKVM_MSR_EXIT_REASON_FILTER}(hj~chhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj{cubah}(h]h ]h"]h$]h&]uh1jhjxcubj)}(hhh]h)}(h(access blocked by KVM_X86_SET_MSR_FILTERh]h(access blocked by KVM_X86_SET_MSR_FILTER}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhjcubah}(h]h ]h"]h$]h&]uh1jhjxcubeh}(h]h ]h"]h$]h&]uh1j~hjcubeh}(h]h ]h"]h$]h&]uh1jyhjbubeh}(h]h ]h"]h$]h&]colsKuh1j^hjbubah}(h]h ]h"]h$]h&]uh1jYhj`hhhhhNubh)}(hX.For KVM_EXIT_X86_RDMSR, the "index" field tells userspace which MSR the guest wants to read. To respond to this request with a successful read, userspace writes the respective data into the "data" field and must continue guest execution to ensure the read data is transferred into guest register state.h]hX6For KVM_EXIT_X86_RDMSR, the “index” field tells userspace which MSR the guest wants to read. To respond to this request with a successful read, userspace writes the respective data into the “data” field and must continue guest execution to ensure the read data is transferred into guest register state.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj`hhubh)}(hIf the RDMSR request was unsuccessful, userspace indicates that with a "1" in the "error" field. This will inject a #GP into the guest when the VCPU is executed again.h]hIf the RDMSR request was unsuccessful, userspace indicates that with a “1” in the “error” field. This will inject a #GP into the guest when the VCPU is executed again.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hFor KVM_EXIT_X86_WRMSR, the "index" field tells userspace which MSR the guest wants to write. Once finished processing the event, userspace must continue vCPU execution. If the MSR write was unsuccessful, userspace also sets the "error" field to "1".h]hXFor KVM_EXIT_X86_WRMSR, the “index” field tells userspace which MSR the guest wants to write. Once finished processing the event, userspace must continue vCPU execution. If the MSR write was unsuccessful, userspace also sets the “error” field to “1”.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hMSee KVM_X86_SET_MSR_FILTER for details on the interaction with MSR filtering.h]hMSee KVM_X86_SET_MSR_FILTER for details on the interaction with MSR filtering.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(hXS struct kvm_xen_exit { #define KVM_EXIT_XEN_HCALL 1 __u32 type; union { struct { __u32 longmode; __u32 cpl; __u64 input; __u64 result; __u64 params[6]; } hcall; } u; }; /* KVM_EXIT_XEN */ struct kvm_hyperv_exit xen;h]hXS struct kvm_xen_exit { #define KVM_EXIT_XEN_HCALL 1 __u32 type; union { struct { __u32 longmode; __u32 cpl; __u64 input; __u64 result; __u64 params[6]; } hcall; } u; }; /* KVM_EXIT_XEN */ struct kvm_hyperv_exit xen;}hjcsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(h\Indicates that the VCPU exits into userspace to process some tasks related to Xen emulation.h]h\Indicates that the VCPU exits into userspace to process some tasks related to Xen emulation.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hValid values for 'type' are:h]h Valid values for ‘type’ are:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(h- KVM_EXIT_XEN_HCALL -- synchronously notify user-space about Xen hypercall. Userspace is expected to place the hypercall result into the appropriate field before invoking KVM_RUN again. h]j)}(hhh]j)}(hKVM_EXIT_XEN_HCALL -- synchronously notify user-space about Xen hypercall. Userspace is expected to place the hypercall result into the appropriate field before invoking KVM_RUN again. h]h)}(hKVM_EXIT_XEN_HCALL -- synchronously notify user-space about Xen hypercall. Userspace is expected to place the hypercall result into the appropriate field before invoking KVM_RUN again.h]hKVM_EXIT_XEN_HCALL -- synchronously notify user-space about Xen hypercall. Userspace is expected to place the hypercall result into the appropriate field before invoking KVM_RUN again.}(hj/dhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+dubah}(h]h ]h"]h$]h&]uh1jhj(dubah}(h]h ]h"]h$]h&]jjuh1jhhhMhj$dubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubj8)}(h/* KVM_EXIT_RISCV_SBI */ struct { unsigned long extension_id; unsigned long function_id; unsigned long args[6]; unsigned long ret[2]; } riscv_sbi;h]h/* KVM_EXIT_RISCV_SBI */ struct { unsigned long extension_id; unsigned long function_id; unsigned long args[6]; unsigned long ret[2]; } riscv_sbi;}hjOdsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(hXIf exit reason is KVM_EXIT_RISCV_SBI then it indicates that the VCPU has done a SBI call which is not handled by KVM RISC-V kernel module. The details of the SBI call are available in 'riscv_sbi' member of kvm_run structure. The 'extension_id' field of 'riscv_sbi' represents SBI extension ID whereas the 'function_id' field represents function ID of given SBI extension. The 'args' array field of 'riscv_sbi' represents parameters for the SBI call and 'ret' array field represents return values. The userspace should update the return values of SBI call before resuming the VCPU. For more details on RISC-V SBI spec refer, https://github.com/riscv/riscv-sbi-doc.h](hXIf exit reason is KVM_EXIT_RISCV_SBI then it indicates that the VCPU has done a SBI call which is not handled by KVM RISC-V kernel module. The details of the SBI call are available in ‘riscv_sbi’ member of kvm_run structure. The ‘extension_id’ field of ‘riscv_sbi’ represents SBI extension ID whereas the ‘function_id’ field represents function ID of given SBI extension. The ‘args’ array field of ‘riscv_sbi’ represents parameters for the SBI call and ‘ret’ array field represents return values. The userspace should update the return values of SBI call before resuming the VCPU. For more details on RISC-V SBI spec refer, }(hj]dhhhNhNubj)}(h&https://github.com/riscv/riscv-sbi-doch]h&https://github.com/riscv/riscv-sbi-doc}(hjedhhhNhNubah}(h]h ]h"]h$]h&]refurijgduh1jhj]dubh.}(hj]dhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(h /* KVM_EXIT_MEMORY_FAULT */ struct { #define KVM_MEMORY_EXIT_FLAG_PRIVATE (1ULL << 3) __u64 flags; __u64 gpa; __u64 size; } memory_fault;h]h /* KVM_EXIT_MEMORY_FAULT */ struct { #define KVM_MEMORY_EXIT_FLAG_PRIVATE (1ULL << 3) __u64 flags; __u64 gpa; __u64 size; } memory_fault;}hj~dsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(hX/KVM_EXIT_MEMORY_FAULT indicates the vCPU has encountered a memory fault that could not be resolved by KVM. The 'gpa' and 'size' (in bytes) describe the guest physical address range [gpa, gpa + size) of the fault. The 'flags' field describes properties of the faulting access that are likely pertinent:h]hX;KVM_EXIT_MEMORY_FAULT indicates the vCPU has encountered a memory fault that could not be resolved by KVM. The ‘gpa’ and ‘size’ (in bytes) describe the guest physical address range [gpa, gpa + size) of the fault. The ‘flags’ field describes properties of the faulting access that are likely pertinent:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(h- KVM_MEMORY_EXIT_FLAG_PRIVATE - When set, indicates the memory fault occurred on a private memory access. When clear, indicates the fault occurred on a shared access. h]j)}(hhh]j)}(hKVM_MEMORY_EXIT_FLAG_PRIVATE - When set, indicates the memory fault occurred on a private memory access. When clear, indicates the fault occurred on a shared access. h]h)}(hKVM_MEMORY_EXIT_FLAG_PRIVATE - When set, indicates the memory fault occurred on a private memory access. When clear, indicates the fault occurred on a shared access.h]hKVM_MEMORY_EXIT_FLAG_PRIVATE - When set, indicates the memory fault occurred on a private memory access. When clear, indicates the fault occurred on a shared access.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjdubah}(h]h ]h"]h$]h&]uh1jhjdubah}(h]h ]h"]h$]h&]jjuh1jhhhMhjdubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubh)}(hX0Note! KVM_EXIT_MEMORY_FAULT is unique among all KVM exit reasons in that it accompanies a return code of '-1', not '0'! errno will always be set to EFAULT or EHWPOISON when KVM exits with KVM_EXIT_MEMORY_FAULT, userspace should assume kvm_run.exit_reason is stale/undefined for all other error numbers.h]hX8Note! KVM_EXIT_MEMORY_FAULT is unique among all KVM exit reasons in that it accompanies a return code of ‘-1’, not ‘0’! errno will always be set to EFAULT or EHWPOISON when KVM exits with KVM_EXIT_MEMORY_FAULT, userspace should assume kvm_run.exit_reason is stale/undefined for all other error numbers.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj8)}(hn /* KVM_EXIT_NOTIFY */ struct { #define KVM_NOTIFY_CONTEXT_INVALID (1 << 0) __u32 flags; } notify;h]hn /* KVM_EXIT_NOTIFY */ struct { #define KVM_NOTIFY_CONTEXT_INVALID (1 << 0) __u32 flags; } notify;}hjdsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(hXvUsed on x86 systems. When the VM capability KVM_CAP_X86_NOTIFY_VMEXIT is enabled, a VM exit generated if no event window occurs in VM non-root mode for a specified amount of time. Once KVM_X86_NOTIFY_VMEXIT_USER is set when enabling the cap, it would exit to userspace with the exit reason KVM_EXIT_NOTIFY for further handling. The "flags" field contains more detailed info.h]hXzUsed on x86 systems. When the VM capability KVM_CAP_X86_NOTIFY_VMEXIT is enabled, a VM exit generated if no event window occurs in VM non-root mode for a specified amount of time. Once KVM_X86_NOTIFY_VMEXIT_USER is set when enabling the cap, it would exit to userspace with the exit reason KVM_EXIT_NOTIFY for further handling. The “flags” field contains more detailed info.}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hThe valid value for 'flags' is:h]h#The valid value for ‘flags’ is:}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(h- KVM_NOTIFY_CONTEXT_INVALID -- the VM context is corrupted and not valid in VMCS. It would run into unknown result if resume the target VM. h]j)}(hhh]j)}(hKVM_NOTIFY_CONTEXT_INVALID -- the VM context is corrupted and not valid in VMCS. It would run into unknown result if resume the target VM. h]h)}(hKVM_NOTIFY_CONTEXT_INVALID -- the VM context is corrupted and not valid in VMCS. It would run into unknown result if resume the target VM.h]hKVM_NOTIFY_CONTEXT_INVALID -- the VM context is corrupted and not valid in VMCS. It would run into unknown result if resume the target VM.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjeubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]jjuh1jhhhMhjdubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubj8)}(hX/* KVM_EXIT_TDX */ struct { __u64 flags; __u64 nr; union { struct { u64 ret; u64 data[5]; } unknown; struct { u64 ret; u64 gpa; u64 size; } get_quote; struct { u64 ret; u64 leaf; u64 r11, r12, r13, r14; } get_tdvmcall_info; struct { u64 ret; u64 vector; } setup_event_notify; }; } tdx;h]hX/* KVM_EXIT_TDX */ struct { __u64 flags; __u64 nr; union { struct { u64 ret; u64 data[5]; } unknown; struct { u64 ret; u64 gpa; u64 size; } get_quote; struct { u64 ret; u64 leaf; u64 r11, r12, r13, r14; } get_tdvmcall_info; struct { u64 ret; u64 vector; } setup_event_notify; }; } tdx;}hj(esbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhj`hhubh)}(hX"Process a TDVMCALL from the guest. KVM forwards select TDVMCALL based on the Guest-Hypervisor Communication Interface (GHCI) specification; KVM bridges these requests to the userspace VMM with minimal changes, placing the inputs in the union and copying them back to the guest on re-entry.h]hX"Process a TDVMCALL from the guest. KVM forwards select TDVMCALL based on the Guest-Hypervisor Communication Interface (GHCI) specification; KVM bridges these requests to the userspace VMM with minimal changes, placing the inputs in the union and copying them back to the guest on re-entry.}(hj6ehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hFlags are currently always zero, whereas ``nr`` contains the TDVMCALL number from register R11. The remaining field of the union provide the inputs and outputs of the TDVMCALL. Currently the following values of ``nr`` are defined:h](h)Flags are currently always zero, whereas }(hjDehhhNhNubj)}(h``nr``h]hnr}(hjLehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDeubh contains the TDVMCALL number from register R11. The remaining field of the union provide the inputs and outputs of the TDVMCALL. Currently the following values of }(hjDehhhNhNubj)}(h``nr``h]hnr}(hj^ehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDeubh are defined:}(hjDehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hj`hhubj )}(hXF* ``TDVMCALL_GET_QUOTE``: the guest has requested to generate a TD-Quote signed by a service hosting TD-Quoting Enclave operating on the host. Parameters and return value are in the ``get_quote`` field of the union. The ``gpa`` field and ``size`` specify the guest physical address (without the shared bit set) and the size of a shared-memory buffer, in which the TDX guest passes a TD Report. The ``ret`` field represents the return value of the GetQuote request. When the request has been queued successfully, the TDX guest can poll the status field in the shared-memory area to check whether the Quote generation is completed or not. When completed, the generated Quote is returned via the same buffer. * ``TDVMCALL_GET_TD_VM_CALL_INFO``: the guest has requested the support status of TDVMCALLs. The output values for the given leaf should be placed in fields from ``r11`` to ``r14`` of the ``get_tdvmcall_info`` field of the union. * ``TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT``: the guest has requested to set up a notification interrupt for vector ``vector``. h]j)}(hhh](j)}(hX``TDVMCALL_GET_QUOTE``: the guest has requested to generate a TD-Quote signed by a service hosting TD-Quoting Enclave operating on the host. Parameters and return value are in the ``get_quote`` field of the union. The ``gpa`` field and ``size`` specify the guest physical address (without the shared bit set) and the size of a shared-memory buffer, in which the TDX guest passes a TD Report. The ``ret`` field represents the return value of the GetQuote request. When the request has been queued successfully, the TDX guest can poll the status field in the shared-memory area to check whether the Quote generation is completed or not. When completed, the generated Quote is returned via the same buffer. h]h)}(hX``TDVMCALL_GET_QUOTE``: the guest has requested to generate a TD-Quote signed by a service hosting TD-Quoting Enclave operating on the host. Parameters and return value are in the ``get_quote`` field of the union. The ``gpa`` field and ``size`` specify the guest physical address (without the shared bit set) and the size of a shared-memory buffer, in which the TDX guest passes a TD Report. The ``ret`` field represents the return value of the GetQuote request. When the request has been queued successfully, the TDX guest can poll the status field in the shared-memory area to check whether the Quote generation is completed or not. When completed, the generated Quote is returned via the same buffer.h](j)}(h``TDVMCALL_GET_QUOTE``h]hTDVMCALL_GET_QUOTE}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh: the guest has requested to generate a TD-Quote signed by a service hosting TD-Quoting Enclave operating on the host. Parameters and return value are in the }(hjehhhNhNubj)}(h ``get_quote``h]h get_quote}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh field of the union. The }(hjehhhNhNubj)}(h``gpa``h]hgpa}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh field and }(hjehhhNhNubj)}(h``size``h]hsize}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh specify the guest physical address (without the shared bit set) and the size of a shared-memory buffer, in which the TDX guest passes a TD Report. The }(hjehhhNhNubj)}(h``ret``h]hret}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubhX- field represents the return value of the GetQuote request. When the request has been queued successfully, the TDX guest can poll the status field in the shared-memory area to check whether the Quote generation is completed or not. When completed, the generated Quote is returned via the same buffer.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj}eubah}(h]h ]h"]h$]h&]uh1jhjzeubj)}(h``TDVMCALL_GET_TD_VM_CALL_INFO``: the guest has requested the support status of TDVMCALLs. The output values for the given leaf should be placed in fields from ``r11`` to ``r14`` of the ``get_tdvmcall_info`` field of the union. h]h)}(h``TDVMCALL_GET_TD_VM_CALL_INFO``: the guest has requested the support status of TDVMCALLs. The output values for the given leaf should be placed in fields from ``r11`` to ``r14`` of the ``get_tdvmcall_info`` field of the union.h](j)}(h ``TDVMCALL_GET_TD_VM_CALL_INFO``h]hTDVMCALL_GET_TD_VM_CALL_INFO}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh: the guest has requested the support status of TDVMCALLs. The output values for the given leaf should be placed in fields from }(hjehhhNhNubj)}(h``r11``h]hr11}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh to }(hjehhhNhNubj)}(h``r14``h]hr14}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh of the }(hjehhhNhNubj)}(h``get_tdvmcall_info``h]hget_tdvmcall_info}(hj)fhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubh field of the union.}(hjehhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjeubah}(h]h ]h"]h$]h&]uh1jhjzeubj)}(h}``TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT``: the guest has requested to set up a notification interrupt for vector ``vector``. h]h)}(h|``TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT``: the guest has requested to set up a notification interrupt for vector ``vector``.h](j)}(h)``TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT``h]h%TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT}(hjOfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKfubhH: the guest has requested to set up a notification interrupt for vector }(hjKfhhhNhNubj)}(h ``vector``h]hvector}(hjafhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjKfubh.}(hjKfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjGfubah}(h]h ]h"]h$]h&]uh1jhjzeubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjveubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubh)}(hX|KVM may add support for more values in the future that may cause a userspace exit, even without calls to ``KVM_ENABLE_CAP`` or similar. In this case, it will enter with output fields already valid; in the common case, the ``unknown.ret`` field of the union will be ``TDVMCALL_STATUS_SUBFUNC_UNSUPPORTED``. Userspace need not do anything if it does not wish to support a TDVMCALL.h](hiKVM may add support for more values in the future that may cause a userspace exit, even without calls to }(hjfhhhNhNubj)}(h``KVM_ENABLE_CAP``h]hKVM_ENABLE_CAP}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubhd or similar. In this case, it will enter with output fields already valid; in the common case, the }(hjfhhhNhNubj)}(h``unknown.ret``h]h unknown.ret}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh field of the union will be }(hjfhhhNhNubj)}(h'``TDVMCALL_STATUS_SUBFUNC_UNSUPPORTED``h]h#TDVMCALL_STATUS_SUBFUNC_UNSUPPORTED}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubhK. Userspace need not do anything if it does not wish to support a TDVMCALL.}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM!hj`hhubj8)}(hX /* KVM_EXIT_ARM_SEA */ struct { #define KVM_EXIT_ARM_SEA_FLAG_GPA_VALID (1ULL << 0) __u64 flags; __u64 esr; __u64 gva; __u64 gpa; } arm_sea;h]hX /* KVM_EXIT_ARM_SEA */ struct { #define KVM_EXIT_ARM_SEA_FLAG_GPA_VALID (1ULL << 0) __u64 flags; __u64 esr; __u64 gva; __u64 gpa; } arm_sea;}hjfsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM)hj`hhubh)}(hUsed on arm64 systems. When the VM capability ``KVM_CAP_ARM_SEA_TO_USER`` is enabled, a KVM exits to userspace if a guest access causes a synchronous external abort (SEA) and the host APEI fails to handle the SEA.h](h.Used on arm64 systems. When the VM capability }(hjfhhhNhNubj)}(h``KVM_CAP_ARM_SEA_TO_USER``h]hKVM_CAP_ARM_SEA_TO_USER}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubh is enabled, a KVM exits to userspace if a guest access causes a synchronous external abort (SEA) and the host APEI fails to handle the SEA.}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM2hj`hhubh)}(hs``esr`` is set to a sanitized value of ESR_EL2 from the exception taken to KVM, consisting of the following fields:h](j)}(h``esr``h]hesr}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjfubhl is set to a sanitized value of ESR_EL2 from the exception taken to KVM, consisting of the following fields:}(hjfhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM6hj`hhubj )}(h- ``ESR_EL2.EC`` - ``ESR_EL2.IL`` - ``ESR_EL2.FnV`` - ``ESR_EL2.EA`` - ``ESR_EL2.CM`` - ``ESR_EL2.WNR`` - ``ESR_EL2.FSC`` - ``ESR_EL2.SET`` (when FEAT_RAS is implemented for the VM) h]j)}(hhh](j)}(h``ESR_EL2.EC``h]h)}(hj"gh]j)}(hj"gh]h ESR_EL2.EC}(hj'ghhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$gubah}(h]h ]h"]h$]h&]uh1hhhhM9hj gubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.IL``h]h)}(hjBgh]j)}(hjBgh]h ESR_EL2.IL}(hjGghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjDgubah}(h]h ]h"]h$]h&]uh1hhhhM:hj@gubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.FnV``h]h)}(hjbgh]j)}(hjbgh]h ESR_EL2.FnV}(hjgghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdgubah}(h]h ]h"]h$]h&]uh1hhhhM;hj`gubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.EA``h]h)}(hjgh]j)}(hjgh]h ESR_EL2.EA}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hhhhM<hjgubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.CM``h]h)}(hjgh]j)}(hjgh]h ESR_EL2.CM}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hhhhM=hjgubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.WNR``h]h)}(hjgh]j)}(hjgh]h ESR_EL2.WNR}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hhhhM>hjgubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h``ESR_EL2.FSC``h]h)}(hjgh]j)}(hjgh]h ESR_EL2.FSC}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjgubah}(h]h ]h"]h$]h&]uh1hhhhM?hjgubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(h:``ESR_EL2.SET`` (when FEAT_RAS is implemented for the VM) h]h)}(h9``ESR_EL2.SET`` (when FEAT_RAS is implemented for the VM)h](j)}(h``ESR_EL2.SET``h]h ESR_EL2.SET}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubh* (when FEAT_RAS is implemented for the VM)}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM@hjhubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]jjuh1jhhhM9hjgubah}(h]h ]h"]h$]h&]uh1j hhhM9hj`hhubh)}(h``gva`` is set to the value of FAR_EL2 from the exception taken to KVM when ``ESR_EL2.FnV == 0``. Otherwise, the value of ``gva`` is unknown.h](j)}(h``gva``h]hgva}(hj6hhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2hubhE is set to the value of FAR_EL2 from the exception taken to KVM when }(hj2hhhhNhNubj)}(h``ESR_EL2.FnV == 0``h]hESR_EL2.FnV == 0}(hjHhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2hubh. Otherwise, the value of }(hj2hhhhNhNubj)}(h``gva``h]hgva}(hjZhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2hubh is unknown.}(hj2hhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMBhj`hhubh)}(h``gpa`` is set to the faulting IPA from the exception taken to KVM when the ``KVM_EXIT_ARM_SEA_FLAG_GPA_VALID`` flag is set. Otherwise, the value of ``gpa`` is unknown.h](j)}(h``gpa``h]hgpa}(hjvhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrhubhE is set to the faulting IPA from the exception taken to KVM when the }(hjrhhhhNhNubj)}(h#``KVM_EXIT_ARM_SEA_FLAG_GPA_VALID``h]hKVM_EXIT_ARM_SEA_FLAG_GPA_VALID}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrhubh& flag is set. Otherwise, the value of }(hjrhhhhNhNubj)}(h``gpa``h]hgpa}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjrhubh is unknown.}(hjrhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMEhj`hhubj8)}(hX /* Fix the size of the union. */ char padding[256]; }; /* * shared registers between kvm and userspace. * kvm_valid_regs specifies the register classes set by the host * kvm_dirty_regs specified the register classes dirtied by userspace * struct kvm_sync_regs is architecture specific, as well as the * bits for kvm_valid_regs and kvm_dirty_regs */ __u64 kvm_valid_regs; __u64 kvm_dirty_regs; union { struct kvm_sync_regs regs; char padding[SYNC_REGS_SIZE_BYTES]; } s;h]hX /* Fix the size of the union. */ char padding[256]; }; /* * shared registers between kvm and userspace. * kvm_valid_regs specifies the register classes set by the host * kvm_dirty_regs specified the register classes dirtied by userspace * struct kvm_sync_regs is architecture specific, as well as the * bits for kvm_valid_regs and kvm_dirty_regs */ __u64 kvm_valid_regs; __u64 kvm_dirty_regs; union { struct kvm_sync_regs regs; char padding[SYNC_REGS_SIZE_BYTES]; } s;}hjhsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMKhj`hhubh)}(hXIf KVM_CAP_SYNC_REGS is defined, these fields allow userspace to access certain guest registers without having to call SET/GET_*REGS. Thus we can avoid some system call overhead if userspace has to handle the exit. Userspace can query the validity of the structure by checking kvm_valid_regs for specific bits. These bits are architecture specific and usually define the validity of a groups of registers. (e.g. one bit for general purpose registers)h]hXIf KVM_CAP_SYNC_REGS is defined, these fields allow userspace to access certain guest registers without having to call SET/GET_*REGS. Thus we can avoid some system call overhead if userspace has to handle the exit. Userspace can query the validity of the structure by checking kvm_valid_regs for specific bits. These bits are architecture specific and usually define the validity of a groups of registers. (e.g. one bit for general purpose registers)}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hj`hhubh)}(hPlease note that the kernel is allowed to use the kvm_run structure as the primary storage for certain register types. Therefore, the kernel may use the values in kvm_run even if the corresponding bit in kvm_dirty_regs is not set.h]hPlease note that the kernel is allowed to use the kvm_run structure as the primary storage for certain register types. Therefore, the kernel may use the values in kvm_run even if the corresponding bit in kvm_dirty_regs is not set.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj`hhubj8)}(h{/* KVM_EXIT_SNP_REQ_CERTS */ struct kvm_exit_snp_req_certs { __u64 gpa; __u64 npages; __u64 ret; };h]h{/* KVM_EXIT_SNP_REQ_CERTS */ struct kvm_exit_snp_req_certs { __u64 gpa; __u64 npages; __u64 ret; };}hjhsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMkhj`hhubh)}(hXKVM_EXIT_SNP_REQ_CERTS indicates an SEV-SNP guest with certificate-fetching enabled (see KVM_SEV_SNP_ENABLE_REQ_CERTS) has generated an Extended Guest Request NAE #VMGEXIT (SNP_GUEST_REQUEST) with message type MSG_REPORT_REQ, i.e. has requested an attestation report from firmware, and would like the certificate data corresponding to the attestation report signature to be provided by the hypervisor as part of the request.h]hXKVM_EXIT_SNP_REQ_CERTS indicates an SEV-SNP guest with certificate-fetching enabled (see KVM_SEV_SNP_ENABLE_REQ_CERTS) has generated an Extended Guest Request NAE #VMGEXIT (SNP_GUEST_REQUEST) with message type MSG_REPORT_REQ, i.e. has requested an attestation report from firmware, and would like the certificate data corresponding to the attestation report signature to be provided by the hypervisor as part of the request.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhj`hhubh)}(hXgTo allow for userspace to provide the certificate, the 'gpa' and 'npages' are forwarded verbatim from the guest request (the RAX and RBX GHCB fields respectively). 'ret' is not an "output" from KVM, and is always '0' on exit. KVM verifies the 'gpa' is 4KiB aligned prior to exiting to userspace, but otherwise the information from the guest isn't validated.h]hXTo allow for userspace to provide the certificate, the ‘gpa’ and ‘npages’ are forwarded verbatim from the guest request (the RAX and RBX GHCB fields respectively). ‘ret’ is not an “output” from KVM, and is always ‘0’ on exit. KVM verifies the ‘gpa’ is 4KiB aligned prior to exiting to userspace, but otherwise the information from the guest isn’t validated.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj`hhubh)}(hX!Upon the next KVM_RUN, e.g. after userspace has serviced the request (or not), KVM will complete the #VMGEXIT, using the 'ret' field to determine whether to signal success or failure to the guest, and on failure, what reason code will be communicated via SW_EXITINFO2. If 'ret' is set to an unsupported value (see the table below), KVM_RUN will fail with -EINVAL. For a 'ret' of 'ENOSPC', KVM also consumes the 'npages' field, i.e. userspace can use the field to inform the guest of the number of pages needed to hold all the certificate data.h]hX5Upon the next KVM_RUN, e.g. after userspace has serviced the request (or not), KVM will complete the #VMGEXIT, using the ‘ret’ field to determine whether to signal success or failure to the guest, and on failure, what reason code will be communicated via SW_EXITINFO2. If ‘ret’ is set to an unsupported value (see the table below), KVM_RUN will fail with -EINVAL. For a ‘ret’ of ‘ENOSPC’, KVM also consumes the ‘npages’ field, i.e. userspace can use the field to inform the guest of the number of pages needed to hold all the certificate data.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubh)}(hGThe supported 'ret' values and their respective SW_EXITINFO2 encodings:h]hKThe supported ‘ret’ values and their respective SW_EXITINFO2 encodings:}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`hhubj )}(hX====== ============================================================= 0 0x0, i.e. success. KVM will emit an SNP_GUEST_REQUEST command to SNP firmware. ENOSPC 0x0000000100000000, i.e. not enough guest pages to hold the certificate table and certificate data. KVM will also set the RBX field in the GHBC to 'npages'. EAGAIN 0x0000000200000000, i.e. the host is busy and the guest should retry the request. EIO 0xffffffff00000000, for all other errors (this return code is a KVM-defined hypervisor value, as allowed by the GHCB) ====== ============================================================= h]jZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj)iubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK>uh1jchj)iubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjIihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjFiubah}(h]h ]h"]h$]h&]uh1jhjCiubj)}(hhh]h)}(hO0x0, i.e. success. KVM will emit an SNP_GUEST_REQUEST command to SNP firmware.h]hO0x0, i.e. success. KVM will emit an SNP_GUEST_REQUEST command to SNP firmware.}(hj_ihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\iubah}(h]h ]h"]h$]h&]uh1jhjCiubeh}(h]h ]h"]h$]h&]uh1j~hj@iubj)}(hhh](j)}(hhh]h)}(hENOSPCh]hENOSPC}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj|iubah}(h]h ]h"]h$]h&]uh1jhjyiubj)}(hhh]h)}(h0x0000000100000000, i.e. not enough guest pages to hold the certificate table and certificate data. KVM will also set the RBX field in the GHBC to 'npages'.h]h0x0000000100000000, i.e. not enough guest pages to hold the certificate table and certificate data. KVM will also set the RBX field in the GHBC to ‘npages’.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjyiubeh}(h]h ]h"]h$]h&]uh1j~hj@iubj)}(hhh](j)}(hhh]h)}(hEAGAINh]hEAGAIN}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh]h)}(hQ0x0000000200000000, i.e. the host is busy and the guest should retry the request.h]hQ0x0000000200000000, i.e. the host is busy and the guest should retry the request.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j~hj@iubj)}(hhh](j)}(hhh]h)}(hEIOh]hEIO}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjiubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh]h)}(hu0xffffffff00000000, for all other errors (this return code is a KVM-defined hypervisor value, as allowed by the GHCB)h]hu0xffffffff00000000, for all other errors (this return code is a KVM-defined hypervisor value, as allowed by the GHCB)}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjubah}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]uh1j~hj@iubeh}(h]h ]h"]h$]h&]uh1jyhj)iubeh}(h]h ]h"]h$]h&]colsKuh1j^hj&iubah}(h]h ]h"]h$]h&]uh1jYhj"iubah}(h]h ]h"]h$]h&]uh1j hhhMhj`hhubjT)}(h.. _cap_enable:h]h}(h]h ]h"]h$]h&]j_ cap-enableuh1jShMhj`hhhhubeh}(h] for-arm-arm64ah ]h"]for arm/arm64:ah$]h&]uh1hhjYhhhhhMubeh}(h](the-kvm-run-structurejYeh ]h"](5. the kvm_run structurekvm_runeh$]h&]uh1hhhhhhhhM j}jPjjYsj}jYjYsubh)}(hhh](h)}(h,6. Capabilities that can be enabled on vCPUsh]h,6. Capabilities that can be enabled on vCPUs}(hjXjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUjhhhhhMubh)}(hThere are certain capabilities that change the behavior of the virtual CPU or the virtual machine when enabled. To enable them, please see :ref:`KVM_ENABLE_CAP`.h](hThere are certain capabilities that change the behavior of the virtual CPU or the virtual machine when enabled. To enable them, please see }(hjfjhhhNhNubh)}(h:ref:`KVM_ENABLE_CAP`h]j)}(hjpjh]hKVM_ENABLE_CAP}(hjrjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjnjubah}(h]h ]h"]h$]h&]refdocj refdomainj|jreftyperef refexplicitrefwarnjkvm_enable_capuh1hhhhMhjfjubh.}(hjfjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjUjhhubh)}(hyBelow you can find a list of capabilities and what their effect on the vCPU or the virtual machine is when enabling them.h]hyBelow you can find a list of capabilities and what their effect on the vCPU or the virtual machine is when enabling them.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUjhhubh)}(hAThe following information is provided along with the description:h]hAThe following information is provided along with the description:}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjUjhhubj )}(hX~Architectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. Target: whether this is a per-vcpu or per-vm capability. Parameters: what parameters are accepted by the capability. Returns: the return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are. h]j )}(hhh](j)}(hjArchitectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. h](j)}(hArchitectures:h]hArchitectures:}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjjubj%)}(hhh]h)}(hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.h]hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjubah}(h]h ]h"]h$]h&]uh1j$hjjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjjubj)}(h9Target: whether this is a per-vcpu or per-vm capability. h](j)}(hTarget:h]hTarget:}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjjubj%)}(hhh]h)}(h0whether this is a per-vcpu or per-vm capability.h]h0whether this is a per-vcpu or per-vm capability.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjjubah}(h]h ]h"]h$]h&]uh1j$hjjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjjubj)}(hFor mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:h]h>For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjmhhubj )}(hX- The "params" field is of type "struct kvm_book3e_206_tlb_params". - The "array" field points to an array of type "struct kvm_book3e_206_tlb_entry". - The array consists of all entries in the first TLB, followed by all entries in the second TLB. - Within a TLB, entries are ordered first by increasing set number. Within a set, entries are ordered by way (increasing ESEL). - The hash for determining set number in TLB0 is: (MAS2 >> 12) & (num_sets - 1) where "num_sets" is the tlb_sizes[] value divided by the tlb_ways[] value. - The tsize field of mas1 shall be set to 4K on TLB0, even though the hardware ignores this value for TLB0. h]j)}(hhh](j)}(hAThe "params" field is of type "struct kvm_book3e_206_tlb_params".h]h)}(hjnh]hIThe “params” field is of type “struct kvm_book3e_206_tlb_params”.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hOThe "array" field points to an array of type "struct kvm_book3e_206_tlb_entry".h]h)}(hOThe "array" field points to an array of type "struct kvm_book3e_206_tlb_entry".h]hWThe “array” field points to an array of type “struct kvm_book3e_206_tlb_entry”.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(h^The array consists of all entries in the first TLB, followed by all entries in the second TLB.h]h)}(h^The array consists of all entries in the first TLB, followed by all entries in the second TLB.h]h^The array consists of all entries in the first TLB, followed by all entries in the second TLB.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(h~Within a TLB, entries are ordered first by increasing set number. Within a set, entries are ordered by way (increasing ESEL).h]h)}(h~Within a TLB, entries are ordered first by increasing set number. Within a set, entries are ordered by way (increasing ESEL).h]h~Within a TLB, entries are ordered first by increasing set number. Within a set, entries are ordered by way (increasing ESEL).}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hThe hash for determining set number in TLB0 is: (MAS2 >> 12) & (num_sets - 1) where "num_sets" is the tlb_sizes[] value divided by the tlb_ways[] value.h]h)}(hThe hash for determining set number in TLB0 is: (MAS2 >> 12) & (num_sets - 1) where "num_sets" is the tlb_sizes[] value divided by the tlb_ways[] value.h]hThe hash for determining set number in TLB0 is: (MAS2 >> 12) & (num_sets - 1) where “num_sets” is the tlb_sizes[] value divided by the tlb_ways[] value.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj oubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hjThe tsize field of mas1 shall be set to 4K on TLB0, even though the hardware ignores this value for TLB0. h]h)}(hiThe tsize field of mas1 shall be set to 4K on TLB0, even though the hardware ignores this value for TLB0.h]hiThe tsize field of mas1 shall be set to 4K on TLB0, even though the hardware ignores this value for TLB0.}(hj(ohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$oubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjnubah}(h]h ]h"]h$]h&]uh1j hhhMhjmhhubeh}(h]kvm-cap-sw-tlbah ]h"]6.3 kvm_cap_sw_tlbah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h6.4 KVM_CAP_S390_CSS_SUPPORTh]h6.4 KVM_CAP_S390_CSS_SUPPORT}(hjSohhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPohhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjgohhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjdohhhKubj)}(hs390h]h)}(hjwoh]hs390}(hjyohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjuoubah}(h]h ]h"]h$]h&]uh1jhjdoubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjaohhubjx)}(hhh](j})}(hTargeth]hTarget}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(hvcpuh]h)}(hjoh]hvcpu}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjaohhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(hnoneh]h)}(hjoh]hnone}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjaohhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjohhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjoubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjaohhubeh}(h]h ]h"]h$]h&]uh1jrhjPohhhhhM ubh)}(hIThis capability enables support for handling of channel I/O instructions.h]hIThis capability enables support for handling of channel I/O instructions.}(hj#phhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPohhubh)}(hTEST PENDING INTERRUPTION and the interrupt portion of TEST SUBCHANNEL are handled in-kernel, while the other I/O instructions are passed to userspace.h]hTEST PENDING INTERRUPTION and the interrupt portion of TEST SUBCHANNEL are handled in-kernel, while the other I/O instructions are passed to userspace.}(hj1phhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPohhubh)}(h]When this capability is enabled, KVM_EXIT_S390_TSCH will occur on TEST SUBCHANNEL intercepts.h]h]When this capability is enabled, KVM_EXIT_S390_TSCH will occur on TEST SUBCHANNEL intercepts.}(hj?phhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPohhubh)}(hdNote that even though this capability is enabled per-vcpu, the complete virtual machine is affected.h]hdNote that even though this capability is enabled per-vcpu, the complete virtual machine is affected.}(hjMphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjPohhubeh}(h]kvm-cap-s390-css-supportah ]h"]6.4 kvm_cap_s390_css_supportah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h6.5 KVM_CAP_PPC_EPRh]h6.5 KVM_CAP_PPC_EPR}(hjfphhhNhNubah}(h]h ]h"]h$]h&]uh1hhjcphhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjzphhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjwphhhKubj)}(hppch]h)}(hjph]hppc}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1jhjwpubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjtphhubjx)}(hhh](j})}(hTargeth]hTarget}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjphhhKubj)}(hvcpuh]h)}(hjph]hvcpu}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjtphhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjphhhKubj)}(h4args[0] defines whether the proxy facility is activeh]h)}(hjph]h4args[0] defines whether the proxy facility is active}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1jhjpubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjtphhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjtphhubeh}(h]h ]h"]h$]h&]uh1jrhjcphhhhhMubh)}(hcThis capability enables or disables the delivery of interrupts through the external proxy facility.h]hcThis capability enables or disables the delivery of interrupts through the external proxy facility.}(hj6qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjcphhubh)}(hWhen enabled (args[0] != 0), every time the guest gets an external interrupt delivered, it automatically exits into user space with a KVM_EXIT_EPR exit to receive the topmost interrupt vector.h]hWhen enabled (args[0] != 0), every time the guest gets an external interrupt delivered, it automatically exits into user space with a KVM_EXIT_EPR exit to receive the topmost interrupt vector.}(hjDqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjcphhubh)}(hMWhen disabled (args[0] == 0), behavior is as if this facility is unsupported.h]hMWhen disabled (args[0] == 0), behavior is as if this facility is unsupported.}(hjRqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hjcphhubh)}(h8When this capability is enabled, KVM_EXIT_EPR can occur.h]h8When this capability is enabled, KVM_EXIT_EPR can occur.}(hj`qhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hjcphhubeh}(h]kvm-cap-ppc-eprah ]h"]6.5 kvm_cap_ppc_eprah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h6.6 KVM_CAP_IRQ_MPICh]h6.6 KVM_CAP_IRQ_MPIC}(hjyqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjvqhhhhhM.ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(hppch]h)}(hjqh]hppc}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM0hjqhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(hLargs[0] is the MPIC device fd; args[1] is the MPIC CPU number for this vcpu h]h)}(hKargs[0] is the MPIC device fd; args[1] is the MPIC CPU number for this vcpuh]hKargs[0] is the MPIC device fd; args[1] is the MPIC CPU number for this vcpu}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hjqubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM1hjqhhubeh}(h]h ]h"]h$]h&]uh1jrhjvqhhhhhM0ubh)}(h>This capability connects the vcpu to an in-kernel MPIC device.h]h>This capability connects the vcpu to an in-kernel MPIC device.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4hjvqhhubeh}(h]kvm-cap-irq-mpicah ]h"]6.6 kvm_cap_irq_mpicah$]h&]uh1hhjUjhhhhhM.ubh)}(hhh](h)}(h6.7 KVM_CAP_IRQ_XICSh]h6.7 KVM_CAP_IRQ_XICS}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhM7ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjrhhhKubj)}(hppch]h)}(hj*rh]hppc}(hj,rhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj(rubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jwhhhM9hjrhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjHrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjErhhhKubj)}(hvcpuh]h)}(hjXrh]hvcpu}(hjZrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hjVrubah}(h]h ]h"]h$]h&]uh1jhjErubeh}(h]h ]h"]h$]h&]uh1jwhhhM:hjrhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjvrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjsrhhhKubj)}(hXargs[0] is the XICS device fd; args[1] is the XICS CPU number (server ID) for this vcpu h]h)}(hWargs[0] is the XICS device fd; args[1] is the XICS CPU number (server ID) for this vcpuh]hWargs[0] is the XICS device fd; args[1] is the XICS CPU number (server ID) for this vcpu}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjrubah}(h]h ]h"]h$]h&]uh1jhjsrubeh}(h]h ]h"]h$]h&]uh1jwhhhM;hjrhhubeh}(h]h ]h"]h$]h&]uh1jrhjrhhhhhM9ubh)}(h>This capability connects the vcpu to an in-kernel XICS device.h]h>This capability connects the vcpu to an in-kernel XICS device.}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hjrhhubeh}(h]kvm-cap-irq-xicsah ]h"]6.7 kvm_cap_irq_xicsah$]h&]uh1hhjUjhhhhhM7ubh)}(hhh](h)}(h6.8 KVM_CAP_S390_IRQCHIPh]h6.8 KVM_CAP_S390_IRQCHIP}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhMAubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjrhhhKubj)}(hs390h]h)}(hjrh]hs390}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMChjrubah}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]uh1jwhhhMChjrhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjshhhKubj)}(hvmh]h)}(hjsh]hvm}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMDhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jwhhhMDhjrhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj1shhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj.shhhKubj)}(hnone h]h)}(hnoneh]hnone}(hjCshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhj?subah}(h]h ]h"]h$]h&]uh1jhj.subeh}(h]h ]h"]h$]h&]uh1jwhhhMEhjrhhubeh}(h]h ]h"]h$]h&]uh1jrhjrhhhhhMCubh)}(hnThis capability enables the in-kernel irqchip for s390. Please refer to "4.24 KVM_CREATE_IRQCHIP" for details.h]hrThis capability enables the in-kernel irqchip for s390. Please refer to “4.24 KVM_CREATE_IRQCHIP” for details.}(hjcshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjrhhubeh}(h]kvm-cap-s390-irqchipah ]h"]6.8 kvm_cap_s390_irqchipah$]h&]uh1hhjUjhhhhhMAubh)}(hhh](h)}(h6.9 KVM_CAP_MIPS_FPUh]h6.9 KVM_CAP_MIPS_FPU}(hj|shhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyshhhhhMKubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjshhhKubj)}(hmipsh]h)}(hjsh]hmips}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jwhhhMMhjshhubjx)}(hhh](j})}(hTargeth]hTarget}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjshhhKubj)}(hvcpuh]h)}(hjsh]hvcpu}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jwhhhMNhjshhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjshhhKubj)}(h2args[0] is reserved for future use (should be 0). h]h)}(h1args[0] is reserved for future use (should be 0).h]h1args[0] is reserved for future use (should be 0).}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjsubah}(h]h ]h"]h$]h&]uh1jhjsubeh}(h]h ]h"]h$]h&]uh1jwhhhMOhjshhubeh}(h]h ]h"]h$]h&]uh1jrhjyshhhhhMMubh)}(hXThis capability allows the use of the host Floating Point Unit by the guest. It allows the Config1.FP bit to be set to enable the FPU in the guest. Once this is done the ``KVM_REG_MIPS_FPR_*`` and ``KVM_REG_MIPS_FCR_*`` registers can be accessed (depending on the current guest FPU register mode), and the Status.FR, Config5.FRE bits are accessible via the KVM API and also from the guest, depending on them being supported by the FPU.h](hThis capability allows the use of the host Floating Point Unit by the guest. It allows the Config1.FP bit to be set to enable the FPU in the guest. Once this is done the }(hjthhhNhNubj)}(h``KVM_REG_MIPS_FPR_*``h]hKVM_REG_MIPS_FPR_*}(hj&thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh and }(hjthhhNhNubj)}(h``KVM_REG_MIPS_FCR_*``h]hKVM_REG_MIPS_FCR_*}(hj8thhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh registers can be accessed (depending on the current guest FPU register mode), and the Status.FR, Config5.FRE bits are accessible via the KVM API and also from the guest, depending on them being supported by the FPU.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMQhjyshhubeh}(h]kvm-cap-mips-fpuah ]h"]6.9 kvm_cap_mips_fpuah$]h&]uh1hhjUjhhhhhMKubh)}(hhh](h)}(h6.10 KVM_CAP_MIPS_MSAh]h6.10 KVM_CAP_MIPS_MSA}(hj[thhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXthhhhhMYubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjothhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjlthhhKubj)}(hmipsh]h)}(hjth]hmips}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj}tubah}(h]h ]h"]h$]h&]uh1jhjltubeh}(h]h ]h"]h$]h&]uh1jwhhhM[hjithhubjx)}(hhh](j})}(hTargeth]hTarget}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjthhhKubj)}(hvcpuh]h)}(hjth]hvcpu}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jwhhhM\hjithhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjthhhKubj)}(h2args[0] is reserved for future use (should be 0). h]h)}(h1args[0] is reserved for future use (should be 0).h]h1args[0] is reserved for future use (should be 0).}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjtubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jwhhhM]hjithhubeh}(h]h ]h"]h$]h&]uh1jrhjXthhhhhM[ubh)}(hXTThis capability allows the use of the MIPS SIMD Architecture (MSA) by the guest. It allows the Config3.MSAP bit to be set to enable the use of MSA by the guest. Once this is done the ``KVM_REG_MIPS_VEC_*`` and ``KVM_REG_MIPS_MSA_*`` registers can be accessed, and the Config5.MSAEn bit is accessible via the KVM API and also from the guest.h](hThis capability allows the use of the MIPS SIMD Architecture (MSA) by the guest. It allows the Config3.MSAP bit to be set to enable the use of MSA by the guest. Once this is done the }(hjthhhNhNubj)}(h``KVM_REG_MIPS_VEC_*``h]hKVM_REG_MIPS_VEC_*}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubh and }(hjthhhNhNubj)}(h``KVM_REG_MIPS_MSA_*``h]hKVM_REG_MIPS_MSA_*}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjtubhl registers can be accessed, and the Config5.MSAEn bit is accessible via the KVM API and also from the guest.}(hjthhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM_hjXthhubeh}(h]kvm-cap-mips-msaah ]h"]6.10 kvm_cap_mips_msaah$]h&]uh1hhjUjhhhhhMYubh)}(hhh](h)}(h6.74 KVM_CAP_SYNC_REGSh]h6.74 KVM_CAP_SYNC_REGS}(hj:uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7uhhhhhMfubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjNuhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKuhhhKubj)}(h s390, x86h]h)}(hj^uh]h s390, x86}(hj`uhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhj\uubah}(h]h ]h"]h$]h&]uh1jhjKuubeh}(h]h ]h"]h$]h&]uh1jwhhhMhhjHuhhubjx)}(hhh](j})}(hTargeth]hTarget}(hj|uhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyuhhhKubj)}(hs390: always enabled, x86: vcpuh]h)}(hjuh]hs390: always enabled, x86: vcpu}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihjuubah}(h]h ]h"]h$]h&]uh1jhjyuubeh}(h]h ]h"]h$]h&]uh1jwhhhMihjHuhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjuhhhKubj)}(hnoneh]h)}(hjuh]hnone}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jwhhhMjhjHuhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjuhhhKubj)}(hx86: KVM_CHECK_EXTENSION returns a bit-array indicating which register sets are supported (bitfields defined in arch/x86/include/uapi/asm/kvm.h). h]h)}(hx86: KVM_CHECK_EXTENSION returns a bit-array indicating which register sets are supported (bitfields defined in arch/x86/include/uapi/asm/kvm.h).h]hx86: KVM_CHECK_EXTENSION returns a bit-array indicating which register sets are supported (bitfields defined in arch/x86/include/uapi/asm/kvm.h).}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjuubah}(h]h ]h"]h$]h&]uh1jhjuubeh}(h]h ]h"]h$]h&]uh1jwhhhMkhjHuhhubeh}(h]h ]h"]h$]h&]uh1jrhj7uhhhhhMhubh)}(hXAs described above in the kvm_sync_regs struct info in section :ref:`kvm_run`, KVM_CAP_SYNC_REGS "allow[s] userspace to access certain guest registers without having to call SET/GET_*REGS". This reduces overhead by eliminating repeated ioctl calls for setting and/or getting register values. This is particularly important when userspace is making synchronous guest state modifications, e.g. when emulating and/or intercepting instructions in userspace.h](h?As described above in the kvm_sync_regs struct info in section }(hj vhhhNhNubh)}(h:ref:`kvm_run`h]j)}(hjvh]hkvm_run}(hjvhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjvubah}(h]h ]h"]h$]h&]refdocj refdomainj vreftyperef refexplicitrefwarnjkvm_runuh1hhhhMohj vubhX|, KVM_CAP_SYNC_REGS “allow[s] userspace to access certain guest registers without having to call SET/GET_*REGS”. This reduces overhead by eliminating repeated ioctl calls for setting and/or getting register values. This is particularly important when userspace is making synchronous guest state modifications, e.g. when emulating and/or intercepting instructions in userspace.}(hj vhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMohj7uhhubh)}(h4For s390 specifics, please refer to the source code.h]h4For s390 specifics, please refer to the source code.}(hjThis capability connects the vcpu to an in-kernel XIVE device.h]h>This capability connects the vcpu to an in-kernel XIVE device.}(hjvwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjvhhubeh}(h]kvm-cap-ppc-irq-xiveah ]h"]6.75 kvm_cap_ppc_irq_xiveah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h6.76 KVM_CAP_HYPERV_SYNICh]h6.76 KVM_CAP_HYPERV_SYNIC}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjwhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjwhhhKubj)}(hx86h]h)}(hjwh]hx86}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjwhhhKubj)}(hvcpu h]h)}(hvcpuh]hvcpu}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwubah}(h]h ]h"]h$]h&]uh1jhjwubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjwhhubeh}(h]h ]h"]h$]h&]uh1jrhjwhhhhhMubh)}(hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel has an implementation of the Hyper-V Synthetic interrupt controller(SynIC). Hyper-V SynIC is used to support Windows Hyper-V based guest paravirt drivers(VMBus).h]hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel has an implementation of the Hyper-V Synthetic interrupt controller(SynIC). Hyper-V SynIC is used to support Windows Hyper-V based guest paravirt drivers(VMBus).}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwhhubh)}(hXIn order to use SynIC, it has to be activated by setting this capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this will disable the use of APIC hardware virtualization even if supported by the CPU, as it's incompatible with SynIC auto-EOI behavior.h]hXIn order to use SynIC, it has to be activated by setting this capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this will disable the use of APIC hardware virtualization even if supported by the CPU, as it’s incompatible with SynIC auto-EOI behavior.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjwhhubeh}(h]kvm-cap-hyperv-synicah ]h"]6.76 kvm_cap_hyperv_synicah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h6.77 KVM_CAP_HYPERV_SYNIC2h]h6.77 KVM_CAP_HYPERV_SYNIC2}(hj*xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'xhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj>xhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj;xhhhKubj)}(hx86h]h)}(hjNxh]hx86}(hjPxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLxubah}(h]h ]h"]h$]h&]uh1jhj;xubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj8xhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjlxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjixhhhKubj)}(hvcpu h]h)}(hvcpuh]hvcpu}(hj~xhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjzxubah}(h]h ]h"]h$]h&]uh1jhjixubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj8xhhubeh}(h]h ]h"]h$]h&]uh1jrhj'xhhhhhMubh)}(hXThis capability enables a newer version of Hyper-V Synthetic interrupt controller (SynIC). The only difference with KVM_CAP_HYPERV_SYNIC is that KVM doesn't clear SynIC message and event flags pages when they are enabled by writing to the respective MSRs.h]hXThis capability enables a newer version of Hyper-V Synthetic interrupt controller (SynIC). The only difference with KVM_CAP_HYPERV_SYNIC is that KVM doesn’t clear SynIC message and event flags pages when they are enabled by writing to the respective MSRs.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'xhhubeh}(h]kvm-cap-hyperv-synic2ah ]h"]6.77 kvm_cap_hyperv_synic2ah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h#6.78 KVM_CAP_HYPERV_DIRECT_TLBFLUSHh]h#6.78 KVM_CAP_HYPERV_DIRECT_TLBFLUSH}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjxhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxhhhKubj)}(hx86h]h)}(hjxh]hx86}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjxubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjxhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjxhhhKubj)}(hvcpu h]h)}(hvcpuh]hvcpu}(hj yhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyubah}(h]h ]h"]h$]h&]uh1jhjxubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjxhhubeh}(h]h ]h"]h$]h&]uh1jrhjxhhhhhMubh)}(hXmThis capability indicates that KVM running on top of Hyper-V hypervisor enables Direct TLB flush for its guests meaning that TLB flush hypercalls are handled by Level 0 hypervisor (Hyper-V) bypassing KVM. Due to the different ABI for hypercall parameters between Hyper-V and KVM, enabling this capability effectively disables all hypercall handling by KVM (as some KVM hypercall may be mistakenly treated as TLB flush hypercalls by Hyper-V) so userspace should disable KVM identification in CPUID and only exposes Hyper-V identification. In this case, guest thinks it's running on Hyper-V and only use Hyper-V hypercalls.h]hXoThis capability indicates that KVM running on top of Hyper-V hypervisor enables Direct TLB flush for its guests meaning that TLB flush hypercalls are handled by Level 0 hypervisor (Hyper-V) bypassing KVM. Due to the different ABI for hypercall parameters between Hyper-V and KVM, enabling this capability effectively disables all hypercall handling by KVM (as some KVM hypercall may be mistakenly treated as TLB flush hypercalls by Hyper-V) so userspace should disable KVM identification in CPUID and only exposes Hyper-V identification. In this case, guest thinks it’s running on Hyper-V and only use Hyper-V hypercalls.}(hj+yhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjxhhubeh}(h]kvm-cap-hyperv-direct-tlbflushah ]h"]#6.78 kvm_cap_hyperv_direct_tlbflushah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h!6.79 KVM_CAP_HYPERV_ENFORCE_CPUIDh]h!6.79 KVM_CAP_HYPERV_ENFORCE_CPUID}(hjDyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAyhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjXyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUyhhhKubj)}(hx86h]h)}(hjhyh]hx86}(hjjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfyubah}(h]h ]h"]h$]h&]uh1jhjUyubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRyhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hvcpu h]h)}(hvcpuh]hvcpu}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjRyhhubeh}(h]h ]h"]h$]h&]uh1jrhjAyhhhhhMubh)}(hX)When enabled, KVM will disable emulated Hyper-V features provided to the guest according to the bits Hyper-V CPUID feature leaves. Otherwise, all currently implemented Hyper-V features are provided unconditionally when Hyper-V identification is set in the HYPERV_CPUID_INTERFACE (0x40000001) leaf.h]hX)When enabled, KVM will disable emulated Hyper-V features provided to the guest according to the bits Hyper-V CPUID feature leaves. Otherwise, all currently implemented Hyper-V features are provided unconditionally when Hyper-V identification is set in the HYPERV_CPUID_INTERFACE (0x40000001) leaf.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAyhhubeh}(h]kvm-cap-hyperv-enforce-cpuidah ]h"]!6.79 kvm_cap_hyperv_enforce_cpuidah$]h&]uh1hhjUjhhhhhMubh)}(hhh](h)}(h%6.80 KVM_CAP_ENFORCE_PV_FEATURE_CPUIDh]h%6.80 KVM_CAP_ENFORCE_PV_FEATURE_CPUID}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjyhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hx86h]h)}(hjyh]hx86}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjyhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjzhhhKubj)}(hvcpu h]h)}(hvcpuh]hvcpu}(hj%zhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!zubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjyhhubeh}(h]h ]h"]h$]h&]uh1jrhjyhhhhhMubh)}(hX When enabled, KVM will disable paravirtual features provided to the guest according to the bits in the KVM_CPUID_FEATURES CPUID leaf (0x40000001). Otherwise, a guest may use the paravirtual features regardless of what has actually been exposed through the CPUID leaf.h]hX When enabled, KVM will disable paravirtual features provided to the guest according to the bits in the KVM_CPUID_FEATURES CPUID leaf (0x40000001). Otherwise, a guest may use the paravirtual features regardless of what has actually been exposed through the CPUID leaf.}(hjEzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjyhhubjT)}(h.. _KVM_CAP_DIRTY_LOG_RING:h]h}(h]h ]h"]h$]h&]j_kvm-cap-dirty-log-ringuh1jShMhjyhhhhubjT)}(h.. _cap_enable_vm:h]h}(h]h ]h"]h$]h&]j_ cap-enable-vmuh1jShMhjyhhhhj}kvm_cap_dirty_log_ringjSzsj}j]zjSzsubeh}(h] kvm-cap-enforce-pv-feature-cpuidah ]h"]%6.80 kvm_cap_enforce_pv_feature_cpuidah$]h&]uh1hhjUjhhhhhMubeh}(h]()capabilities-that-can-be-enabled-on-vcpusjAjeh ]h"](,6. capabilities that can be enabled on vcpus cap_enableeh$]h&]uh1hhhhhhhhMj}jzzj7jsj}jAjj7jsubh)}(hhh](h)}(h*7. Capabilities that can be enabled on VMsh]h*7. Capabilities that can be enabled on VMs}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhhhhhMubh)}(hThere are certain capabilities that change the behavior of the virtual machine when enabled. To enable them, please see section :ref:`KVM_ENABLE_CAP`. Below you can find a list of capabilities and what their effect on the VM is when enabling them.h](hThere are certain capabilities that change the behavior of the virtual machine when enabled. To enable them, please see section }(hjzhhhNhNubh)}(h:ref:`KVM_ENABLE_CAP`h]j)}(hjzh]hKVM_ENABLE_CAP}(hjzhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjzubah}(h]h ]h"]h$]h&]refdocj refdomainjzreftyperef refexplicitrefwarnjkvm_enable_capuh1hhhhMhjzubhb. Below you can find a list of capabilities and what their effect on the VM is when enabling them.}(hjzhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjzhhubh)}(hAThe following information is provided along with the description:h]hAThe following information is provided along with the description:}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjzhhubj )}(hX@Architectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. Parameters: what parameters are accepted by the capability. Returns: the return value. General error numbers (EBADF, ENOMEM, EINVAL) are not detailed, but errors with specific meanings are. h]j )}(hhh](j)}(hjArchitectures: which instruction set architectures provide this ioctl. x86 includes both i386 and x86_64. h](j)}(hArchitectures:h]hArchitectures:}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjzubj%)}(hhh]h)}(hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.h]hZwhich instruction set architectures provide this ioctl. x86 includes both i386 and x86_64.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjzubah}(h]h ]h"]h$]h&]uh1j$hjzubeh}(h]h ]h"]h$]h&]uh1jhhhMhjzubj)}(hrun::h]hVBefore exiting to userspace, kvm handlers should fill in s390_stsi field of vcpu->run:}(hjq~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj}hhubj8)}(hstruct { __u64 addr; __u8 ar; __u8 reserved; __u8 fc; __u8 sel1; __u16 sel2; } s390_stsi; @addr - guest address of STSI SYSIB @fc - function code @sel1 - selector 1 @sel2 - selector 2 @ar - access register numberh]hstruct { __u64 addr; __u8 ar; __u8 reserved; __u8 fc; __u8 sel1; __u16 sel2; } s390_stsi; @addr - guest address of STSI SYSIB @fc - function code @sel1 - selector 1 @sel2 - selector 2 @ar - access register number}hj~sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM>hj}hhubh)}(h9KVM handlers should exit to userspace with rc = -EREMOTE.h]h9KVM handlers should exit to userspace with rc = -EREMOTE.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj}hhubeh}(h]kvm-cap-s390-user-stsiah ]h"]7.4 kvm_cap_s390_user_stsiah$]h&]uh1hhjzhhhhhM2ubh)}(hhh](h)}(h7.5 KVM_CAP_SPLIT_IRQCHIPh]h7.5 KVM_CAP_SPLIT_IRQCHIP}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhhhMPubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(hx86h]h)}(hj~h]hx86}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhMRhj~hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(h9args[0] - number of routes reserved for userspace IOAPICsh]h)}(hj~h]h9args[0] - number of routes reserved for userspace IOAPICs}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj~ubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhMShj~hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -1 on error h]h)}(h0 on success, -1 on errorh]h0 on success, -1 on error}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThj$ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMThj~hhubeh}(h]h ]h"]h$]h&]uh1jrhj~hhhhhMRubh)}(hCreate a local apic for each processor in the kernel. This can be used instead of KVM_CREATE_IRQCHIP if the userspace VMM wishes to emulate the IOAPIC and PIC (and also the PIT, even though this has to be enabled separately).h]hCreate a local apic for each processor in the kernel. This can be used instead of KVM_CREATE_IRQCHIP if the userspace VMM wishes to emulate the IOAPIC and PIC (and also the PIT, even though this has to be enabled separately).}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj~hhubh)}(hX]This capability also enables in kernel routing of interrupt requests; when KVM_CAP_SPLIT_IRQCHIP only routes of KVM_IRQ_ROUTING_MSI type are used in the IRQ routing table. The first args[0] MSI routes are reserved for the IOAPIC pins. Whenever the LAPIC receives an EOI for these routes, a KVM_EXIT_IOAPIC_EOI vmexit will be reported to userspace.h]hX]This capability also enables in kernel routing of interrupt requests; when KVM_CAP_SPLIT_IRQCHIP only routes of KVM_IRQ_ROUTING_MSI type are used in the IRQ routing table. The first args[0] MSI routes are reserved for the IOAPIC pins. Whenever the LAPIC receives an EOI for these routes, a KVM_EXIT_IOAPIC_EOI vmexit will be reported to userspace.}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hj~hhubh)}(hAs with ``KVM_CREATE_IRQCHIP``, subsequent vcpu creation may install a private memory slot at the APIC base address (0xfee00000) that must not overlap user memory regions. See ``KVM_CREATE_IRQCHIP`` for details.h](hAs with }(hjdhhhNhNubj)}(h``KVM_CREATE_IRQCHIP``h]hKVM_CREATE_IRQCHIP}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh, subsequent vcpu creation may install a private memory slot at the APIC base address (0xfee00000) that must not overlap user memory regions. See }(hjdhhhNhNubj)}(h``KVM_CREATE_IRQCHIP``h]hKVM_CREATE_IRQCHIP}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh for details.}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMahj~hhubh)}(hFails if VCPU has already been created, or if the irqchip is already in the kernel (i.e. KVM_CREATE_IRQCHIP has already been called).h]hFails if VCPU has already been created, or if the irqchip is already in the kernel (i.e. KVM_CREATE_IRQCHIP has already been called).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehj~hhubeh}(h]kvm-cap-split-irqchipah ]h"]7.5 kvm_cap_split_irqchipah$]h&]uh1hhjzhhhhhMPubh)}(hhh](h)}(h7.6 KVM_CAP_S390_RIh]h7.6 KVM_CAP_S390_RI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMiubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMkhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMlhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMkubh)}(hAllows use of runtime-instrumentation introduced with zEC12 processor. Will return -EINVAL if the machine does not support runtime-instrumentation. Will return -EBUSY if a VCPU has already been created.h]hAllows use of runtime-instrumentation introduced with zEC12 processor. Will return -EINVAL if the machine does not support runtime-instrumentation. Will return -EBUSY if a VCPU has already been created.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhjhhubeh}(h]kvm-cap-s390-riah ]h"]7.6 kvm_cap_s390_riah$]h&]uh1hhjzhhhhhMiubh)}(hhh](h)}(h7.7 KVM_CAP_X2APIC_APIh]h7.7 KVM_CAP_X2APIC_API}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMsubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hx86h]h)}(hj`h]hx86}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMuhj^ubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhMuhjJhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj{hhhKubj)}(h)args[0] - features that should be enabledh]h)}(hjh]h)args[0] - features that should be enabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMvhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jwhhhMvhjJhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h=0 on success, -EINVAL when args[0] contains invalid features h]h)}(h<0 on success, -EINVAL when args[0] contains invalid featuresh]h<0 on success, -EINVAL when args[0] contains invalid features}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMwhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMwhjJhhubeh}(h]h ]h"]h$]h&]uh1jrhj9hhhhhMuubh)}(h$Valid feature flags in args[0] are::h]h#Valid feature flags in args[0] are:}(hjހhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj9hhubj8)}(hX'#define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) #define KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST (1ULL << 2) #define KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST (1ULL << 3)h]hX'#define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) #define KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST (1ULL << 2) #define KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST (1ULL << 3)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM{hj9hhubh)}(hEnabling KVM_X2APIC_API_USE_32BIT_IDS changes the behavior of KVM_SET_GSI_ROUTING, KVM_SIGNAL_MSI, KVM_SET_LAPIC, and KVM_GET_LAPIC, allowing the use of 32-bit APIC IDs. See KVM_CAP_X2APIC_API in their respective sections.h]hEnabling KVM_X2APIC_API_USE_32BIT_IDS changes the behavior of KVM_SET_GSI_ROUTING, KVM_SIGNAL_MSI, KVM_SET_LAPIC, and KVM_GET_LAPIC, allowing the use of 32-bit APIC IDs. See KVM_CAP_X2APIC_API in their respective sections.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hXIKVM_X2APIC_API_DISABLE_BROADCAST_QUIRK must be enabled for x2APIC to work in logical mode or with more than 255 VCPUs. Otherwise, KVM treats 0xff as a broadcast even in x2APIC mode in order to support physical x2APIC without interrupt remapping. This is undesirable in logical mode, where 0xff represents CPUs 0-7 in cluster 0.h]hXIKVM_X2APIC_API_DISABLE_BROADCAST_QUIRK must be enabled for x2APIC to work in logical mode or with more than 255 VCPUs. Otherwise, KVM treats 0xff as a broadcast even in x2APIC mode in order to support physical x2APIC without interrupt remapping. This is undesirable in logical mode, where 0xff represents CPUs 0-7 in cluster 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hXISetting KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST instructs KVM to enable Suppress EOI Broadcasts. KVM will advertise support for Suppress EOI Broadcast to the guest and suppress LAPIC EOI broadcasts when the guest sets the Suppress EOI Broadcast bit in the SPIV register. This flag is supported only when using a split IRQCHIP.h]hXISetting KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST instructs KVM to enable Suppress EOI Broadcasts. KVM will advertise support for Suppress EOI Broadcast to the guest and suppress LAPIC EOI broadcasts when the guest sets the Suppress EOI Broadcast bit in the SPIV register. This flag is supported only when using a split IRQCHIP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hSetting KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST disables support for Suppress EOI Broadcasts entirely, i.e. instructs KVM to NOT advertise support to the guest.h]hSetting KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST disables support for Suppress EOI Broadcasts entirely, i.e. instructs KVM to NOT advertise support to the guest.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hX|Modern VMMs should either enable KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST or KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST. If not, legacy quirky behavior will be used by KVM: in split IRQCHIP mode, KVM will advertise support for Suppress EOI Broadcasts but not actually suppress EOI broadcasts; for in-kernel IRQCHIP mode, KVM will not advertise support for Suppress EOI Broadcasts.h]hX|Modern VMMs should either enable KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST or KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST. If not, legacy quirky behavior will be used by KVM: in split IRQCHIP mode, KVM will advertise support for Suppress EOI Broadcasts but not actually suppress EOI broadcasts; for in-kernel IRQCHIP mode, KVM will not advertise support for Suppress EOI Broadcasts.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubh)}(hSetting both KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST and KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST will fail with an EINVAL error, as will setting KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST without a split IRCHIP.h]hSetting both KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST and KVM_X2APIC_DISABLE_SUPPRESS_EOI_BROADCAST will fail with an EINVAL error, as will setting KVM_X2APIC_ENABLE_SUPPRESS_EOI_BROADCAST without a split IRCHIP.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubeh}(h]kvm-cap-x2apic-apiah ]h"]7.7 kvm_cap_x2apic_apiah$]h&]uh1hhjzhhhhhMsubh)}(hhh](h)}(h7.8 KVM_CAP_S390_USER_INSTR0h]h7.8 KVM_CAP_S390_USER_INSTR0}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjVhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjjhhhKubj)}(hs390h]h)}(hj}h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj{ubah}(h]h ]h"]h$]h&]uh1jhjjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjghhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjghhubeh}(h]h ]h"]h$]h&]uh1jrhjVhhhhhMubh)}(hX5With this capability enabled, the illegal instruction 0x0000 (2 bytes) will be intercepted and forwarded to user space. User space can use this mechanism e.g. to realize 2-byte software breakpoints. The kernel will not inject an operating exception for these instructions, user space has to take care of that.h]hX5With this capability enabled, the illegal instruction 0x0000 (2 bytes) will be intercepted and forwarded to user space. User space can use this mechanism e.g. to realize 2-byte software breakpoints. The kernel will not inject an operating exception for these instructions, user space has to take care of that.}(hj́hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubh)}(h^This capability can be enabled dynamically even if VCPUs were already created and are running.h]h^This capability can be enabled dynamically even if VCPUs were already created and are running.}(hjہhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjVhhubeh}(h]kvm-cap-s390-user-instr0ah ]h"]7.8 kvm_cap_s390_user_instr0ah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.9 KVM_CAP_S390_GSh]h7.9 KVM_CAP_S390_GS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj3hhhKubj)}(hnoneh]h)}(hjFh]hnone}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjDubah}(h]h ]h"]h$]h&]uh1jhj3ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjahhhKubj)}(hr0 on success; -EINVAL if the machine does not support guarded storage; -EBUSY if a VCPU has already been created. h]h)}(hq0 on success; -EINVAL if the machine does not support guarded storage; -EBUSY if a VCPU has already been created.h]hq0 on success; -EINVAL if the machine does not support guarded storage; -EBUSY if a VCPU has already been created.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjrubah}(h]h ]h"]h$]h&]uh1jhjaubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(h0Allows use of guarded storage for the KVM guest.h]h0Allows use of guarded storage for the KVM guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-cap-s390-gsah ]h"]7.9 kvm_cap_s390_gsah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.10 KVM_CAP_S390_AISh]h7.10 KVM_CAP_S390_AIS}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjÂhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjӂh]hs390}(hjՂhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjтubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMubh)}(hqAllow use of adapter-interruption suppression. :Returns: 0 on success; -EBUSY if a VCPU has already been created.h]hqAllow use of adapter-interruption suppression. :Returns: 0 on success; -EBUSY if a VCPU has already been created.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]kvm-cap-s390-aisah ]h"]7.10 kvm_cap_s390_aisah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.11 KVM_CAP_PPC_SMTh]h7.11 KVM_CAP_PPC_SMT}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hppch]h)}(hj`h]hppc}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^ubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjJhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj{hhhKubj)}(hvsmt_mode, flags h]h)}(hvsmt_mode, flagsh]hvsmt_mode, flags}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjJhhubeh}(h]h ]h"]h$]h&]uh1jrhj9hhhhhMubh)}(hXEnabling this capability on a VM provides userspace with a way to set the desired virtual SMT mode (i.e. the number of virtual CPUs per virtual core). The virtual SMT mode, vsmt_mode, must be a power of 2 between 1 and 8. On POWER8, vsmt_mode must also be no greater than the number of threads per subcore for the host. Currently flags must be 0. A successful call to enable this capability will result in vsmt_mode being returned when the KVM_CAP_PPC_SMT capability is subsequently queried for the VM. This capability is only supported by HV KVM, and can only be set before any VCPUs have been created. The KVM_CAP_PPC_SMT_POSSIBLE capability indicates which virtual SMT modes are available.h]hXEnabling this capability on a VM provides userspace with a way to set the desired virtual SMT mode (i.e. the number of virtual CPUs per virtual core). The virtual SMT mode, vsmt_mode, must be a power of 2 between 1 and 8. On POWER8, vsmt_mode must also be no greater than the number of threads per subcore for the host. Currently flags must be 0. A successful call to enable this capability will result in vsmt_mode being returned when the KVM_CAP_PPC_SMT capability is subsequently queried for the VM. This capability is only supported by HV KVM, and can only be set before any VCPUs have been created. The KVM_CAP_PPC_SMT_POSSIBLE capability indicates which virtual SMT modes are available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9hhubeh}(h]kvm-cap-ppc-smtah ]h"]7.11 kvm_cap_ppc_smtah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.12 KVM_CAP_PPC_FWNMIh]h7.12 KVM_CAP_PPC_FWNMI}(hjɃhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjƃhhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj݃hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjڃhhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjڃubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj׃hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhj׃hhubeh}(h]h ]h"]h$]h&]uh1jrhjƃhhhhhMubh)}(hX6With this capability a machine check exception in the guest address space will cause KVM to exit the guest with NMI exit reason. This enables QEMU to build error log and branch to guest kernel registered machine check handling routine. Without this capability KVM will branch to guests' 0x200 interrupt vector.h]hX8With this capability a machine check exception in the guest address space will cause KVM to exit the guest with NMI exit reason. This enables QEMU to build error log and branch to guest kernel registered machine check handling routine. Without this capability KVM will branch to guests’ 0x200 interrupt vector.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjƃhhubeh}(h]kvm-cap-ppc-fwnmiah ]h"]7.12 kvm_cap_ppc_fwnmiah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.13 KVM_CAP_X86_DISABLE_EXITSh]h7.13 KVM_CAP_X86_DISABLE_EXITS}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhMubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjghhhKubj)}(hx86h]h)}(hjzh]hx86}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjxubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h(args[0] defines which exits are disabledh]h)}(hjh]h(args[0] defines which exits are disabled}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjƄhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjÄhhhKubj)}(hd0 on success, -EINVAL when args[0] contains invalid exits or if any vCPUs have already been created h]h)}(hc0 on success, -EINVAL when args[0] contains invalid exits or if any vCPUs have already been createdh]hc0 on success, -EINVAL when args[0] contains invalid exits or if any vCPUs have already been created}(hj؄hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjԄubah}(h]h ]h"]h$]h&]uh1jhjÄubeh}(h]h ]h"]h$]h&]uh1jwhhhMhjdhhubeh}(h]h ]h"]h$]h&]uh1jrhjShhhhhMubh)}(hValid bits in args[0] are::h]hValid bits in args[0] are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjShhubj8)}(hX#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0) #define KVM_X86_DISABLE_EXITS_HLT (1 << 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2) #define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3) #define KVM_X86_DISABLE_EXITS_APERFMPERF (1 << 4)h]hX#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0) #define KVM_X86_DISABLE_EXITS_HLT (1 << 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2) #define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3) #define KVM_X86_DISABLE_EXITS_APERFMPERF (1 << 4)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMhjShhubh)}(hXcEnabling this capability on a VM provides userspace with a way to no longer intercept some instructions for improved latency in some workloads, and is suggested when vCPUs are associated to dedicated physical CPUs. More bits can be added in the future; userspace can just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable all such vmexits.h]hXcEnabling this capability on a VM provides userspace with a way to no longer intercept some instructions for improved latency in some workloads, and is suggested when vCPUs are associated to dedicated physical CPUs. More bits can be added in the future; userspace can just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable all such vmexits.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjShhubh)}(h=Do not enable KVM_FEATURE_PV_UNHALT if you disable HLT exits.h]h=Do not enable KVM_FEATURE_PV_UNHALT if you disable HLT exits.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjShhubh)}(hXhVirtualizing the ``IA32_APERF`` and ``IA32_MPERF`` MSRs requires more than just disabling APERF/MPERF exits. While both Intel and AMD document strict usage conditions for these MSRs--emphasizing that only the ratio of their deltas over a time interval (T0 to T1) is architecturally defined--simply passing through the MSRs can still produce an incorrect ratio.h](hVirtualizing the }(hj0hhhNhNubj)}(h``IA32_APERF``h]h IA32_APERF}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh and }(hj0hhhNhNubj)}(h``IA32_MPERF``h]h IA32_MPERF}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubhX6 MSRs requires more than just disabling APERF/MPERF exits. While both Intel and AMD document strict usage conditions for these MSRs--emphasizing that only the ratio of their deltas over a time interval (T0 to T1) is architecturally defined--simply passing through the MSRs can still produce an incorrect ratio.}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjShhubh)}(h5This erroneous ratio can occur if, between T0 and T1:h]h5This erroneous ratio can occur if, between T0 and T1:}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjShhubjz)}(hhh](j)}(h4The vCPU thread migrates between logical processors.h]h)}(hjuh]h4The vCPU thread migrates between logical processors.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjsubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(h7Live migration or suspend/resume operations take place.h]h)}(hjh]h7Live migration or suspend/resume operations take place.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(h1Another task shares the vCPU's logical processor.h]h)}(hjh]h3Another task shares the vCPU’s logical processor.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(hAC-states lower than C0 are emulated (e.g., via HLT interception).h]h)}(hjh]hAC-states lower than C0 are emulated (e.g., via HLT interception).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubj)}(h>The guest TSC frequency doesn't match the host TSC frequency. h]h)}(h=The guest TSC frequency doesn't match the host TSC frequency.h]h?The guest TSC frequency doesn’t match the host TSC frequency.}(hjӅhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjυubah}(h]h ]h"]h$]h&]uh1jhjphhhhhNubeh}(h]h ]h"]h$]h&]jjKjhjjuh1jyhjShhhhhM ubh)}(hX.Due to these complexities, KVM does not automatically associate this passthrough capability with the guest CPUID bit, ``CPUID.6:ECX.APERFMPERF[bit 0]``. Userspace VMMs that deem this mechanism adequate for virtualizing the ``IA32_APERF`` and ``IA32_MPERF`` MSRs must set the guest CPUID bit explicitly.h](hvDue to these complexities, KVM does not automatically associate this passthrough capability with the guest CPUID bit, }(hjhhhNhNubj)}(h!``CPUID.6:ECX.APERFMPERF[bit 0]``h]hCPUID.6:ECX.APERFMPERF[bit 0]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubhH. Userspace VMMs that deem this mechanism adequate for virtualizing the }(hjhhhNhNubj)}(h``IA32_APERF``h]h IA32_APERF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h``IA32_MPERF``h]h IA32_MPERF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh. MSRs must set the guest CPUID bit explicitly.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM hjShhubeh}(h]kvm-cap-x86-disable-exitsah ]h"]7.13 kvm_cap_x86_disable_exitsah$]h&]uh1hhjzhhhhhMubh)}(hhh](h)}(h7.14 KVM_CAP_S390_HPAGE_1Mh]h7.14 KVM_CAP_S390_HPAGE_1M}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj9hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjMhhhKubj)}(hs390h]h)}(hj`h]hs390}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj^ubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjJhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj{hhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjJhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EINVAL if hpage module parameter was not set or cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag set h]h)}(h0 on success, -EINVAL if hpage module parameter was not set or cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag seth]h0 on success, -EINVAL if hpage module parameter was not set or cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag set}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjJhhubeh}(h]h ]h"]h$]h&]uh1jrhj9hhhhhM ubh)}(hXOWith this capability the KVM support for memory backing with 1m pages through hugetlbfs can be enabled for a VM. After the capability is enabled, cmma can't be enabled anymore and pfmfi and the storage key interpretation are disabled. If cmma has already been enabled or the hpage module parameter is not set to 1, -EINVAL is returned.h]hXQWith this capability the KVM support for memory backing with 1m pages through hugetlbfs can be enabled for a VM. After the capability is enabled, cmma can’t be enabled anymore and pfmfi and the storage key interpretation are disabled. If cmma has already been enabled or the hpage module parameter is not set to 1, -EINVAL is returned.}(hjކhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj9hhubh)}(hwWhile it is generally possible to create a huge page backed VM without this capability, the VM will not be able to run.h]hwWhile it is generally possible to create a huge page backed VM without this capability, the VM will not be able to run.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj9hhubeh}(h]kvm-cap-s390-hpage-1mah ]h"]7.14 kvm_cap_s390_hpage_1mah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.15 KVM_CAP_MSR_PLATFORM_INFOh]h7.15 KVM_CAP_MSR_PLATFORM_INFO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM# ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hj)h]hx86}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM% hj'ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM% hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjDhhhKubj)}(h1args[0] whether feature should be enabled or not h]h)}(h0args[0] whether feature should be enabled or noth]h0args[0] whether feature should be enabled or not}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM& hjUubah}(h]h ]h"]h$]h&]uh1jhjDubeh}(h]h ]h"]h$]h&]uh1jwhhhM& hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM% ubh)}(hWith this capability, a guest may read the MSR_PLATFORM_INFO MSR. Otherwise, a #GP would be raised when the guest tries to access. Currently, this capability does not enable write permissions of this MSR for the guest.h]hWith this capability, a guest may read the MSR_PLATFORM_INFO MSR. Otherwise, a #GP would be raised when the guest tries to access. Currently, this capability does not enable write permissions of this MSR for the guest.}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM( hjhhubeh}(h]kvm-cap-msr-platform-infoah ]h"]7.15 kvm_cap_msr_platform_infoah$]h&]uh1hhjzhhhhhM# ubh)}(hhh](h)}(h7.16 KVM_CAP_PPC_NESTED_HVh]h7.16 KVM_CAP_PPC_NESTED_HV}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM- ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/ hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM/ hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjԇhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjчhhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0 hjubah}(h]h ]h"]h$]h&]uh1jhjчubeh}(h]h ]h"]h$]h&]uh1jwhhhM0 hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hX0 on success, -EINVAL when the implementation doesn't support nested-HV virtualization. h]h)}(hW0 on success, -EINVAL when the implementation doesn't support nested-HV virtualization.h]hY0 on success, -EINVAL when the implementation doesn’t support nested-HV virtualization.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1 hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM1 hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM/ ubh)}(hXeHV-KVM on POWER9 and later systems allows for "nested-HV" virtualization, which provides a way for a guest VM to run guests that can run using the CPU's supervisor mode (privileged non-hypervisor state). Enabling this capability on a VM depends on the CPU having the necessary functionality and on the facility being enabled with a kvm-hv module parameter.h]hXkHV-KVM on POWER9 and later systems allows for “nested-HV” virtualization, which provides a way for a guest VM to run guests that can run using the CPU’s supervisor mode (privileged non-hypervisor state). Enabling this capability on a VM depends on the CPU having the necessary functionality and on the facility being enabled with a kvm-hv module parameter.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4 hjhhubeh}(h]kvm-cap-ppc-nested-hvah ]h"]7.16 kvm_cap_ppc_nested_hvah$]h&]uh1hhjzhhhhhM- ubh)}(hhh](h)}(h7.17 KVM_CAP_EXCEPTION_PAYLOADh]h7.17 KVM_CAP_EXCEPTION_PAYLOAD}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJhhhhhM< ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj^hhhKubj)}(hx86h]h)}(hjqh]hx86}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM> hjoubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jwhhhM> hj[hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h1args[0] whether feature should be enabled or not h]h)}(h0args[0] whether feature should be enabled or noth]h0args[0] whether feature should be enabled or not}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM? hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM? hj[hhubeh}(h]h ]h"]h$]h&]uh1jrhjJhhhhhM> ubh)}(hXWith this capability enabled, CR2 will not be modified prior to the emulated VM-exit when L1 intercepts a #PF exception that occurs in L2. Similarly, for kvm-intel only, DR6 will not be modified prior to the emulated VM-exit when L1 intercepts a #DB exception that occurs in L2. As a result, when KVM_GET_VCPU_EVENTS reports a pending #PF (or #DB) exception for L2, exception.has_payload will be set and the faulting address (or the new DR6 bits*) will be reported in the exception_payload field. Similarly, when userspace injects a #PF (or #DB) into L2 using KVM_SET_VCPU_EVENTS, it is expected to set exception.has_payload and to put the faulting address - or the new DR6 bits\ [#]_ - in the exception_payload field.h](hXWith this capability enabled, CR2 will not be modified prior to the emulated VM-exit when L1 intercepts a #PF exception that occurs in L2. Similarly, for kvm-intel only, DR6 will not be modified prior to the emulated VM-exit when L1 intercepts a #DB exception that occurs in L2. As a result, when KVM_GET_VCPU_EVENTS reports a pending #PF (or #DB) exception for L2, exception.has_payload will be set and the faulting address (or the new DR6 bits*) will be reported in the exception_payload field. Similarly, when userspace injects a #PF (or #DB) into L2 using KVM_SET_VCPU_EVENTS, it is expected to set exception.has_payload and to put the faulting address - or the new DR6 bits }(hjhhhNhNubj)}(h[#]_h]h3}(hjɈhhhNhNubah}(h]id22ah ]h"]h$]h&]autoKj_id23jjuh1jhjjKubh" - in the exception_payload field.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMA hjJhhubh)}(hThis capability also enables exception.pending in struct kvm_vcpu_events, which allows userspace to distinguish between pending and injected exceptions.h]hThis capability also enables exception.pending in struct kvm_vcpu_events, which allows userspace to distinguish between pending and injected exceptions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMM hjJhhubjǣ)}(hXFor the new DR6 bits, note that bit 16 is set iff the #DB exception will clear DR6.RTM. h](jͣ)}(hhh]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j̣hjhhhNhNubh)}(hWFor the new DR6 bits, note that bit 16 is set iff the #DB exception will clear DR6.RTM.h]hWFor the new DR6 bits, note that bit 16 is set iff the #DB exception will clear DR6.RTM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMR hjubeh}(h]jوah ]h"]3ah$]h&]jӈaj؈Kjjuh1jƣhhhMR hjJhhubeh}(h]kvm-cap-exception-payloadah ]h"]7.17 kvm_cap_exception_payloadah$]h&]uh1hhjzhhhhhM< ubh)}(hhh](h)}(h&7.18 KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2h]h&7.18 KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMV ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hx86, arm64, mipsh]h)}(hjGh]hx86, arm64, mips}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMX hjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhMX hj1hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(h1args[0] whether feature should be enabled or not h]h)}(h0args[0] whether feature should be enabled or noth]h0args[0] whether feature should be enabled or not}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY hjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhMY hj1hhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhMX ubh)}(hValid flags are::h]hValid flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[ hj hhubj8)}(hm#define KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (1 << 0) #define KVM_DIRTY_LOG_INITIALLY_SET (1 << 1)h]hm#define KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (1 << 0) #define KVM_DIRTY_LOG_INITIALLY_SET (1 << 1)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM] hj hhubh)}(hWith KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE is set, KVM_GET_DIRTY_LOG will not automatically clear and write-protect all pages that are returned as dirty. Rather, userspace will have to do this operation separately using KVM_CLEAR_DIRTY_LOG.h]hWith KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE is set, KVM_GET_DIRTY_LOG will not automatically clear and write-protect all pages that are returned as dirty. Rather, userspace will have to do this operation separately using KVM_CLEAR_DIRTY_LOG.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM` hj hhubh)}(hX(At the cost of a slightly more complicated operation, this provides better scalability and responsiveness for two reasons. First, KVM_CLEAR_DIRTY_LOG ioctl can operate on a 64-page granularity rather than requiring to sync a full memslot; this ensures that KVM does not take spinlocks for an extended period of time. Second, in some cases a large amount of time can pass between a call to KVM_GET_DIRTY_LOG and userspace actually using the data in the page. Pages can be modified during this time, which is inefficient for both the guest and userspace: the guest will incur a higher penalty due to write protection faults, while userspace can see false reports of dirty pages. Manual reprotection helps reducing this time, improving guest performance and reducing the number of dirty log false positives.h]hX(At the cost of a slightly more complicated operation, this provides better scalability and responsiveness for two reasons. First, KVM_CLEAR_DIRTY_LOG ioctl can operate on a 64-page granularity rather than requiring to sync a full memslot; this ensures that KVM does not take spinlocks for an extended period of time. Second, in some cases a large amount of time can pass between a call to KVM_GET_DIRTY_LOG and userspace actually using the data in the page. Pages can be modified during this time, which is inefficient for both the guest and userspace: the guest will incur a higher penalty due to write protection faults, while userspace can see false reports of dirty pages. Manual reprotection helps reducing this time, improving guest performance and reducing the number of dirty log false positives.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMe hj hhubh)}(hXWith KVM_DIRTY_LOG_INITIALLY_SET set, all the bits of the dirty bitmap will be initialized to 1 when created. This also improves performance because dirty logging can be enabled gradually in small chunks on the first call to KVM_CLEAR_DIRTY_LOG. KVM_DIRTY_LOG_INITIALLY_SET depends on KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (it is also only available on x86, arm64 and riscv for now).h]hXWith KVM_DIRTY_LOG_INITIALLY_SET set, all the bits of the dirty bitmap will be initialized to 1 when created. This also improves performance because dirty logging can be enabled gradually in small chunks on the first call to KVM_CLEAR_DIRTY_LOG. KVM_DIRTY_LOG_INITIALLY_SET depends on KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (it is also only available on x86, arm64 and riscv for now).}(hjωhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMr hj hhubh)}(hX\KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 was previously available under the name KVM_CAP_MANUAL_DIRTY_LOG_PROTECT, but the implementation had bugs that make it hard or impossible to use it correctly. The availability of KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 signals that those bugs are fixed. Userspace should not try to use KVM_CAP_MANUAL_DIRTY_LOG_PROTECT.h]hX\KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 was previously available under the name KVM_CAP_MANUAL_DIRTY_LOG_PROTECT, but the implementation had bugs that make it hard or impossible to use it correctly. The availability of KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 signals that those bugs are fixed. Userspace should not try to use KVM_CAP_MANUAL_DIRTY_LOG_PROTECT.}(hj݉hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMy hj hhubeh}(h]!kvm-cap-manual-dirty-log-protect2ah ]h"]&7.18 kvm_cap_manual_dirty_log_protect2ah$]h&]uh1hhjzhhhhhMV ubh)}(hhh](h)}(h7.19 KVM_CAP_PPC_SECURE_GUESTh]h7.19 KVM_CAP_PPC_SECURE_GUEST}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppc h]h)}(hppch]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)A}(hXThis capability indicates that KVM is running on a host that has ultravisor firmware and thus can support a secure guest. On such a system, a guest can ask the ultravisor to make it a secure guest, one whose memory is inaccessible to the host except for pages which are explicitly requested to be shared with the host. The ultravisor notifies KVM when a guest requests to become a secure guest, and KVM has the opportunity to veto the transition.h]hXThis capability indicates that KVM is running on a host that has ultravisor firmware and thus can support a secure guest. On such a system, a guest can ask the ultravisor to make it a secure guest, one whose memory is inaccessible to the host except for pages which are explicitly requested to be shared with the host. The ultravisor notifies KVM when a guest requests to become a secure guest, and KVM has the opportunity to veto the transition.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hIf present, this capability can be enabled for a VM, meaning that KVM will allow the transition to secure guest mode. Otherwise KVM will veto the transition.h]hIf present, this capability can be enabled for a VM, meaning that KVM will allow the transition to secure guest mode. Otherwise KVM will veto the transition.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]kvm-cap-ppc-secure-guestah ]h"]7.19 kvm_cap_ppc_secure_guestah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.20 KVM_CAP_HALT_POLLh]h7.20 KVM_CAP_HALT_POLL}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhj`hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjthhhKubj)}(hallh]h)}(hjh]hall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjtubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjqhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjqhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjӊhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjЊhhhKubj)}(h/args[0] is the maximum poll time in nanosecondsh]h)}(hjh]h/args[0] is the maximum poll time in nanoseconds}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjЊubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjqhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjqhhubeh}(h]h ]h"]h$]h&]uh1jrhj`hhhhhM ubh)}(hKVM_CAP_HALT_POLL overrides the kvm.halt_poll_ns module parameter to set the maximum halt-polling time for all vCPUs in the target VM. This capability can be invoked at any time and any number of times to dynamically change the maximum halt-polling time.h]hKVM_CAP_HALT_POLL overrides the kvm.halt_poll_ns module parameter to set the maximum halt-polling time for all vCPUs in the target VM. This capability can be invoked at any time and any number of times to dynamically change the maximum halt-polling time.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`hhubh)}(hQSee Documentation/virt/kvm/halt-polling.rst for more information on halt polling.h]hQSee Documentation/virt/kvm/halt-polling.rst for more information on halt polling.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj`hhubeh}(h]kvm-cap-halt-pollah ]h"]7.20 kvm_cap_halt_pollah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.21 KVM_CAP_X86_USER_SPACE_MSRh]h7.21 KVM_CAP_X86_USER_SPACE_MSR}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjWhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjkhhhKubj)}(hx86h]h)}(hj~h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj|ubah}(h]h ]h"]h$]h&]uh1jhjkubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjʋhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjNjhhhKubj)}(hCargs[0] contains the mask of KVM_MSR_EXIT_REASON_* events to reporth]h)}(hjڋh]hCargs[0] contains the mask of KVM_MSR_EXIT_REASON_* events to report}(hj܋hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj؋ubah}(h]h ]h"]h$]h&]uh1jhjNjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -1 on error h]h)}(h0 on success; -1 on errorh]h0 on success; -1 on error}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhhubeh}(h]h ]h"]h$]h&]uh1jrhjWhhhhhM ubh)}(hThis capability allows userspace to intercept RDMSR and WRMSR instructions if access to an MSR is denied. By default, KVM injects #GP on denied accesses.h]hThis capability allows userspace to intercept RDMSR and WRMSR instructions if access to an MSR is denied. By default, KVM injects #GP on denied accesses.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjWhhubh)}(hWhen a guest requests to read or write an MSR, KVM may not implement all MSRs that are relevant to a respective system. It also does not differentiate by CPU type.h]hWhen a guest requests to read or write an MSR, KVM may not implement all MSRs that are relevant to a respective system. It also does not differentiate by CPU type.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjWhhubh)}(hXTo allow more fine grained control over MSR handling, userspace may enable this capability. With it enabled, MSR accesses that match the mask specified in args[0] and would trigger a #GP inside the guest will instead trigger KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR exit notifications. Userspace can then implement model specific MSR handling and/or user notifications to inform a user that an MSR was not emulated/virtualized by KVM.h]hXTo allow more fine grained control over MSR handling, userspace may enable this capability. With it enabled, MSR accesses that match the mask specified in args[0] and would trigger a #GP inside the guest will instead trigger KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR exit notifications. Userspace can then implement model specific MSR handling and/or user notifications to inform a user that an MSR was not emulated/virtualized by KVM.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjWhhubh)}(hThe valid mask flags are:h]hThe valid mask flags are:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjWhhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjeubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthK/uh1jchjeubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_UNKNOWNh]hKVM_MSR_EXIT_REASON_UNKNOWN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h+intercept accesses to unknown (to KVM) MSRsh]h+intercept accesses to unknown (to KVM) MSRs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj|ubj)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_INVALh]hKVM_MSR_EXIT_REASON_INVAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(h[intercept accesses that are architecturally invalid according to the vCPU model and/or modeh]h[intercept accesses that are architecturally invalid according to the vCPU model and/or mode}(hjӌhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjЌubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj|ubj)}(hhh](j)}(hhh]h)}(hKVM_MSR_EXIT_REASON_FILTERh]hKVM_MSR_EXIT_REASON_FILTER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hJintercept accesses that are denied by userspace via KVM_X86_SET_MSR_FILTERh]hJintercept accesses that are denied by userspace via KVM_X86_SET_MSR_FILTER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj|ubeh}(h]h ]h"]h$]h&]uh1jyhjeubeh}(h]h ]h"]h$]h&]colsKuh1j^hjbubah}(h]h ]h"]h$]h&]uh1jYhjWhhhhhNubeh}(h]kvm-cap-x86-user-space-msrah ]h"]7.21 kvm_cap_x86_user_space_msrah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.22 KVM_CAP_X86_BUS_LOCK_EXITh]h7.22 KVM_CAP_X86_BUS_LOCK_EXIT}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjShhhKubj)}(hx86h]h)}(hjfh]hx86}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjdubah}(h]h ]h"]h$]h&]uh1jhjSubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjPhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjPhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h@args[0] defines the policy used when bus locks detected in guesth]h)}(hjh]h@args[0] defines the policy used when bus locks detected in guest}(hjčhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjPhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjݍhhhKubj)}(h90 on success, -EINVAL when args[0] contains invalid bits h]h)}(h80 on success, -EINVAL when args[0] contains invalid bitsh]h80 on success, -EINVAL when args[0] contains invalid bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjݍubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjPhhubeh}(h]h ]h"]h$]h&]uh1jrhj?hhhhhM ubh)}(hValid bits in args[0] are::h]hValid bits in args[0] are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubj8)}(ha#define KVM_BUS_LOCK_DETECTION_OFF (1 << 0) #define KVM_BUS_LOCK_DETECTION_EXIT (1 << 1)h]ha#define KVM_BUS_LOCK_DETECTION_OFF (1 << 0) #define KVM_BUS_LOCK_DETECTION_EXIT (1 << 1)}hj sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM hj?hhubh)}(hX"Enabling this capability on a VM provides userspace with a way to select a policy to handle the bus locks detected in guest. Userspace can obtain the supported modes from the result of KVM_CHECK_EXTENSION and define it through the KVM_ENABLE_CAP. The supported modes are mutually-exclusive.h]hX"Enabling this capability on a VM provides userspace with a way to select a policy to handle the bus locks detected in guest. Userspace can obtain the supported modes from the result of KVM_CHECK_EXTENSION and define it through the KVM_ENABLE_CAP. The supported modes are mutually-exclusive.}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubh)}(hXgThis capability allows userspace to force VM exits on bus locks detected in the guest, irrespective whether or not the host has enabled split-lock detection (which triggers an #AC exception that KVM intercepts). This capability is intended to mitigate attacks where a malicious/buggy guest can exploit bus locks to degrade the performance of the whole system.h]hXgThis capability allows userspace to force VM exits on bus locks detected in the guest, irrespective whether or not the host has enabled split-lock detection (which triggers an #AC exception that KVM intercepts). This capability is intended to mitigate attacks where a malicious/buggy guest can exploit bus locks to degrade the performance of the whole system.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubh)}(hIf KVM_BUS_LOCK_DETECTION_OFF is set, KVM doesn't force guest bus locks to VM exit, although the host kernel's split-lock #AC detection still applies, if enabled.h]hIf KVM_BUS_LOCK_DETECTION_OFF is set, KVM doesn’t force guest bus locks to VM exit, although the host kernel’s split-lock #AC detection still applies, if enabled.}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubh)}(hXIf KVM_BUS_LOCK_DETECTION_EXIT is set, KVM enables a CPU feature that ensures bus locks in the guest trigger a VM exit, and KVM exits to userspace for all such VM exits, e.g. to allow userspace to throttle the offending guest and/or apply some other policy-based mitigation. When exiting to userspace, KVM sets KVM_RUN_X86_BUS_LOCK in vcpu-run->flags, and conditionally sets the exit_reason to KVM_EXIT_X86_BUS_LOCK.h]hXIf KVM_BUS_LOCK_DETECTION_EXIT is set, KVM enables a CPU feature that ensures bus locks in the guest trigger a VM exit, and KVM exits to userspace for all such VM exits, e.g. to allow userspace to throttle the offending guest and/or apply some other policy-based mitigation. When exiting to userspace, KVM sets KVM_RUN_X86_BUS_LOCK in vcpu-run->flags, and conditionally sets the exit_reason to KVM_EXIT_X86_BUS_LOCK.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubh)}(hX&Due to differences in the underlying hardware implementation, the vCPU's RIP at the time of exit diverges between Intel and AMD. On Intel hosts, RIP points at the next instruction, i.e. the exit is trap-like. On AMD hosts, RIP points at the offending instruction, i.e. the exit is fault-like.h]hX(Due to differences in the underlying hardware implementation, the vCPU’s RIP at the time of exit diverges between Intel and AMD. On Intel hosts, RIP points at the next instruction, i.e. the exit is trap-like. On AMD hosts, RIP points at the offending instruction, i.e. the exit is fault-like.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubh)}(hNote! Detected bus locks may be coincident with other exits to userspace, i.e. KVM_RUN_X86_BUS_LOCK should be checked regardless of the primary exit reason if userspace wants to take action on all detected bus locks.h]hNote! Detected bus locks may be coincident with other exits to userspace, i.e. KVM_RUN_X86_BUS_LOCK should be checked regardless of the primary exit reason if userspace wants to take action on all detected bus locks.}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj?hhubeh}(h]kvm-cap-x86-bus-lock-exitah ]h"]7.22 kvm_cap_x86_bus_lock_exitah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.23 KVM_CAP_PPC_DAWR1h]h7.23 KVM_CAP_PPC_DAWR1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppch]h)}(hjh]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjώhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj̎hhhKubj)}(hnoneh]h)}(hjߎh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjݎubah}(h]h ]h"]h$]h&]uh1jhj̎ubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h80 on success, -EINVAL when CPU doesn't support 2nd DAWR h]h)}(h70 on success, -EINVAL when CPU doesn't support 2nd DAWRh]h90 on success, -EINVAL when CPU doesn’t support 2nd DAWR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM ubh)}(h]This capability can be used to check / enable 2nd DAWR feature provided by POWER10 processor.h]h]This capability can be used to check / enable 2nd DAWR feature provided by POWER10 processor.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubeh}(h]kvm-cap-ppc-dawr1ah ]h"]7.23 kvm_cap_ppc_dawr1ah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h%7.24 KVM_CAP_VM_COPY_ENC_CONTEXT_FROMh]h%7.24 KVM_CAP_VM_COPY_ENC_CONTEXT_FROM}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhhhhhM ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hx86 SEV enabledh]h)}(hjlh]hx86 SEV enabled}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjjubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjVhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvmh]h)}(hjh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjVhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h"args[0] is the fd of the source vmh]h)}(hjȏh]h"args[0] is the fd of the source vm}(hjʏhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjƏubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjVhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; ENOTTY on error h]h)}(h0 on success; ENOTTY on errorh]h0 on success; ENOTTY on error}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM hjVhhubeh}(h]h ]h"]h$]h&]uh1jrhjEhhhhhM ubh)}(hyThis capability enables userspace to copy encryption context from the vm indicated by the fd to the vm this is called on.h]hyThis capability enables userspace to copy encryption context from the vm indicated by the fd to the vm this is called on.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjEhhubh)}(hThis is intended to support in-guest workloads scheduled by the host. This allows the in-guest workload to maintain its own NPTs and keeps the two vms from accidentally clobbering each other with interrupts and the like (separate APIC/MSRs/etc).h]hThis is intended to support in-guest workloads scheduled by the host. This allows the in-guest workload to maintain its own NPTs and keeps the two vms from accidentally clobbering each other with interrupts and the like (separate APIC/MSRs/etc).}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjEhhubeh}(h] kvm-cap-vm-copy-enc-context-fromah ]h"]%7.24 kvm_cap_vm_copy_enc_context_fromah$]h&]uh1hhjzhhhhhM ubh)}(hhh](h)}(h7.25 KVM_CAP_SGX_ATTRIBUTEh]h7.25 KVM_CAP_SGX_ATTRIBUTE}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<hhhhhM!ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hx86h]h)}(hjch]hx86}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM !hjaubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhM !hjMhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM !hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhM !hjMhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h>args[0] is a file handle of a SGX attribute file in securityfsh]h)}(hjh]h>args[0] is a file handle of a SGX attribute file in securityfs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM !hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM !hjMhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjݐhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjڐhhhKubj)}(hi0 on success, -EINVAL if the file handle is invalid or if a requested attribute is not supported by KVM. h]h)}(hh0 on success, -EINVAL if the file handle is invalid or if a requested attribute is not supported by KVM.h]hh0 on success, -EINVAL if the file handle is invalid or if a requested attribute is not supported by KVM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM !hjubah}(h]h ]h"]h$]h&]uh1jhjڐubeh}(h]h ]h"]h$]h&]uh1jwhhhM !hjMhhubeh}(h]h ]h"]h$]h&]uh1jrhj<hhhhhM !ubh)}(hXKVM_CAP_SGX_ATTRIBUTE enables a userspace VMM to grant a VM access to one or more privileged enclave attributes. args[0] must hold a file handle to a valid SGX attribute file corresponding to an attribute that is supported/restricted by KVM (currently only PROVISIONKEY).h]hXKVM_CAP_SGX_ATTRIBUTE enables a userspace VMM to grant a VM access to one or more privileged enclave attributes. args[0] must hold a file handle to a valid SGX attribute file corresponding to an attribute that is supported/restricted by KVM (currently only PROVISIONKEY).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj<hhubh)}(hXThe SGX subsystem restricts access to a subset of enclave attributes to provide additional security for an uncompromised kernel, e.g. use of the PROVISIONKEY is restricted to deter malware from using the PROVISIONKEY to obtain a stable system fingerprint. To prevent userspace from circumventing such restrictions by running an enclave in a VM, KVM prevents access to privileged attributes by default.h]hXThe SGX subsystem restricts access to a subset of enclave attributes to provide additional security for an uncompromised kernel, e.g. use of the PROVISIONKEY is restricted to deter malware from using the PROVISIONKEY to obtain a stable system fingerprint. To prevent userspace from circumventing such restrictions by running an enclave in a VM, KVM prevents access to privileged attributes by default.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj<hhubh)}(h4See Documentation/arch/x86/sgx.rst for more details.h]h4See Documentation/arch/x86/sgx.rst for more details.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj<hhubeh}(h]kvm-cap-sgx-attributeah ]h"]7.25 kvm_cap_sgx_attributeah$]h&]uh1hhjzhhhhhM!ubh)}(hhh](h)}(h&7.27 KVM_CAP_EXIT_ON_EMULATION_FAILUREh]h&7.27 KVM_CAP_EXIT_ON_EMULATION_FAILURE}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhM!ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjUhhhKubj)}(hx86h]h)}(hjhh]hx86}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!!hjfubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jwhhhM!!hjRhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h5args[0] whether the feature should be enabled or not h]h)}(h4args[0] whether the feature should be enabled or noth]h4args[0] whether the feature should be enabled or not}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM"!hjRhhubeh}(h]h ]h"]h$]h&]uh1jrhjAhhhhhM!!ubh)}(hX When this capability is enabled, an emulation failure will result in an exit to userspace with KVM_INTERNAL_ERROR (except when the emulator was invoked to handle a VMware backdoor instruction). Furthermore, KVM will now provide up to 15 instruction bytes for any exit to userspace resulting from an emulation failure. When these exits to userspace occur use the emulation_failure struct instead of the internal struct. They both have the same layout, but the emulation_failure struct matches the content better. It also explicitly defines the 'flags' field which is used to describe the fields in the struct that are valid (ie: if KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES is set in the 'flags' field then both 'insn_size' and 'insn_bytes' have valid data in them.)h]hXWhen this capability is enabled, an emulation failure will result in an exit to userspace with KVM_INTERNAL_ERROR (except when the emulator was invoked to handle a VMware backdoor instruction). Furthermore, KVM will now provide up to 15 instruction bytes for any exit to userspace resulting from an emulation failure. When these exits to userspace occur use the emulation_failure struct instead of the internal struct. They both have the same layout, but the emulation_failure struct matches the content better. It also explicitly defines the ‘flags’ field which is used to describe the fields in the struct that are valid (ie: if KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES is set in the ‘flags’ field then both ‘insn_size’ and ‘insn_bytes’ have valid data in them.)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$!hjAhhubeh}(h]!kvm-cap-exit-on-emulation-failureah ]h"]&7.27 kvm_cap_exit_on_emulation_failureah$]h&]uh1hhjzhhhhhM!ubh)}(hhh](h)}(h7.28 KVM_CAP_ARM_MTEh]h7.28 KVM_CAP_ARM_MTE}(hjёhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjΑhhhhhM1!ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hjh]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3!hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM3!hjߑhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4!hj!ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM4!hjߑhhubeh}(h]h ]h"]h$]h&]uh1jrhjΑhhhhhM3!ubh)}(hXfThis capability indicates that KVM (and the hardware) supports exposing the Memory Tagging Extensions (MTE) to the guest. It must also be enabled by the VMM before creating any VCPUs to allow the guest access. Note that MTE is only available to a guest running in AArch64 mode and enabling this capability will cause attempts to create AArch32 VCPUs to fail.h]hXfThis capability indicates that KVM (and the hardware) supports exposing the Memory Tagging Extensions (MTE) to the guest. It must also be enabled by the VMM before creating any VCPUs to allow the guest access. Note that MTE is only available to a guest running in AArch64 mode and enabling this capability will cause attempts to create AArch32 VCPUs to fail.}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM6!hjΑhhubh)}(hXWhen enabled the guest is able to access tags associated with any memory given to the guest. KVM will ensure that the tags are maintained during swap or hibernation of the host; however the VMM needs to manually save/restore the tags as appropriate if the VM is migrated.h]hXWhen enabled the guest is able to access tags associated with any memory given to the guest. KVM will ensure that the tags are maintained during swap or hibernation of the host; however the VMM needs to manually save/restore the tags as appropriate if the VM is migrated.}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMh]h2args[0] - maximum APIC ID value set for current VM}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hj<ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jwhhhM!hj̗hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hd0 on success, -EINVAL if args[0] is beyond KVM_MAX_VCPU_IDS supported in KVM or if it has been set. h]h)}(hc0 on success, -EINVAL if args[0] is beyond KVM_MAX_VCPU_IDS supported in KVM or if it has been set.h]hc0 on success, -EINVAL if args[0] is beyond KVM_MAX_VCPU_IDS supported in KVM or if it has been set.}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjjubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhM!hj̗hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM!ubh)}(hXThis capability allows userspace to specify maximum possible APIC ID assigned for current VM session prior to the creation of vCPUs, saving memory for data structures indexed by the APIC ID. Userspace is able to calculate the limit to APIC ID values from designated CPU topology.h]hXThis capability allows userspace to specify maximum possible APIC ID assigned for current VM session prior to the creation of vCPUs, saving memory for data structures indexed by the APIC ID. Userspace is able to calculate the limit to APIC ID values from designated CPU topology.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM!hjhhubh)}(hX(The value can be changed only until KVM_ENABLE_CAP is set to a nonzero value or until a vCPU is created. Upon creation of the first vCPU, if the value was set to zero or KVM_ENABLE_CAP was not invoked, KVM uses the return value of KVM_CHECK_EXTENSION(KVM_CAP_MAX_VCPU_ID) as the maximum APIC ID.h]hX(The value can be changed only until KVM_ENABLE_CAP is set to a nonzero value or until a vCPU is created. Upon creation of the first vCPU, if the value was set to zero or KVM_ENABLE_CAP was not invoked, KVM uses the return value of KVM_CHECK_EXTENSION(KVM_CAP_MAX_VCPU_ID) as the maximum APIC ID.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjhhubeh}(h]kvm-cap-max-vcpu-idah ]h"]7.32 kvm_cap_max_vcpu_idah$]h&]uh1hhjzhhhhhM!ubh)}(hhh](h)}(h7.33 KVM_CAP_X86_NOTIFY_VMEXITh]h7.33 KVM_CAP_X86_NOTIFY_VMEXIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM "ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjɘhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjƘhhhKubj)}(hx86h]h)}(hj٘h]hx86}(hjۘhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM "hjטubah}(h]h ]h"]h$]h&]uh1jhjƘubeh}(h]h ]h"]h$]h&]uh1jwhhhM "hjØhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM "hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM "hjØhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj"hhhKubj)}(h;args[0] is the value of notify window as well as some flagsh]h)}(hj5h]h;args[0] is the value of notify window as well as some flags}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj3ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjØhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjPhhhKubj)}(hZ0 on success, -EINVAL if args[0] contains invalid flags or notify VM exit is unsupported. h]h)}(hY0 on success, -EINVAL if args[0] contains invalid flags or notify VM exit is unsupported.h]hY0 on success, -EINVAL if args[0] contains invalid flags or notify VM exit is unsupported.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjaubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjØhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM "ubh)}(hkBits 63:32 of args[0] are used for notify window. Bits 31:0 of args[0] are for some flags. Valid bits are::h]hjBits 63:32 of args[0] are used for notify window. Bits 31:0 of args[0] are for some flags. Valid bits are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjhhubj8)}(hc#define KVM_X86_NOTIFY_VMEXIT_ENABLED (1 << 0) #define KVM_X86_NOTIFY_VMEXIT_USER (1 << 1)h]hc#define KVM_X86_NOTIFY_VMEXIT_ENABLED (1 << 0) #define KVM_X86_NOTIFY_VMEXIT_USER (1 << 1)}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM"hjhhubh)}(hXThis capability allows userspace to configure the notify VM exit on/off in per-VM scope during VM creation. Notify VM exit is disabled by default. When userspace sets KVM_X86_NOTIFY_VMEXIT_ENABLED bit in args[0], VMM will enable this feature with the notify window provided, which will generate a VM exit if no event window occurs in VM non-root mode for a specified of time (notify window).h]hXThis capability allows userspace to configure the notify VM exit on/off in per-VM scope during VM creation. Notify VM exit is disabled by default. When userspace sets KVM_X86_NOTIFY_VMEXIT_ENABLED bit in args[0], VMM will enable this feature with the notify window provided, which will generate a VM exit if no event window occurs in VM non-root mode for a specified of time (notify window).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjhhubh)}(hwIf KVM_X86_NOTIFY_VMEXIT_USER is set in args[0], upon notify VM exits happen, KVM would exit to userspace for handling.h]hwIf KVM_X86_NOTIFY_VMEXIT_USER is set in args[0], upon notify VM exits happen, KVM would exit to userspace for handling.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjhhubh)}(hThis capability is aimed to mitigate the threat that malicious VMs can cause CPU stuck (due to event windows don't open up) and make the CPU unavailable to host or other VMs.h]hThis capability is aimed to mitigate the threat that malicious VMs can cause CPU stuck (due to event windows don’t open up) and make the CPU unavailable to host or other VMs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM""hjhhubeh}(h]kvm-cap-x86-notify-vmexitah ]h"]7.33 kvm_cap_x86_notify_vmexitah$]h&]uh1hhjzhhhhhM "ubh)}(hhh](h)}(h#7.35 KVM_CAP_X86_APIC_BUS_CYCLES_NSh]h#7.35 KVM_CAP_X86_APIC_BUS_CYCLES_NS}(hj֙hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjәhhhhhM'"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM)"hjhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hj(h]hVM}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM*"hj&ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM*"hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjChhhKubj)}(h:args[0] is the desired APIC bus clock rate, in nanosecondsh]h)}(hjVh]h:args[0] is the desired APIC bus clock rate, in nanoseconds}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+"hjTubah}(h]h ]h"]h$]h&]uh1jhjCubeh}(h]h ]h"]h$]h&]uh1jwhhhM+"hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(h0 on success, -EINVAL if args[0] contains an invalid value for the frequency or if any vCPUs have been created, -ENXIO if a virtual local APIC has not been created using KVM_CREATE_IRQCHIP. h]h)}(h0 on success, -EINVAL if args[0] contains an invalid value for the frequency or if any vCPUs have been created, -ENXIO if a virtual local APIC has not been created using KVM_CREATE_IRQCHIP.h]h0 on success, -EINVAL if args[0] contains an invalid value for the frequency or if any vCPUs have been created, -ENXIO if a virtual local APIC has not been created using KVM_CREATE_IRQCHIP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,"hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM,"hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjәhhhhhM)"ubh)}(hThis capability sets the VM's APIC bus clock frequency, used by KVM's in-kernel virtual APIC when emulating APIC timers. KVM's default value can be retrieved by KVM_CHECK_EXTENSION.h]hThis capability sets the VM’s APIC bus clock frequency, used by KVM’s in-kernel virtual APIC when emulating APIC timers. KVM’s default value can be retrieved by KVM_CHECK_EXTENSION.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0"hjәhhubh)}(hNote: Userspace is responsible for correctly configuring CPUID 0x15, a.k.a. the core crystal clock frequency, if a non-zero CPUID 0x15 is exposed to the guest.h]hNote: Userspace is responsible for correctly configuring CPUID 0x15, a.k.a. the core crystal clock frequency, if a non-zero CPUID 0x15 is exposed to the guest.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM4"hjәhhubeh}(h]kvm-cap-x86-apic-bus-cycles-nsah ]h"]#7.35 kvm_cap_x86_apic_bus_cycles_nsah$]h&]uh1hhjzhhhhhM'"ubh)}(hhh](h)}(h:7.36 KVM_CAP_DIRTY_LOG_RING/KVM_CAP_DIRTY_LOG_RING_ACQ_RELh]h:7.36 KVM_CAP_DIRTY_LOG_RING/KVM_CAP_DIRTY_LOG_RING_ACQ_REL}(hj͚hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjʚhhhhhM8"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjޚhhhKubj)}(hx86, arm64, riscvh]h)}(hjh]hx86, arm64, riscv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:"hjubah}(h]h ]h"]h$]h&]uh1jhjޚubeh}(h]h ]h"]h$]h&]uh1jwhhhM:"hjۚhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvmh]h)}(hjh]hvm}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;"hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM;"hjۚhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj:hhhKubj)}(h%args[0] - size of the dirty log ring h]h)}(h$args[0] - size of the dirty log ringh]h$args[0] - size of the dirty log ring}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<"hjKubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jwhhhM<"hjۚhhubeh}(h]h ]h"]h$]h&]uh1jrhjʚhhhhhM:"ubh)}(h}KVM is capable of tracking dirty memory using ring buffers that are mmapped into userspace; there is one dirty ring per vcpu.h]h}KVM is capable of tracking dirty memory using ring buffers that are mmapped into userspace; there is one dirty ring per vcpu.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>"hjʚhhubh)}(hsThe dirty ring is available to userspace as an array of ``struct kvm_dirty_gfn``. Each dirty entry is defined as::h](h8The dirty ring is available to userspace as an array of }(hj}hhhNhNubj)}(h``struct kvm_dirty_gfn``h]hstruct kvm_dirty_gfn}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj}ubh". Each dirty entry is defined as:}(hj}hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMA"hjʚhhubj8)}(hnstruct kvm_dirty_gfn { __u32 flags; __u32 slot; /* as_id | slot_id */ __u64 offset; };h]hnstruct kvm_dirty_gfn { __u32 flags; __u32 slot; /* as_id | slot_id */ __u64 offset; };}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMD"hjʚhhubh)}(h_The following values are defined for the flags field to define the current state of the entry::h]h^The following values are defined for the flags field to define the current state of the entry:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJ"hjʚhhubj8)}(h#define KVM_DIRTY_GFN_F_DIRTY BIT(0) #define KVM_DIRTY_GFN_F_RESET BIT(1) #define KVM_DIRTY_GFN_F_MASK 0x3h]h#define KVM_DIRTY_GFN_F_DIRTY BIT(0) #define KVM_DIRTY_GFN_F_RESET BIT(1) #define KVM_DIRTY_GFN_F_MASK 0x3}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhMM"hjʚhhubh)}(hXUserspace should call KVM_ENABLE_CAP ioctl right after KVM_CREATE_VM ioctl to enable this capability for the new guest and set the size of the rings. Enabling the capability is only allowed before creating any vCPU, and the size of the ring must be a power of two. The larger the ring buffer, the less likely the ring is full and the VM is forced to exit to userspace. The optimal size depends on the workload, but it is recommended that it be at least 64 KiB (4096 entries).h]hXUserspace should call KVM_ENABLE_CAP ioctl right after KVM_CREATE_VM ioctl to enable this capability for the new guest and set the size of the rings. Enabling the capability is only allowed before creating any vCPU, and the size of the ring must be a power of two. The larger the ring buffer, the less likely the ring is full and the VM is forced to exit to userspace. The optimal size depends on the workload, but it is recommended that it be at least 64 KiB (4096 entries).}(hjǛhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQ"hjʚhhubh)}(hXJust like for dirty page bitmaps, the buffer tracks writes to all user memory regions for which the KVM_MEM_LOG_DIRTY_PAGES flag was set in KVM_SET_USER_MEMORY_REGION. Once a memory region is registered with the flag set, userspace can start harvesting dirty pages from the ring buffer.h]hXJust like for dirty page bitmaps, the buffer tracks writes to all user memory regions for which the KVM_MEM_LOG_DIRTY_PAGES flag was set in KVM_SET_USER_MEMORY_REGION. Once a memory region is registered with the flag set, userspace can start harvesting dirty pages from the ring buffer.}(hj՛hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY"hjʚhhubh)}(hAn entry in the ring buffer can be unused (flag bits ``00``), dirty (flag bits ``01``) or harvested (flag bits ``1X``). The state machine for the entry is as follows::h](h5An entry in the ring buffer can be unused (flag bits }(hjhhhNhNubj)}(h``00``h]h00}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh), dirty (flag bits }(hjhhhNhNubj)}(h``01``h]h01}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh) or harvested (flag bits }(hjhhhNhNubj)}(h``1X``h]h1X}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh2). The state machine for the entry is as follows:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM_"hjʚhhubj8)}(h dirtied harvested reset 00 -----------> 01 -------------> 1X -------+ ^ | | | +------------------------------------------+h]h dirtied harvested reset 00 -----------> 01 -------------> 1X -------+ ^ | | | +------------------------------------------+}hj'sbah}(h]h ]h"]h$]h&]hhuh1j7hhhMc"hjʚhhubh)}(hXcTo harvest the dirty pages, userspace accesses the mmapped ring buffer to read the dirty GFNs. If the flags has the DIRTY bit set (at this stage the RESET bit must be cleared), then it means this GFN is a dirty GFN. The userspace should harvest this GFN and mark the flags from state ``01b`` to ``1Xb`` (bit 0 will be ignored by KVM, but bit 1 must be set to show that this GFN is harvested and waiting for a reset), and move on to the next GFN. The userspace should continue to do this until the flags of a GFN have the DIRTY bit cleared, meaning that it has harvested all the dirty GFNs that were available.h](hXTo harvest the dirty pages, userspace accesses the mmapped ring buffer to read the dirty GFNs. If the flags has the DIRTY bit set (at this stage the RESET bit must be cleared), then it means this GFN is a dirty GFN. The userspace should harvest this GFN and mark the flags from state }(hj5hhhNhNubj)}(h``01b``h]h01b}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubh to }(hj5hhhNhNubj)}(h``1Xb``h]h1Xb}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj5ubhX4 (bit 0 will be ignored by KVM, but bit 1 must be set to show that this GFN is harvested and waiting for a reset), and move on to the next GFN. The userspace should continue to do this until the flags of a GFN have the DIRTY bit cleared, meaning that it has harvested all the dirty GFNs that were available.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMi"hjʚhhubh)}(hXNote that on weakly ordered architectures, userspace accesses to the ring buffer (and more specifically the 'flags' field) must be ordered, using load-acquire/store-release accessors when available, or any other memory barrier that will ensure this ordering.h]hXNote that on weakly ordered architectures, userspace accesses to the ring buffer (and more specifically the ‘flags’ field) must be ordered, using load-acquire/store-release accessors when available, or any other memory barrier that will ensure this ordering.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMs"hjʚhhubh)}(hIt's not necessary for userspace to harvest the all dirty GFNs at once. However it must collect the dirty GFNs in sequence, i.e., the userspace program cannot skip one dirty GFN to collect the one next to it.h]hIt’s not necessary for userspace to harvest the all dirty GFNs at once. However it must collect the dirty GFNs in sequence, i.e., the userspace program cannot skip one dirty GFN to collect the one next to it.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMx"hjʚhhubh)}(hXAfter processing one or more entries in the ring buffer, userspace calls the VM ioctl KVM_RESET_DIRTY_RINGS to notify the kernel about it, so that the kernel will reprotect those collected GFNs. Therefore, the ioctl must be called *before* reading the content of the dirty pages.h](hAfter processing one or more entries in the ring buffer, userspace calls the VM ioctl KVM_RESET_DIRTY_RINGS to notify the kernel about it, so that the kernel will reprotect those collected GFNs. Therefore, the ioctl must be called }(hjhhhNhNubj)}(h*before*h]hbefore}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh( reading the content of the dirty pages.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM|"hjʚhhubh)}(h}The dirty ring can get full. When it happens, the KVM_RUN of the vcpu will return with exit reason KVM_EXIT_DIRTY_RING_FULL.h]h}The dirty ring can get full. When it happens, the KVM_RUN of the vcpu will return with exit reason KVM_EXIT_DIRTY_RING_FULL.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hXThe dirty ring interface has a major difference comparing to the KVM_GET_DIRTY_LOG interface in that, when reading the dirty ring from userspace, it's still possible that the kernel has not yet flushed the processor's dirty page buffers into the kernel buffer (with dirty bitmaps, the flushing is done by the KVM_GET_DIRTY_LOG ioctl). To achieve that, one needs to kick the vcpu out of KVM_RUN using a signal. The resulting vmexit ensures that all dirty GFNs are flushed to the dirty rings.h]hXThe dirty ring interface has a major difference comparing to the KVM_GET_DIRTY_LOG interface in that, when reading the dirty ring from userspace, it’s still possible that the kernel has not yet flushed the processor’s dirty page buffers into the kernel buffer (with dirty bitmaps, the flushing is done by the KVM_GET_DIRTY_LOG ioctl). To achieve that, one needs to kick the vcpu out of KVM_RUN using a signal. The resulting vmexit ensures that all dirty GFNs are flushed to the dirty rings.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hXNOTE: KVM_CAP_DIRTY_LOG_RING_ACQ_REL is the only capability that should be exposed by weakly ordered architecture, in order to indicate the additional memory ordering requirements imposed on userspace when reading the state of an entry and mutating it from DIRTY to HARVESTED. Architecture with TSO-like ordering (such as x86) are allowed to expose both KVM_CAP_DIRTY_LOG_RING and KVM_CAP_DIRTY_LOG_RING_ACQ_REL to userspace.h]hXNOTE: KVM_CAP_DIRTY_LOG_RING_ACQ_REL is the only capability that should be exposed by weakly ordered architecture, in order to indicate the additional memory ordering requirements imposed on userspace when reading the state of an entry and mutating it from DIRTY to HARVESTED. Architecture with TSO-like ordering (such as x86) are allowed to expose both KVM_CAP_DIRTY_LOG_RING and KVM_CAP_DIRTY_LOG_RING_ACQ_REL to userspace.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hXAfter enabling the dirty rings, the userspace needs to detect the capability of KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP to see whether the ring structures can be backed by per-slot bitmaps. With this capability advertised, it means the architecture can dirty guest pages without vcpu/ring context, so that some of the dirty information will still be maintained in the bitmap structure. KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP can't be enabled if the capability of KVM_CAP_DIRTY_LOG_RING_ACQ_REL hasn't been enabled, or any memslot has been existing.h]hXAfter enabling the dirty rings, the userspace needs to detect the capability of KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP to see whether the ring structures can be backed by per-slot bitmaps. With this capability advertised, it means the architecture can dirty guest pages without vcpu/ring context, so that some of the dirty information will still be maintained in the bitmap structure. KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP can’t be enabled if the capability of KVM_CAP_DIRTY_LOG_RING_ACQ_REL hasn’t been enabled, or any memslot has been existing.}(hj͜hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hX%Note that the bitmap here is only a backup of the ring structure. The use of the ring and bitmap combination is only beneficial if there is only a very small amount of memory that is dirtied out of vcpu/ring context. Otherwise, the stand-alone per-slot bitmap mechanism needs to be considered.h]hX%Note that the bitmap here is only a backup of the ring structure. The use of the ring and bitmap combination is only beneficial if there is only a very small amount of memory that is dirtied out of vcpu/ring context. Otherwise, the stand-alone per-slot bitmap mechanism needs to be considered.}(hjۜhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hXTo collect dirty bits in the backup bitmap, userspace can use the same KVM_GET_DIRTY_LOG ioctl. KVM_CLEAR_DIRTY_LOG isn't needed as long as all the generation of the dirty bits is done in a single pass. Collecting the dirty bitmap should be the very last thing that the VMM does before considering the state as complete. VMM needs to ensure that the dirty state is final and avoid missing dirty pages from another ioctl ordered after the bitmap collection.h]hXTo collect dirty bits in the backup bitmap, userspace can use the same KVM_GET_DIRTY_LOG ioctl. KVM_CLEAR_DIRTY_LOG isn’t needed as long as all the generation of the dirty bits is done in a single pass. Collecting the dirty bitmap should be the very last thing that the VMM does before considering the state as complete. VMM needs to ensure that the dirty state is final and avoid missing dirty pages from another ioctl ordered after the bitmap collection.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubh)}(hXNOTE: Multiple examples of using the backup bitmap: (1) save vgic/its tables through command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_SAVE_TABLES} on KVM device "kvm-arm-vgic-its". (2) restore vgic/its tables through command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_RESTORE_TABLES} on KVM device "kvm-arm-vgic-its". VGICv3 LPI pending status is restored. (3) save vgic3 pending table through KVM_DEV_ARM_VGIC_{GRP_CTRL, SAVE_PENDING_TABLES} command on KVM device "kvm-arm-vgic-v3".h]hXNOTE: Multiple examples of using the backup bitmap: (1) save vgic/its tables through command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_SAVE_TABLES} on KVM device “kvm-arm-vgic-its”. (2) restore vgic/its tables through command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_RESTORE_TABLES} on KVM device “kvm-arm-vgic-its”. VGICv3 LPI pending status is restored. (3) save vgic3 pending table through KVM_DEV_ARM_VGIC_{GRP_CTRL, SAVE_PENDING_TABLES} command on KVM device “kvm-arm-vgic-v3”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjʚhhubeh}(h]5kvm-cap-dirty-log-ring-kvm-cap-dirty-log-ring-acq-relah ]h"]:7.36 kvm_cap_dirty_log_ring/kvm_cap_dirty_log_ring_acq_relah$]h&]uh1hhjzhhhhhM8"ubh)}(hhh](h)}(h7.37 KVM_CAP_PMU_CAPABILITYh]h7.37 KVM_CAP_PMU_CAPABILITY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj!hhhKubj)}(hx86h]h)}(hj4h]hx86}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj2ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjOhhhKubj)}(hvmh]h)}(hjbh]hvm}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj`ubah}(h]h ]h"]h$]h&]uh1jhjOubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj}hhhKubj)}(h5arg[0] is bitmask of PMU virtualization capabilities.h]h)}(hjh]h5arg[0] is bitmask of PMU virtualization capabilities.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhj}ubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h80 on success, -EINVAL when arg[0] contains invalid bits h]h)}(h70 on success, -EINVAL when arg[0] contains invalid bitsh]h70 on success, -EINVAL when arg[0] contains invalid bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjhhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhM"ubh)}(h1This capability alters PMU virtualization in KVM.h]h1This capability alters PMU virtualization in KVM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(hCalling KVM_CHECK_EXTENSION for this capability returns a bitmask of PMU virtualization capabilities that can be adjusted on a VM.h]hCalling KVM_CHECK_EXTENSION for this capability returns a bitmask of PMU virtualization capabilities that can be adjusted on a VM.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(hThe argument to KVM_ENABLE_CAP is also a bitmask and selects specific PMU virtualization capabilities to be applied to the VM. This can only be invoked on a VM prior to the creation of VCPUs.h]hThe argument to KVM_ENABLE_CAP is also a bitmask and selects specific PMU virtualization capabilities to be applied to the VM. This can only be invoked on a VM prior to the creation of VCPUs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(hAt this time, KVM_PMU_CAP_DISABLE is the only capability. Setting this capability will disable PMU virtualization for that VM. Usermode should adjust CPUID leaf 0xA to reflect that the PMU is disabled.h]hAt this time, KVM_PMU_CAP_DISABLE is the only capability. Setting this capability will disable PMU virtualization for that VM. Usermode should adjust CPUID leaf 0xA to reflect that the PMU is disabled.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubeh}(h]kvm-cap-pmu-capabilityah ]h"]7.37 kvm_cap_pmu_capabilityah$]h&]uh1hhjzhhhhhM"ubh)}(hhh](h)}(h%7.38 KVM_CAP_VM_DISABLE_NX_HUGE_PAGESh]h%7.38 KVM_CAP_VM_DISABLE_NX_HUGE_PAGES}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj4hhhKubj)}(hx86h]h)}(hjGh]hx86}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjEubah}(h]h ]h"]h$]h&]uh1jhj4ubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj1hhubjx)}(hhh](j})}(hTypeh]hType}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(hvmh]h)}(hjuh]hvm}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj1hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harg[0] must be 0.h]h)}(hjh]harg[0] must be 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj1hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success, -EPERM if the userspace process does not have CAP_SYS_BOOT, -EINVAL if args[0] is not 0 or any vCPUs have been created. h]h)}(h0 on success, -EPERM if the userspace process does not have CAP_SYS_BOOT, -EINVAL if args[0] is not 0 or any vCPUs have been created.h]h0 on success, -EPERM if the userspace process does not have CAP_SYS_BOOT, -EINVAL if args[0] is not 0 or any vCPUs have been created.}(hjӞhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjϞubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj1hhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhM"ubh)}(hHThis capability disables the NX huge pages mitigation for iTLB MULTIHIT.h]hHThis capability disables the NX huge pages mitigation for iTLB MULTIHIT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(hNThe capability has no effect if the nx_huge_pages module parameter is not set.h]hNThe capability has no effect if the nx_huge_pages module parameter is not set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubh)}(h=This capability may only be set before any vCPUs are created.h]h=This capability may only be set before any vCPUs are created.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj hhubeh}(h] kvm-cap-vm-disable-nx-huge-pagesah ]h"]%7.38 kvm_cap_vm_disable_nx_huge_pagesah$]h&]uh1hhjzhhhhhM"ubh)}(hhh](h)}(h'7.39 KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZEh]h'7.39 KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhhhM"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj9hhhKubj)}(harm64h]h)}(hjLh]harm64}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjJubah}(h]h ]h"]h$]h&]uh1jhj9ubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj6hhubjx)}(hhh](j})}(hTypeh]hType}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjghhhKubj)}(hvmh]h)}(hjzh]hvm}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjxubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj6hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h#arg[0] is the new split chunk size.h]h)}(hjh]h#arg[0] is the new split chunk size.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj6hhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjƟhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjßhhhKubj)}(h:0 on success, -EINVAL if any memslot was already created. h]h)}(h90 on success, -EINVAL if any memslot was already created.h]h90 on success, -EINVAL if any memslot was already created.}(hj؟hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjԟubah}(h]h ]h"]h$]h&]uh1jhjßubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hj6hhubeh}(h]h ]h"]h$]h&]uh1jrhj%hhhhhM"ubh)}(hAThis capability sets the chunk size used in Eager Page Splitting.h]hAThis capability sets the chunk size used in Eager Page Splitting.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj%hhubh)}(hXTEager Page Splitting improves the performance of dirty-logging (used in live migrations) when guest memory is backed by huge-pages. It avoids splitting huge-pages (into PAGE_SIZE pages) on fault, by doing it eagerly when enabling dirty logging (with the KVM_MEM_LOG_DIRTY_PAGES flag for a memory region), or when using KVM_CLEAR_DIRTY_LOG.h]hXTEager Page Splitting improves the performance of dirty-logging (used in live migrations) when guest memory is backed by huge-pages. It avoids splitting huge-pages (into PAGE_SIZE pages) on fault, by doing it eagerly when enabling dirty logging (with the KVM_MEM_LOG_DIRTY_PAGES flag for a memory region), or when using KVM_CLEAR_DIRTY_LOG.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj%hhubh)}(hThe chunk size specifies how many pages to break at a time, using a single allocation for each chunk. Bigger the chunk size, more pages need to be allocated ahead of time.h]hThe chunk size specifies how many pages to break at a time, using a single allocation for each chunk. Bigger the chunk size, more pages need to be allocated ahead of time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj%hhubh)}(hThe chunk size needs to be a valid block size. The list of acceptable block sizes is exposed in KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES as a 64-bit bitmap (each bit describing a block size). The default value is 0, to disable the eager page splitting.h]hThe chunk size needs to be a valid block size. The list of acceptable block sizes is exposed in KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES as a 64-bit bitmap (each bit describing a block size). The default value is 0, to disable the eager page splitting.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj%hhubeh}(h]"kvm-cap-arm-eager-split-chunk-sizeah ]h"]'7.39 kvm_cap_arm_eager_split_chunk_sizeah$]h&]uh1hhjzhhhhhM"ubh)}(hhh](h)}(h7.40 KVM_CAP_EXIT_HYPERCALLh]h7.40 KVM_CAP_EXIT_HYPERCALL}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8hhhhhM"ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjLhhhKubj)}(hx86h]h)}(hj_h]hx86}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj]ubah}(h]h ]h"]h$]h&]uh1jhjLubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjIhhubjx)}(hhh](j})}(hTypeh]hType}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjzhhhKubj)}(hvm h]h)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjubah}(h]h ]h"]h$]h&]uh1jhjzubeh}(h]h ]h"]h$]h&]uh1jwhhhM"hjIhhubeh}(h]h ]h"]h$]h&]uh1jrhj8hhhhhM"ubh)}(hX/This capability, if enabled, will cause KVM to exit to userspace with KVM_EXIT_HYPERCALL exit reason to process some hypercalls. Userspace may fail the hypercall by setting hypercall.ret to EINVAL or may request the hypercall to be retried the next time the guest run by setting hypercall.ret to EAGAIN.h]hX/This capability, if enabled, will cause KVM to exit to userspace with KVM_EXIT_HYPERCALL exit reason to process some hypercalls. Userspace may fail the hypercall by setting hypercall.ret to EINVAL or may request the hypercall to be retried the next time the guest run by setting hypercall.ret to EAGAIN.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj8hhubh)}(hCalling KVM_CHECK_EXTENSION for this capability will return a bitmask of hypercalls that can be configured to exit to userspace. Right now, the only such hypercall is KVM_HC_MAP_GPA_RANGE.h]hCalling KVM_CHECK_EXTENSION for this capability will return a bitmask of hypercalls that can be configured to exit to userspace. Right now, the only such hypercall is KVM_HC_MAP_GPA_RANGE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hj8hhubh)}(hThe argument to KVM_ENABLE_CAP is also a bitmask, and must be a subset of the result of KVM_CHECK_EXTENSION. KVM will forward to userspace the hypercalls whose corresponding bit is in the argument, and return ENOSYS for the others.h]hThe argument to KVM_ENABLE_CAP is also a bitmask, and must be a subset of the result of KVM_CHECK_EXTENSION. KVM will forward to userspace the hypercalls whose corresponding bit is in the argument, and return ENOSYS for the others.}(hjˠhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj8hhubeh}(h]kvm-cap-exit-hypercallah ]h"]7.40 kvm_cap_exit_hypercallah$]h&]uh1hhjzhhhhhM"ubh)}(hhh](h)}(h7.41 KVM_CAP_ARM_SYSTEM_SUSPENDh]h7.41 KVM_CAP_ARM_SYSTEM_SUSPEND}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM #ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hjh]harm64}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM #hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM #hjhhubjx)}(hhh](j})}(hTypeh]hType}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj#hhhKubj)}(hvm h]h)}(hvmh]hvm}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM #hj4ubah}(h]h ]h"]h$]h&]uh1jhj#ubeh}(h]h ]h"]h$]h&]uh1jwhhhM #hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM #ubh)}(hWhen enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request.h]hWhen enabled, KVM will exit to userspace with KVM_EXIT_SYSTEM_EVENT of type KVM_SYSTEM_EVENT_SUSPEND to process the guest suspend request.}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubeh}(h]kvm-cap-arm-system-suspendah ]h"]7.41 kvm_cap_arm_system_suspendah$]h&]uh1hhjzhhhhhM #ubh)}(hhh](h)}(h%7.42 KVM_CAP_ARM_WRITABLE_IMP_ID_REGSh]h%7.42 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhhhhhM#ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hjh]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjáh]hVM}(hjšhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjޡhhhKubj)}(hNoneh]h)}(hjh]hNone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjޡubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hR0 on success, -EINVAL if vCPUs have been created before enabling this capability. h]h)}(hQ0 on success, -EINVAL if vCPUs have been created before enabling this capability.h]hQ0 on success, -EINVAL if vCPUs have been created before enabling this capability.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjnhhhhhM#ubh)}(hThis capability changes the behavior of the registers that identify a PE implementation of the Arm architecture: MIDR_EL1, REVIDR_EL1, and AIDR_EL1. By default, these registers are visible to userspace but treated as invariant.h]hThis capability changes the behavior of the registers that identify a PE implementation of the Arm architecture: MIDR_EL1, REVIDR_EL1, and AIDR_EL1. By default, these registers are visible to userspace but treated as invariant.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjnhhubh)}(hWhen this capability is enabled, KVM allows userspace to change the aforementioned registers before the first KVM_RUN. These registers are VM scoped, meaning that the same set of values are presented on all vCPUs in a given VM.h]hWhen this capability is enabled, KVM allows userspace to change the aforementioned registers before the first KVM_RUN. These registers are VM scoped, meaning that the same set of values are presented on all vCPUs in a given VM.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjnhhubeh}(h] kvm-cap-arm-writable-imp-id-regsah ]h"]%7.42 kvm_cap_arm_writable_imp_id_regsah$]h&]uh1hhjzhhhhhM#ubh)}(hhh](h)}(h!7.43 KVM_CAP_RISCV_MP_STATE_RESETh]h!7.43 KVM_CAP_RISCV_MP_STATE_RESET}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhM$#ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hriscvh]h)}(hjh]hriscv}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&#hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhM&#hjvhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM'#hjvhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjآhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjբhhhKubj)}(hNoneh]h)}(hjh]hNone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(#hjubah}(h]h ]h"]h$]h&]uh1jhjբubeh}(h]h ]h"]h$]h&]uh1jwhhhM(#hjvhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h,0 on success, -EINVAL if arg[0] is not zero h]h)}(h+0 on success, -EINVAL if arg[0] is not zeroh]h+0 on success, -EINVAL if arg[0] is not zero}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM)#hjvhhubeh}(h]h ]h"]h$]h&]uh1jrhjehhhhhM&#ubh)}(hWhen this capability is enabled, KVM resets the VCPU when setting MP_STATE_INIT_RECEIVED through IOCTL. The original MP_STATE is preserved.h]hWhen this capability is enabled, KVM resets the VCPU when setting MP_STATE_INIT_RECEIVED through IOCTL. The original MP_STATE is preserved.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+#hjehhubeh}(h]kvm-cap-riscv-mp-state-resetah ]h"]!7.43 kvm_cap_riscv_mp_state_resetah$]h&]uh1hhjzhhhhhM$#ubh)}(hhh](h)}(h+7.44 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTEDh]h+7.44 KVM_CAP_ARM_CACHEABLE_PFNMAP_SUPPORTED}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhM/#ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjbhhhKubj)}(harm64h]h)}(hjuh]harm64}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1#hjsubah}(h]h ]h"]h$]h&]uh1jhjbubeh}(h]h ]h"]h$]h&]uh1jwhhhM1#hj_hhubjx)}(hhh](j})}(hTargeth]hTarget}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hVMh]h)}(hjh]hVM}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM2#hj_hhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hNone h]h)}(hNoneh]hNone}(hjӣhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3#hjϣubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM3#hj_hhubeh}(h]h ]h"]h$]h&]uh1jrhjNhhhhhM1#ubh)}(hThis capability indicate to the userspace whether a PFNMAP memory region can be safely mapped as cacheable. This relies on the presence of force write back (FWB) feature support on the hardware.h]hThis capability indicate to the userspace whether a PFNMAP memory region can be safely mapped as cacheable. This relies on the presence of force write back (FWB) feature support on the hardware.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5#hjNhhubeh}(h]&kvm-cap-arm-cacheable-pfnmap-supportedah ]h"]+7.44 kvm_cap_arm_cacheable_pfnmap_supportedah$]h&]uh1hhjzhhhhhM/#ubh)}(hhh](h)}(h7.45 KVM_CAP_ARM_SEA_TO_USERh]h7.45 KVM_CAP_ARM_SEA_TO_USER}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM:#ubjs)}(hhh](jx)}(hhh](j})}(h Architectureh]h Architecture}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64h]h)}(hj0h]harm64}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<#hj.ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM<#hjhhubjx)}(hhh](j})}(hTargeth]hTarget}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjKhhhKubj)}(hVMh]h)}(hj^h]hVM}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM=#hj\ubah}(h]h ]h"]h$]h&]uh1jhjKubeh}(h]h ]h"]h$]h&]uh1jwhhhM=#hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>#hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhM>#hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h&0 on success, -EINVAL if unsupported. h]h)}(h%0 on success, -EINVAL if unsupported.h]h%0 on success, -EINVAL if unsupported.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM?#hjhhubeh}(h]h ]h"]h$]h&]uh1jrhj hhhhhM<#ubh)}(hWhen this capability is enabled, KVM may exit to userspace for SEAs taken to EL2 resulting from a guest access. See ``KVM_EXIT_ARM_SEA`` for more information.h](htWhen this capability is enabled, KVM may exit to userspace for SEAs taken to EL2 resulting from a guest access. See }(hjܤhhhNhNubj)}(h``KVM_EXIT_ARM_SEA``h]hKVM_EXIT_ARM_SEA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjܤubh for more information.}(hjܤhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMA#hj hhubeh}(h]kvm-cap-arm-sea-to-userah ]h"]7.45 kvm_cap_arm_sea_to_userah$]h&]uh1hhjzhhhhhM:#ubh)}(hhh](h)}(h7.46 KVM_CAP_S390_USER_OPEREXECh]h7.46 KVM_CAP_S390_USER_OPEREXEC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMF#ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hj+h]hs390}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH#hj)ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMH#hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjFhhhKubj)}(hnone h]h)}(hnoneh]hnone}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMI#hjWubah}(h]h ]h"]h$]h&]uh1jhjFubeh}(h]h ]h"]h$]h&]uh1jwhhhMI#hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMH#ubh)}(hX+When this capability is enabled KVM forwards all operation exceptions that it doesn't handle itself to user space. This also includes the 0x0000 instructions managed by KVM_CAP_S390_USER_INSTR0. This is helpful if user space wants to emulate instructions which are not (yet) implemented in hardware.h]hX-When this capability is enabled KVM forwards all operation exceptions that it doesn’t handle itself to user space. This also includes the 0x0000 instructions managed by KVM_CAP_S390_USER_INSTR0. This is helpful if user space wants to emulate instructions which are not (yet) implemented in hardware.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMK#hjhhubh)}(h^This capability can be enabled dynamically even if VCPUs were already created and are running.h]h^This capability can be enabled dynamically even if VCPUs were already created and are running.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQ#hjhhubeh}(h]kvm-cap-s390-user-operexecah ]h"]7.46 kvm_cap_s390_user_operexecah$]h&]uh1hhjzhhhhhMF#ubh)}(hhh](h)}(h7.47 KVM_CAP_S390_HPAGE_2Gh]h7.47 KVM_CAP_S390_HPAGE_2G}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMU#ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390h]h)}(hjƥh]hs390}(hjȥhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMW#hjĥubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMW#hjhhubjx)}(hhh](j})}(h Parametersh]h Parameters}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMX#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMX#hjhhubjx)}(hhh](j})}(hReturnsh]hReturns}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h0 on success; -EINVAL if hpage_2g module parameter was not set, cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag set; -EBUSY if vCPUs were already created for the VM. h]h)}(h0 on success; -EINVAL if hpage_2g module parameter was not set, cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag set; -EBUSY if vCPUs were already created for the VM.h]h0 on success; -EINVAL if hpage_2g module parameter was not set, cmma is enabled, or the VM has the KVM_VM_S390_UCONTROL flag set; -EBUSY if vCPUs were already created for the VM.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY#hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMY#hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhMW#ubh)}(hXRWith this capability the KVM support for memory backing with 2g pages through hugetlbfs can be enabled for a VM. After the capability is enabled, cmma can't be enabled anymore and pfmfi and the storage key interpretation are disabled. If cmma has already been enabled or the hpage_2g module parameter is not set to 1, -EINVAL is returned.h]hXTWith this capability the KVM support for memory backing with 2g pages through hugetlbfs can be enabled for a VM. After the capability is enabled, cmma can’t be enabled anymore and pfmfi and the storage key interpretation are disabled. If cmma has already been enabled or the hpage_2g module parameter is not set to 1, -EINVAL is returned.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]#hjhhubeh}(h]kvm-cap-s390-hpage-2gah ]h"]7.47 kvm_cap_s390_hpage_2gah$]h&]uh1hhjzhhhhhMU#ubeh}(h]('capabilities-that-can-be-enabled-on-vmsjhzj]zeh ]h"](*7. capabilities that can be enabled on vms cap_enable_vmjjzeh$]h&]uh1hhhhhhhhMj}(j`j^zjjzjSzuj}(jhzj^zj]zjSzuubh)}(hhh](h)}(h8. Other capabilities.h]h8. Other capabilities.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhMd#ubh)}(heThis section lists capabilities that give information about other features of the KVM implementation.h]heThis section lists capabilities that give information about other features of the KVM implementation.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMf#hjehhubh)}(hhh](h)}(h8.1 KVM_CAP_PPC_HWRNGh]h8.1 KVM_CAP_PPC_HWRNG}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMj#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppc h]h)}(hppch]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMl#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMl#hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMl#ubh)}(hX.This capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel has an implementation of the H_RANDOM hypercall backed by a hardware random-number generator. If present, the kernel H_RANDOM handler can be enabled for guest use with the KVM_CAP_PPC_ENABLE_HCALL capability.h]hX.This capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel has an implementation of the H_RANDOM hypercall backed by a hardware random-number generator. If present, the kernel H_RANDOM handler can be enabled for guest use with the KVM_CAP_PPC_ENABLE_HCALL capability.}(hjͦhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMn#hjhhubeh}(h]kvm-cap-ppc-hwrngah ]h"]8.1 kvm_cap_ppc_hwrngah$]h&]uh1hhjehhhhhMj#ubh)}(hhh](h)}(h8.3 KVM_CAP_PPC_MMU_RADIXh]h8.3 KVM_CAP_PPC_MMU_RADIX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMu#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppc h]h)}(hppch]hppc}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMw#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMw#hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMw#ubh)}(hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel can support guests using the radix MMU defined in Power ISA V3.00 (as implemented in the POWER9 processor).h]hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel can support guests using the radix MMU defined in Power ISA V3.00 (as implemented in the POWER9 processor).}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMy#hjhhubeh}(h]kvm-cap-ppc-mmu-radixah ]h"]8.3 kvm_cap_ppc_mmu_radixah$]h&]uh1hhjehhhhhMu#ubh)}(hhh](h)}(h8.4 KVM_CAP_PPC_MMU_HASH_V3h]h8.4 KVM_CAP_PPC_MMU_HASH_V3}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjBhhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjVhhhKubj)}(hppc h]h)}(hppch]hppc}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjgubah}(h]h ]h"]h$]h&]uh1jhjVubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjShhubah}(h]h ]h"]h$]h&]uh1jrhjBhhhhhM#ubh)}(hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel can support guests using the hashed page table MMU defined in Power ISA V3.00 (as implemented in the POWER9 processor), including in-memory segment tables.h]hThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that the kernel can support guests using the hashed page table MMU defined in Power ISA V3.00 (as implemented in the POWER9 processor), including in-memory segment tables.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjBhhubeh}(h]kvm-cap-ppc-mmu-hash-v3ah ]h"]8.4 kvm_cap_ppc_mmu_hash_v3ah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.5 KVM_CAP_MIPS_VZh]h8.5 KVM_CAP_MIPS_VZ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hmips h]h)}(hmipsh]hmips}(hjʧhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjƧubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM#ubh)}(hX3This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that it is available, means that full hardware assisted virtualization capabilities of the hardware are available for use through KVM. An appropriate KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which utilises it.h]hX3This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that it is available, means that full hardware assisted virtualization capabilities of the hardware are available for use through KVM. An appropriate KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which utilises it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hIf KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is available, it means that the VM is using full hardware assisted virtualization capabilities of the hardware. This is useful to check after creating a VM with KVM_VM_MIPS_DEFAULT.h]hIf KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is available, it means that the VM is using full hardware assisted virtualization capabilities of the hardware. This is useful to check after creating a VM with KVM_VM_MIPS_DEFAULT.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hX The value returned by KVM_CHECK_EXTENSION should be compared against known values (see below). All other values are reserved. This is to allow for the possibility of other hardware assisted virtualization implementations which may be incompatible with the MIPS VZ ASE.h]hX The value returned by KVM_CHECK_EXTENSION should be compared against known values (see below). All other values are reserved. This is to allow for the possibility of other hardware assisted virtualization implementations which may be incompatible with the MIPS VZ ASE.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchjubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKJuh1jchjubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj4ubah}(h]h ]h"]h$]h&]uh1jhj1ubj)}(hhh]h)}(hThe trap & emulate implementation is in use to run guest code in user mode. Guest virtual memory segments are rearranged to fit the guest in the user mode address space.h]hThe trap & emulate implementation is in use to run guest code in user mode. Guest virtual memory segments are rearranged to fit the guest in the user mode address space.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjJubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1j~hj.ubj)}(hhh](j)}(hhh]h)}(h1h]h1}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjjubah}(h]h ]h"]h$]h&]uh1jhjgubj)}(hhh]h)}(h}The MIPS VZ ASE is in use, providing full hardware assisted virtualization, including standard guest virtual memory segments.h]h}The MIPS VZ ASE is in use, providing full hardware assisted virtualization, including standard guest virtual memory segments.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjgubeh}(h]h ]h"]h$]h&]uh1j~hj.ubeh}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjhhhhhNubeh}(h]kvm-cap-mips-vzah ]h"]8.5 kvm_cap_mips_vzah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.7 KVM_CAP_MIPS_64BITh]h8.7 KVM_CAP_MIPS_64BIT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjШhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjͨhhhKubj)}(hmips h]h)}(hmipsh]hmips}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjިubah}(h]h ]h"]h$]h&]uh1jhjͨubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjʨhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM#ubh)}(hvThis capability indicates the supported architecture type of the guest, i.e. the supported register and address width.h]hvThis capability indicates the supported architecture type of the guest, i.e. the supported register and address width.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hThe values returned when this capability is checked by KVM_CHECK_EXTENSION on a kvm VM handle correspond roughly to the CP0_Config.AT register field, and should be checked specifically against known values (see below). All other values are reserved.h]hThe values returned when this capability is checked by KVM_CHECK_EXTENSION on a kvm VM handle correspond roughly to the CP0_Config.AT register field, and should be checked specifically against known values (see below). All other values are reserved.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubjZ)}(hhh]j_)}(hhh](jd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jchj!ubjd)}(hhh]h}(h]h ]h"]h$]h&]colwidthKHuh1jchj!ubjz)}(hhh](j)}(hhh](j)}(hhh]h)}(hjh]h0}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj>ubah}(h]h ]h"]h$]h&]uh1jhj;ubj)}(hhh]h)}(hxMIPS32 or microMIPS32. Both registers and addresses are 32-bits wide. It will only be possible to run 32-bit guest code.h]hxMIPS32 or microMIPS32. Both registers and addresses are 32-bits wide. It will only be possible to run 32-bit guest code.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjTubah}(h]h ]h"]h$]h&]uh1jhj;ubeh}(h]h ]h"]h$]h&]uh1j~hj8ubj)}(hhh](j)}(hhh]h)}(hjoh]h1}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]h)}(hMIPS64 or microMIPS64 with access only to 32-bit compatibility segments. Registers are 64-bits wide, but addresses are 32-bits wide. 64-bit guest code may run but cannot access MIPS64 memory segments. It will also be possible to run 32-bit guest code.h]hMIPS64 or microMIPS64 with access only to 32-bit compatibility segments. Registers are 64-bits wide, but addresses are 32-bits wide. 64-bit guest code may run but cannot access MIPS64 memory segments. It will also be possible to run 32-bit guest code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1j~hj8ubj)}(hhh](j)}(hhh]h)}(h2h]h2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]h)}(hMIPS64 or microMIPS64 with access to all address segments. Both registers and addresses are 64-bits wide. It will be possible to run 64-bit or 32-bit guest code.h]hMIPS64 or microMIPS64 with access to all address segments. Both registers and addresses are 64-bits wide. It will be possible to run 64-bit or 32-bit guest code.}(hjĩhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j~hj8ubeh}(h]h ]h"]h$]h&]uh1jyhj!ubeh}(h]h ]h"]h$]h&]colsKuh1j^hjubah}(h]h ]h"]h$]h&]uh1jYhjhhhhhNubeh}(h]kvm-cap-mips-64bitah ]h"]8.7 kvm_cap_mips_64bitah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.9 KVM_CAP_ARM_USER_IRQh]h8.9 KVM_CAP_ARM_USER_IRQ}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(harm64 h]h)}(harm64h]harm64}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hj hhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM#ubh)}(hXThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that if userspace creates a VM without an in-kernel interrupt controller, it will be notified of changes to the output level of in-kernel emulated devices, which can generate virtual interrupts, presented to the VM. For such VMs, on every return to userspace, the kernel updates the vcpu's run->s.regs.device_irq_level field to represent the actual output level of the device.h]hXThis capability, if KVM_CHECK_EXTENSION indicates that it is available, means that if userspace creates a VM without an in-kernel interrupt controller, it will be notified of changes to the output level of in-kernel emulated devices, which can generate virtual interrupts, presented to the VM. For such VMs, on every return to userspace, the kernel updates the vcpu’s run->s.regs.device_irq_level field to represent the actual output level of the device.}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hXWhenever kvm detects a change in the device output level, kvm guarantees at least one return to userspace before running the VM. This exit could either be a KVM_EXIT_INTR or any other exit event, like KVM_EXIT_MMIO. This way, userspace can always sample the device output level and re-compute the state of the userspace interrupt controller. Userspace should always check the state of run->s.regs.device_irq_level on every kvm exit. The value in run->s.regs.device_irq_level can represent both level and edge triggered interrupt signals, depending on the device. Edge triggered interrupt signals will exit to userspace with the bit in run->s.regs.device_irq_level set exactly once per edge signal.h]hXWhenever kvm detects a change in the device output level, kvm guarantees at least one return to userspace before running the VM. This exit could either be a KVM_EXIT_INTR or any other exit event, like KVM_EXIT_MMIO. This way, userspace can always sample the device output level and re-compute the state of the userspace interrupt controller. Userspace should always check the state of run->s.regs.device_irq_level on every kvm exit. The value in run->s.regs.device_irq_level can represent both level and edge triggered interrupt signals, depending on the device. Edge triggered interrupt signals will exit to userspace with the bit in run->s.regs.device_irq_level set exactly once per edge signal.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hsThe field run->s.regs.device_irq_level is available independent of run->kvm_valid_regs or run->kvm_dirty_regs bits.h]hsThe field run->s.regs.device_irq_level is available independent of run->kvm_valid_regs or run->kvm_dirty_regs bits.}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hIf KVM_CAP_ARM_USER_IRQ is supported, the KVM_CHECK_EXTENSION ioctl returns a number larger than 0 indicating the version of this capability is implemented and thereby which bits in run->s.regs.device_irq_level can signal values.h]hIf KVM_CAP_ARM_USER_IRQ is supported, the KVM_CHECK_EXTENSION ioctl returns a number larger than 0 indicating the version of this capability is implemented and thereby which bits in run->s.regs.device_irq_level can signal values.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hJCurrently the following bits are defined for the device_irq_level bitmap::h]hICurrently the following bits are defined for the device_irq_level bitmap:}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubj8)}(hKVM_CAP_ARM_USER_IRQ >= 1: KVM_ARM_DEV_EL1_VTIMER - EL1 virtual timer KVM_ARM_DEV_EL1_PTIMER - EL1 physical timer KVM_ARM_DEV_PMU - ARM PMU overflow interrupt signalh]hKVM_CAP_ARM_USER_IRQ >= 1: KVM_ARM_DEV_EL1_VTIMER - EL1 virtual timer KVM_ARM_DEV_EL1_PTIMER - EL1 physical timer KVM_ARM_DEV_PMU - ARM PMU overflow interrupt signal}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM#hjhhubh)}(hFuture versions of kvm may implement additional events. These will get indicated by returning a higher number from KVM_CHECK_EXTENSION and will be listed above.h]hFuture versions of kvm may implement additional events. These will get indicated by returning a higher number from KVM_CHECK_EXTENSION and will be listed above.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubeh}(h]kvm-cap-arm-user-irqah ]h"]8.9 kvm_cap_arm_user_irqah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.10 KVM_CAP_PPC_SMT_POSSIBLEh]h8.10 KVM_CAP_PPC_SMT_POSSIBLE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjêhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppc h]h)}(hppch]hppc}(hjժhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjѪubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM#ubh)}(hQuerying this capability returns a bitmap indicating the possible virtual SMT modes that can be set using KVM_CAP_PPC_SMT. If bit N (counting from the right) is set, then a virtual SMT mode of 2^N is available.h]hQuerying this capability returns a bitmap indicating the possible virtual SMT modes that can be set using KVM_CAP_PPC_SMT. If bit N (counting from the right) is set, then a virtual SMT mode of 2^N is available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubeh}(h]kvm-cap-ppc-smt-possibleah ]h"]8.10 kvm_cap_ppc_smt_possibleah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.12 KVM_CAP_HYPERV_VP_INDEXh]h8.12 KVM_CAP_HYPERV_VP_INDEX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM#ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86 h]h)}(hx86h]hx86}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM#hjhhubah}(h]h ]h"]h$]h&]uh1jrhj hhhhhM#ubh)}(hX&This capability indicates that userspace can load HV_X64_MSR_VP_INDEX msr. Its value is used to denote the target vcpu for a SynIC interrupt. For compatibility, KVM initializes this msr to KVM's internal vcpu index. When this capability is absent, userspace can still query this msr's value.h]hX*This capability indicates that userspace can load HV_X64_MSR_VP_INDEX msr. Its value is used to denote the target vcpu for a SynIC interrupt. For compatibility, KVM initializes this msr to KVM’s internal vcpu index. When this capability is absent, userspace can still query this msr’s value.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hj hhubeh}(h]kvm-cap-hyperv-vp-indexah ]h"]8.12 kvm_cap_hyperv_vp_indexah$]h&]uh1hhjehhhhhM#ubh)}(hhh](h)}(h8.13 KVM_CAP_S390_AIS_MIGRATIONh]h8.13 KVM_CAP_S390_AIS_MIGRATION}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjjhhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj~hhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhj~ubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hj{hhubah}(h]h ]h"]h$]h&]uh1jrhjjhhhhhM$ubh)}(hThis capability indicates if the flic device will be able to get/set the AIS states for migration via the KVM_DEV_FLIC_AISM_ALL attribute and allows to discover this without having to create a flic device.h]hThis capability indicates if the flic device will be able to get/set the AIS states for migration via the KVM_DEV_FLIC_AISM_ALL attribute and allows to discover this without having to create a flic device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjjhhubeh}(h]kvm-cap-s390-ais-migrationah ]h"]8.13 kvm_cap_s390_ais_migrationah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.14 KVM_CAP_S390_PSWh]h8.14 KVM_CAP_S390_PSW}(hj̫hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjɫhhhhhM $ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjݫhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM $hjubah}(h]h ]h"]h$]h&]uh1jhjݫubeh}(h]h ]h"]h$]h&]uh1jwhhhM $hjګhhubah}(h]h ]h"]h$]h&]uh1jrhjɫhhhhhM $ubh)}(hLThis capability indicates that the PSW is exposed via the kvm_run structure.h]hLThis capability indicates that the PSW is exposed via the kvm_run structure.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjɫhhubeh}(h]kvm-cap-s390-pswah ]h"]8.14 kvm_cap_s390_pswah$]h&]uh1hhjehhhhhM $ubh)}(hhh](h)}(h8.15 KVM_CAP_S390_GMAPh]h8.15 KVM_CAP_S390_GMAP}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj<hhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjMubah}(h]h ]h"]h$]h&]uh1jhj<ubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hj9hhubah}(h]h ]h"]h$]h&]uh1jrhj(hhhhhM$ubh)}(hThis capability indicates that the user space memory used as guest mapping can be anywhere in the user memory address space, as long as the memory slots are aligned and sized to a segment (1MB) boundary.h]hThis capability indicates that the user space memory used as guest mapping can be anywhere in the user memory address space, as long as the memory slots are aligned and sized to a segment (1MB) boundary.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj(hhubeh}(h]kvm-cap-s390-gmapah ]h"]8.15 kvm_cap_s390_gmapah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.16 KVM_CAP_S390_COWh]h8.16 KVM_CAP_S390_COW}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM$ubh)}(hThis capability indicates that the user space memory used as guest mapping can use copy-on-write semantics as well as dirty pages tracking via read-only page tables.h]hThis capability indicates that the user space memory used as guest mapping can use copy-on-write semantics as well as dirty pages tracking via read-only page tables.}(hjЬhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubeh}(h]kvm-cap-s390-cowah ]h"]8.16 kvm_cap_s390_cowah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.17 KVM_CAP_S390_BPBh]h8.17 KVM_CAP_S390_BPB}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&$hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM&$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM&$ubh)}(hThis capability indicates that kvm will implement the interfaces to handle reset, migration and nested KVM for branch prediction blocking. The stfle facility 82 should not be provided to the guest without this capability.h]hThis capability indicates that kvm will implement the interfaces to handle reset, migration and nested KVM for branch prediction blocking. The stfle facility 82 should not be provided to the guest without this capability.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM($hjhhubeh}(h]kvm-cap-s390-bpbah ]h"]8.17 kvm_cap_s390_bpbah$]h&]uh1hhjehhhhhM$$ubh)}(hhh](h)}(h8.18 KVM_CAP_HYPERV_TLBFLUSHh]h8.18 KVM_CAP_HYPERV_TLBFLUSH}(hjHhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjEhhhhhM-$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjYhhhKubj)}(hx86 h]h)}(hx86h]hx86}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/$hjjubah}(h]h ]h"]h$]h&]uh1jhjYubeh}(h]h ]h"]h$]h&]uh1jwhhhM/$hjVhhubah}(h]h ]h"]h$]h&]uh1jrhjEhhhhhM/$ubh)}(hThis capability indicates that KVM supports paravirtualized Hyper-V TLB Flush hypercalls: HvFlushVirtualAddressSpace, HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressList, HvFlushVirtualAddressListEx.h]hThis capability indicates that KVM supports paravirtualized Hyper-V TLB Flush hypercalls: HvFlushVirtualAddressSpace, HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressList, HvFlushVirtualAddressListEx.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1$hjEhhubeh}(h]kvm-cap-hyperv-tlbflushah ]h"]8.18 kvm_cap_hyperv_tlbflushah$]h&]uh1hhjehhhhhM-$ubh)}(hhh](h)}(h"8.19 KVM_CAP_ARM_INJECT_SERROR_ESRh]h"8.19 KVM_CAP_ARM_INJECT_SERROR_ESR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM7$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(harm64 h]h)}(harm64h]harm64}(hjͭhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9$hjɭubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM9$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM9$ubh)}(hXThis capability indicates that userspace can specify (via the KVM_SET_VCPU_EVENTS ioctl) the syndrome value reported to the guest when it takes a virtual SError interrupt exception. If KVM advertises this capability, userspace can only specify the ISS field for the ESR syndrome. Other parts of the ESR, such as the EC are generated by the CPU when the exception is taken. If this virtual SError is taken to EL1 using AArch64, this value will be reported in the ISS field of ESR_ELx.h]hXThis capability indicates that userspace can specify (via the KVM_SET_VCPU_EVENTS ioctl) the syndrome value reported to the guest when it takes a virtual SError interrupt exception. If KVM advertises this capability, userspace can only specify the ISS field for the ESR syndrome. Other parts of the ESR, such as the EC are generated by the CPU when the exception is taken. If this virtual SError is taken to EL1 using AArch64, this value will be reported in the ISS field of ESR_ELx.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;$hjhhubh)}(h)See KVM_CAP_VCPU_EVENTS for more details.h]h)See KVM_CAP_VCPU_EVENTS for more details.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC$hjhhubeh}(h]kvm-cap-arm-inject-serror-esrah ]h"]"8.19 kvm_cap_arm_inject_serror_esrah$]h&]uh1hhjehhhhhM7$ubh)}(hhh](h)}(h8.20 KVM_CAP_HYPERV_SEND_IPIh]h8.20 KVM_CAP_HYPERV_SEND_IPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMF$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj%hhhKubj)}(hx86 h]h)}(hx86h]hx86}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMH$hj6ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jwhhhMH$hj"hhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMH$ubh)}(hThis capability indicates that KVM supports paravirtualized Hyper-V IPI send hypercalls: HvCallSendSyntheticClusterIpi, HvCallSendSyntheticClusterIpiEx.h]hThis capability indicates that KVM supports paravirtualized Hyper-V IPI send hypercalls: HvCallSendSyntheticClusterIpi, HvCallSendSyntheticClusterIpiEx.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJ$hjhhubeh}(h]kvm-cap-hyperv-send-ipiah ]h"]8.20 kvm_cap_hyperv_send_ipiah$]h&]uh1hhjehhhhhMF$ubh)}(hhh](h)}(h8.22 KVM_CAP_S390_VCPU_RESETSh]h8.22 KVM_CAP_S390_VCPU_RESETS}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhjphhhhhMO$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQ$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMQ$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjphhhhhMQ$ubh)}(hgThis capability indicates that the KVM_S390_NORMAL_RESET and KVM_S390_CLEAR_RESET ioctls are available.h]hgThis capability indicates that the KVM_S390_NORMAL_RESET and KVM_S390_CLEAR_RESET ioctls are available.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMS$hjphhubeh}(h]kvm-cap-s390-vcpu-resetsah ]h"]8.22 kvm_cap_s390_vcpu_resetsah$]h&]uh1hhjehhhhhMO$ubh)}(hhh](h)}(h8.23 KVM_CAP_S390_PROTECTEDh]h8.23 KVM_CAP_S390_PROTECTED}(hjҮhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjϮhhhhhMW$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMY$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMY$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjϮhhhhhMY$ubh)}(hXThis capability indicates that the Ultravisor has been initialized and KVM can therefore start protected VMs. This capability governs the KVM_S390_PV_COMMAND ioctl and the KVM_MP_STATE_LOAD MP_STATE. KVM_SET_MP_STATE can fail for protected guests when the state change is invalid.h]hXThis capability indicates that the Ultravisor has been initialized and KVM can therefore start protected VMs. This capability governs the KVM_S390_PV_COMMAND ioctl and the KVM_MP_STATE_LOAD MP_STATE. KVM_SET_MP_STATE can fail for protected guests when the state change is invalid.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[$hjϮhhubeh}(h]kvm-cap-s390-protectedah ]h"]8.23 kvm_cap_s390_protectedah$]h&]uh1hhjehhhhhMW$ubh)}(hhh](h)}(h8.24 KVM_CAP_STEAL_TIMEh]h8.24 KVM_CAP_STEAL_TIME}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhhhMb$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjBhhhKubj)}(h arm64, x86 h]h)}(h arm64, x86h]h arm64, x86}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd$hjSubah}(h]h ]h"]h$]h&]uh1jhjBubeh}(h]h ]h"]h$]h&]uh1jwhhhMd$hj?hhubah}(h]h ]h"]h$]h&]uh1jrhj.hhhhhMd$ubh)}(hXThis capability indicates that KVM supports steal time accounting. When steal time accounting is supported it may be enabled with architecture-specific interfaces. This capability and the architecture- specific interfaces must be consistent, i.e. if one says the feature is supported, than the other should as well and vice versa. For arm64 see Documentation/virt/kvm/devices/vcpu.rst "KVM_ARM_VCPU_PVTIME_CTRL". For x86 see Documentation/virt/kvm/x86/msr.rst "MSR_KVM_STEAL_TIME".h]hXThis capability indicates that KVM supports steal time accounting. When steal time accounting is supported it may be enabled with architecture-specific interfaces. This capability and the architecture- specific interfaces must be consistent, i.e. if one says the feature is supported, than the other should as well and vice versa. For arm64 see Documentation/virt/kvm/devices/vcpu.rst “KVM_ARM_VCPU_PVTIME_CTRL”. For x86 see Documentation/virt/kvm/x86/msr.rst “MSR_KVM_STEAL_TIME”.}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMf$hj.hhubeh}(h]kvm-cap-steal-timeah ]h"]8.24 kvm_cap_steal_timeah$]h&]uh1hhjehhhhhMb$ubh)}(hhh](h)}(h8.25 KVM_CAP_S390_DIAG318h]h8.25 KVM_CAP_S390_DIAG318}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMo$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMq$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMq$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMq$ubh)}(hXThis capability enables a guest to set information about its control program (i.e. guest kernel type and version). The information is helpful during system/firmware service events, providing additional data about the guest environments running on the machine.h]hXThis capability enables a guest to set information about its control program (i.e. guest kernel type and version). The information is helpful during system/firmware service events, providing additional data about the guest environments running on the machine.}(hj֯hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMs$hjhhubh)}(hXThe information is associated with the DIAGNOSE 0x318 instruction, which sets an 8-byte value consisting of a one-byte Control Program Name Code (CPNC) and a 7-byte Control Program Version Code (CPVC). The CPNC determines what environment the control program is running in (e.g. Linux, z/VM...), and the CPVC is used for information specific to OS (e.g. Linux version, Linux distribution...)h]hXThe information is associated with the DIAGNOSE 0x318 instruction, which sets an 8-byte value consisting of a one-byte Control Program Name Code (CPNC) and a 7-byte Control Program Version Code (CPVC). The CPNC determines what environment the control program is running in (e.g. Linux, z/VM...), and the CPVC is used for information specific to OS (e.g. Linux version, Linux distribution...)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMx$hjhhubh)}(hIf this capability is available, then the CPNC and CPVC can be synchronized between KVM and userspace via the sync regs mechanism (KVM_SYNC_DIAG318).h]hIf this capability is available, then the CPNC and CPVC can be synchronized between KVM and userspace via the sync regs mechanism (KVM_SYNC_DIAG318).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubeh}(h]kvm-cap-s390-diag318ah ]h"]8.25 kvm_cap_s390_diag318ah$]h&]uh1hhjehhhhhMo$ubh)}(hhh](h)}(h8.26 KVM_CAP_X86_USER_SPACE_MSRh]h8.26 KVM_CAP_X86_USER_SPACE_MSR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86 h]h)}(hx86h]hx86}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM$ubh)}(hX?This capability indicates that KVM supports deflection of MSR reads and writes to user space. It can be enabled on a VM level. If enabled, MSR accesses that would usually trigger a #GP by KVM into the guest will instead get bounced to user space through the KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR exit notifications.h]hX?This capability indicates that KVM supports deflection of MSR reads and writes to user space. It can be enabled on a VM level. If enabled, MSR accesses that would usually trigger a #GP by KVM into the guest will instead get bounced to user space through the KVM_EXIT_X86_RDMSR and KVM_EXIT_X86_WRMSR exit notifications.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubeh}(h]id24ah ]h"]8.26 kvm_cap_x86_user_space_msrah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.27 KVM_CAP_X86_MSR_FILTERh]h8.27 KVM_CAP_X86_MSR_FILTER}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjghhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj{hhhKubj)}(hx86 h]h)}(hx86h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhj{ubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjxhhubah}(h]h ]h"]h$]h&]uh1jrhjghhhhhM$ubh)}(hXThis capability indicates that KVM supports that accesses to user defined MSRs may be rejected. With this capability exposed, KVM exports new VM ioctl KVM_X86_SET_MSR_FILTER which user space can call to specify bitmaps of MSR ranges that KVM should deny access to.h]hXThis capability indicates that KVM supports that accesses to user defined MSRs may be rejected. With this capability exposed, KVM exports new VM ioctl KVM_X86_SET_MSR_FILTER which user space can call to specify bitmaps of MSR ranges that KVM should deny access to.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjghhubh)}(hIn combination with KVM_CAP_X86_USER_SPACE_MSR, this allows user space to trap and emulate MSRs that are outside of the scope of KVM as well as limit the attack surface on KVM's MSR emulation code.h]hIn combination with KVM_CAP_X86_USER_SPACE_MSR, this allows user space to trap and emulate MSRs that are outside of the scope of KVM as well as limit the attack surface on KVM’s MSR emulation code.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjghhubeh}(h]kvm-cap-x86-msr-filterah ]h"]8.27 kvm_cap_x86_msr_filterah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.30 KVM_CAP_XEN_HVMh]h8.30 KVM_CAP_XEN_HVM}(hjװhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj԰hhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86 h]h)}(hx86h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjhhubah}(h]h ]h"]h$]h&]uh1jrhj԰hhhhhM$ubh)}(hhThis capability indicates the features that Xen supports for hosting Xen PVHVM guests. Valid flags are::h]hgThis capability indicates the features that Xen supports for hosting Xen PVHVM guests. Valid flags are:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubj8)}(hX#define KVM_XEN_HVM_CONFIG_HYPERCALL_MSR (1 << 0) #define KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL (1 << 1) #define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2) #define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3) #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4) #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5) #define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6) #define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE (1 << 7)h]hX#define KVM_XEN_HVM_CONFIG_HYPERCALL_MSR (1 << 0) #define KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL (1 << 1) #define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2) #define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3) #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4) #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5) #define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6) #define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE (1 << 7)}hj+sbah}(h]h ]h"]h$]h&]hhuh1j7hhhM$hj԰hhubh)}(hThe KVM_XEN_HVM_CONFIG_HYPERCALL_MSR flag indicates that the KVM_XEN_HVM_CONFIG ioctl is available, for the guest to set its hypercall page.h]hThe KVM_XEN_HVM_CONFIG_HYPERCALL_MSR flag indicates that the KVM_XEN_HVM_CONFIG ioctl is available, for the guest to set its hypercall page.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hX*If KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL is also set, the same flag may also be provided in the flags to KVM_XEN_HVM_CONFIG, without providing hypercall page contents, to request that KVM generate hypercall page content automatically and also enable interception of guest hypercalls with KVM_EXIT_XEN.h]hX*If KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL is also set, the same flag may also be provided in the flags to KVM_XEN_HVM_CONFIG, without providing hypercall page contents, to request that KVM generate hypercall page content automatically and also enable interception of guest hypercalls with KVM_EXIT_XEN.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hX7The KVM_XEN_HVM_CONFIG_SHARED_INFO flag indicates the availability of the KVM_XEN_HVM_SET_ATTR, KVM_XEN_HVM_GET_ATTR, KVM_XEN_VCPU_SET_ATTR and KVM_XEN_VCPU_GET_ATTR ioctls, as well as the delivery of exception vectors for event channel upcalls when the evtchn_upcall_pending field of a vcpu's vcpu_info is set.h]hX9The KVM_XEN_HVM_CONFIG_SHARED_INFO flag indicates the availability of the KVM_XEN_HVM_SET_ATTR, KVM_XEN_HVM_GET_ATTR, KVM_XEN_VCPU_SET_ATTR and KVM_XEN_VCPU_GET_ATTR ioctls, as well as the delivery of exception vectors for event channel upcalls when the evtchn_upcall_pending field of a vcpu’s vcpu_info is set.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hThe KVM_XEN_HVM_CONFIG_RUNSTATE flag indicates that the runstate-related features KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR/_CURRENT/_DATA/_ADJUST are supported by the KVM_XEN_VCPU_SET_ATTR/KVM_XEN_VCPU_GET_ATTR ioctls.h]hThe KVM_XEN_HVM_CONFIG_RUNSTATE flag indicates that the runstate-related features KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR/_CURRENT/_DATA/_ADJUST are supported by the KVM_XEN_VCPU_SET_ATTR/KVM_XEN_VCPU_GET_ATTR ioctls.}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hThe KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL flag indicates that IRQ routing entries of the type KVM_IRQ_ROUTING_XEN_EVTCHN are supported, with the priority field set to indicate 2 level event channel delivery.h]hThe KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL flag indicates that IRQ routing entries of the type KVM_IRQ_ROUTING_XEN_EVTCHN are supported, with the priority field set to indicate 2 level event channel delivery.}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hXThe KVM_XEN_HVM_CONFIG_EVTCHN_SEND flag indicates that KVM supports injecting event channel events directly into the guest with the KVM_XEN_HVM_EVTCHN_SEND ioctl. It also indicates support for the KVM_XEN_ATTR_TYPE_EVTCHN/XEN_VERSION HVM attributes and the KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID/TIMER/UPCALL_VECTOR vCPU attributes. related to event channel delivery, timers, and the XENVER_version interception.h]hXThe KVM_XEN_HVM_CONFIG_EVTCHN_SEND flag indicates that KVM supports injecting event channel events directly into the guest with the KVM_XEN_HVM_EVTCHN_SEND ioctl. It also indicates support for the KVM_XEN_ATTR_TYPE_EVTCHN/XEN_VERSION HVM attributes and the KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID/TIMER/UPCALL_VECTOR vCPU attributes. related to event channel delivery, timers, and the XENVER_version interception.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hX)The KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG flag indicates that KVM supports the KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG attribute in the KVM_XEN_SET_ATTR and KVM_XEN_GET_ATTR ioctls. This controls whether KVM will set the XEN_RUNSTATE_UPDATE flag in guest memory mapped vcpu_runstate_info during updates of the runstate information. Note that versions of KVM which support the RUNSTATE feature above, but not the RUNSTATE_UPDATE_FLAG feature, will always set the XEN_RUNSTATE_UPDATE flag when updating the guest structure, which is perhaps counterintuitive. When this flag is advertised, KVM will behave more correctly, not using the XEN_RUNSTATE_UPDATE flag until/unless specifically enabled (by the guest making the hypercall, causing the VMM to enable the KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG attribute).h]hX)The KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG flag indicates that KVM supports the KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG attribute in the KVM_XEN_SET_ATTR and KVM_XEN_GET_ATTR ioctls. This controls whether KVM will set the XEN_RUNSTATE_UPDATE flag in guest memory mapped vcpu_runstate_info during updates of the runstate information. Note that versions of KVM which support the RUNSTATE feature above, but not the RUNSTATE_UPDATE_FLAG feature, will always set the XEN_RUNSTATE_UPDATE flag when updating the guest structure, which is perhaps counterintuitive. When this flag is advertised, KVM will behave more correctly, not using the XEN_RUNSTATE_UPDATE flag until/unless specifically enabled (by the guest making the hypercall, causing the VMM to enable the KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG attribute).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubh)}(hThe KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE flag indicates that KVM supports clearing the PVCLOCK_TSC_STABLE_BIT flag in Xen pvclock sources. This will be done when the KVM_CAP_XEN_HVM ioctl sets the KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE flag.h]hThe KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE flag indicates that KVM supports clearing the PVCLOCK_TSC_STABLE_BIT flag in Xen pvclock sources. This will be done when the KVM_CAP_XEN_HVM ioctl sets the KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE flag.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj԰hhubeh}(h]kvm-cap-xen-hvmah ]h"]8.30 kvm_cap_xen_hvmah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.31 KVM_CAP_SPAPR_MULTITCEh]h8.31 KVM_CAP_SPAPR_MULTITCE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjȱhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjűhhhKubj)}(hppch]h)}(hjرh]hppc}(hjڱhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjֱubah}(h]h ]h"]h$]h&]uh1jhjűubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hj±hhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm h]h)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hj±hhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM$ubh)}(hXThis capability means the kernel is capable of handling hypercalls H_PUT_TCE_INDIRECT and H_STUFF_TCE without passing those into the user space. This significantly accelerates DMA operations for PPC KVM guests. User space should expect that its handlers for these hypercalls are not going to be called if user space previously registered LIOBN in KVM (via KVM_CREATE_SPAPR_TCE or similar calls).h]hXThis capability means the kernel is capable of handling hypercalls H_PUT_TCE_INDIRECT and H_STUFF_TCE without passing those into the user space. This significantly accelerates DMA operations for PPC KVM guests. User space should expect that its handlers for these hypercalls are not going to be called if user space previously registered LIOBN in KVM (via KVM_CREATE_SPAPR_TCE or similar calls).}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubh)}(hX In order to enable H_PUT_TCE_INDIRECT and H_STUFF_TCE use in the guest, user space might have to advertise it for the guest. For example, IBM pSeries (sPAPR) guest starts using them if "hcall-multi-tce" is present in the "ibm,hypertas-functions" device-tree property.h]hXIn order to enable H_PUT_TCE_INDIRECT and H_STUFF_TCE use in the guest, user space might have to advertise it for the guest. For example, IBM pSeries (sPAPR) guest starts using them if “hcall-multi-tce” is present in the “ibm,hypertas-functions” device-tree property.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubh)}(hXThe hypercalls mentioned above may or may not be processed successfully in the kernel based fast path. If they can not be handled by the kernel, they will get passed on to user space. So user space still has to have an implementation for these despite the in kernel acceleration.h]hXThe hypercalls mentioned above may or may not be processed successfully in the kernel based fast path. If they can not be handled by the kernel, they will get passed on to user space. So user space still has to have an implementation for these despite the in kernel acceleration.}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubh)}(h"This capability is always enabled.h]h"This capability is always enabled.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubeh}(h]kvm-cap-spapr-multitceah ]h"]8.31 kvm_cap_spapr_multitceah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.32 KVM_CAP_PTP_KVMh]h8.32 KVM_CAP_PTP_KVM}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhhM$ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj|hhhKubj)}(harm64 h]h)}(harm64h]harm64}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1jwhhhM$hjyhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhhM$ubh)}(hThis capability indicates that the KVM virtual PTP service is supported in the host. A VMM can check whether the service is available to the guest on migration.h]hThis capability indicates that the KVM virtual PTP service is supported in the host. A VMM can check whether the service is available to the guest on migration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjhhhubeh}(h]kvm-cap-ptp-kvmah ]h"]8.32 kvm_cap_ptp_kvmah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h 8.37 KVM_CAP_S390_PROTECTED_DUMPh]h 8.37 KVM_CAP_S390_PROTECTED_DUMP}(hjʲhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDzhhhhhM$ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj޲hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj۲hhhKubj)}(hs390h]h)}(hjh]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjubah}(h]h ]h"]h$]h&]uh1jhj۲ubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hjزhhubjx)}(hhh](j})}(hTypeh]hType}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hvm h]h)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhM%hjزhhubeh}(h]h ]h"]h$]h&]uh1jrhjDzhhhhhM%ubh)}(hXBThis capability indicates that KVM and the Ultravisor support dumping PV guests. The `KVM_PV_DUMP` command is available for the `KVM_S390_PV_COMMAND` ioctl and the `KVM_PV_INFO` command provides dump related UV data. Also the vcpu ioctl `KVM_S390_PV_CPU_COMMAND` is available and supports the `KVM_PV_DUMP_CPU` subcommand.h](hUThis capability indicates that KVM and the Ultravisor support dumping PV guests. The }(hj>hhhNhNubj,)}(h `KVM_PV_DUMP`h]h KVM_PV_DUMP}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj>ubh command is available for the }(hj>hhhNhNubj,)}(h`KVM_S390_PV_COMMAND`h]hKVM_S390_PV_COMMAND}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj>ubh ioctl and the }(hj>hhhNhNubj,)}(h `KVM_PV_INFO`h]h KVM_PV_INFO}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj>ubh< command provides dump related UV data. Also the vcpu ioctl }(hj>hhhNhNubj,)}(h`KVM_S390_PV_CPU_COMMAND`h]hKVM_S390_PV_CPU_COMMAND}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj>ubh is available and supports the }(hj>hhhNhNubj,)}(h`KVM_PV_DUMP_CPU`h]hKVM_PV_DUMP_CPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j,hj>ubh subcommand.}(hj>hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjDzhhubeh}(h]kvm-cap-s390-protected-dumpah ]h"] 8.37 kvm_cap_s390_protected_dumpah$]h&]uh1hhjehhhhhM$ubh)}(hhh](h)}(h8.39 KVM_CAP_S390_CPU_TOPOLOGYh]h8.39 KVM_CAP_S390_CPU_TOPOLOGY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM %ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjųhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj³hhhKubj)}(hs390h]h)}(hjճh]hs390}(hj׳hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM %hjӳubah}(h]h ]h"]h$]h&]uh1jhj³ubeh}(h]h ]h"]h$]h&]uh1jwhhhM %hjhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hvm h]h)}(hvmh]hvm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM %hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM %hjhhubeh}(h]h ]h"]h$]h&]uh1jrhjhhhhhM %ubh)}(hX<This capability indicates that KVM will provide the S390 CPU Topology facility which consist of the interpretation of the PTF instruction for the function code 2 along with interception and forwarding of both the PTF instruction with function codes 0 or 1 and the STSI(15,1,x) instruction to the userland hypervisor.h]hX<This capability indicates that KVM will provide the S390 CPU Topology facility which consist of the interpretation of the PTF instruction for the function code 2 along with interception and forwarding of both the PTF instruction with function codes 0 or 1 and the STSI(15,1,x) instruction to the userland hypervisor.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubh)}(hkThe stfle facility 11, CPU Topology facility, should not be indicated to the guest without this capability.h]hkThe stfle facility 11, CPU Topology facility, should not be indicated to the guest without this capability.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubh)}(hWhen this capability is present, KVM provides a new attribute group on vm fd, KVM_S390_VM_CPU_TOPOLOGY. This new attribute allows to get, set or clear the Modified Change Topology Report (MTCR) bit of the SCA through the kvm_device_attr structure.h]hWhen this capability is present, KVM provides a new attribute group on vm fd, KVM_S390_VM_CPU_TOPOLOGY. This new attribute allows to get, set or clear the Modified Change Topology Report (MTCR) bit of the SCA through the kvm_device_attr structure.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubh)}(hWhen getting the Modified Change Topology Report value, the attr->addr must point to a byte where the value will be stored or retrieved from.h]hWhen getting the Modified Change Topology Report value, the attr->addr must point to a byte where the value will be stored or retrieved from.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubeh}(h]kvm-cap-s390-cpu-topologyah ]h"]8.39 kvm_cap_s390_cpu_topologyah$]h&]uh1hhjehhhhhM %ubh)}(hhh](h)}(h8.41 KVM_CAP_VM_TYPESh]h8.41 KVM_CAP_VM_TYPES}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhhhM"%ubjs)}(hhh](jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjyhhhKubj)}(hx86h]h)}(hjh]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$%hjubah}(h]h ]h"]h$]h&]uh1jhjyubeh}(h]h ]h"]h$]h&]uh1jwhhhM$%hjvhhubjx)}(hhh](j})}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(h system ioctl h]h)}(h system ioctlh]h system ioctl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhM%%hjvhhubeh}(h]h ]h"]h$]h&]uh1jrhjehhhhhM$%ubh)}(hThis capability returns a bitmap of support VM types. The 1-setting of bit @n means the VM type with value @n is supported. Possible values of @n are::h]hThis capability returns a bitmap of support VM types. The 1-setting of bit @n means the VM type with value @n is supported. Possible values of @n are:}(hjܴhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'%hjehhubj8)}(h#define KVM_X86_DEFAULT_VM 0 #define KVM_X86_SW_PROTECTED_VM 1 #define KVM_X86_SEV_VM 2 #define KVM_X86_SEV_ES_VM 3 #define KVM_X86_SNP_VM 4 #define KVM_X86_TDX_VM 5h]h#define KVM_X86_DEFAULT_VM 0 #define KVM_X86_SW_PROTECTED_VM 1 #define KVM_X86_SEV_VM 2 #define KVM_X86_SEV_ES_VM 3 #define KVM_X86_SNP_VM 4 #define KVM_X86_TDX_VM 5}hjsbah}(h]h ]h"]h$]h&]hhuh1j7hhhM*%hjehhubh)}(hNote, KVM_X86_SW_PROTECTED_VM is currently only for development and testing. Do not use KVM_X86_SW_PROTECTED_VM for "real" VMs, and especially not in production. The behavior and effective ABI for software-protected VMs is unstable.h]hNote, KVM_X86_SW_PROTECTED_VM is currently only for development and testing. Do not use KVM_X86_SW_PROTECTED_VM for “real” VMs, and especially not in production. The behavior and effective ABI for software-protected VMs is unstable.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1%hjehhubeh}(h]kvm-cap-vm-typesah ]h"]8.41 kvm_cap_vm_typesah$]h&]uh1hhjehhhhhM"%ubh)}(hhh](h)}(h8.42 KVM_CAP_PPC_RPT_INVALIDATEh]h8.42 KVM_CAP_PPC_RPT_INVALIDATE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM7%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj"hhhKubj)}(hppc h]h)}(hppch]hppc}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9%hj3ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jwhhhM9%hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhM9%ubh)}(hXThis capability indicates that the kernel is capable of handling H_RPT_INVALIDATE hcall.h]hXThis capability indicates that the kernel is capable of handling H_RPT_INVALIDATE hcall.}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;%hjhhubh)}(hXIn order to enable the use of H_RPT_INVALIDATE in the guest, user space might have to advertise it for the guest. For example, IBM pSeries (sPAPR) guest starts using it if "hcall-rpt-invalidate" is present in the "ibm,hypertas-functions" device-tree property.h]hX In order to enable the use of H_RPT_INVALIDATE in the guest, user space might have to advertise it for the guest. For example, IBM pSeries (sPAPR) guest starts using it if “hcall-rpt-invalidate” is present in the “ibm,hypertas-functions” device-tree property.}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>%hjhhubh)}(h[This capability is enabled for hypervisors on platforms like POWER9 that support radix MMU.h]h[This capability is enabled for hypervisors on platforms like POWER9 that support radix MMU.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMC%hjhhubeh}(h]kvm-cap-ppc-rpt-invalidateah ]h"]8.42 kvm_cap_ppc_rpt_invalidateah$]h&]uh1hhjehhhhhM7%ubh)}(hhh](h)}(h8.43 KVM_CAP_PPC_AIL_MODE_3h]h8.43 KVM_CAP_PPC_AIL_MODE_3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMG%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hppc h]h)}(hppch]hppc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMI%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMI%hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMI%ubh)}(hThis capability indicates that the kernel supports the mode 3 setting for the "Address Translation Mode on Interrupt" aka "Alternate Interrupt Location" resource that is controlled with the H_SET_MODE hypercall.h]hThis capability indicates that the kernel supports the mode 3 setting for the “Address Translation Mode on Interrupt” aka “Alternate Interrupt Location” resource that is controlled with the H_SET_MODE hypercall.}(hjҵhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMK%hjhhubh)}(hpThis capability allows a guest kernel to use a better-performance mode for handling interrupts and system calls.h]hpThis capability allows a guest kernel to use a better-performance mode for handling interrupts and system calls.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMO%hjhhubeh}(h]kvm-cap-ppc-ail-mode-3ah ]h"]8.43 kvm_cap_ppc_ail_mode_3ah$]h&]uh1hhjehhhhhMG%ubh)}(hhh](h)}(h8.44 KVM_CAP_MEMORY_FAULT_INFOh]h8.44 KVM_CAP_MEMORY_FAULT_INFO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMS%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hj hhhKubj)}(hx86 h]h)}(hx86h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMU%hjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jwhhhMU%hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMU%ubh)}(hThe presence of this capability indicates that KVM_RUN will fill kvm_run.memory_fault if KVM cannot resolve a guest page fault VM-Exit, e.g. if there is a valid memslot but no backing VMA for the corresponding host virtual address.h]hThe presence of this capability indicates that KVM_RUN will fill kvm_run.memory_fault if KVM cannot resolve a guest page fault VM-Exit, e.g. if there is a valid memslot but no backing VMA for the corresponding host virtual address.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMW%hjhhubh)}(hThe information in kvm_run.memory_fault is valid if and only if KVM_RUN returns an error with errno=EFAULT or errno=EHWPOISON *and* kvm_run.exit_reason is set to KVM_EXIT_MEMORY_FAULT.h](h~The information in kvm_run.memory_fault is valid if and only if KVM_RUN returns an error with errno=EFAULT or errno=EHWPOISON }(hjMhhhNhNubj)}(h*and*h]hand}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjMubh5 kvm_run.exit_reason is set to KVM_EXIT_MEMORY_FAULT.}(hjMhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM\%hjhhubh)}(hNote: Userspaces which attempt to resolve memory faults so that they can retry KVM_RUN are encouraged to guard against repeatedly receiving the same error/annotated fault.h]hNote: Userspaces which attempt to resolve memory faults so that they can retry KVM_RUN are encouraged to guard against repeatedly receiving the same error/annotated fault.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`%hjhhubh)}(h/See KVM_EXIT_MEMORY_FAULT for more information.h]h/See KVM_EXIT_MEMORY_FAULT for more information.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMd%hjhhubeh}(h]kvm-cap-memory-fault-infoah ]h"]8.44 kvm_cap_memory_fault_infoah$]h&]uh1hhjehhhhhMS%ubh)}(hhh](h)}(h8.45 KVM_CAP_X86_GUEST_MODEh]h8.45 KVM_CAP_X86_GUEST_MODE}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMg%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hx86 h]h)}(hx86h]hx86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMi%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMi%hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMi%ubh)}(hThe presence of this capability indicates that KVM_RUN will update the KVM_RUN_X86_GUEST_MODE bit in kvm_run.flags to indicate whether the vCPU was executing nested guest code when it exited.h]hThe presence of this capability indicates that KVM_RUN will update the KVM_RUN_X86_GUEST_MODE bit in kvm_run.flags to indicate whether the vCPU was executing nested guest code when it exited.}(hjڶhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMk%hjhhubeh}(h]kvm-cap-x86-guest-modeah ]h"]8.45 kvm_cap_x86_guest_modeah$]h&]uh1hhjehhhhhMg%ubh)}(hhh](h)}(h8.46 KVM_CAP_S390_KEYOPh]h8.46 KVM_CAP_S390_KEYOP}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMp%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMr%hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jwhhhMr%hjhhubah}(h]h ]h"]h$]h&]uh1jrhjhhhhhMr%ubh)}(hUThe presence of this capability indicates that the KVM_S390_KEYOP ioctl is available.h]hUThe presence of this capability indicates that the KVM_S390_KEYOP ioctl is available.}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMt%hjhhubh)}(hKVM exits with the register state of either the L1 or L2 guest depending on which executed at the time of an exit. Userspace must take care to differentiate between these cases.h]hKVM exits with the register state of either the L1 or L2 guest depending on which executed at the time of an exit. Userspace must take care to differentiate between these cases.}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMw%hjhhubeh}(h]kvm-cap-s390-keyopah ]h"]8.46 kvm_cap_s390_keyopah$]h&]uh1hhjehhhhhMp%ubh)}(hhh](h)}(h8.47 KVM_CAP_S390_VSIE_ESAMODEh]h8.47 KVM_CAP_S390_VSIE_ESAMODE}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]hhhhhM|%ubjs)}(hhh]jx)}(hhh](j})}(h Architecturesh]h Architectures}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1j|hjqhhhKubj)}(hs390 h]h)}(hs390h]hs390}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~%hjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jwhhhM~%hjnhhubah}(h]h ]h"]h$]h&]uh1jrhj]hhhhhM~%ubh)}(hZThe presence of this capability indicates that the nested KVM guest can start in ESA mode.h]hZThe presence of this capability indicates that the nested KVM guest can start in ESA mode.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hj]hhubeh}(h]kvm-cap-s390-vsie-esamodeah ]h"]8.47 kvm_cap_s390_vsie_esamodeah$]h&]uh1hhjehhhhhM|%ubeh}(h]other-capabilitiesah ]h"]8. other capabilities.ah$]h&]uh1hhhhhhhhMd#ubh)}(hhh](h)}(h9. Known KVM API problemsh]h9. Known KVM API problems}(hjǷhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjķhhhhhM%ubh)}(hIn some cases, KVM's API has some inconsistencies or common pitfalls that userspace need to be aware of. This section details some of these issues.h]hIn some cases, KVM’s API has some inconsistencies or common pitfalls that userspace need to be aware of. This section details some of these issues.}(hjշhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjķhhubh)}(hPMost of them are architecture specific, so the section is split by architecture.h]hPMost of them are architecture specific, so the section is split by architecture.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjķhhubh)}(hhh](h)}(h9.1. x86h]h9.1. x86}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM%ubh)}(hhh](h)}(h"``KVM_GET_SUPPORTED_CPUID`` issuesh](j)}(h``KVM_GET_SUPPORTED_CPUID``h]hKVM_GET_SUPPORTED_CPUID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh issues}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhjhhhhhM%ubh)}(hIn general, ``KVM_GET_SUPPORTED_CPUID`` is designed so that it is possible to take its result and pass it directly to ``KVM_SET_CPUID2``. This section documents some cases in which that requires some care.h](h In general, }(hj!hhhNhNubj)}(h``KVM_GET_SUPPORTED_CPUID``h]hKVM_GET_SUPPORTED_CPUID}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubhO is designed so that it is possible to take its result and pass it directly to }(hj!hhhNhNubj)}(h``KVM_SET_CPUID2``h]hKVM_SET_CPUID2}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubhF. This section documents some cases in which that requires some care.}(hj!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubh)}(hhh](h)}(hLocal APIC featuresh]hLocal APIC features}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhhhM%ubh)}(hCPU[EAX=1]:ECX[21] (X2APIC) is reported by ``KVM_GET_SUPPORTED_CPUID``, but it can only be enabled if ``KVM_CREATE_IRQCHIP`` or ``KVM_ENABLE_CAP(KVM_CAP_IRQCHIP_SPLIT)`` are used to enable in-kernel emulation of the local APIC.h](h+CPU[EAX=1]:ECX[21] (X2APIC) is reported by }(hjdhhhNhNubj)}(h``KVM_GET_SUPPORTED_CPUID``h]hKVM_GET_SUPPORTED_CPUID}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh , but it can only be enabled if }(hjdhhhNhNubj)}(h``KVM_CREATE_IRQCHIP``h]hKVM_CREATE_IRQCHIP}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh or }(hjdhhhNhNubj)}(h)``KVM_ENABLE_CAP(KVM_CAP_IRQCHIP_SPLIT)``h]h%KVM_ENABLE_CAP(KVM_CAP_IRQCHIP_SPLIT)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjdubh: are used to enable in-kernel emulation of the local APIC.}(hjdhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjShhubh)}(hKThe same is true for the ``KVM_FEATURE_PV_UNHALT`` paravirtualized feature.h](hThe same is true for the }(hjhhhNhNubj)}(h``KVM_FEATURE_PV_UNHALT``h]hKVM_FEATURE_PV_UNHALT}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh paravirtualized feature.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjShhubh)}(hXCOn older versions of Linux, CPU[EAX=1]:ECX[24] (TSC_DEADLINE) is not reported by ``KVM_GET_SUPPORTED_CPUID``, but it can be enabled if ``KVM_CAP_TSC_DEADLINE_TIMER`` is present and the kernel has enabled in-kernel emulation of the local APIC. On newer versions, ``KVM_GET_SUPPORTED_CPUID`` does report the bit as available.h](hQOn older versions of Linux, CPU[EAX=1]:ECX[24] (TSC_DEADLINE) is not reported by }(hjȸhhhNhNubj)}(h``KVM_GET_SUPPORTED_CPUID``h]hKVM_GET_SUPPORTED_CPUID}(hjиhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȸubh, but it can be enabled if }(hjȸhhhNhNubj)}(h``KVM_CAP_TSC_DEADLINE_TIMER``h]hKVM_CAP_TSC_DEADLINE_TIMER}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȸubha is present and the kernel has enabled in-kernel emulation of the local APIC. On newer versions, }(hjȸhhhNhNubj)}(h``KVM_GET_SUPPORTED_CPUID``h]hKVM_GET_SUPPORTED_CPUID}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjȸubh" does report the bit as available.}(hjȸhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjShhubeh}(h]local-apic-featuresah ]h"]local apic featuresah$]h&]uh1hhjhhhhhM%ubh)}(hhh](h)}(h CPU topologyh]h CPU topology}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM%ubh)}(hXSeveral CPUID values include topology information for the host CPU: 0x0b and 0x1f for Intel systems, 0x8000001e for AMD systems. Different versions of KVM return different values for this information and userspace should not rely on it. Currently they return all zeroes.h]hXSeveral CPUID values include topology information for the host CPU: 0x0b and 0x1f for Intel systems, 0x8000001e for AMD systems. Different versions of KVM return different values for this information and userspace should not rely on it. Currently they return all zeroes.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubh)}(hXCIf userspace wishes to set up a guest topology, it should be careful that the values of these three leaves differ for each CPU. In particular, the APIC ID is found in EDX for all subleaves of 0x0b and 0x1f, and in EAX for 0x8000001e; the latter also encodes the core id and node id in bits 7:0 of EBX and ECX respectively.h]hXCIf userspace wishes to set up a guest topology, it should be careful that the values of these three leaves differ for each CPU. In particular, the APIC ID is found in EDX for all subleaves of 0x0b and 0x1f, and in EAX for 0x8000001e; the latter also encodes the core id and node id in bits 7:0 of EBX and ECX respectively.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubeh}(h] cpu-topologyah ]h"] cpu topologyah$]h&]uh1hhjhhhhhM%ubeh}(h]kvm-get-supported-cpuid-issuesah ]h"]kvm_get_supported_cpuid issuesah$]h&]uh1hhjhhhhhM%ubh)}(hhh](h)}(h Obsolete ioctls and capabilitiesh]h Obsolete ioctls and capabilities}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhjQhhhhhM%ubh)}(hKVM_CAP_DISABLE_QUIRKS does not let userspace know which quirks are actually available. Use ``KVM_CHECK_EXTENSION(KVM_CAP_DISABLE_QUIRKS2)`` instead if available.h](h]KVM_CAP_DISABLE_QUIRKS does not let userspace know which quirks are actually available. Use }(hjbhhhNhNubj)}(h0``KVM_CHECK_EXTENSION(KVM_CAP_DISABLE_QUIRKS2)``h]h,KVM_CHECK_EXTENSION(KVM_CAP_DISABLE_QUIRKS2)}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjbubh instead if available.}(hjbhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM%hjQhhubeh}(h] obsolete-ioctls-and-capabilitiesah ]h"] obsolete ioctls and capabilitiesah$]h&]uh1hhjhhhhhM%ubh)}(hhh](h)}(h&Ordering of KVM_GET_*/KVM_SET_* ioctlsh]h&Ordering of KVM_GET_*/KVM_SET_* ioctls}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM%ubh)}(hTBDh]hTBD}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjhhubeh}(h]"ordering-of-kvm-get-kvm-set-ioctlsah ]h"]&ordering of kvm_get_*/kvm_set_* ioctlsah$]h&]uh1hhjhhhhhM%ubeh}(h]id25ah ]h"]9.1. x86ah$]h&]uh1hhjķhhhhhM%ubeh}(h]known-kvm-api-problemsah ]h"]9. known kvm api problemsah$]h&]uh1hhhhhhhhM%ubeh}(h]Athe-definitive-kvm-kernel-based-virtual-machine-api-documentationah ]h"]Cthe definitive kvm (kernel-based virtual machine) api documentationah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksjfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourcehnj _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}(1](jjjȢe2]jaurefids}(j`]jUajJ ]j@ aj9]j9aj]jajG]jGajY]jYajAj]j7jaj]z]jSzajhz]j^zajو]jɈaunameids}(jƹjùjWjTjjjjjYjYj~j`j}jzj@j=x86:Ns390:Nmips:Narm64:NjP jM jv jJ ju jr j j jejbjjjjjjj9j6jljijjjjj3j0j8j5jjj+j(jtjqjjjG jD jz!jw!j"j"j#j#j%j%j'j'j(j(j)j)jB+j?+jc-j`-j/j.jy1jv1j_4j\4j5j5j6j6jd8ja8j9j9j+<j9j*<j'<j`@j]@ for arm64:NjX@jU@jAjAjAjAjBjBjDjDj7Ej4Ej|FjyFjGjGjHjHjKjKjLjLjNjNj:Pj7PjQQjNQjRjRjSjSj>Uj;UjVjVjWjWjYjYjZjZj\j\j3]j0]jj j jj)j¤j0j-jUjRjjjGjDjjj,j)jjjjj9j6jjjjjZjWj_j\jIjFjjjjjjjjjrjoj*j'jAj>jjjJjGjjjjj3j0jjjjj:j7jjjujrjjjjj*j'jjjPjMjjjjjjjjj5j2jLjIjcj`jjj= j: j j j! j jF jC jyjvjjjjjjjjjjjCj@jjjijfjjj!j!j"j"j#j#j$j$j+j+j8.j5.jO/jL/je2jb2j3j3j5j5j!7j7j88j58j@j@jAjAj$Cj!CjDjDjHFjEFjGjGjIjGjIjIjIjIjAKj>KjLjLjNjNj>Rj;RjTY;jTjYjYjPjjYjOjjLjjGjjDjjzzjAjjyzjvzjwljtljmjmjMojJoj`pj]pjsqjpqjrjqjrjrjvsjssjUtjRtj4uj1ujvjvjwjwj$xj!xjxjxj>yj;yjyjyjqzjnzjjzj]zj`jhzj_j\j|j|j.}j+}j}j}j~j~jjj6j3jSjPjjjjj6j3jÃjjPjMj6j3jjjjjGjDjjjjj]jZjTjQj<j9jjjBj?j9j6j>j;jˑjȑj jjjjjjjjЙj͙jǚjĚj jjjj"jj5j2jޠj۠jkjhjbj_jKjHjjjjjjjWjTjjjjݦj?j<jjjjjjjjjjjgjdjƫjëj%j"jjjjjBj?jjjj jmjjj̮jɮj+j(jjjjjdjajѰjΰjjjejbjIJjjjjbj_j jjjjjjjjjjZjWjjjjjjjNjKjjjFjCjjjjjjوu nametypes}(jƹjWjjjYj~j}j@j=j>j?j@jP jv ju j jejjjj9jljjj3j8jj+jtjjG jz!j"j#j%j'j(j)jB+jc-j/jy1j_4j5j6jd8j9j+<j*<j`@jAjX@jAjAjBjDj7Ej|FjGjHjKjLjNj:PjQQjRjSj>UjVjWjYjZj\j3]jj j)j0jUjjGjj,jjj9jjjZj_jIjjjjjrj*jAjjJjjj3jjj:jjujjj*jjPjjjjj5jLjcjj= j j! jF jyjjjjjjCjjijj!j"j#j$j+j8.jO/je2j3j5j!7j88j@jAj$CjDjHFjGjIjIjIjAKjLjNj>RjTjYjPjjOjjGjjzzjyzjwljmjMoj`pjsqjrjrjvsjUtj4ujvjwj$xjxj>yjyjqzjjzj`j_j|j.}j}j~jj6jSjjj6jÃjPj6jjjGjjj]jTj<jjBj9j>jˑj jjjjЙjǚj jj"j5jޠjkjbjKjjjjWjjj?jjjjjjgjƫj%jjjBjjjmj̮j+jjjdjѰjjejIJjjbj jjjjjZjjjjNjjFjjjuh}(jùhjThjjZjjjYjj`jajzjaj=jjjjjjjj5j jM jCjJ jS jr jS j j{ jbj jjhjjjjj6jjij<jjojjj0jjUjj5jZjjj;jjoj(jjqj6jjwjD jjw!jJ j"j}!j#j"j%j#j'j%j(j'j)j(j?+j)j`-jE+j.jf-jv1j/j0j20jo1j0j\4j|1j3j2jT4j3j5jb4j6j5ja8j6jZ8j98j9jg8j9j9j'<j9j]@j0<j @j?jU@j&@jAjc@jAjAjBjAjDjBj4EjDjyFj:EjGjFjHjGjKjHjLjKjNjLj7PjNjNQj=PjRjTQjSjRj;UjSjVjAUjWjVjYjWjZjYj\jZj0]j\j j6]jjj#jjҢjȢjjȣjjj¤jj-jjRj3jjXjDjjjJj)jjjjj/j6jjj<jjjWjj\j]jFjbjjLjjjjjj"jojj'juj>j-jjDjGjjjMjjj0jjj6jjj7jjj=jrjjjxjjj'jjj-jMjjjSjjjjjjj2jjIj8j`jOjjfj: jj j@ j j jC j$ jvjI jj|jjjjjjjjj@jjjFjfjjjlj!jj"j!j#j"j$j#j+j$j5.j+jL/j;.jb2jR/j3jh2j5j3j7j5j58j$7j@j;8jAj@j!CjBjDj'CjEFjDjGjKFjGjGjIjGjIjfIj>KjIj6KjKjLjDKjNjLj;RjNjTjARjYjTjYjYjLjjYj `j0\jDjj`jAjjUjjvzjUjjtljkjmjzljJojmj]pjPojpqjcpjqjvqjrjrjssjrjRtjysj1ujXtjvj7ujwjvj!xjwjxj'xj;yjxjyjAyjnzjyj]zjzjhzjzj\jzj|jp{j+}j |j}j1}j~j}jj~j3jjPj9jjVjjj3jjj9jMjƃj3jSjj9jjjDjjjJjӈjɈjوjjj jZjjQj`j9jWjj?j?jj6jEj;j<jȑjAjjΑjj jjjjj͙jjĚjәjjʚjj jj j2j%j۠j8jhjj_jnjHjejjNjj jjjTjjjejݦjj<jjjBjjjjjjjjjdj jëjjj"jɫjj(jjj?jjjEj jjjjjɮjpj(jϮjj.jjjajjΰjgjj԰jbjjjhjjDzj_jjjejjjjjjjjjWjjj]jjķjjjKjjjSjCjjjQjju footnote_refs}(j+](jjjȢej-]jau citation_refs} autofootnotes]jaautofootnote_refs]jɈasymbol_footnotes]symbol_footnote_refs] footnotes](jȣje citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}jKsRparse_messages](hsystem_message)}(hhh]h)}(h'Duplicate implicit target name: "x86:".h]h+Duplicate implicit target name: “x86:”.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhjdubah}(h]h ]h"]h$]h&]jUalevelKtypeINFOsourcehnjlineM4uh1jbhjhhhhhM4ubjc)}(hhh]h)}(h(Duplicate implicit target name: "mips:".h]h,Duplicate implicit target name: “mips:”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jjalevelKtypej}sourcehnjlineMbuh1jbhj;hhhhhMbubjc)}(hhh]h)}(h'Duplicate implicit target name: "x86:".h]h+Duplicate implicit target name: “x86:”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]j0alevelKtypej}sourcehnjlineMyuh1jbhj20hhhhhMyubjc)}(hhh]h)}(h)Duplicate implicit target name: "arm64:".h]h-Duplicate implicit target name: “arm64:”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jo1alevelKtypej}sourcehnjlineMuh1jbhj0hhhhhMubjc)}(hhh]h)}(h'Duplicate implicit target name: "x86:".h]h+Duplicate implicit target name: “x86:”.}(hjԺhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjѺubah}(h]h ]h"]h$]h&]j3alevelKtypej}sourcehnjlineMuh1jbhj2hhhhhMubjc)}(hhh]h)}(h)Duplicate implicit target name: "arm64:".h]h-Duplicate implicit target name: “arm64:”.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jT4alevelKtypej}sourcehnjlineMuh1jbhj3hhhhhMubjc)}(hhh]h)}(h(Duplicate implicit target name: "s390:".h]h,Duplicate implicit target name: “s390:”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]jZ8alevelKtypej}sourcehnjlineMuh1jbhj98hhhhhMubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"ubah}(h]h ]h"]h$]h&]levelKtypej}lineMU sourcehuh1jbhjjubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=ubah}(h]h ]h"]h$]h&]levelKtypej}lineMX sourcehuh1jbhjkubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXubah}(h]h ]h"]h$]h&]levelKtypej}lineM[ sourcehuh1jbhjRlubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjsubah}(h]h ]h"]h$]h&]levelKtypej}lineM sourcehuh1jbhj‚ubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}lineM sourcehuh1jbhjubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}lineM sourcehuh1jbhjubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjǻhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjĻubah}(h]h ]h"]h$]h&]levelKtypej}lineM' sourcehuh1jbhjubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj߻ubah}(h]h ]h"]h$]h&]levelKtypej}lineM5 sourcehuh1jbhj=ubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}lineML sourcehuh1jbhjubjc)}(hhh]h)}(heUnexpected possible title overline or transition. Treating it as ordinary text because it's so short.h]hgUnexpected possible title overline or transition. Treating it as ordinary text because it’s so short.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}lineM] sourcehuh1jbhjºubjc)}(hhh]h)}(h`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.h]hdBlank line missing before literal block (after the “::”)? Interpreted as a definition list item.}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0ubah}(h]h ]h"]h$]h&]levelKtypej}lineMp sourcehuh1jbhjubjc)}(hhh]h)}(h(Duplicate implicit target name: "s390:".h]h,Duplicate implicit target name: “s390:”.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]h ]h"]h$]h&]j6KalevelKtypej}sourcehnjlineMuh1jbhjKhhhhhMubjc)}(hhh]h)}(h-Duplicate implicit target name: "for arm64:".h]h1Duplicate implicit target name: “for arm64:”.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhjfubah}(h]h ]h"]h$]h&]j `alevelKtypej}sourcehnjlineMuh1jbhj0\hhhhhMubetransform_messages](jc)}(hhh]h)}(hhh]h9Hyperlink target "kvm-get-api-version" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineKuh1jbubjc)}(hhh]h)}(hhh]h9Hyperlink target "kvm-check-extension" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineMuh1jbubjc)}(hhh]h)}(hhh]h4Hyperlink target "kvm-enable-cap" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineMuh1jbubjc)}(hhh]h)}(hhh]h7Hyperlink target "kvm-arm-vcpu-init" is not referenced.}hjԼsbah}(h]h ]h"]h$]h&]uh1hhjѼubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineM uh1jbubjc)}(hhh]h)}(hhh]hDHyperlink target "kvm-arm-get-reg-writable-masks" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineMuh1jbubjc)}(hhh]h)}(hhh]h*Hyperlink target "id20" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineM uh1jbubjc)}(hhh]h)}(hhh]h0Hyperlink target "cap-enable" is not referenced.}hj"sbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypej}sourcehnjlineMuh1jbubjc)}(hhh]h)}(hhh]h