€•Ø]      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ"/translations/zh_CN/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/zh_TW/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/it_IT/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ja_JP/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/ko_KR/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ"/translations/sp_SP/trace/intel_th”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1h¡hhhžhhŸŒ</var/lib/git/docbuild/linux/Documentation/trace/intel_th.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒIntel(R) Trace Hub (TH)”h]”hŒIntel(R) Trace Hub (TH)”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒOverview”h]”hŒOverview”…””}”(hhÌhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhÉhžhhŸh³h KubhŒ	paragraph”“”)”}”(hXh  Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
switch and output trace data from multiple hardware and software
sources over several types of trace output ports encoded in System
Trace Protocol (MIPI STPv2) and is intended to perform full system
debugging. For more information on the hardware, see Intel(R) Trace
Hub developer's manual [1].”h]”hXj  Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
switch and output trace data from multiple hardware and software
sources over several types of trace output ports encoded in System
Trace Protocol (MIPI STPv2) and is intended to perform full system
debugging. For more information on the hardware, see Intel(R) Trace
Hub developerâ€™s manual [1].”…””}”(hhÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K
hhÉhžhubhÛ)”}”(hŒßIt consists of trace sources, trace destinations (outputs) and a
switch (Global Trace Hub, GTH). These devices are placed on a bus of
their own ("intel_th"), where they can be discovered and configured
via sysfs attributes.”h]”hŒãIt consists of trace sources, trace destinations (outputs) and a
switch (Global Trace Hub, GTH). These devices are placed on a bus of
their own (â€œintel_thâ€), where they can be discovered and configured
via sysfs attributes.”…””}”(hhêhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KhhÉhžhubhŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hXÏ  Currently, the following Intel TH subdevices (blocks) are supported:
- Software Trace Hub (STH), trace source, which is a System Trace
  Module (STM) device,
- Memory Storage Unit (MSU), trace output, which allows storing
  trace hub output in system memory,
- Parallel Trace Interface output (PTI), trace output to an external
  debug host via a PTI port,
- Global Trace Hub (GTH), which is a switch and a central component
  of Intel(R) Trace Hub architecture.
”h]”(hŒterm”“”)”}”(hŒDCurrently, the following Intel TH subdevices (blocks) are supported:”h]”hŒDCurrently, the following Intel TH subdevices (blocks) are supported:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh³h KhhÿubhŒ
definition”“”)”}”(hhh]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒTSoftware Trace Hub (STH), trace source, which is a System Trace
Module (STM) device,”h]”hÛ)”}”(hŒTSoftware Trace Hub (STH), trace source, which is a System Trace
Module (STM) device,”h]”hŒTSoftware Trace Hub (STH), trace source, which is a System Trace
Module (STM) device,”…””}”(hj#  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒ`Memory Storage Unit (MSU), trace output, which allows storing
trace hub output in system memory,”h]”hÛ)”}”(hŒ`Memory Storage Unit (MSU), trace output, which allows storing
trace hub output in system memory,”h]”hŒ`Memory Storage Unit (MSU), trace output, which allows storing
trace hub output in system memory,”…””}”(hj;  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Khj7  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒ]Parallel Trace Interface output (PTI), trace output to an external
debug host via a PTI port,”h]”hÛ)”}”(hŒ]Parallel Trace Interface output (PTI), trace output to an external
debug host via a PTI port,”h]”hŒ]Parallel Trace Interface output (PTI), trace output to an external
debug host via a PTI port,”…””}”(hjS  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KhjO  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubj  )”}”(hŒfGlobal Trace Hub (GTH), which is a switch and a central component
of Intel(R) Trace Hub architecture.
”h]”hÛ)”}”(hŒeGlobal Trace Hub (GTH), which is a switch and a central component
of Intel(R) Trace Hub architecture.”h]”hŒeGlobal Trace Hub (GTH), which is a switch and a central component
of Intel(R) Trace Hub architecture.”…””}”(hjk  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Khjg  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j  hŸh³h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hhÿubeh}”(h]”h ]”h"]”h$]”h&]”uh1hýhŸh³h Khhúubah}”(h]”h ]”h"]”h$]”h&]”uh1høhhÉhžhhŸNh NubhÛ)”}”(hŒãCommon attributes for output devices are described in
Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
notable of them is "active", which enables or disables trace output
into that particular output device.”h]”hŒçCommon attributes for output devices are described in
Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
notable of them is â€œactiveâ€, which enables or disables trace output
into that particular output device.”…””}”(hj™  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K hhÉhžhubhÛ)”}”(hŒÑGTH allows directing different STP masters into different output ports
via its "masters" attribute group. More detailed GTH interface
description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.”h]”hŒÕGTH allows directing different STP masters into different output ports
via its â€œmastersâ€ attribute group. More detailed GTH interface
description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.”…””}”(hj§  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K%hhÉhžhubhÛ)”}”(hŒ¹STH registers an stm class device, through which it provides interface
to userspace and kernelspace software trace sources. See
Documentation/trace/stm.rst for more information on that.”h]”hŒ¹STH registers an stm class device, through which it provides interface
to userspace and kernelspace software trace sources. See
Documentation/trace/stm.rst for more information on that.”…””}”(hjµ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K)hhÉhžhubhÛ)”}”(hŒõMSU can be configured to collect trace data into a system memory
buffer, which can later on be read from its device nodes via read() or
mmap() interface and directed to a "software sink" driver that will
consume the data and/or relay it further.”h]”hŒùMSU can be configured to collect trace data into a system memory
buffer, which can later on be read from its device nodes via read() or
mmap() interface and directed to a â€œsoftware sinkâ€ driver that will
consume the data and/or relay it further.”…””}”(hjÃ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K-hhÉhžhubhÛ)”}”(hŒ¹On the whole, Intel(R) Trace Hub does not require any special
userspace software to function; everything can be configured, started
and collected via sysfs attributes, and device nodes.”h]”hŒ¹On the whole, Intel(R) Trace Hub does not require any special
userspace software to function; everything can be configured, started
and collected via sysfs attributes, and device nodes.”…””}”(hjÑ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K2hhÉhžhubhÛ)”}”(hŒ^[1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf”h]”(hŒ[1] ”…””}”(hjß  hžhhŸNh NubhŒ	reference”“”)”}”(hŒZhttps://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf”h]”hŒZhttps://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf”…””}”(hjé  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”jë  uh1jç  hjß  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K6hhÉhžhubeh}”(h]”Œoverview”ah ]”h"]”Œoverview”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kubhµ)”}”(hhh]”(hº)”}”(hŒBus and Subdevices”h]”hŒBus and Subdevices”…””}”(hj	  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj  hžhhŸh³h K9ubhÛ)”}”(hX8  For each Intel TH device in the system a bus of its own is
created and assigned an id number that reflects the order in which TH
devices were enumerated. All TH subdevices (devices on intel_th bus)
begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
followed by device's name and an optional index.”h]”hX:  For each Intel TH device in the system a bus of its own is
created and assigned an id number that reflects the order in which TH
devices were enumerated. All TH subdevices (devices on intel_th bus)
begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
followed by deviceâ€™s name and an optional index.”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K;hj  hžhubhÛ)”}”(hŒºOutput devices also get a device node in /dev/intel_thN, where N is
the Intel TH device id. For example, MSU's memory buffers, when
allocated, are accessible via /dev/intel_th0/msc{0,1}.”h]”hŒ¼Output devices also get a device node in /dev/intel_thN, where N is
the Intel TH device id. For example, MSUâ€™s memory buffers, when
allocated, are accessible via /dev/intel_th0/msc{0,1}.”…””}”(hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KAhj  hžhubeh}”(h]”Œbus-and-subdevices”ah ]”h"]”Œbus and subdevices”ah$]”h&]”uh1h´hh¶hžhhŸh³h K9ubhµ)”}”(hhh]”(hº)”}”(hŒQuick example”h]”hŒQuick example”…””}”(hj>  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj;  hžhhŸh³h KFubhÛ)”}”(hŒ<# figure out which GTH port is the first memory controller::”h]”hŒ;# figure out which GTH port is the first memory controller:”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KHhj;  hžhubhŒliteral_block”“”)”}”(hŒ-$ cat /sys/bus/intel_th/devices/0-msc0/port
0”h]”hŒ-$ cat /sys/bus/intel_th/devices/0-msc0/port
0”…””}”hj\  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h KJhj;  hžhubhÛ)”}”(hŒF# looks like it's port 0, configure master 33 to send data to port 0::”h]”hŒG# looks like itâ€™s port 0, configure master 33 to send data to port 0:”…””}”(hjj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KMhj;  hžhubj[  )”}”(hŒ5$ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33”h]”hŒ5$ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33”…””}”hjx  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h KOhj;  hžhubhÛ)”}”(hŒ`# allocate a 2-windowed multiblock buffer on the first memory
# controller, each with 64 pages::”h]”hŒ_# allocate a 2-windowed multiblock buffer on the first memory
# controller, each with 64 pages:”…””}”(hj†  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KQhj;  hžhubj[  )”}”(hŒm$ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
$ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages”h]”hŒm$ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
$ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages”…””}”hj”  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h KThj;  hžhubhÛ)”}”(hŒ,# enable wrapping for this controller, too::”h]”hŒ+# enable wrapping for this controller, too:”…””}”(hj¢  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h KWhj;  hžhubj[  )”}”(hŒ0$ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap”h]”hŒ0$ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap”…””}”hj°  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h KYhj;  hžhubhÛ)”}”(hŒ%# and enable tracing into this port::”h]”hŒ$# and enable tracing into this port:”…””}”(hj¾  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K[hj;  hžhubj[  )”}”(hŒ2$ echo 1 > /sys/bus/intel_th/devices/0-msc0/active”h]”hŒ2$ echo 1 > /sys/bus/intel_th/devices/0-msc0/active”…””}”hjÌ  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h K]hj;  hžhubhÛ)”}”(hŒy# .. send data to master 33, see stm.txt for more details ..
# .. wait for traces to pile up ..
# .. and stop the trace::”h]”hŒx# .. send data to master 33, see stm.txt for more details ..
# .. wait for traces to pile up ..
# .. and stop the trace:”…””}”(hjÚ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K_hj;  hžhubj[  )”}”(hŒ2$ echo 0 > /sys/bus/intel_th/devices/0-msc0/active”h]”hŒ2$ echo 0 > /sys/bus/intel_th/devices/0-msc0/active”…””}”hjè  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h Kchj;  hžhubhÛ)”}”(hŒ:# and now you can collect the trace from the device node::”h]”hŒ9# and now you can collect the trace from the device node:”…””}”(hjö  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Kehj;  hžhubj[  )”}”(hŒ($ cat /dev/intel_th0/msc0 > my_stp_trace”h]”hŒ($ cat /dev/intel_th0/msc0 > my_stp_trace”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jZ  hŸh³h Kghj;  hžhubeh}”(h]”Œquick-example”ah ]”h"]”Œquick example”ah$]”h&]”uh1h´hh¶hžhhŸh³h KFubhµ)”}”(hhh]”(hº)”}”(hŒHost Debugger Mode”h]”hŒHost Debugger Mode”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj  hžhhŸh³h KjubhÛ)”}”(hX  It is possible to configure the Trace Hub and control its trace
capture from a remote debug host, which should be connected via one of
the hardware debugging interfaces, which will then be used to both
control Intel Trace Hub and transfer its trace data to the debug host.”h]”hX  It is possible to configure the Trace Hub and control its trace
capture from a remote debug host, which should be connected via one of
the hardware debugging interfaces, which will then be used to both
control Intel Trace Hub and transfer its trace data to the debug host.”…””}”(hj+  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Klhj  hžhubhÛ)”}”(hXÒ  The driver needs to be told that such an arrangement is taking place
so that it does not touch any capture/port configuration and avoids
conflicting with the debug host's configuration accesses. The only
activity that the driver will perform in this mode is collecting
software traces to the Software Trace Hub (an stm class device). The
user is still responsible for setting up adequate master/channel
mappings that the decoder on the receiving end would recognize.”h]”hXÔ  The driver needs to be told that such an arrangement is taking place
so that it does not touch any capture/port configuration and avoids
conflicting with the debug hostâ€™s configuration accesses. The only
activity that the driver will perform in this mode is collecting
software traces to the Software Trace Hub (an stm class device). The
user is still responsible for setting up adequate master/channel
mappings that the decoder on the receiving end would recognize.”…””}”(hj9  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Kqhj  hžhubhÛ)”}”(hX@  In order to enable the host mode, set the 'host_mode' parameter of the
'intel_th' kernel module to 'y'. None of the virtual output devices
will show up on the intel_th bus. Also, trace configuration and
capture controlling attribute groups of the 'gth' device will not be
exposed. The 'sth' device will operate as usual.”h]”hXT  In order to enable the host mode, set the â€˜host_modeâ€™ parameter of the
â€˜intel_thâ€™ kernel module to â€˜yâ€™. None of the virtual output devices
will show up on the intel_th bus. Also, trace configuration and
capture controlling attribute groups of the â€˜gthâ€™ device will not be
exposed. The â€˜sthâ€™ device will operate as usual.”…””}”(hjG  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Kyhj  hžhubeh}”(h]”Œhost-debugger-mode”ah ]”h"]”Œhost debugger mode”ah$]”h&]”uh1h´hh¶hžhhŸh³h Kjubhµ)”}”(hhh]”(hº)”}”(hŒSoftware Sinks”h]”hŒSoftware Sinks”…””}”(hj`  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj]  hžhhŸh³h K€ubhÛ)”}”(hŒôThe Memory Storage Unit (MSU) driver provides an in-kernel API for
drivers to register themselves as software sinks for the trace data.
Such drivers can further export the data via other devices, such as
USB device controllers or network cards.”h]”hŒôThe Memory Storage Unit (MSU) driver provides an in-kernel API for
drivers to register themselves as software sinks for the trace data.
Such drivers can further export the data via other devices, such as
USB device controllers or network cards.”…””}”(hjn  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K‚hj]  hžhubhù)”}”(hhh]”hþ)”}”(hX  The API has two main parts::
- notifying the software sink that a particular window is full, and
  "locking" that window, that is, making it unavailable for the trace
  collection; when this happens, the MSU driver will automatically
  switch to the next window in the buffer if it is unlocked, or stop
  the trace capture if it's not;
- tracking the "locked" state of windows and providing a way for the
  software sink driver to notify the MSU driver when a window is
  unlocked and can be used again to collect trace data.
”h]”(j  )”}”(hŒThe API has two main parts::”h]”hŒThe API has two main parts::”…””}”(hjƒ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hŸh³h Khj  ubj  )”}”(hhh]”j  )”}”(hhh]”(j  )”}”(hX(  notifying the software sink that a particular window is full, and
"locking" that window, that is, making it unavailable for the trace
collection; when this happens, the MSU driver will automatically
switch to the next window in the buffer if it is unlocked, or stop
the trace capture if it's not;”h]”hÛ)”}”(hX(  notifying the software sink that a particular window is full, and
"locking" that window, that is, making it unavailable for the trace
collection; when this happens, the MSU driver will automatically
switch to the next window in the buffer if it is unlocked, or stop
the trace capture if it's not;”h]”hX.  notifying the software sink that a particular window is full, and
â€œlockingâ€ that window, that is, making it unavailable for the trace
collection; when this happens, the MSU driver will automatically
switch to the next window in the buffer if it is unlocked, or stop
the trace capture if itâ€™s not;”…””}”(hj›  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Kˆhj—  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj”  ubj  )”}”(hŒ¸tracking the "locked" state of windows and providing a way for the
software sink driver to notify the MSU driver when a window is
unlocked and can be used again to collect trace data.
”h]”hÛ)”}”(hŒ·tracking the "locked" state of windows and providing a way for the
software sink driver to notify the MSU driver when a window is
unlocked and can be used again to collect trace data.”h]”hŒ»tracking the â€œlockedâ€ state of windows and providing a way for the
software sink driver to notify the MSU driver when a window is
unlocked and can be used again to collect trace data.”…””}”(hj³  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h Khj¯  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj”  ubeh}”(h]”h ]”h"]”h$]”h&]”j…  j†  uh1j  hŸh³h Kˆhj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hýhŸh³h Khj|  ubah}”(h]”h ]”h"]”h$]”h&]”uh1høhj]  hžhhŸNh NubhÛ)”}”(hX‹  An example sink driver, msu-sink illustrates the implementation of a
software sink. Functionally, it simply unlocks windows as soon as they
are full, keeping the MSU running in a circular buffer mode. Unlike the
"multi" mode, it will fill out all the windows in the buffer as opposed
to just the first one. It can be enabled by writing "sink" to the "mode"
file (assuming msu-sink.ko is loaded).”h]”hX—  An example sink driver, msu-sink illustrates the implementation of a
software sink. Functionally, it simply unlocks windows as soon as they
are full, keeping the MSU running in a circular buffer mode. Unlike the
â€œmultiâ€ mode, it will fill out all the windows in the buffer as opposed
to just the first one. It can be enabled by writing â€œsinkâ€ to the â€œmodeâ€
file (assuming msu-sink.ko is loaded).”…””}”(hjß  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhŸh³h K‘hj]  hžhubeh}”(h]”Œsoftware-sinks”ah ]”h"]”Œsoftware sinks”ah$]”h&]”uh1h´hh¶hžhhŸh³h K€ubeh}”(h]”Œintel-r-trace-hub-th”ah ]”h"]”Œintel(r) trace hub (th)”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j   Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jú  j÷  j  j   j8  j5  j  j  jZ  jW  jò  jï  uŒ	nametypes”}”(jú  ‰j  ‰j8  ‰j  ‰jZ  ‰jò  ‰uh}”(j÷  h¶j   hÉj5  j  j  j;  jW  j  jï  j]  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”hŒsystem_message”“”)”}”(hhh]”hÛ)”}”(hŒ`Blank line missing before literal block (after the "::")? Interpreted as a definition list item.”h]”hŒdBlank line missing before literal block (after the â€œ::â€)? Interpreted as a definition list item.”…””}”(hj‡  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÚhj„  ubah}”(h]”h ]”h"]”h$]”h&]”Œlevel”KŒtype”ŒINFO”Œline”KŒsource”h³uh1j‚  hj‘  ubaŒtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.