Ksphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget-/translations/zh_CN/trace/coresight/coresightmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/zh_TW/trace/coresight/coresightmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/it_IT/trace/coresight/coresightmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ja_JP/trace/coresight/coresightmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/ko_KR/trace/coresight/coresightmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget-/translations/sp_SP/trace/coresight/coresightmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h&Coresight - HW Assisted Tracing on ARMh]h&Coresight - HW Assisted Tracing on ARM}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhG/var/lib/git/docbuild/linux/Documentation/trace/coresight/coresight.rsthKubh block_quote)}(hX:Author: Mathieu Poirier :Date: September 11th, 2014 h]h field_list)}(hhh](hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h,Mathieu Poirier h]h paragraph)}(hhh](hMathieu Poirier <}(hhhhhNhNubh reference)}(hmathieu.poirier@linaro.orgh]hmathieu.poirier@linaro.org}(hhhhhNhNubah}(h]h ]h"]h$]h&]refuri!mailto:mathieu.poirier@linaro.orguh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(hhh](h)}(hDateh]hDate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hSeptember 11th, 2014 h]h)}(hSeptember 11th, 2014h]hSeptember 11th, 2014}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(h Introductionh]h Introduction}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIhhhhhK ubh)}(hCoresight is an umbrella of technologies allowing for the debugging of ARM based SoC. It includes solutions for JTAG and HW assisted tracing. This document is concerned with the latter.h]hCoresight is an umbrella of technologies allowing for the debugging of ARM based SoC. It includes solutions for JTAG and HW assisted tracing. This document is concerned with the latter.}(hjZhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjIhhubh)}(hXHW assisted tracing is becoming increasingly useful when dealing with systems that have many SoCs and other components like GPU and DMA engines. ARM has developed a HW assisted tracing solution by means of different components, each being added to a design at synthesis time to cater to specific tracing needs. Components are generally categorised as source, link and sinks and are (usually) discovered using the AMBA bus.h]hXHW assisted tracing is becoming increasingly useful when dealing with systems that have many SoCs and other components like GPU and DMA engines. ARM has developed a HW assisted tracing solution by means of different components, each being added to a design at synthesis time to cater to specific tracing needs. Components are generally categorised as source, link and sinks and are (usually) discovered using the AMBA bus.}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh)}(hX"Sources" generate a compressed stream representing the processor instruction path based on tracing scenarios as configured by users. From there the stream flows through the coresight system (via ATB bus) using links that are connecting the emanating source to a sink(s). Sinks serve as endpoints to the coresight implementation, either storing the compressed stream in a memory buffer or creating an interface to the outside world where data can be transferred to a host without fear of filling up the onboard coresight memory buffer.h]hX“Sources” generate a compressed stream representing the processor instruction path based on tracing scenarios as configured by users. From there the stream flows through the coresight system (via ATB bus) using links that are connecting the emanating source to a sink(s). Sinks serve as endpoints to the coresight implementation, either storing the compressed stream in a memory buffer or creating an interface to the outside world where data can be transferred to a host without fear of filling up the onboard coresight memory buffer.}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh)}(h2At typical coresight system would look like this::h]h1At typical coresight system would look like this:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjIhhubh literal_block)}(hX ***************************************************************** **************************** AMBA AXI ****************************===|| ***************************************************************** || ^ ^ | || | | * ** 0000000 ::::: 0000000 ::::: ::::: @@@@@@@ |||||||||||| 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System || |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory || | #######<-->: I : | #######<-->: I : : I : @@@<-| |||||||||||| | # ETM # ::::: | # PTM # ::::: ::::: @ | | ##### ^ ^ | ##### ^ ! ^ ! . | ||||||||| | |->### | ! | |->### | ! | ! . | || DAP || | | # | ! | | # | ! | ! . | ||||||||| | | . | ! | | . | ! | ! . | | | | | . | ! | | . | ! | ! . | | * | | . | ! | | . | ! | ! . | | SWD/ | | . | ! | | . | ! | ! . | | JTAG *****************************************************************<-| *************************** AMBA Debug APB ************************ ***************************************************************** | . ! . ! ! . | | . * . * * . | ***************************************************************** ******************** Cross Trigger Matrix (CTM) ******************* ***************************************************************** | . ^ . . | | * ! * * | ***************************************************************** ****************** AMBA Advanced Trace Bus (ATB) ****************** ***************************************************************** | ! =============== | | * ===== F =====<---------| | ::::::::: ==== U ==== |-->:: CTI ::&& ETB &&<......II I ======= | ! &&&&&&&&& II I . | ! I I . | ! I REP I<.......... | ! I I | !!>&&&&&&&&& II I *Source: ARM ltd. |------>& TPIU &<......II I DAP = Debug Access Port &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell ; PTM = Program Trace Macrocell ; CTI = Cross Trigger Interface * ETB = Embedded Trace Buffer To trace port TPIU= Trace Port Interface Unit SWD = Serial Wire Debugh]hX ***************************************************************** **************************** AMBA AXI ****************************===|| ***************************************************************** || ^ ^ | || | | * ** 0000000 ::::: 0000000 ::::: ::::: @@@@@@@ |||||||||||| 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System || |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory || | #######<-->: I : | #######<-->: I : : I : @@@<-| |||||||||||| | # ETM # ::::: | # PTM # ::::: ::::: @ | | ##### ^ ^ | ##### ^ ! ^ ! . | ||||||||| | |->### | ! | |->### | ! | ! . | || DAP || | | # | ! | | # | ! | ! . | ||||||||| | | . | ! | | . | ! | ! . | | | | | . | ! | | . | ! | ! . | | * | | . | ! | | . | ! | ! . | | SWD/ | | . | ! | | . | ! | ! . | | JTAG *****************************************************************<-| *************************** AMBA Debug APB ************************ ***************************************************************** | . ! . ! ! . | | . * . * * . | ***************************************************************** ******************** Cross Trigger Matrix (CTM) ******************* ***************************************************************** | . ^ . . | | * ! * * | ***************************************************************** ****************** AMBA Advanced Trace Bus (ATB) ****************** ***************************************************************** | ! =============== | | * ===== F =====<---------| | ::::::::: ==== U ==== |-->:: CTI ::&& ETB &&<......II I ======= | ! &&&&&&&&& II I . | ! I I . | ! I REP I<.......... | ! I I | !!>&&&&&&&&& II I *Source: ARM ltd. |------>& TPIU &<......II I DAP = Debug Access Port &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell ; PTM = Program Trace Macrocell ; CTI = Cross Trigger Interface * ETB = Embedded Trace Buffer To trace port TPIU= Trace Port Interface Unit SWD = Serial Wire Debug}hjsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jhhhK hjIhhubh)}(hWhile on target configuration of the components is done via the APB bus, all trace data are carried out-of-band on the ATB bus. The CTM provides a way to aggregate and distribute signals between CoreSight components.h]hWhile on target configuration of the components is done via the APB bus, all trace data are carried out-of-band on the ATB bus. The CTM provides a way to aggregate and distribute signals between CoreSight components.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKShjIhhubh)}(hXKThe coresight framework provides a central point to represent, configure and manage coresight devices on a platform. This first implementation centers on the basic tracing functionality, enabling components such ETM/PTM, funnel, replicator, TMC, TPIU and ETB. Future work will enable more intricate IP blocks such as STM and CTI.h]hXKThe coresight framework provides a central point to represent, configure and manage coresight devices on a platform. This first implementation centers on the basic tracing functionality, enabling components such ETM/PTM, funnel, replicator, TMC, TPIU and ETB. Future work will enable more intricate IP blocks such as STM and CTI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKWhjIhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hAcronyms and Classificationh]hAcronyms and Classification}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK_ubh)}(h Acronyms:h]h Acronyms:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hPTM: Program Trace Macrocellh](hterm)}(hPTM:h]hPTM:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKchjubh definition)}(hhh]h)}(hProgram Trace Macrocellh]hProgram Trace Macrocell}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKdhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKchjubj)}(hETM: Embedded Trace Macrocellh](j)}(hETM:h]hETM:}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKehj!ubj)}(hhh]h)}(hEmbedded Trace Macrocellh]hEmbedded Trace Macrocell}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhj3ubah}(h]h ]h"]h$]h&]uh1jhj!ubeh}(h]h ]h"]h$]h&]uh1jhhhKehjhhubj)}(hSTM: System trace Macrocellh](j)}(hSTM:h]hSTM:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKghjPubj)}(hhh]h)}(hSystem trace Macrocellh]hSystem trace Macrocell}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhjbubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhhhKghjhhubj)}(hETB: Embedded Trace Bufferh](j)}(hETB:h]hETB:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKihjubj)}(hhh]h)}(hEmbedded Trace Bufferh]hEmbedded Trace Buffer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKjhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKihjhhubj)}(h$ITM: Instrumentation Trace Macrocellh](j)}(hITM:h]hITM:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKkhjubj)}(hhh]h)}(hInstrumentation Trace Macrocellh]hInstrumentation Trace Macrocell}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKlhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKkhjhhubj)}(hTPIU: Trace Port Interface Unith](j)}(hTPIU:h]hTPIU:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKmhjubj)}(hhh]h)}(hTrace Port Interface Unith]hTrace Port Interface Unit}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKmhjhhubj)}(hETMC-ETR: Trace Memory Controller, configured as Embedded Trace Routerh](j)}(hTMC-ETR:h]hTMC-ETR:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKohj ubj)}(hhh]h)}(h``Documentation/devicetree/bindings/arm/arm,coresight-*.yaml``h]h:Documentation/devicetree/bindings/arm/arm,coresight-*.yaml}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh for details.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjzhhubh)}(hxAs of this writing drivers for ITM, STMs and CTIs are not provided but are expected to be added as the solution matures.h]hxAs of this writing drivers for ITM, STMs and CTIs are not provided but are expected to be added as the solution matures.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjzhhubeh}(h]device-tree-bindingsah ]h"]device tree bindingsah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hFramework and implementationh]hFramework and implementation}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hThe coresight framework provides a central point to represent, configure and manage coresight devices on a platform. Any coresight compliant device can register with the framework for as long as they use the right APIs:h]hThe coresight framework provides a central point to represent, configure and manage coresight devices on a platform. Any coresight compliant device can register with the framework for as long as they use the right APIs:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubhindex)}(hhh]h}(h]h ]h"]h$]h&]entries](singlecoresight_register (C function)c.coresight_registerhNtauh1jhjhhhNhNubhdesc)}(hhh](hdesc_signature)}(hIstruct coresight_device *coresight_register(struct coresight_desc *desc);h]hdesc_signature_line)}(hIstruct coresight_device *coresight_register(struct coresight_desc *desc);h](hdesc_sig_keyword)}(hstructh]hstruct}(hjhhhNhNubah}(h]h ]kah"]h$]h&]uh1jhjhhhhhKubhdesc_sig_space)}(h h]h }(hjhhhNhNubah}(h]h ]wah"]h$]h&]uh1jhjhhhhhKubh)}(hhh]h desc_sig_name)}(hcoresight_deviceh]hcoresight_device}(hj+hhhNhNubah}(h]h ]nah"]h$]h&]uh1j)hj&ubah}(h]h ]h"]h$]h&] refdomaincreftype identifier reftargetj-modnameN classnameN c:parent_keysphinx.domains.c LookupKey)}data]jH ASTIdentifier)}jCcoresight_registersbc.coresight_registerasbuh1hhjhhhhhKubj)}(h h]h }(hjVhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhjhhhhhKubhdesc_sig_punctuation)}(h*h]h*}(hjfhhhNhNubah}(h]h ]pah"]h$]h&]uh1jdhjhhhhhKubh desc_name)}(hcoresight_registerh]j*)}(hjSh]hcoresight_register}(hj{hhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjwubah}(h]h ](sig-namedescnameeh"]h$]h&]jjuh1juhjhhhhhKubhdesc_parameterlist)}(h(struct coresight_desc *desc)h]hdesc_parameter)}(hstruct coresight_desc *desch](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhjubh)}(hhh]j*)}(hcoresight_desch]hcoresight_desc}(hjhhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&] refdomainjAreftypejC reftargetjmodnameN classnameNjGjJ)}jM]jQc.coresight_registerasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhjubje)}(hjhh]h*}(hjhhhNhNubah}(h]h ]jqah"]h$]h&]uh1jdhjubj*)}(hdesch]hdesc}(hjhhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhjhhhhhKubje)}(h;h]h;}(hjhhhNhNubah}(h]h ]jqah"]h$]h&]uh1jdhjhhhhhKubeh}(h]h ]h"]h$]h&]jj add_permalinkuh1jsphinx_line_type declaratorhjhhhhhKubah}(h]jah ](sig sig-objecteh"]h$]h&] is_multiline _toc_parts) _toc_namehuh1jhhhKhjhhubh desc_content)}(hhh]h}(h]h ]h"]h$]h&]uh1j0hjhhhhhKubeh}(h]h ](jAfunctioneh"]h$]h&]domainjAobjtypej>desctypej>noindex noindexentrynocontentsentryuh1jhhhjhNhNubj)}(hhh]h}(h]h ]h"]h$]h&]entries](j!coresight_unregister (C function)c.coresight_unregisterhNtauh1jhjhhhNhNubj)}(hhh](j)}(h:void coresight_unregister(struct coresight_device *csdev);h]j)}(h:void coresight_unregister(struct coresight_device *csdev);h](hdesc_sig_keyword_type)}(hvoidh]hvoid}(hjchhhNhNubah}(h]h ]ktah"]h$]h&]uh1jahj]hhhhhKubj)}(h h]h }(hjrhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhj]hhhhhKubjv)}(hcoresight_unregisterh]j*)}(hcoresight_unregisterh]hcoresight_unregister}(hjhhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjubah}(h]h ](jjeh"]h$]h&]jjuh1juhj]hhhhhKubj)}(h (struct coresight_device *csdev)h]j)}(hstruct coresight_device *csdevh](j)}(hjh]hstruct}(hjhhhNhNubah}(h]h ]jah"]h$]h&]uh1jhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhjubh)}(hhh]j*)}(hcoresight_deviceh]hcoresight_device}(hjhhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjubah}(h]h ]h"]h$]h&] refdomainjAreftypejC reftargetjmodnameN classnameNjGjJ)}jM]jP)}jCjsbc.coresight_unregisterasbuh1hhjubj)}(h h]h }(hjhhhNhNubah}(h]h ]j"ah"]h$]h&]uh1jhjubje)}(hjhh]h*}(hjhhhNhNubah}(h]h ]jqah"]h$]h&]uh1jdhjubj*)}(hcsdevh]hcsdev}(hjhhhNhNubah}(h]h ]j6ah"]h$]h&]uh1j)hjubeh}(h]h ]h"]h$]h&]noemphjjuh1jhjubah}(h]h ]h"]h$]h&]jjuh1jhj]hhhhhKubje)}(hjh]h;}(hjhhhNhNubah}(h]h ]jqah"]h$]h&]uh1jdhj]hhhhhKubeh}(h]h ]h"]h$]h&]jjj"uh1jj#j$hjYhhhhhKubah}(h]jTah ](j(j)eh"]h$]h&]j-j.)j/huh1jhhhKhjVhhubj1)}(hhh]h}(h]h ]h"]h$]h&]uh1j0hjVhhhhhKubeh}(h]h ](jAfunctioneh"]h$]h&]jBjAjCj9jDj9jEjFjGuh1jhhhjhNhNubh)}(hThe registering function is taking a ``struct coresight_desc *desc`` and register the device with the core framework. The unregister function takes a reference to a ``struct coresight_device *csdev`` obtained at registration time.h](h%The registering function is taking a }(hj=hhhNhNubj)}(h``struct coresight_desc *desc``h]hstruct coresight_desc *desc}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubha and register the device with the core framework. The unregister function takes a reference to a }(hj=hhhNhNubj)}(h"``struct coresight_device *csdev``h]hstruct coresight_device *csdev}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj=ubh obtained at registration time.}(hj=hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hIf everything goes well during the registration process the new devices will show up under /sys/bus/coresight/devices, as showns here for a TC2 platform::h]hIf everything goes well during the registration process the new devices will show up under /sys/bus/coresight/devices, as showns here for a TC2 platform:}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hroot:~# ls /sys/bus/coresight/devices/ replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm root:~#h]hroot:~# ls /sys/bus/coresight/devices/ replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm root:~#}hj}sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hIThe functions take a ``struct coresight_device``, which looks like this::h](hThe functions take a }(hjhhhNhNubj)}(h``struct coresight_device``h]hstruct coresight_device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, which looks like this:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hXstruct coresight_desc { enum coresight_dev_type type; struct coresight_dev_subtype subtype; const struct coresight_ops *ops; struct coresight_platform_data *pdata; struct device *dev; const struct attribute_group **groups; };h]hXstruct coresight_desc { enum coresight_dev_type type; struct coresight_dev_subtype subtype; const struct coresight_ops *ops; struct coresight_platform_data *pdata; struct device *dev; const struct attribute_group **groups; };}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hThe "coresight_dev_type" identifies what the device is, i.e, source link or sink while the "coresight_dev_subtype" will characterise that type further.h]hThe “coresight_dev_type” identifies what the device is, i.e, source link or sink while the “coresight_dev_subtype” will characterise that type further.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hX3The ``struct coresight_ops`` is mandatory and will tell the framework how to perform base operations related to the components, each component having a different set of requirement. For that ``struct coresight_ops_sink``, ``struct coresight_ops_link`` and ``struct coresight_ops_source`` have been provided.h](hThe }(hjhhhNhNubj)}(h``struct coresight_ops``h]hstruct coresight_ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is mandatory and will tell the framework how to perform base operations related to the components, each component having a different set of requirement. For that }(hjhhhNhNubj)}(h``struct coresight_ops_sink``h]hstruct coresight_ops_sink}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh, }(hjhhhNhNubj)}(h``struct coresight_ops_link``h]hstruct coresight_ops_link}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh and }(hjhhhNhNubj)}(h``struct coresight_ops_source``h]hstruct coresight_ops_source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh have been provided.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hThe next field ``struct coresight_platform_data *pdata`` is acquired by calling ``of_get_coresight_platform_data()``, as part of the driver's _probe routine and ``struct device *dev`` gets the device reference embedded in the ``amba_device``::h](hThe next field }(hjhhhNhNubj)}(h)``struct coresight_platform_data *pdata``h]h%struct coresight_platform_data *pdata}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is acquired by calling }(hjhhhNhNubj)}(h$``of_get_coresight_platform_data()``h]h of_get_coresight_platform_data()}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh/, as part of the driver’s _probe routine and }(hjhhhNhNubj)}(h``struct device *dev``h]hstruct device *dev}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh+ gets the device reference embedded in the }(hjhhhNhNubj)}(h``amba_device``h]h amba_device}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh:}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hwstatic int etm_probe(struct amba_device *adev, const struct amba_id *id) { ... ... drvdata->dev = &adev->dev; ... }h]hwstatic int etm_probe(struct amba_device *adev, const struct amba_id *id) { ... ... drvdata->dev = &adev->dev; ... }}hjssbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hXUSpecific class of device (source, link, or sink) have generic operations that can be performed on them (see ``struct coresight_ops``). The ``**groups`` is a list of sysfs entries pertaining to operations specific to that component only. "Implementation defined" customisations are expected to be accessed and controlled using those entries.h](hlSpecific class of device (source, link, or sink) have generic operations that can be performed on them (see }(hjhhhNhNubj)}(h``struct coresight_ops``h]hstruct coresight_ops}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh). The }(hjhhhNhNubj)}(h ``**groups``h]h**groups}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh is a list of sysfs entries pertaining to operations specific to that component only. “Implementation defined” customisations are expected to be accessed and controlled using those entries.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]framework-and-implementationah ]h"]framework and implementationah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hDevice Naming schemeh]hDevice Naming scheme}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hXFThe devices that appear on the "coresight" bus were named the same as their parent devices, i.e, the real devices that appears on AMBA bus or the platform bus. Thus the names were based on the Linux Open Firmware layer naming convention, which follows the base physical address of the device followed by the device type. e.g::h]hXIThe devices that appear on the “coresight” bus were named the same as their parent devices, i.e, the real devices that appears on AMBA bus or the platform bus. Thus the names were based on the Linux Open Firmware layer naming convention, which follows the base physical address of the device followed by the device type. e.g:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hXroot:~# ls /sys/bus/coresight/devices/ 20010000.etf 20040000.funnel 20100000.stm 22040000.etm 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu 20070000.etr 20120000.replicator 220c0000.funnel 23040000.etm 23140000.etm 23340000.etmh]hXroot:~# ls /sys/bus/coresight/devices/ 20010000.etf 20040000.funnel 20100000.stm 22040000.etm 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu 20070000.etr 20120000.replicator 220c0000.funnel 23040000.etm 23140000.etm 23340000.etm}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hHowever, with the introduction of ACPI support, the names of the real devices are a bit cryptic and non-obvious. Thus, a new naming scheme was introduced to use more generic names based on the type of the device. The following rules apply::h]hHowever, with the introduction of ACPI support, the names of the real devices are a bit cryptic and non-obvious. Thus, a new naming scheme was introduced to use more generic names based on the type of the device. The following rules apply:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hX1) Devices that are bound to CPUs, are named based on the CPU logical number. e.g, ETM bound to CPU0 is named "etm0" 2) All other devices follow a pattern, "N", where : - A prefix specific to the type of the device N - a sequential number assigned based on the order of probing. e.g, tmc_etf0, tmc_etr0, funnel0, funnel1h]hX1) Devices that are bound to CPUs, are named based on the CPU logical number. e.g, ETM bound to CPU0 is named "etm0" 2) All other devices follow a pattern, "N", where : - A prefix specific to the type of the device N - a sequential number assigned based on the order of probing. e.g, tmc_etf0, tmc_etr0, funnel0, funnel1}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(h8Thus, with the new scheme the devices could appear as ::h]h5Thus, with the new scheme the devices could appear as}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hroot:~# ls /sys/bus/coresight/devices/ etm0 etm1 etm2 etm3 etm4 etm5 funnel0 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0h]hroot:~# ls /sys/bus/coresight/devices/ etm0 etm1 etm2 etm3 etm4 etm5 funnel0 funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubh)}(hSome of the examples below might refer to old naming scheme and some to the newer scheme, to give a confirmation that what you see on your system is not unexpected. One must use the "names" as they appear on the system under specified locations.h]hSome of the examples below might refer to old naming scheme and some to the newer scheme, to give a confirmation that what you see on your system is not unexpected. One must use the “names” as they appear on the system under specified locations.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]device-naming-schemeah ]h"]device naming schemeah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hTopology Representationh]hTopology Representation}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj6 hhhhhKubh)}(hXEach CoreSight component has a ``connections`` directory which will contain links to other CoreSight components. This allows the user to explore the trace topology and for larger systems, determine the most appropriate sink for a given source. The connection information can also be used to establish which CTI devices are connected to a given component. This directory contains a ``nr_links`` attribute detailing the number of links in the directory.h](hEach CoreSight component has a }(hjG hhhNhNubj)}(h``connections``h]h connections}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG ubhXO directory which will contain links to other CoreSight components. This allows the user to explore the trace topology and for larger systems, determine the most appropriate sink for a given source. The connection information can also be used to establish which CTI devices are connected to a given component. This directory contains a }(hjG hhhNhNubj)}(h ``nr_links``h]hnr_links}(hja hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjG ubh: attribute detailing the number of links in the directory.}(hjG hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubh)}(h\For an ETM source, in this case ``etm0`` on a Juno platform, a typical arrangement will be::h](h For an ETM source, in this case }(hjy hhhNhNubj)}(h``etm0``h]hetm0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjy ubh3 on a Juno platform, a typical arrangement will be:}(hjy hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj6 hhubj)}(hlinaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections cti_cpu0 -> ../../../23020000.cti/cti_cpu0 nr_links out:0 -> ../../../230c0000.funnel/funnel2h]hlinaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections cti_cpu0 -> ../../../23020000.cti/cti_cpu0 nr_links out:0 -> ../../../230c0000.funnel/funnel2}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj6 hhubh)}(h'Following the out port to ``funnel2``::h](hFollowing the out port to }(hj hhhNhNubj)}(h ``funnel2``h]hfunnel2}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj6 hhubj)}(hXalinaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections in:0 -> ../../../23040000.etm/etm0 in:1 -> ../../../23140000.etm/etm3 in:2 -> ../../../23240000.etm/etm4 in:3 -> ../../../23340000.etm/etm5 nr_links out:0 -> ../../../20040000.funnel/funnel0h]hXalinaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections in:0 -> ../../../23040000.etm/etm0 in:1 -> ../../../23140000.etm/etm3 in:2 -> ../../../23240000.etm/etm4 in:3 -> ../../../23340000.etm/etm5 nr_links out:0 -> ../../../20040000.funnel/funnel0}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj6 hhubh)}(hAnd again to ``funnel0``::h](h And again to }(hj hhhNhNubj)}(h ``funnel0``h]hfunnel0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj6 hhubj)}(hXlinaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections in:0 -> ../../../220c0000.funnel/funnel1 in:1 -> ../../../230c0000.funnel/funnel2 nr_links out:0 -> ../../../20010000.etf/tmc_etf0h]hXlinaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections in:0 -> ../../../220c0000.funnel/funnel1 in:1 -> ../../../230c0000.funnel/funnel2 nr_links out:0 -> ../../../20010000.etf/tmc_etf0}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj6 hhubh)}(hFinding the first sink ``tmc_etf0``. This can be used to collect data as a sink, or as a link to propagate further along the chain::h](hFinding the first sink }(hj hhhNhNubj)}(h ``tmc_etf0``h]htmc_etf0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh`. This can be used to collect data as a sink, or as a link to propagate further along the chain:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj6 hhubj)}(hX linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections cti_sys0 -> ../../../20020000.cti/cti_sys0 in:0 -> ../../../20040000.funnel/funnel0 nr_links out:0 -> ../../../20150000.funnel/funnel4h]hX linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections cti_sys0 -> ../../../20020000.cti/cti_sys0 in:0 -> ../../../20040000.funnel/funnel0 nr_links out:0 -> ../../../20150000.funnel/funnel4}hj# sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj6 hhubh)}(hvia ``funnel4``::h](hvia }(hj1 hhhNhNubj)}(h ``funnel4``h]hfunnel4}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1 ubh:}(hj1 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM!hj6 hhubj)}(hX linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections in:0 -> ../../../20010000.etf/tmc_etf0 in:1 -> ../../../20140000.etf/tmc_etf1 nr_links out:0 -> ../../../20120000.replicator/replicator0h]hX linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections in:0 -> ../../../20010000.etf/tmc_etf0 in:1 -> ../../../20140000.etf/tmc_etf1 nr_links out:0 -> ../../../20120000.replicator/replicator0}hjQ sbah}(h]h ]h"]h$]h&]jjuh1jhhhM#hj6 hhubh)}(hand a ``replicator0``::h](hand a }(hj_ hhhNhNubj)}(h``replicator0``h]h replicator0}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_ ubh:}(hj_ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM)hj6 hhubj)}(hXlinaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections in:0 -> ../../../20150000.funnel/funnel4 nr_links out:0 -> ../../../20030000.tpiu/tpiu0 out:1 -> ../../../20070000.etr/tmc_etr0h]hXlinaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections in:0 -> ../../../20150000.funnel/funnel4 nr_links out:0 -> ../../../20030000.tpiu/tpiu0 out:1 -> ../../../20070000.etr/tmc_etr0}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhM+hj6 hhubh)}(h7Arriving at the final sink in the chain, ``tmc_etr0``::h](h)Arriving at the final sink in the chain, }(hj hhhNhNubj)}(h ``tmc_etr0``h]htmc_etr0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM1hj6 hhubj)}(hlinaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections cti_sys0 -> ../../../20020000.cti/cti_sys0 in:0 -> ../../../20120000.replicator/replicator0 nr_linksh]hlinaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections cti_sys0 -> ../../../20020000.cti/cti_sys0 in:0 -> ../../../20120000.replicator/replicator0 nr_links}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhM3hj6 hhubh)}(hAs described below, when using sysfs it is sufficient to enable a sink and a source for successful trace. The framework will correctly enable all intermediate links as required.h]hAs described below, when using sysfs it is sufficient to enable a sink and a source for successful trace. The framework will correctly enable all intermediate links as required.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj6 hhubh)}(hXNote: ``cti_sys0`` appears in two of the connections lists above. CTIs can connect to multiple devices and are arranged in a star topology via the CTM. See (Documentation/trace/coresight/coresight-ect.rst) [#fourth]_ for further details. Looking at this device we see 4 connections::h](hNote: }(hj hhhNhNubj)}(h ``cti_sys0``h]hcti_sys0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh appears in two of the connections lists above. CTIs can connect to multiple devices and are arranged in a star topology via the CTM. See (Documentation/trace/coresight/coresight-ect.rst) }(hj hhhNhNubhfootnote_reference)}(h [#fourth]_h]h4}(hj hhhNhNubah}(h]id1ah ]h"]h$]h&]autoKrefidfourthdocnametrace/coresight/coresightuh1j hj resolvedKubhB for further details. Looking at this device we see 4 connections:}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM<hj6 hhubj)}(hX<linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections nr_links stm0 -> ../../../20100000.stm/stm0 tmc_etf0 -> ../../../20010000.etf/tmc_etf0 tmc_etr0 -> ../../../20070000.etr/tmc_etr0 tpiu0 -> ../../../20030000.tpiu/tpiu0h]hX<linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections nr_links stm0 -> ../../../20100000.stm/stm0 tmc_etf0 -> ../../../20010000.etf/tmc_etf0 tmc_etr0 -> ../../../20070000.etr/tmc_etr0 tpiu0 -> ../../../20030000.tpiu/tpiu0}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMBhj6 hhubeh}(h]topology-representationah ]h"]topology representationah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hHow to use the tracer modulesh]hHow to use the tracer modules}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMKubh)}(h2There are two ways to use the Coresight framework:h]h2There are two ways to use the Coresight framework:}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhj hhubhenumerated_list)}(hhh](h list_item)}(husing the perf cmd line tools.h]h)}(hjB h]husing the perf cmd line tools.}(hjD hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhj@ ubah}(h]h ]h"]h$]h&]uh1j> hj; hhhhhNubj? )}(hKinteracting directly with the Coresight devices using the sysFS interface. h]h)}(hJinteracting directly with the Coresight devices using the sysFS interface.h]hJinteracting directly with the Coresight devices using the sysFS interface.}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMPhjW ubah}(h]h ]h"]h$]h&]uh1j> hj; hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix.uh1j9 hj hhhhhMOubh)}(hPreference is given to the former as using the sysFS interface requires a deep understanding of the Coresight HW. The following sections provide details on using both methods.h]hPreference is given to the former as using the sysFS interface requires a deep understanding of the Coresight HW. The following sections provide details on using both methods.}(hjz hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMRhj hhubh)}(hhh](h)}(hUsing the sysFS interfaceh]hUsing the sysFS interface}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMWubh)}(hXBefore trace collection can start, a coresight sink needs to be identified. There is no limit on the amount of sinks (nor sources) that can be enabled at any given moment. As a generic operation, all device pertaining to the sink class will have an "active" entry in sysfs::h]hXBefore trace collection can start, a coresight sink needs to be identified. There is no limit on the amount of sinks (nor sources) that can be enabled at any given moment. As a generic operation, all device pertaining to the sink class will have an “active” entry in sysfs:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhj hhubj)}(hXroot:/sys/bus/coresight/devices# ls replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm root:/sys/bus/coresight/devices# ls 20010000.etb enable_sink status trigger_cntr root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink 1 root:/sys/bus/coresight/devices#h]hXroot:/sys/bus/coresight/devices# ls replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm root:/sys/bus/coresight/devices# ls 20010000.etb enable_sink status trigger_cntr root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink 1 root:/sys/bus/coresight/devices#}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhM^hj hhubh)}(hAt boot time the current etm3x driver will configure the first address comparator with "_stext" and "_etext", essentially tracing any instruction that falls within that range. As such "enabling" a source will immediately trigger a trace capture::h]hXAt boot time the current etm3x driver will configure the first address comparator with “_stext” and “_etext”, essentially tracing any instruction that falls within that range. As such “enabling” a source will immediately trigger a trace capture:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhj hhubj)}(hXroot:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source 1 root:/sys/bus/coresight/devices# cat 20010000.etb/status Depth: 0x2000 Status: 0x1 RAM read ptr: 0x0 RAM wrt ptr: 0x19d3 <----- The write pointer is moving Trigger cnt: 0x0 Control: 0x1 Flush status: 0x0 Flush ctrl: 0x2001 root:/sys/bus/coresight/devices#h]hXroot:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source 1 root:/sys/bus/coresight/devices# cat 20010000.etb/status Depth: 0x2000 Status: 0x1 RAM read ptr: 0x0 RAM wrt ptr: 0x19d3 <----- The write pointer is moving Trigger cnt: 0x0 Control: 0x1 Flush status: 0x0 Flush ctrl: 0x2001 root:/sys/bus/coresight/devices#}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMmhj hhubh)}(h*Trace collection is stopped the same way::h]h)Trace collection is stopped the same way:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM{hj hhubj)}(heroot:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source root:/sys/bus/coresight/devices#h]heroot:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source root:/sys/bus/coresight/devices#}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhM}hj hhubh)}(hCThe content of the ETB buffer can be harvested directly from /dev::h]hBThe content of the ETB buffer can be harvested directly from /dev:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hroot:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \ of=~/cstrace.bin 64+0 records in 64+0 records out 32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s root:/sys/bus/coresight/devices#h]hroot:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \ of=~/cstrace.bin 64+0 records in 64+0 records out 32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s root:/sys/bus/coresight/devices#}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj hhubh)}(hLThe file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.h]hPThe file cstrace.bin can be decompressed using “ptm2human”, DS-5 or Trace32.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hFollowing is a DS-5 output of an experimental loop that increments a variable up to a certain value. The example is simple and yet provides a glimpse of the wealth of possibilities that coresight provides. ::h]hFollowing is a DS-5 output of an experimental loop that increments a variable up to a certain value. The example is simple and yet provides a glimpse of the wealth of possibilities that coresight provides.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hXInfo Tracing enabled Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr} Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc Instruction 0 0x8026B544 E3A03000 false MOV r3,#0 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Timestamp Timestamp: 17106715833 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1 Instruction 0 0x8026B564 E1A0100D false MOV r1,sp Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0 Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4] Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368 Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc] Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0] Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4 Info Tracing enabled Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc} Timestamp Timestamp: 17107041535h]hXInfo Tracing enabled Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr} Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc Instruction 0 0x8026B544 E3A03000 false MOV r3,#0 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Timestamp Timestamp: 17106715833 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4] Instruction 0 0x8026B550 E3530004 false CMP r3,#4 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4] Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1 Instruction 0 0x8026B564 E1A0100D false MOV r1,sp Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0 Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4] Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368 Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc] Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0] Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4 Info Tracing enabled Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc} Timestamp Timestamp: 17107041535{}hj% sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj hhubeh}(h]using-the-sysfs-interfaceah ]h"]using the sysfs interfaceah$]h&]uh1hhj hhhhhMWubh)}(hhh](h)}(hUsing perf frameworkh]hUsing perf framework}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj; hhhhhMubh)}(hXYCoresight tracers are represented using the Perf framework's Performance Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of controlling when tracing gets enabled based on when the process of interest is scheduled. When configured in a system, Coresight PMUs will be listed when queried by the perf command line tool:h]hX[Coresight tracers are represented using the Perf framework’s Performance Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of controlling when tracing gets enabled based on when the process of interest is scheduled. When configured in a system, Coresight PMUs will be listed when queried by the perf command line tool:}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj; hhubh)}(hlinaro@linaro-nano:~$ ./perf list pmu List of pre-defined events (to be used in -e): cs_etm// [Kernel PMU event] h](h)}(h%linaro@linaro-nano:~$ ./perf list pmuh](h)}(hlinaro@linaro-nanoh]hlinaro@linaro-nano}(hjb hhhNhNubah}(h]h ]h"]h$]h&]refurimailto:linaro@linaro-nanouh1hhj^ ubh:~$ ./perf list pmu}(hj^ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjZ ubh)}(hoList of pre-defined events (to be used in -e): cs_etm// [Kernel PMU event] h](h)}(h.List of pre-defined events (to be used in -e):h]h.List of pre-defined events (to be used in -e):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj| ubh)}(h>cs_etm// [Kernel PMU event]h]h>cs_etm// [Kernel PMU event]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj| ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjZ ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj; hhubh)}(hRegardless of the number of tracers available in a system (usually equal to the amount of processor cores), the "cs_etm" PMU will be listed only once.h]hRegardless of the number of tracers available in a system (usually equal to the amount of processor cores), the “cs_etm” PMU will be listed only once.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj; hhubh)}(hA Coresight PMU works the same way as any other PMU, i.e the name of the PMU is provided along with configuration options within forward slashes '/' (see `Config option formats`_).h](hA Coresight PMU works the same way as any other PMU, i.e the name of the PMU is provided along with configuration options within forward slashes ‘/’ (see }(hj hhhNhNubh)}(h`Config option formats`_h]hConfig option formats}(hj hhhNhNubah}(h]h ]h"]h$]h&]nameConfig option formatsj config-option-formatsuh1hhj j Kubh).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj; hhubeh}(h]using-perf-frameworkah ]h"]using perf frameworkah$]h&]uh1hhj hhhhhM referencedKubeh}(h]how-to-use-the-tracer-modulesah ]h"]how to use the tracer modulesah$]h&]uh1hhhhhhhhMKubh)}(hhh](h)}(hAdvanced Perf framework usageh]hAdvanced Perf framework usage}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hSink selectionh]hSink selection}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hAn appropriate sink will be selected automatically for use with Perf, but since there will typically be more than one sink, the name of the sink to use may be specified as a special config option prefixed with '@'.h]hAn appropriate sink will be selected automatically for use with Perf, but since there will typically be more than one sink, the name of the sink to use may be specified as a special config option prefixed with ‘@’.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(h_The available sinks are listed in sysFS under ($SYSFS)/bus/event_source/devices/cs_etm/sinks/::h]h^The available sinks are listed in sysFS under ($SYSFS)/bus/event_source/devices/cs_etm/sinks/:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hroot@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls tmc_etf0 tmc_etr0 tpiu0 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread programh]hroot@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls tmc_etf0 tmc_etr0 tpiu0 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program}hj( sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj hhubh)}(hMore information on the above and other example on how to use Coresight with the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub repository [#third]_.h](hMore information on the above and other example on how to use Coresight with the perf tools can be found in the “HOWTO.md” file of the openCSD gitHub repository }(hj6 hhhNhNubj )}(h [#third]_h]h3}(hj> hhhNhNubah}(h]id2ah ]h"]h$]h&]j Kj thirdj j uh1j hj6 j Kubh.}(hj6 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]sink-selectionah ]h"]sink selectionah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h%AutoFDO analysis using the perf toolsh]h%AutoFDO analysis using the perf tools}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj` hhhhhMubh)}(h9perf can be used to record and analyze trace of programs.h]h9perf can be used to record and analyze trace of programs.}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj` hhubh)}(hxExecution can be recorded using 'perf record' with the cs_etm event, specifying the name of the sink to record to, e.g::h]h{Execution can be recorded using ‘perf record’ with the cs_etm event, specifying the name of the sink to record to, e.g:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj` hhubj)}(h%perf record -e cs_etm//u --per-threadh]h%perf record -e cs_etm//u --per-thread}hj sbah}(h]h ]h"]h$]h&]jjuh1jhhhMhj` hhubh)}(hXJThe 'perf report' and 'perf script' commands can be used to analyze execution, synthesizing instruction and branch events from the instruction trace. 'perf inject' can be used to replace the trace data with the synthesized events. The --itrace option controls the type and frequency of synthesized events (see perf documentation).h]hXVThe ‘perf report’ and ‘perf script’ commands can be used to analyze execution, synthesizing instruction and branch events from the instruction trace. ‘perf inject’ can be used to replace the trace data with the synthesized events. The --itrace option controls the type and frequency of synthesized events (see perf documentation).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj` hhubh)}(hNote that only 64-bit programs are currently supported - further work is required to support instruction decode of 32-bit Arm programs.h]hNote that only 64-bit programs are currently supported - further work is required to support instruction decode of 32-bit Arm programs.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj` hhubeh}(h]%autofdo-analysis-using-the-perf-toolsah ]h"]%autofdo analysis using the perf toolsah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(h Tracing PIDh]h Tracing PID}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hXBThe kernel can be built to write the PID value into the PE ContextID registers. For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may implement Arm Virtualization Host Extensions (VHE), which the kernel can run at EL2 as a virtualisation host; in this case, the PID value is stored in CONTEXTIDR_EL2.h]hXBThe kernel can be built to write the PID value into the PE ContextID registers. For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may implement Arm Virtualization Host Extensions (VHE), which the kernel can run at EL2 as a virtualisation host; in this case, the PID value is stored in CONTEXTIDR_EL2.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(hperf provides PMU formats that program the ETM to insert these values into the trace data; the PMU formats are defined as below:h]hperf provides PMU formats that program the ETM to insert these values into the trace data; the PMU formats are defined as below:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubh)}(hXN"contextid1": Available on both EL1 kernel and EL2 kernel. When the kernel is running at EL1, "contextid1" enables the PID tracing; when the kernel is running at EL2, this enables tracing the PID of guest applications. "contextid2": Only usable when the kernel is running at EL2. When selected, enables PID tracing on EL2 kernel. "contextid": Will be an alias for the option that enables PID tracing. I.e, contextid == contextid1, on EL1 kernel. contextid == contextid2, on EL2 kernel. h]j)}(hhh](j)}(h"contextid1": Available on both EL1 kernel and EL2 kernel. When the kernel is running at EL1, "contextid1" enables the PID tracing; when the kernel is running at EL2, this enables tracing the PID of guest applications. h](j)}(hD"contextid1": Available on both EL1 kernel and EL2 kernel. When theh]hH“contextid1”: Available on both EL1 kernel and EL2 kernel. When the}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(hkernel is running at EL1, "contextid1" enables the PID tracing; when the kernel is running at EL2, this enables tracing the PID of guest applications.h]hkernel is running at EL1, “contextid1” enables the PID tracing; when the kernel is running at EL2, this enables tracing the PID of guest applications.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hp"contextid2": Only usable when the kernel is running at EL2. When selected, enables PID tracing on EL2 kernel. h](j)}(hB"contextid2": Only usable when the kernel is running at EL2. Whenh]hF“contextid2”: Only usable when the kernel is running at EL2. When}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj"ubj)}(hhh]h)}(h,selected, enables PID tracing on EL2 kernel.h]h,selected, enables PID tracing on EL2 kernel.}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(h"contextid": Will be an alias for the option that enables PID tracing. I.e, contextid == contextid1, on EL1 kernel. contextid == contextid2, on EL2 kernel. h](j)}(h>"contextid": Will be an alias for the option that enables PIDh]hB“contextid”: Will be an alias for the option that enables PID}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjQubj)}(hhh]h)}(h^tracing. I.e, contextid == contextid1, on EL1 kernel. contextid == contextid2, on EL2 kernel.h]h^tracing. I.e, contextid == contextid1, on EL1 kernel. contextid == contextid2, on EL2 kernel.}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjcubah}(h]h ]h"]h$]h&]uh1jhjQubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubh)}(hXiperf will always enable PID tracing at the relevant EL, this is accomplished by automatically enable the "contextid" config - but for EL2 it is possible to make specific adjustments using configs "contextid1" and "contextid2", E.g. if a user wants to trace PIDs for both host and guest, the two configs "contextid1" and "contextid2" can be set at the same time:h]hX}perf will always enable PID tracing at the relevant EL, this is accomplished by automatically enable the “contextid” config - but for EL2 it is possible to make specific adjustments using configs “contextid1” and “contextid2”, E.g. if a user wants to trace PIDs for both host and guest, the two configs “contextid1” and “contextid2” can be set at the same time:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(h5perf record -e cs_etm/contextid1,contextid2/u -- vm h]h)}(h3perf record -e cs_etm/contextid1,contextid2/u -- vmh]h3perf record -e cs_etm/contextid1,contextid2/u -- vm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubah}(h]h ]h"]h$]h&]uh1hhhhM hj hhubeh}(h] tracing-pidah ]h"] tracing pidah$]h&]uh1hhj hhhhhMj Kubh)}(hhh](h)}(hEGenerating coverage files for Feedback Directed Optimization: AutoFDOh]hEGenerating coverage files for Feedback Directed Optimization: AutoFDO}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM$ubh)}(h'perf inject' accepts the --itrace option in which case tracing data is removed and replaced with the synthesized events. e.g. ::h]h‘perf inject’ accepts the --itrace option in which case tracing data is removed and replaced with the synthesized events. e.g.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjhhubj)}(h:perf inject --itrace --strip -i perf.data -o perf.data.newh]h:perf inject --itrace --strip -i perf.data -o perf.data.new}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhM*hjhhubh)}(hBelow is an example of using ARM ETM for autoFDO. It requires autofdo (https://github.com/google/autofdo) and gcc version 5. The bubble sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial). ::h](hHBelow is an example of using ARM ETM for autoFDO. It requires autofdo (}(hjhhhNhNubh)}(h!https://github.com/google/autofdoh]h!https://github.com/google/autofdo}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1hhjubhL) and gcc version 5. The bubble sort example is from the AutoFDO tutorial (}(hjhhhNhNubh)}(h)https://gcc.gnu.org/wiki/AutoFDO/Tutorialh]h)https://gcc.gnu.org/wiki/AutoFDO/Tutorial}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1hhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM,hjhhubj)}(hXN$ gcc-5 -O3 sort.c -o sort $ taskset -c 2 ./sort Bubble sorting array of 30000 elements 5910 ms $ perf record -e cs_etm//u --per-thread taskset -c 2 ./sort Bubble sorting array of 30000 elements 12543 ms [ perf record: Woken up 35 times to write data ] [ perf record: Captured and wrote 69.640 MB perf.data ] $ perf inject -i perf.data -o inj.data --itrace=il64 --strip $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo $ taskset -c 2 ./sort_autofdo Bubble sorting array of 30000 elements 5806 msh]hXN$ gcc-5 -O3 sort.c -o sort $ taskset -c 2 ./sort Bubble sorting array of 30000 elements 5910 ms $ perf record -e cs_etm//u --per-thread taskset -c 2 ./sort Bubble sorting array of 30000 elements 12543 ms [ perf record: Woken up 35 times to write data ] [ perf record: Captured and wrote 69.640 MB perf.data ] $ perf inject -i perf.data -o inj.data --itrace=il64 --strip $ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo $ taskset -c 2 ./sort_autofdo Bubble sorting array of 30000 elements 5806 ms}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhM1hjhhubeh}(h]Dgenerating-coverage-files-for-feedback-directed-optimization-autofdoah ]h"]Egenerating coverage files for feedback directed optimization: autofdoah$]h&]uh1hhj hhhhhM$ubh)}(hhh](h)}(hConfig option formatsh]hConfig option formats}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhhhMDubh)}(hThe following strings can be provided between // on the perf command line to enable various options. They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/h]hThe following strings can be provided between // on the perf command line to enable various options. They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj1hhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK2uh1jZhjWubj[)}(hhh]h}(h]h ]h"]h$]h&]jeK2uh1jZhjWubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hOptionh]hOption}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj{ubah}(h]h ]h"]h$]h&]uh1jyhjvubjz)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMMhjubah}(h]h ]h"]h$]h&]uh1jyhjvubeh}(h]h ]h"]h$]h&]uh1jthjqubah}(h]h ]h"]h$]h&]uh1johjWubhtbody)}(hhh](ju)}(hhh](jz)}(hhh]h)}(hbranch_broadcasth]hbranch_broadcast}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(haSession local version of the system wide setting: :ref:`ETM_MODE_BB `h](h2Session local version of the system wide setting: }(hjhhhNhNubh)}(h/:ref:`ETM_MODE_BB `h]hinline)}(hjh]h ETM_MODE_BB}(hjhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarn reftargetcoresight-branch-broadcastuh1hhhhMOhjubeh}(h]h ]h"]h$]h&]uh1hhhhMOhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(h contextidh]h contextid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hSee `Tracing PID`_h](hSee }(hj2hhhNhNubh)}(h`Tracing PID`_h]h Tracing PID}(hj:hhhNhNubah}(h]h ]h"]h$]h&]name Tracing PIDj juh1hhj2j Kubeh}(h]h ]h"]h$]h&]uh1hhhhMRhj/ubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(h contextid1h]h contextid1}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj_ubah}(h]h ]h"]h$]h&]uh1jyhj\ubjz)}(hhh]h)}(hSee `Tracing PID`_h](hSee }(hjyhhhNhNubh)}(h`Tracing PID`_h]h Tracing PID}(hjhhhNhNubah}(h]h ]h"]h$]h&]name Tracing PIDj juh1hhjyj Kubeh}(h]h ]h"]h$]h&]uh1hhhhMThjvubah}(h]h ]h"]h$]h&]uh1jyhj\ubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(h contextid2h]h contextid2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hSee `Tracing PID`_h](hSee }(hjhhhNhNubh)}(h`Tracing PID`_h]h Tracing PID}(hjhhhNhNubah}(h]h ]h"]h$]h&]name Tracing PIDj juh1hhjj Kubeh}(h]h ]h"]h$]h&]uh1hhhhMVhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(hconfigidh]hconfigid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hSelection for a custom configuration. This is an implementation detail and not used directly, see :ref:`trace/coresight/coresight-config:Using Configurations in perf`h](hbSelection for a custom configuration. This is an implementation detail and not used directly, see }(hjhhhNhNubh)}(hD:ref:`trace/coresight/coresight-config:Using Configurations in perf`h]j)}(hjh]h=trace/coresight/coresight-config:Using Configurations in perf}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj=trace/coresight/coresight-config:using configurations in perfuh1hhhhMXhjubeh}(h]h ]h"]h$]h&]uh1hhhhMXhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(hpreseth]hpreset}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjDubah}(h]h ]h"]h$]h&]uh1jyhjAubjz)}(hhh]h)}(h{Override for parameters in a custom configuration, see :ref:`trace/coresight/coresight-config:Using Configurations in perf`h](h7Override for parameters in a custom configuration, see }(hj^hhhNhNubh)}(hD:ref:`trace/coresight/coresight-config:Using Configurations in perf`h]j)}(hjhh]h=trace/coresight/coresight-config:Using Configurations in perf}(hjjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjfubah}(h]h ]h"]h$]h&]refdocj refdomainjtreftyperef refexplicitrefwarnj=trace/coresight/coresight-config:using configurations in perfuh1hhhhM[hj^ubeh}(h]h ]h"]h$]h&]uh1hhhhM[hj[ubah}(h]h ]h"]h$]h&]uh1jyhjAubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(hsinkidh]hsinkid}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM]hjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hHashed version of the string to select a sink, automatically set when using the @ notation. This is an internal implementation detail and is not used directly, see `Using perf framework`_.h](hHashed version of the string to select a sink, automatically set when using the @ notation. This is an internal implementation detail and is not used directly, see }(hjhhhNhNubh)}(h`Using perf framework`_h]hUsing perf framework}(hjhhhNhNubah}(h]h ]h"]h$]h&]nameUsing perf frameworkj j uh1hhjj Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM^hjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(hcycacch]hcycacc}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(heSession local version of the system wide setting: :ref:`ETMv4_MODE_CYCACC `h](h2Session local version of the system wide setting: }(hjhhhNhNubh)}(h3:ref:`ETMv4_MODE_CYCACC `h]j)}(hj h]hETMv4_MODE_CYCACC}(hj hhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjcoresight-cycle-accurateuh1hhhhMbhjubeh}(h]h ]h"]h$]h&]uh1hhhhMbhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(hretstackh]hretstack}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMdhj=ubah}(h]h ]h"]h$]h&]uh1jyhj:ubjz)}(hhh]h)}(hfSession local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK `h](h2Session local version of the system wide setting: }(hjWhhhNhNubh)}(h4:ref:`ETM_MODE_RETURNSTACK `h]j)}(hjah]hETM_MODE_RETURNSTACK}(hjchhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhj_ubah}(h]h ]h"]h$]h&]refdocj refdomainjmreftyperef refexplicitrefwarnjcoresight-return-stackuh1hhhhMehjWubeh}(h]h ]h"]h$]h&]uh1hhhhMehjTubah}(h]h ]h"]h$]h&]uh1jyhj:ubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(h timestamph]h timestamp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hcSession local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP `h](h2Session local version of the system wide setting: }(hjhhhNhNubh)}(h1:ref:`ETMv4_MODE_TIMESTAMP `h]j)}(hjh]hETMv4_MODE_TIMESTAMP}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnjcoresight-timestampuh1hhhhMhhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubju)}(hhh](jz)}(hhh]h)}(h cc_thresholdh]h cc_threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjubah}(h]h ]h"]h$]h&]uh1jyhjubjz)}(hhh]h)}(hXCycle count threshold value. If nothing is provided here or the provided value is 0, then the default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.h]hXCycle count threshold value. If nothing is provided here or the provided value is 0, then the default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMkhjubah}(h]h ]h"]h$]h&]uh1jyhjubeh}(h]h ]h"]h$]h&]uh1jthjubeh}(h]h ]h"]h$]h&]uh1jhjWubeh}(h]h ]h"]h$]h&]colsKuh1jUhjRubah}(h]h ]h"]h$]h&]uh1jPhj1hhhNhNubeh}(h]j ah ]h"]config option formatsah$]h&]uh1hhj hhhhhMDj Kubeh}(h]advanced-perf-framework-usageah ]h"]advanced perf framework usageah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hHow to use the STM moduleh]hHow to use the STM module}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjAhhhhhMpubh)}(hUsing the System Trace Macrocell module is the same as the tracers - the only difference is that clients are driving the trace capture rather than the program flow through the code.h]hUsing the System Trace Macrocell module is the same as the tracers - the only difference is that clients are driving the trace capture rather than the program flow through the code.}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjAhhubh)}(hAs with any other CoreSight component, specifics about the STM tracer can be found in sysfs with more information on each entry being found in [#first]_::h](hAs with any other CoreSight component, specifics about the STM tracer can be found in sysfs with more information on each entry being found in }(hj`hhhNhNubj )}(h [#first]_h]h1}(hjhhhhNhNubah}(h]id3ah ]h"]h$]h&]j Kj firstj j uh1j hj`j Kubh:}(hj`hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMvhjAhhubj)}(hroot@genericarmv8:~# ls /sys/bus/coresight/devices/stm0 enable_source hwevent_select port_enable subsystem uevent hwevent_enable mgmt port_select traceid root@genericarmv8:~#h]hroot@genericarmv8:~# ls /sys/bus/coresight/devices/stm0 enable_source hwevent_select port_enable subsystem uevent hwevent_enable mgmt port_select traceid root@genericarmv8:~#}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhMyhjAhhubh)}(h[Like any other source a sink needs to be identified and the STM enabled before being used::h]hZLike any other source a sink needs to be identified and the STM enabled before being used:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjAhhubj)}(hroot@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_sourceh]hroot@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_source}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhMhjAhhubh)}(hFrom there user space applications can request and use channels using the devfs interface provided for that purpose by the generic STM API::h]hFrom there user space applications can request and use channels using the devfs interface provided for that purpose by the generic STM API:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubj)}(h|root@genericarmv8:~# ls -l /dev/stm0 crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0 root@genericarmv8:~#h]h|root@genericarmv8:~# ls -l /dev/stm0 crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0 root@genericarmv8:~#}hjsbah}(h]h ]h"]h$]h&]jjuh1jhhhMhjAhhubh)}(hfDetails on how to use the generic STM API can be found here: - Documentation/trace/stm.rst [#second]_.h](h[Details on how to use the generic STM API can be found here: - Documentation/trace/stm.rst }(hjhhhNhNubj )}(h [#second]_h]h2}(hjhhhNhNubah}(h]id4ah ]h"]h$]h&]j Kj secondj j uh1j hjj Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjAhhubeh}(h]how-to-use-the-stm-moduleah ]h"]how to use the stm moduleah$]h&]uh1hhhhhhhhMpubh)}(hhh](h)}(hThe CTI & CTM Modulesh]hThe CTI & CTM Modules}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hThe CTI (Cross Trigger Interface) provides a set of trigger signals between individual CTIs and components, and can propagate these between all CTIs via channels on the CTM (Cross Trigger Matrix).h]hThe CTI (Cross Trigger Interface) provides a set of trigger signals between individual CTIs and components, and can propagate these between all CTIs via channels on the CTM (Cross Trigger Matrix).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hA separate documentation file is provided to explain the use of these devices. (Documentation/trace/coresight/coresight-ect.rst) [#fourth]_.h](hA separate documentation file is provided to explain the use of these devices. (Documentation/trace/coresight/coresight-ect.rst) }(hjhhhNhNubj )}(h [#fourth]_h]h4}(hjhhhNhNubah}(h]id5ah ]h"]h$]h&]j Kj j j j uh1j hjj Kubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]the-cti-ctm-modulesah ]h"]the cti & ctm modulesah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hCoreSight System Configurationh]hCoreSight System Configuration}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhhhMubh)}(hCoreSight components can be complex devices with many programming options. Furthermore, components can be programmed to interact with each other across the complete system.h]hCoreSight components can be complex devices with many programming options. Furthermore, components can be programmed to interact with each other across the complete system.}(hjKhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:hhubh)}(hA CoreSight System Configuration manager is provided to allow these complex programming configurations to be selected and used easily from perf and sysfs.h]hA CoreSight System Configuration manager is provided to allow these complex programming configurations to be selected and used easily from perf and sysfs.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:hhubh)}(hrSee the separate document for further information. (Documentation/trace/coresight/coresight-config.rst) [#fifth]_.h](hhSee the separate document for further information. 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