sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget=/translations/zh_CN/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/zh_TW/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/it_IT/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/ja_JP/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/ko_KR/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/pt_BR/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget=/translations/sp_SP/trace/coresight/coresight-etm4x-referencemodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(h/ETMv4 sysfs linux driver programming reference.h]h/ETMv4 sysfs linux driver programming reference.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhW/var/lib/git/docbuild/linux/Documentation/trace/coresight/coresight-etm4x-reference.rsthKubh block_quote)}(hL:Author: Mike Leach :Date: October 11th, 2019 h]h field_list)}(hhh](hfield)}(hhh](h field_name)}(hAuthorh]hAuthor}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhKubh field_body)}(h"Mike Leach h]h paragraph)}(hhh](h Mike Leach <}(hhhhhNhNubh reference)}(hmike.leach@linaro.orgh]hmike.leach@linaro.org}(hhhhhNhNubah}(h]h ]h"]h$]h&]refurimailto:mike.leach@linaro.orguh1hhhubh>}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubah}(h]h ]h"]h$]h&]uh1hhhubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubh)}(hhh](h)}(hDateh]hDate}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhKubh)}(hOctober 11th, 2019 h]h)}(hOctober 11th, 2019h]hOctober 11th, 2019}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj3ubah}(h]h ]h"]h$]h&]uh1hhj"ubeh}(h]h ]h"]h$]h&]uh1hhhhKhhubeh}(h]h ]h"]h$]h&]uh1hhhubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h2Supplement to existing ETMv4 driver documentation.h]h2Supplement to existing ETMv4 driver documentation.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hhh](h)}(hSysfs files and directoriesh]hSysfs files and directories}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhhhK ubh)}(h+Root: ``/sys/bus/coresight/devices/etm``h](hRoot: }(hj|hhhNhNubhliteral)}(h%``/sys/bus/coresight/devices/etm``h]h!/sys/bus/coresight/devices/etm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj|ubeh}(h]h ]h"]h$]h&]uh1hhhhK hjkhhubh)}(hThe following paragraphs explain the association between sysfs files and the ETMv4 registers that they effect. Note the register names are given without the ‘TRC’ prefix.h]hThe following paragraphs explain the association between sysfs files and the ETMv4 registers that they effect. Note the register names are given without the ‘TRC’ prefix.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjkhhubh transition)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``mode`` (rw)h]h)}(hjh](j)}(h``mode``h]hmode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h{CONFIGR + others}h]h)}(hjh]h{CONFIGR + others}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(hBit select trace features. See ‘mode’ section below. Bits in this will cause equivalent programming of trace config and other registers to enable the features requested. h]h)}(hBit select trace features. See ‘mode’ section below. Bits in this will cause equivalent programming of trace config and other registers to enable the features requested.h]hBit select trace features. See ‘mode’ section below. Bits in this will cause equivalent programming of trace config and other registers to enable the features requested.}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(h Syntax & egh]h Syntax & eg}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhKubh)}(hI``echo bitfield > mode`` bitfield up to 32 bits setting trace features. h](h)}(h``echo bitfield > mode``h]j)}(hjgh]hecho bitfield > mode}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jhjeubah}(h]h ]h"]h$]h&]uh1hhhhKhjaubh)}(h.bitfield up to 32 bits setting trace features.h]h.bitfield up to 32 bits setting trace features.}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjaubeh}(h]h ]h"]h$]h&]uh1hhjPubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``$> echo 0x012 > mode`` h]h)}(h``$> echo 0x012 > mode``h]j)}(hjh]h$> echo 0x012 > mode}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK"hjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhK%hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``reset`` (wo)h]h)}(hjh](j)}(h ``reset``h]hreset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (wo)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK'hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hAllh]h)}(hj0h]hAll}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hj.ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK(hjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKhhhKubh)}(h>Reset all programming to trace nothing / no logic programmed. h]h)}(h=Reset all programming to trace nothing / no logic programmed.h]h=Reset all programming to trace nothing / no logic programmed.}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj\ubah}(h]h ]h"]h$]h&]uh1hhjKubeh}(h]h ]h"]h$]h&]uh1hhhhK)hjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjzhhhKubh)}(h``echo 1 > reset`` h]h)}(h``echo 1 > reset``h]j)}(hjh]hecho 1 > reset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1hhjzubeh}(h]h ]h"]h$]h&]uh1hhhhK,hjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhK'ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhK/hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``enable_source`` (wo)h]h)}(hjh](j)}(h``enable_source``h]h enable_source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (wo)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK1hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hPRGCTLR, All hardware regs.h]h)}(hjh]hPRGCTLR, All hardware regs.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK2hjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhKubh)}(h- > 0 : Programs up the hardware with the current values held in the driver and enables trace. - = 0 : disable trace hardware. h]h bullet_list)}(hhh](h list_item)}(h]> 0 : Programs up the hardware with the current values held in the driver and enables trace. h]h)}(h\> 0 : Programs up the hardware with the current values held in the driver and enables trace.h]h\> 0 : Programs up the hardware with the current values held in the driver and enables trace.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hjKubah}(h]h ]h"]h$]h&]uh1jIhjFubjJ)}(h= 0 : disable trace hardware. h]h)}(h= 0 : disable trace hardware.h]h= 0 : disable trace hardware.}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK7hjcubah}(h]h ]h"]h$]h&]uh1jIhjFubeh}(h]h ]h"]h$]h&]bullet-uh1jDhhhK4hj@ubah}(h]h ]h"]h$]h&]uh1hhj/ubeh}(h]h ]h"]h$]h&]uh1hhhhK3hjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``echo 1 > enable_source`` h]h)}(h``echo 1 > enable_source``h]j)}(hjh]hecho 1 > enable_source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhK:hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK9hjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhK1ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK>hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hNone.h]h)}(hj)h]hNone.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK?hj'ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhK?hjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhKubh)}(h%CPU ID that this ETM is attached to. h]h)}(h$CPU ID that this ETM is attached to.h]h$CPU ID that this ETM is attached to.}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKAhjUubah}(h]h ]h"]h$]h&]uh1hhjDubeh}(h]h ]h"]h$]h&]uh1hhhhK@hjhhubh)}(hhh](h)}(hExampleh]hExample}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjshhhKubh)}(h``$> cat cpu`` ``$> 0`` h](h)}(h``$> cat cpu``h]j)}(hjh]h $> cat cpu}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKDhjubh)}(h``$> 0``h]j)}(hjh]h$> 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKFhjubeh}(h]h ]h"]h$]h&]uh1hhjsubeh}(h]h ]h"]h$]h&]uh1hhhhKChjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhK>ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKHhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``ts_source`` (ro)h]h)}(hjh](j)}(h ``ts_source``h]h ts_source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (ro)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKJhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKJhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hNone.h]h)}(hj$h]hNone.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKKhj"ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhKubh)}(hWhen FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1 indicates an unknown time source. Check trcidr0.tssize to see if a global timestamp is available. h]h)}(hWhen FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1 indicates an unknown time source. Check trcidr0.tssize to see if a global timestamp is available.h]hWhen FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1 indicates an unknown time source. Check trcidr0.tssize to see if a global timestamp is available.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKMhjPubah}(h]h ]h"]h$]h&]uh1hhj?ubeh}(h]h ]h"]h$]h&]uh1hhhhKLhjhhubh)}(hhh](h)}(hExampleh]hExample}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhhhKubh)}(h``$> cat ts_source`` ``$> 1`` h](h)}(h``$> cat ts_source``h]j)}(hjh]h$> cat ts_source}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKRhjubh)}(h``$> 1``h]j)}(hjh]h$> 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKThjubeh}(h]h ]h"]h$]h&]uh1hhjnubeh}(h]h ]h"]h$]h&]uh1hhhhKQhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKJubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKVhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``addr_idx`` (rw)h]h)}(hjh](j)}(h ``addr_idx``h]haddr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKXhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKXhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hNone.h]h)}(hjh]hNone.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKYhjubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKYhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj:hhhKubh)}(hmVirtual register to index address comparator and range features. Set index for first of the pair in a range. h]h)}(hlVirtual register to index address comparator and range features. Set index for first of the pair in a range.h]hlVirtual register to index address comparator and range features. Set index for first of the pair in a range.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK[hjKubah}(h]h ]h"]h$]h&]uh1hhj:ubeh}(h]h ]h"]h$]h&]uh1hhhhKZhjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjihhhKubh)}(h5``echo idx > addr_idx`` Where idx < nr_addr_cmp x 2 h](h)}(h``echo idx > addr_idx``h]j)}(hjh]hecho idx > addr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj~ubah}(h]h ]h"]h$]h&]uh1hhhhK_hjzubh)}(hWhere idx < nr_addr_cmp x 2h]hWhere idx < nr_addr_cmp x 2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKahjzubeh}(h]h ]h"]h$]h&]uh1hhjiubeh}(h]h ]h"]h$]h&]uh1hhhhK^hjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKXubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKchjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``addr_range`` (rw)h]h)}(hjh](j)}(h``addr_range``h]h addr_range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKehjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKehjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hACVR[idx, idx+1], VIIECTLRh]h)}(hjh]hACVR[idx, idx+1], VIIECTLR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKfhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhKubh)}(hPair of addresses for a range selected by addr_idx. Include / exclude according to the optional parameter, or if omitted uses the current ‘mode’ setting. Select comparator range in control register. Error if index is odd value. h]h)}(hPair of addresses for a range selected by addr_idx. Include / exclude according to the optional parameter, or if omitted uses the current ‘mode’ setting. Select comparator range in control register. Error if index is odd value.h]hPair of addresses for a range selected by addr_idx. Include / exclude according to the optional parameter, or if omitted uses the current ‘mode’ setting. Select comparator range in control register. Error if index is odd value.}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhj=ubah}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ]h"]h$]h&]uh1hhhhKghjhhubh)}(hhh](h)}(hDependsh]hDepends}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj[hhhKubh)}(h``mode, addr_idx``h]h)}(hjnh]j)}(hjnh]hmode, addr_idx}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhjpubah}(h]h ]h"]h$]h&]uh1hhhhKmhjlubah}(h]h ]h"]h$]h&]uh1hhj[ubeh}(h]h ]h"]h$]h&]uh1hhhhKmhjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``echo addr1 addr2 [exclude] > addr_range`` Where addr1 and addr2 define the range and addr1 < addr2. Optional exclude value:- - 0 for include - 1 for exclude.h](h)}(h+``echo addr1 addr2 [exclude] > addr_range``h]j)}(hjh]h'echo addr1 addr2 [exclude] > addr_range}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKohjubh)}(h9Where addr1 and addr2 define the range and addr1 < addr2.h]h9Where addr1 and addr2 define the range and addr1 < addr2.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjubh)}(hOptional exclude value:-h]hOptional exclude value:-}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKshjubjE)}(hhh](jJ)}(h 0 for includeh]h)}(hjh]h 0 for include}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKuhjubah}(h]h ]h"]h$]h&]uh1jIhjubjJ)}(h1 for exclude.h]h)}(hjh]h1 for exclude.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKvhjubah}(h]h ]h"]h$]h&]uh1jIhjubeh}(h]h ]h"]h$]h&]jjuh1jDhhhKuhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubh)}(hhh](h)}(hExampleh]hExample}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h)``$> echo 0x0000 0x2000 0 > addr_range`` h]h)}(h(``$> echo 0x0000 0x2000 0 > addr_range``h]j)}(hj4 h]h$$> echo 0x0000 0x2000 0 > addr_range}(hj6 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2 ubah}(h]h ]h"]h$]h&]uh1hhhhKxhj. ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKwhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKeubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKzhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjh hhhKubh)}(h``addr_single`` (rw)h]h)}(hj{ h](j)}(h``addr_single``h]h addr_single}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj} ubh (rw)}(hj} hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK|hjy ubah}(h]h ]h"]h$]h&]uh1hhjh ubeh}(h]h ]h"]h$]h&]uh1hhhhK|hje hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h ACVR[idx]h]h)}(hj h]h ACVR[idx]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK}hj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhK}hje hhubh)}(hhh](h)}(hNotesh]hNotes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hSet a single address comparator according to addr_idx. This is used if the address comparator is used as part of event generation logic etc. h]h)}(hSet a single address comparator according to addr_idx. This is used if the address comparator is used as part of event generation logic etc.h]hSet a single address comparator according to addr_idx. This is used if the address comparator is used as part of event generation logic etc.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhK~hje hhubh)}(hhh](h)}(hDependsh]hDepends}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h ``addr_idx``h]h)}(hj h]j)}(hj h]haddr_idx}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhje hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj8 hhhKubh)}(h``echo addr1 > addr_single`` h]h)}(h``echo addr1 > addr_single``h]j)}(hjO h]hecho addr1 > addr_single}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjM ubah}(h]h ]h"]h$]h&]uh1hhhhKhjI ubah}(h]h ]h"]h$]h&]uh1hhj8 ubeh}(h]h ]h"]h$]h&]uh1hhhhKhje hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhK|ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h``addr_start`` (rw)h]h)}(hj h](j)}(h``addr_start``h]h addr_start}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (rw)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hACVR[idx], VISSCTLRh]h)}(hj h]hACVR[idx], VISSCTLR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hNotesh]hNotes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hcSet a trace start address comparator according to addr_idx. Select comparator in control register. h]h)}(hbSet a trace start address comparator according to addr_idx. Select comparator in control register.h]hbSet a trace start address comparator according to addr_idx. Select comparator in control register.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hDependsh]hDepends}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h ``addr_idx``h]h)}(hj/ h]j)}(hj/ h]haddr_idx}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1 ubah}(h]h ]h"]h$]h&]uh1hhhhKhj- ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjV hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjS hhhKubh)}(h``echo addr1 > addr_start`` h]h)}(h``echo addr1 > addr_start``h]j)}(hjj h]hecho addr1 > addr_start}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjh ubah}(h]h ]h"]h$]h&]uh1hhhhKhjd ubah}(h]h ]h"]h$]h&]uh1hhjS ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h``addr_stop`` (rw)h]h)}(hj h](j)}(h ``addr_stop``h]h addr_stop}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (rw)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hACVR[idx], VISSCTLRh]h)}(hj h]hACVR[idx], VISSCTLR}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hNotesh]hNotes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hbSet a trace stop address comparator according to addr_idx. Select comparator in control register. h]h)}(haSet a trace stop address comparator according to addr_idx. Select comparator in control register.h]haSet a trace stop address comparator according to addr_idx. Select comparator in control register.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hDependsh]hDepends}(hj: hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7 hhhKubh)}(h ``addr_idx``h]h)}(hjJ h]j)}(hjJ h]haddr_idx}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjL ubah}(h]h ]h"]h$]h&]uh1hhhhKhjH ubah}(h]h ]h"]h$]h&]uh1hhj7 ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjn hhhKubh)}(h``echo addr1 > addr_stop`` h]h)}(h``echo addr1 > addr_stop``h]j)}(hj h]hecho addr1 > addr_stop}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjn ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h``addr_context`` (rw)h]h)}(hj h](j)}(h``addr_context``h]h addr_context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (rw)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hACATR[idx,{6:4}]h]h)}(hj h]hACATR[idx,{6:4}]}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hNotesh]hNotes}(hj& hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj# hhhKubh)}(h:Link context ID comparator to address comparator addr_idx h]h)}(h9Link context ID comparator to address comparator addr_idxh]h9Link context ID comparator to address comparator addr_idx}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj4 ubah}(h]h ]h"]h$]h&]uh1hhj# ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hDependsh]hDepends}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR hhhKubh)}(h ``addr_idx``h]h)}(hje h]j)}(hje h]haddr_idx}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjg ubah}(h]h ]h"]h$]h&]uh1hhhhKhjc ubah}(h]h ]h"]h$]h&]uh1hhjR ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hj``echo ctxt_idx > addr_context`` Where ctxt_idx is the index of the linked context id / vmid comparator. h](h)}(h ``echo ctxt_idx > addr_context``h]j)}(hj h]hecho ctxt_idx > addr_context}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubh)}(hGWhere ctxt_idx is the index of the linked context id / vmid comparator.h]hGWhere ctxt_idx is the index of the linked context id / vmid comparator.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h``addr_ctxtype`` (rw)h]h)}(hj h](j)}(h``addr_ctxtype``h]h addr_ctxtype}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (rw)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hACATR[idx,{3:2}]h]h)}(hj1h]hACATR[idx,{3:2}]}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj/ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hNotesh]hNotes}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhKubh)}(h>Input value string. Set type for linked context ID comparator h]h)}(h=Input value string. Set type for linked context ID comparatorh]h=Input value string. Set type for linked context ID comparator}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj]ubah}(h]h ]h"]h$]h&]uh1hhjLubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hDependsh]hDepends}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{hhhKubh)}(h ``addr_idx``h]h)}(hjh]j)}(hjh]haddr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhj{ubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hB``echo type > addr_ctxtype`` Type one of {all, vmid, ctxid, none}h](h)}(h``echo type > addr_ctxtype``h]j)}(hjh]hecho type > addr_ctxtype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(h$Type one of {all, vmid, ctxid, none}h]h$Type one of {all, vmid, ctxid, none}}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h!``$> echo ctxid > addr_ctxtype`` h]h)}(h ``$> echo ctxid > addr_ctxtype``h]j)}(hjh]h$> echo ctxid > addr_ctxtype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChhhKubh)}(h``addr_exlevel_s_ns`` (rw)h]h)}(hjVh](j)}(h``addr_exlevel_s_ns``h]haddr_exlevel_s_ns}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjXubh (rw)}(hjXhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjTubah}(h]h ]h"]h$]h&]uh1hhjCubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hACATR[idx,{14:8}]h]h)}(hjh]hACATR[idx,{14:8}]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hTSet the ELx secure and non-secure matching bits for the selected address comparator h]h)}(hSSet the ELx secure and non-secure matching bits for the selected address comparatorh]hSSet the ELx secure and non-secure matching bits for the selected address comparator}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``addr_idx``h]h)}(hjh]j)}(hjh]haddr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``echo val > addr_exlevel_s_ns`` val is a 7 bit value for exception levels to exclude. Input value shifted to correct bits in register.h](h)}(h ``echo val > addr_exlevel_s_ns``h]j)}(hj*h]hecho val > addr_exlevel_s_ns}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubh)}(hfval is a 7 bit value for exception levels to exclude. Input value shifted to correct bits in register.h]hfval is a 7 bit value for exception levels to exclude. Input value shifted to correct bits in register.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj$ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubh)}(hhh](h)}(hExampleh]hExample}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhKubh)}(h%``$> echo 0x4F > addr_exlevel_s_ns`` h]h)}(h$``$> echo 0x4F > addr_exlevel_s_ns``h]j)}(hjph]h $> echo 0x4F > addr_exlevel_s_ns}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjnubah}(h]h ]h"]h$]h&]uh1hhhhKhjjubah}(h]h ]h"]h$]h&]uh1hhjYubeh}(h]h ]h"]h$]h&]uh1hhhhKhj@hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``addr_instdatatype`` (rw)h]h)}(hjh](j)}(h``addr_instdatatype``h]haddr_instdatatype}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hACATR[idx,{1:0}]h]h)}(hjh]hACATR[idx,{1:0}]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(heSet the comparator address type for matching. Driver only supports setting instruction address type. h]h)}(hdSet the comparator address type for matching. Driver only supports setting instruction address type.h]hdSet the comparator address type for matching. Driver only supports setting instruction address type.}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hDependsh]hDepends}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhKubh)}(h ``addr_idx`` h]h)}(h ``addr_idx``h]j)}(hjTh]haddr_idx}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjRubah}(h]h ]h"]h$]h&]uh1hhhhKhjNubah}(h]h ]h"]h$]h&]uh1hhj=ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``addr_cmp_view`` (ro)h]h)}(hjh](j)}(h``addr_cmp_view``h]h addr_cmp_view}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (ro)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h&ACVR[idx, idx+1], ACATR[idx], VIIECTLRh]h)}(hjh]h&ACVR[idx, idx+1], ACATR[idx], VIIECTLR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hfRead the currently selected address comparator. If part of address range then display both addresses. h]h)}(heRead the currently selected address comparator. If part of address range then display both addresses.h]heRead the currently selected address comparator. If part of address range then display both addresses.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hDependsh]hDepends}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(h ``addr_idx``h]h)}(hj4h]j)}(hj4h]haddr_idx}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj6ubah}(h]h ]h"]h$]h&]uh1hhhhKhj2ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjXhhhKubh)}(h``cat addr_cmp_view``h]h)}(hjkh]j)}(hjkh]hcat addr_cmp_view}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1jhjmubah}(h]h ]h"]h$]h&]uh1hhhhKhjiubah}(h]h ]h"]h$]h&]uh1hhjXubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h] ``$> cat addr_cmp_view`` ``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)`` h](h)}(h``$> cat addr_cmp_view`` h]h)}(h``$> cat addr_cmp_view``h]j)}(hjh]h$> cat addr_cmp_view}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubh)}(hA``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)``h]j)}(hjh]h=addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``nr_addr_cmp`` (ro)h]h)}(hjh](j)}(h``nr_addr_cmp``h]h nr_addr_cmp}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (ro)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7hhhKubh)}(h From IDR4h]h)}(hjJh]h From IDR4}(hjLhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjHubah}(h]h ]h"]h$]h&]uh1hhj7ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjehhhKubh)}(h#Number of address comparator pairs h]h)}(h"Number of address comparator pairsh]h"Number of address comparator pairs}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjvubah}(h]h ]h"]h$]h&]uh1hhjeubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``sshot_idx`` (rw)h]h)}(hjh](j)}(h ``sshot_idx``h]h sshot_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hNoneh]h)}(hjh]hNone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h!Select single shot register set. h]h)}(h Select single shot register set.h]h Select single shot register set.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj"ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhKhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjShhhKubh)}(h``sshot_ctrl`` (rw)h]h)}(hjfh](j)}(h``sshot_ctrl``h]h sshot_ctrl}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjhubh (rw)}(hjhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjdubah}(h]h ]h"]h$]h&]uh1hhjSubeh}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h SSCCR[idx]h]h)}(hjh]h SSCCR[idx]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h2Access a single shot comparator control register. h]h)}(h1Access a single shot comparator control register.h]h1Access a single shot comparator control register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``sshot_idx``h]h)}(hjh]j)}(hjh]h sshot_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhKubh)}(hJ``echo val > sshot_ctrl`` Writes val into the selected control register. h](h)}(h``echo val > sshot_ctrl``h]j)}(hj:h]hecho val > sshot_ctrl}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8ubah}(h]h ]h"]h$]h&]uh1hhhhKhj4ubh)}(h.Writes val into the selected control register.h]h.Writes val into the selected control register.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4ubeh}(h]h ]h"]h$]h&]uh1hhj#ubeh}(h]h ]h"]h$]h&]uh1hhhhKhjPhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhKubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj|hhhKubh)}(h``sshot_status`` (ro)h]h)}(hjh](j)}(h``sshot_status``h]h sshot_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (ro)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhj|ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjyhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h SSCSR[idx]h]h)}(hjh]h SSCSR[idx]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjyhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h.Read a single shot comparator status register h]h)}(h-Read a single shot comparator status registerh]h-Read a single shot comparator status register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjyhhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``sshot_idx``h]h)}(hj(h]j)}(hj(h]h sshot_idx}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hhhhM hj&ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM hjyhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjLhhhKubh)}(h"``cat sshot_status`` Read status.h](h)}(h``cat sshot_status``h]j)}(hjch]hcat sshot_status}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jhjaubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubh)}(h Read status.h]h Read status.}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj]ubeh}(h]h ]h"]h$]h&]uh1hhjLubeh}(h]h ]h"]h$]h&]uh1hhhhM hjyhhubh)}(hhh](h)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h!``$> cat sshot_status`` ``0x1`` h](h)}(h``$> cat sshot_status``h]j)}(hjh]h$> cat sshot_status}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h``0x1``h]j)}(hjh]h0x1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjyhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``sshot_pe_ctrl`` (rw)h]h)}(hjh](j)}(h``sshot_pe_ctrl``h]h sshot_pe_ctrl}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj ubh (rw)}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhKubh)}(h SSPCICR[idx]h]h)}(hjCh]h SSPCICR[idx]}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjAubah}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj^hhhKubh)}(h;Access a single shot PE comparator input control register. h]h)}(h:Access a single shot PE comparator input control register.h]h:Access a single shot PE comparator input control register.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjoubah}(h]h ]h"]h$]h&]uh1hhj^ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``sshot_idx``h]h)}(hjh]j)}(hjh]h sshot_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hM``echo val > sshot_pe_ctrl`` Writes val into the selected control register. h](h)}(h``echo val > sshot_pe_ctrl``h]j)}(hjh]hecho val > sshot_pe_ctrl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubh)}(h.Writes val into the selected control register.h]h.Writes val into the selected control register.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``ns_exlevel_vinst`` (rw)h]h)}(hj0h](j)}(h``ns_exlevel_vinst``h]hns_exlevel_vinst}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj2ubh (rw)}(hj2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM"hj.ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM"hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjYhhhKubh)}(h VICTLR{23:20}h]h)}(hjlh]h VICTLR{23:20}}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjjubah}(h]h ]h"]h$]h&]uh1hhjYubeh}(h]h ]h"]h$]h&]uh1hhhhM#hjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hProgram non-secure exception level filters. Set / clear NS exception filter bits. Setting ‘1’ excludes trace from the exception level. h]h)}(hProgram non-secure exception level filters. Set / clear NS exception filter bits. Setting ‘1’ excludes trace from the exception level.h]hProgram non-secure exception level filters. Set / clear NS exception filter bits. Setting ‘1’ excludes trace from the exception level.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM%hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM$hjhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h_``echo bitfield > ns_exlevel_viinst`` Where bitfield contains bits to set clear for EL0 to EL2h](h)}(h%``echo bitfield > ns_exlevel_viinst``h]j)}(hjh]h!echo bitfield > ns_exlevel_viinst}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM*hjubh)}(h8Where bitfield contains bits to set clear for EL0 to EL2h]h8Where bitfield contains bits to set clear for EL0 to EL2}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM,hjubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM)hjhhubh)}(hhh](h)}(hExampleh]hExample}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h<``%> echo 0x4 > ns_exlevel_viinst`` Excludes EL2 NS trace. h](h)}(h#``%> echo 0x4 > ns_exlevel_viinst``h]j)}(hjh]h%> echo 0x4 > ns_exlevel_viinst}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM.hj ubh)}(hExcludes EL2 NS trace.h]hExcludes EL2 NS trace.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM-hjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM"ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM2hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhKubh)}(h ``vinst_pe_cmp_start_stop`` (rw)h]h)}(hjhh](j)}(h``vinst_pe_cmp_start_stop``h]hvinst_pe_cmp_start_stop}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubh (rw)}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM4hjfubah}(h]h ]h"]h$]h&]uh1hhjUubeh}(h]h ]h"]h$]h&]uh1hhhhM4hjRhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h VIPCSSCTLRh]h)}(hjh]h VIPCSSCTLR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM5hjRhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h8Access PE start stop comparator input control registers h]h)}(h7Access PE start stop comparator input control registersh]h7Access PE start stop comparator input control registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM6hjRhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM4ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM9hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``bb_ctrl`` (rw)h]h)}(hjh](j)}(h ``bb_ctrl``h]hbb_ctrl}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM;hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=hhhKubh)}(hBBCTLRh]h)}(hjPh]hBBCTLR}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM<hjNubah}(h]h ]h"]h$]h&]uh1hhj=ubeh}(h]h ]h"]h$]h&]uh1hhhhM<hjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjkhhhKubh)}(hUDefine ranges that Branch Broadcast will operate in. Default (0x0) is all addresses. h]h)}(hTDefine ranges that Branch Broadcast will operate in. Default (0x0) is all addresses.h]hTDefine ranges that Branch Broadcast will operate in. Default (0x0) is all addresses.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj|ubah}(h]h ]h"]h$]h&]uh1hhjkubeh}(h]h ]h"]h$]h&]uh1hhhhM=hjhhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h BB enabled. h]h)}(h BB enabled.h]h BB enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMAhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM;ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMChjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``cyc_threshold`` (rw)h]h)}(hjh](j)}(h``cyc_threshold``h]h cyc_threshold}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMEhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMEhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hCCCTLRh]h)}(hj+h]hCCCTLR}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMFhj)ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMFhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFhhhKubh)}(hSet the threshold for which cycle counts will be emitted. Error if attempt to set below minimum defined in IDR3, masked to width of valid bits. h]h)}(hSet the threshold for which cycle counts will be emitted. Error if attempt to set below minimum defined in IDR3, masked to width of valid bits.h]hSet the threshold for which cycle counts will be emitted. Error if attempt to set below minimum defined in IDR3, masked to width of valid bits.}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMHhjWubah}(h]h ]h"]h$]h&]uh1hhjFubeh}(h]h ]h"]h$]h&]uh1hhhhMGhjhhubh)}(hhh](h)}(hDependsh]hDepends}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjuhhhKubh)}(h CC enabled. h]h)}(h CC enabled.h]h CC enabled.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhjubah}(h]h ]h"]h$]h&]uh1hhjuubeh}(h]h ]h"]h$]h&]uh1hhhhMLhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMEubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMNhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``syncfreq`` (rw)h]h)}(hjh](j)}(h ``syncfreq``h]hsyncfreq}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMPhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMPhjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hSYNCPRh]h)}(hjh]hSYNCPR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMQhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMQhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(hoSet trace synchronisation period. Power of 2 value, 0 (off) or 8-20. Driver defaults to 12 (every 4096 bytes). h]h)}(hnSet trace synchronisation period. Power of 2 value, 0 (off) or 8-20. Driver defaults to 12 (every 4096 bytes).h]hnSet trace synchronisation period. Power of 2 value, 0 (off) or 8-20. Driver defaults to 12 (every 4096 bytes).}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj2ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhMRhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMPubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMVhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjchhhKubh)}(h``cntr_idx`` (rw)h]h)}(hjvh](j)}(h ``cntr_idx``h]hcntr_idx}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjxubh (rw)}(hjxhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMXhjtubah}(h]h ]h"]h$]h&]uh1hhjcubeh}(h]h ]h"]h$]h&]uh1hhhhMXhj`hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hnoneh]h)}(hjh]hnone}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMYhj`hhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hSelect the counter to access h]h)}(hSelect the counter to accessh]hSelect the counter to access}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMZhj`hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h-``echo idx > cntr_idx`` Where idx < nr_cntr h](h)}(h``echo idx > cntr_idx``h]j)}(hjh]hecho idx > cntr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhM^hj ubh)}(hWhere idx < nr_cntrh]hWhere idx < nr_cntr}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM`hj ubeh}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM]hj`hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMXubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMbhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjXhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjUhhhKubh)}(h``cntr_ctrl`` (rw)h]h)}(hjhh](j)}(h ``cntr_ctrl``h]h cntr_ctrl}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjjubh (rw)}(hjjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMdhjfubah}(h]h ]h"]h$]h&]uh1hhjUubeh}(h]h ]h"]h$]h&]uh1hhhhMdhjRhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h CNTCTLR[idx]h]h)}(hjh]h CNTCTLR[idx]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMehjRhhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hSet counter control value. h]h)}(hSet counter control value.h]hSet counter control value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMfhjRhhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``cntr_idx``h]h)}(hjh]j)}(hjh]hcntr_idx}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1hhhhMihjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMihjRhhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhKubh)}(h7``echo val > cntr_ctrl`` Where val is per ETMv4 spec. h](h)}(h``echo val > cntr_ctrl``h]j)}(hj<h]hecho val > cntr_ctrl}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj:ubah}(h]h ]h"]h$]h&]uh1hhhhMkhj6ubh)}(hWhere val is per ETMv4 spec.h]hWhere val is per ETMv4 spec.}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMmhj6ubeh}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]uh1hhhhMjhjRhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMdubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMohjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj~hhhKubh)}(h``cntrldvr`` (rw)h]h)}(hjh](j)}(h ``cntrldvr``h]hcntrldvr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (rw)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMqhjubah}(h]h ]h"]h$]h&]uh1hhj~ubeh}(h]h ]h"]h$]h&]uh1hhhhMqhj{hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h CNTRLDVR[idx]h]h)}(hjh]h CNTRLDVR[idx]}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMrhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMrhj{hhubh)}(hhh](h)}(hNotesh]hNotes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(hSet counter reload value. h]h)}(hSet counter reload value.h]hSet counter reload value.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMthjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMshj{hhubh)}(hhh](h)}(hDependsh]hDepends}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h ``cntr_idx``h]h)}(hj*h]j)}(hj*h]hcntr_idx}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hhhhMvhj(ubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMvhj{hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhKubh)}(h6``echo val > cntrldvr`` Where val is per ETMv4 spec. h](h)}(h``echo val > cntrldvr``h]j)}(hjeh]hecho val > cntrldvr}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jhjcubah}(h]h ]h"]h$]h&]uh1hhhhMxhj_ubh)}(hWhere val is per ETMv4 spec.h]hWhere val is per ETMv4 spec.}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMzhj_ubeh}(h]h ]h"]h$]h&]uh1hhjNubeh}(h]h ]h"]h$]h&]uh1hhhhMwhj{hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMqubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM|hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h``nr_cntr`` (ro)h]h)}(hjh](j)}(h ``nr_cntr``h]hnr_cntr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh (ro)}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM~hjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhM~hjhhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhKubh)}(h From IDR5 h]h)}(h From IDR5h]h From IDR5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1hhjubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(hhh](h)}(hNotesh]hNotes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h Number of counters implemented. h]h)}(hNumber of counters implemented.h]hNumber of counters implemented.}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj# ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM~ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjT hhhKubh)}(h``ctxid_idx`` (rw)h]h)}(hjg h](j)}(h ``ctxid_idx``h]h ctxid_idx}(hjl hhhNhNubah}(h]h ]h"]h$]h&]uh1jhji ubh (rw)}(hji hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhje ubah}(h]h ]h"]h$]h&]uh1hhjT ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjQ hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(hNoneh]h)}(hj h]hNone}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjQ hhubh)}(hhh](h)}(hNotesh]hNotes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h+Select the context ID comparator to access h]h)}(h*Select the context ID comparator to accessh]h*Select the context ID comparator to access}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjQ hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhKubh)}(h.``echo idx > ctxid_idx`` Where idx < numcidc h](h)}(h``echo idx > ctxid_idx``h]j)}(hj!h]hecho idx > ctxid_idx}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubh)}(hWhere idx < numcidch]hWhere idx < numcidc}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubeh}(h]h ]h"]h$]h&]uh1hhj ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjQ hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjI!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjF!hhhKubh)}(h``ctxid_pid`` (rw)h]h)}(hjY!h](j)}(h ``ctxid_pid``h]h ctxid_pid}(hj^!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj[!ubh (rw)}(hj[!hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjW!ubah}(h]h ]h"]h$]h&]uh1hhjF!ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjC!hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(h CIDCVR[idx]h]h)}(hj!h]h CIDCVR[idx]}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjC!hhubh)}(hhh](h)}(hNotesh]hNotes}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(h$Set the context ID comparator value h]h)}(h#Set the context ID comparator valueh]h#Set the context ID comparator value}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjC!hhubh)}(hhh](h)}(hDependsh]hDepends}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj!hhhKubh)}(h``ctxid_idx`` h]h)}(h ``ctxid_idx``h]j)}(hj!h]h ctxid_idx}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!ubah}(h]h ]h"]h$]h&]uh1hhhhMhj!ubah}(h]h ]h"]h$]h&]uh1hhj!ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjC!hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj-"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*"hhhKubh)}(h``ctxid_masks`` (rw)h]h)}(hj="h](j)}(h``ctxid_masks``h]h ctxid_masks}(hjB"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?"ubh (rw)}(hj?"hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;"ubah}(h]h ]h"]h$]h&]uh1hhj*"ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'"hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hji"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf"hhhKubh)}(h!CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>h]h)}(hjy"h]h!CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>}(hj{"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjw"ubah}(h]h ]h"]h$]h&]uh1hhjf"ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'"hhubh)}(hhh](h)}(hNotesh]hNotes}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhKubh)}(hPair of values to set the byte masks for 1-8 context ID comparators. Automatically clears masked bytes to 0 in CID value registers. h]h)}(hPair of values to set the byte masks for 1-8 context ID comparators. Automatically clears masked bytes to 0 in CID value registers.h]hPair of values to set the byte masks for 1-8 context ID comparators. Automatically clears masked bytes to 0 in CID value registers.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"ubah}(h]h ]h"]h$]h&]uh1hhj"ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'"hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj"hhhKubh)}(h``echo m3m2m1m0 [m7m6m5m4] > ctxid_masks`` 32 bit values made up of mask bytes, where mN represents a byte mask value for Context ID comparator N. Second value not required on systems that have fewer than 4 context ID comparators h](h)}(h*``echo m3m2m1m0 [m7m6m5m4] > ctxid_masks``h]j)}(hj"h]h&echo m3m2m1m0 [m7m6m5m4] > ctxid_masks}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj"ubah}(h]h ]h"]h$]h&]uh1hhhhMhj"ubh)}(hg32 bit values made up of mask bytes, where mN represents a byte mask value for Context ID comparator N.h]hg32 bit values made up of mask bytes, where mN represents a byte mask value for Context ID comparator N.}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"ubh)}(hRSecond value not required on systems that have fewer than 4 context ID comparatorsh]hRSecond value not required on systems that have fewer than 4 context ID comparators}(hj"hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"ubeh}(h]h ]h"]h$]h&]uh1hhj"ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'"hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj-#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*#hhhKubh)}(h``numcidc`` (ro)h]h)}(hj=#h](j)}(h ``numcidc``h]hnumcidc}(hjB#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj?#ubh (ro)}(hj?#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj;#ubah}(h]h ]h"]h$]h&]uh1hhj*#ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'#hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hji#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf#hhhKubh)}(h From IDR4h]h)}(hjy#h]h From IDR4}(hj{#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjw#ubah}(h]h ]h"]h$]h&]uh1hhjf#ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'#hhubh)}(hhh](h)}(hNotesh]hNotes}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhKubh)}(h!Number of Context ID comparators h]h)}(h Number of Context ID comparatorsh]h Number of Context ID comparators}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1hhj#ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj'#hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#hhhKubh)}(h``vmid_idx`` (rw)h]h)}(hj#h](j)}(h ``vmid_idx``h]hvmid_idx}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj#ubh (rw)}(hj#hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#ubah}(h]h ]h"]h$]h&]uh1hhj#ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhKubh)}(hNoneh]h)}(hj%$h]hNone}(hj'$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj#$ubah}(h]h ]h"]h$]h&]uh1hhj$ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubh)}(hhh](h)}(hNotesh]hNotes}(hjC$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@$hhhKubh)}(h'Select the VM ID comparator to access. h]h)}(h&Select the VM ID comparator to access.h]h&Select the VM ID comparator to access.}(hjU$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQ$ubah}(h]h ]h"]h$]h&]uh1hhj@$ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjr$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo$hhhKubh)}(h/``echo idx > vmid_idx`` Where idx < numvmidc h](h)}(h``echo idx > vmid_idx``h]j)}(hj$h]hecho idx > vmid_idx}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubh)}(hWhere idx < numvmidch]hWhere idx < numvmidc}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$ubeh}(h]h ]h"]h$]h&]uh1hhjo$ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj#hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$hhhKubh)}(h``vmid_val`` (rw)h]h)}(hj$h](j)}(h ``vmid_val``h]hvmid_val}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj$ubh (rw)}(hj$hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$ubah}(h]h ]h"]h$]h&]uh1hhj$ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhKubh)}(h VMIDCVR[idx]h]h)}(hj%h]h VMIDCVR[idx]}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubh)}(hhh](h)}(hNotesh]hNotes}(hj5%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2%hhhKubh)}(hSet the VM ID comparator value h]h)}(hSet the VM ID comparator valueh]hSet the VM ID comparator value}(hjG%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjC%ubah}(h]h ]h"]h$]h&]uh1hhj2%ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubh)}(hhh](h)}(hDependsh]hDepends}(hjd%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja%hhhKubh)}(h ``vmid_idx`` h]h)}(h ``vmid_idx``h]j)}(hjx%h]hvmid_idx}(hjz%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjv%ubah}(h]h ]h"]h$]h&]uh1hhhhMhjr%ubah}(h]h ]h"]h$]h&]uh1hhja%ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhKubh)}(h``vmid_masks`` (rw)h]h)}(hj%h](j)}(h``vmid_masks``h]h vmid_masks}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj%ubh (rw)}(hj%hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj%hhhKubh)}(h$VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>h]h)}(hj%h]h$VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubah}(h]h ]h"]h$]h&]uh1hhj%ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hhh](h)}(hNotesh]hNotes}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhKubh)}(hPair of values to set the byte masks for 1-8 VM ID comparators. Automatically clears masked bytes to 0 in VMID value registers. h]h)}(hPair of values to set the byte masks for 1-8 VM ID comparators. Automatically clears masked bytes to 0 in VMID value registers.h]hPair of values to set the byte masks for 1-8 VM ID comparators. Automatically clears masked bytes to 0 in VMID value registers.}(hj+&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'&ubah}(h]h ]h"]h$]h&]uh1hhj&ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjH&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjE&hhhKubh)}(h``echo m3m2m1m0 [m7m6m5m4] > vmid_masks`` Where mN represents a byte mask value for VMID comparator N. Second value not required on systems that have fewer than 4 VMID comparators. h](h)}(h)``echo m3m2m1m0 [m7m6m5m4] > vmid_masks``h]j)}(hj\&h]h%echo m3m2m1m0 [m7m6m5m4] > vmid_masks}(hj^&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjZ&ubah}(h]h ]h"]h$]h&]uh1hhhhMhjV&ubh)}(hWhere mN represents a byte mask value for VMID comparator N. Second value not required on systems that have fewer than 4 VMID comparators.h]hWhere mN represents a byte mask value for VMID comparator N. Second value not required on systems that have fewer than 4 VMID comparators.}(hjq&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjV&ubeh}(h]h ]h"]h$]h&]uh1hhjE&ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj%hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhKubh)}(h``numvmidc`` (ro)h]h)}(hj&h](j)}(h ``numvmidc``h]hnumvmidc}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&ubh (ro)}(hj&hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1hhj&ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj&hhhKubh)}(h From IDR4h]h)}(hj&h]h From IDR4}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1hhj&ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubh)}(hhh](h)}(hNotesh]hNotes}(hj 'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhKubh)}(hNumber of VMID comparators h]h)}(hNumber of VMID comparatorsh]hNumber of VMID comparators}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj&hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjM'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjJ'hhhKubh)}(h``res_idx`` (rw)h]h)}(hj]'h](j)}(h ``res_idx``h]hres_idx}(hjb'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj_'ubh (rw)}(hj_'hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj['ubah}(h]h ]h"]h$]h&]uh1hhjJ'ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjG'hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhKubh)}(hNone.h]h)}(hj'h]hNone.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjG'hhubh)}(hhh](h)}(hNotesh]hNotes}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhKubh)}(hhSelect the resource selector control to access. Must be 2 or higher as selectors 0 and 1 are hardwired. h]h)}(hgSelect the resource selector control to access. Must be 2 or higher as selectors 0 and 1 are hardwired.h]hgSelect the resource selector control to access. Must be 2 or higher as selectors 0 and 1 are hardwired.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubah}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjG'hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj'hhhKubh)}(h9``echo idx > res_idx`` Where 2 <= idx < nr_resource x 2 h](h)}(h``echo idx > res_idx``h]j)}(hj'h]hecho idx > res_idx}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj'ubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubh)}(h Where 2 <= idx < nr_resource x 2h]h Where 2 <= idx < nr_resource x 2}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj'ubeh}(h]h ]h"]h$]h&]uh1hhj'ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjG'hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj?(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj<(hhhKubh)}(h``res_ctrl`` (rw)h]h)}(hjO(h](j)}(h ``res_ctrl``h]hres_ctrl}(hjT(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQ(ubh (rw)}(hjQ(hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjM(ubah}(h]h ]h"]h$]h&]uh1hhj<(ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9(hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj{(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjx(hhhKubh)}(h RSCTLR[idx]h]h)}(hj(h]h RSCTLR[idx]}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhjx(ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9(hhubh)}(hhh](h)}(hNotesh]hNotes}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhKubh)}(h;Set resource selector control value. Value per ETMv4 spec. h]h)}(h:Set resource selector control value. Value per ETMv4 spec.h]h:Set resource selector control value. Value per ETMv4 spec.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhj(ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9(hhubh)}(hhh](h)}(hDependsh]hDepends}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj(hhhKubh)}(h ``res_idx``h]h)}(hj(h]j)}(hj(h]hres_idx}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj(ubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1hhj(ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9(hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj )hhhKubh)}(h6``echo val > res_cntr`` Where val is per ETMv4 spec. h](h)}(h``echo val > res_cntr``h]j)}(hj#)h]hecho val > res_cntr}(hj%)hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj!)ubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubh)}(hWhere val is per ETMv4 spec.h]hWhere val is per ETMv4 spec.}(hj8)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubeh}(h]h ]h"]h$]h&]uh1hhj )ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj9(hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjh)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje)hhhKubh)}(h``nr_resource`` (ro)h]h)}(hjx)h](j)}(h``nr_resource``h]h nr_resource}(hj})hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjz)ubh (ro)}(hjz)hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjv)ubah}(h]h ]h"]h$]h&]uh1hhje)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjb)hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhKubh)}(h From IDR4h]h)}(hj)h]h From IDR4}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1hhj)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjb)hhubh)}(hhh](h)}(hNotesh]hNotes}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj)hhhKubh)}(h"Number of resource selector pairs h]h)}(h!Number of resource selector pairsh]h!Number of resource selector pairs}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj)ubah}(h]h ]h"]h$]h&]uh1hhj)ubeh}(h]h ]h"]h$]h&]uh1hhhhMhjb)hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhKubh)}(h``event`` (rw)h]h)}(hj$*h](j)}(h ``event``h]hevent}(hj)*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj&*ubh (rw)}(hj&*hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj"*ubah}(h]h ]h"]h$]h&]uh1hhj*ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjP*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjM*hhhKubh)}(h EVENTCTRL0Rh]h)}(hj`*h]h EVENTCTRL0R}(hjb*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj^*ubah}(h]h ]h"]h$]h&]uh1hhjM*ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubh)}(hhh](h)}(hNotesh]hNotes}(hj~*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj{*hhhKubh)}(h&Set up to 4 implemented event fields. h]h)}(h%Set up to 4 implemented event fields.h]h%Set up to 4 implemented event fields.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubah}(h]h ]h"]h$]h&]uh1hhj{*ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj*hhhKubh)}(h``echo ev3ev2ev1ev0 > event`` Where evN is an 8 bit event field. Up to 4 event fields make up the 32-bit input value. Number of valid fields is implementation dependent, defined in IDR0. h](h)}(h``echo ev3ev2ev1ev0 > event``h]j)}(hj*h]hecho ev3ev2ev1ev0 > event}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj*ubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubh)}(hWhere evN is an 8 bit event field. Up to 4 event fields make up the 32-bit input value. Number of valid fields is implementation dependent, defined in IDR0.h]hWhere evN is an 8 bit event field. Up to 4 event fields make up the 32-bit input value. Number of valid fields is implementation dependent, defined in IDR0.}(hj*hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*ubeh}(h]h ]h"]h$]h&]uh1hhj*ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj*hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj+hhhKubh)}(h``event_instren`` (rw)h]h)}(hj+h](j)}(h``event_instren``h]h event_instren}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubh (rw)}(hj+hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+ubah}(h]h ]h"]h$]h&]uh1hhj+ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjB+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?+hhhKubh)}(h EVENTCTRL1Rh]h)}(hjR+h]h EVENTCTRL1R}(hjT+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjP+ubah}(h]h ]h"]h$]h&]uh1hhj?+ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+hhubh)}(hhh](h)}(hNotesh]hNotes}(hjp+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjm+hhhKubh)}(h event_instren`` Where bitfield is up to 4 bits according to number of event fields. h](h)}(h!``echo bitfield > event_instren``h]j)}(hj+h]hecho bitfield > event_instren}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj+ubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubh)}(hCWhere bitfield is up to 4 bits according to number of event fields.h]hCWhere bitfield is up to 4 bits according to number of event fields.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj+ubeh}(h]h ]h"]h$]h&]uh1hhj+ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj+hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj&,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj#,hhhKubh)}(h``event_ts`` (rw)h]h)}(hj6,h](j)}(h ``event_ts``h]hevent_ts}(hj;,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj8,ubh (rw)}(hj8,hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj4,ubah}(h]h ]h"]h$]h&]uh1hhj#,ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ,hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjb,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_,hhhKubh)}(hTSCTLRh]h)}(hjr,h]hTSCTLR}(hjt,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjp,ubah}(h]h ]h"]h$]h&]uh1hhj_,ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ,hhubh)}(hhh](h)}(hNotesh]hNotes}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhKubh)}(h5Set the event that will generate timestamp requests. h]h)}(h4Set the event that will generate timestamp requests.h]h4Set the event that will generate timestamp requests.}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ,hhubh)}(hhh](h)}(hDependsh]hDepends}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhKubh)}(h``TS activated``h]h)}(hj,h]j)}(hj,h]h TS activated}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj,ubah}(h]h ]h"]h$]h&]uh1hhhhM hj,ubah}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ]h"]h$]h&]uh1hhhhM hj ,hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj,hhhKubh)}(hG``echo evfield > event_ts`` Where evfield is an 8 bit event selector. h](h)}(h``echo evfield > event_ts``h]j)}(hj -h]hecho evfield > event_ts}(hj -hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj-ubah}(h]h ]h"]h$]h&]uh1hhhhM"hj-ubh)}(h)Where evfield is an 8 bit event selector.h]h)Where evfield is an 8 bit event selector.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj-ubeh}(h]h ]h"]h$]h&]uh1hhj,ubeh}(h]h ]h"]h$]h&]uh1hhhhM!hj ,hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM&hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjO-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjL-hhhKubh)}(h``seq_idx`` (rw)h]h)}(hj_-h](j)}(h ``seq_idx``h]hseq_idx}(hjd-hhhNhNubah}(h]h ]h"]h$]h&]uh1jhja-ubh (rw)}(hja-hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM(hj]-ubah}(h]h ]h"]h$]h&]uh1hhjL-ubeh}(h]h ]h"]h$]h&]uh1hhhhM(hjI-hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhKubh)}(hNoneh]h)}(hj-h]hNone}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj-ubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]uh1hhhhM)hjI-hhubh)}(hhh](h)}(hNotesh]hNotes}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhKubh)}(h)Sequencer event register select - 0 to 2 h]h)}(h(Sequencer event register select - 0 to 2h]h(Sequencer event register select - 0 to 2}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj-ubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]uh1hhhhM*hjI-hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM(ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM-hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj-hhhKubh)}(h``seq_state`` (rw)h]h)}(hj .h](j)}(h ``seq_state``h]h seq_state}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj .ubh (rw)}(hj .hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM/hj .ubah}(h]h ]h"]h$]h&]uh1hhj-ubeh}(h]h ]h"]h$]h&]uh1hhhhM/hj-hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj7.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4.hhhKubh)}(hSEQSTRh]h)}(hjG.h]hSEQSTR}(hjI.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hjE.ubah}(h]h ]h"]h$]h&]uh1hhj4.ubeh}(h]h ]h"]h$]h&]uh1hhhhM0hj-hhubh)}(hhh](h)}(hNotesh]hNotes}(hje.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjb.hhhKubh)}(h"Sequencer current state - 0 to 3. h]h)}(h!Sequencer current state - 0 to 3.h]h!Sequencer current state - 0 to 3.}(hjw.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM2hjs.ubah}(h]h ]h"]h$]h&]uh1hhjb.ubeh}(h]h ]h"]h$]h&]uh1hhhhM1hj-hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM/ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM4hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhKubh)}(h``seq_event`` (rw)h]h)}(hj.h](j)}(h ``seq_event``h]h seq_event}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj.ubh (rw)}(hj.hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM6hj.ubah}(h]h ]h"]h$]h&]uh1hhj.ubeh}(h]h ]h"]h$]h&]uh1hhhhM6hj.hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj.hhhKubh)}(h SEQEVR[idx]h]h)}(hj.h]h SEQEVR[idx]}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM7hj.ubah}(h]h ]h"]h$]h&]uh1hhj.ubeh}(h]h ]h"]h$]h&]uh1hhhhM7hj.hhubh)}(hhh](h)}(hNotesh]hNotes}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj/hhhKubh)}(h!State transition event registers h]h)}(h State transition event registersh]h State transition event registers}(hj#/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hj/ubah}(h]h ]h"]h$]h&]uh1hhj/ubeh}(h]h ]h"]h$]h&]uh1hhhhM8hj.hhubh)}(hhh](h)}(hDependsh]hDepends}(hj@/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj=/hhhKubh)}(h ``seq_idx``h]h)}(hjP/h]j)}(hjP/h]hseq_idx}(hjU/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjR/ubah}(h]h ]h"]h$]h&]uh1hhhhM;hjN/ubah}(h]h ]h"]h$]h&]uh1hhj=/ubeh}(h]h ]h"]h$]h&]uh1hhhhM;hj.hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hjw/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjt/hhhKubh)}(h|``echo evBevF > seq_event`` Where evBevF is a 16 bit value made up of two event selectors, - evB : back - evF : forwards. h](h)}(h``echo evBevF > seq_event``h]j)}(hj/h]hecho evBevF > seq_event}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj/ubah}(h]h ]h"]h$]h&]uh1hhhhM=hj/ubh)}(h>Where evBevF is a 16 bit value made up of two event selectors,h]h>Where evBevF is a 16 bit value made up of two event selectors,}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj/ubjE)}(hhh](jJ)}(h evB : backh]h)}(hj/h]h evB : back}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhj/ubah}(h]h ]h"]h$]h&]uh1jIhj/ubjJ)}(hevF : forwards. h]h)}(hevF : forwards.h]hevF : forwards.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhj/ubah}(h]h ]h"]h$]h&]uh1jIhj/ubeh}(h]h ]h"]h$]h&]jjuh1jDhhhMAhj/ubeh}(h]h ]h"]h$]h&]uh1hhjt/ubeh}(h]h ]h"]h$]h&]uh1hhhhM<hj.hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM6ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMDhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhKubh)}(h``seq_reset_event`` (rw)h]h)}(hj0h](j)}(h``seq_reset_event``h]hseq_reset_event}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubh (rw)}(hj0hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMFhj0ubah}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ]h"]h$]h&]uh1hhhhMFhj0hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hjD0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjA0hhhKubh)}(h SEQRSTEVRh]h)}(hjT0h]h SEQRSTEVR}(hjV0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhjR0ubah}(h]h ]h"]h$]h&]uh1hhjA0ubeh}(h]h ]h"]h$]h&]uh1hhhhMGhj0hhubh)}(hhh](h)}(hNotesh]hNotes}(hjr0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjo0hhhKubh)}(hSequencer reset event h]h)}(hSequencer reset eventh]hSequencer reset event}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMIhj0ubah}(h]h ]h"]h$]h&]uh1hhjo0ubeh}(h]h ]h"]h$]h&]uh1hhhhMHhj0hhubh)}(hhh](h)}(hSyntaxh]hSyntax}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhKubh)}(hN``echo evfield > seq_reset_event`` Where evfield is an 8 bit event selector. h](h)}(h"``echo evfield > seq_reset_event``h]j)}(hj0h]hecho evfield > seq_reset_event}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj0ubah}(h]h ]h"]h$]h&]uh1hhhhMLhj0ubh)}(h)Where evfield is an 8 bit event selector.h]h)Where evfield is an 8 bit event selector.}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj0ubeh}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ]h"]h$]h&]uh1hhhhMKhj0hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMFubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMPhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj0hhhKubh)}(h``nrseqstate`` (ro)h]h)}(hj 1h](j)}(h``nrseqstate``h]h nrseqstate}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj 1ubh (ro)}(hj 1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMRhj1ubah}(h]h ]h"]h$]h&]uh1hhj0ubeh}(h]h ]h"]h$]h&]uh1hhhhMRhj0hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj61hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj31hhhKubh)}(h From IDR5h]h)}(hjF1h]h From IDR5}(hjH1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShjD1ubah}(h]h ]h"]h$]h&]uh1hhj31ubeh}(h]h ]h"]h$]h&]uh1hhhhMShj0hhubh)}(hhh](h)}(hNotesh]hNotes}(hjd1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhja1hhhKubh)}(h$Number of sequencer states (0 or 4) h]h)}(h#Number of sequencer states (0 or 4)h]h#Number of sequencer states (0 or 4)}(hjv1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhjr1ubah}(h]h ]h"]h$]h&]uh1hhja1ubeh}(h]h ]h"]h$]h&]uh1hhhhMThj0hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMRubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMWhjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhKubh)}(h``nr_pe_cmp`` (ro)h]h)}(hj1h](j)}(h ``nr_pe_cmp``h]h nr_pe_cmp}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh (ro)}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMYhj1ubah}(h]h ]h"]h$]h&]uh1hhj1ubeh}(h]h ]h"]h$]h&]uh1hhhhMYhj1hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1hhhKubh)}(h From IDR4h]h)}(hj1h]h From IDR4}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhj1ubah}(h]h ]h"]h$]h&]uh1hhj1ubeh}(h]h ]h"]h$]h&]uh1hhhhMZhj1hhubh)}(hhh](h)}(hNotesh]hNotes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj 2hhhKubh)}(hNumber of PE comparator inputs h]h)}(hNumber of PE comparator inputsh]hNumber of PE comparator inputs}(hj"2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM\hj2ubah}(h]h ]h"]h$]h&]uh1hhj 2ubeh}(h]h ]h"]h$]h&]uh1hhhhM[hj1hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMYubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM^hjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hjR2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjO2hhhKubh)}(h``nr_ext_inp`` (ro)h]h)}(hjb2h](j)}(h``nr_ext_inp``h]h nr_ext_inp}(hjg2hhhNhNubah}(h]h ]h"]h$]h&]uh1jhjd2ubh (ro)}(hjd2hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM`hj`2ubah}(h]h ]h"]h$]h&]uh1hhjO2ubeh}(h]h ]h"]h$]h&]uh1hhhhM`hjL2hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhKubh)}(h From IDR5h]h)}(hj2h]h From IDR5}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj2ubah}(h]h ]h"]h$]h&]uh1hhj2ubeh}(h]h ]h"]h$]h&]uh1hhhhMahjL2hhubh)}(hhh](h)}(hNotesh]hNotes}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhKubh)}(hNumber of external inputs h]h)}(hNumber of external inputsh]hNumber of external inputs}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchj2ubah}(h]h ]h"]h$]h&]uh1hhj2ubeh}(h]h ]h"]h$]h&]uh1hhhhMbhjL2hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhM`ubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMehjkhhubh)}(hhh](h)}(hhh](h)}(hFileh]hFile}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj2hhhKubh)}(h``nr_ss_cmp`` (ro)h]h)}(hj3h](j)}(h ``nr_ss_cmp``h]h nr_ss_cmp}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj3ubh (ro)}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMghj 3ubah}(h]h ]h"]h$]h&]uh1hhj2ubeh}(h]h ]h"]h$]h&]uh1hhhhMghj2hhubh)}(hhh](h)}(hTrace Registersh]hTrace Registers}(hj:3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj73hhhKubh)}(h From IDR4h]h)}(hjJ3h]h From IDR4}(hjL3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhhjH3ubah}(h]h ]h"]h$]h&]uh1hhj73ubeh}(h]h ]h"]h$]h&]uh1hhhhMhhj2hhubh)}(hhh](h)}(hNotesh]hNotes}(hjh3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhje3hhhKubh)}(h(Number of Single Shot control registers h]h)}(h'Number of Single Shot control registersh]h'Number of Single Shot control registers}(hjz3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhjv3ubah}(h]h ]h"]h$]h&]uh1hhje3ubeh}(h]h ]h"]h$]h&]uh1hhhhMihj2hhubeh}(h]h ]h"]h$]h&]uh1hhjkhhhhhMgubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMlhjkhhubh)}(h*Note:* When programming any address comparator the driver will tag the comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag is set, then only the values can be changed using the same sysfs file / type used to program it.h](hemphasis)}(h*Note:*h]hNote:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1j3hj3ubh When programming any address comparator the driver will tag the comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag is set, then only the values can be changed using the same sysfs file / type used to program it.}(hj3hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMnhjkhhubh)}(hThus::h]hThus:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshjkhhubh literal_block)}(hX % echo 0 > addr_idx ; select address comparator 0 % echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0, 1. % echo 0x2000 > addr_start ; error as comparator 0 is a range comparator % echo 2 > addr_idx ; select address comparator 2 % echo 0x2000 > addr_start ; this is OK as comparator 2 is unused. % echo 0x3000 > addr_stop ; error as comparator 2 set as start address. % echo 2 > addr_idx ; select address comparator 3 % echo 0x3000 > addr_stop ; this is OKh]hX % echo 0 > addr_idx ; select address comparator 0 % echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0, 1. % echo 0x2000 > addr_start ; error as comparator 0 is a range comparator % echo 2 > addr_idx ; select address comparator 2 % echo 0x2000 > addr_start ; this is OK as comparator 2 is unused. % echo 0x3000 > addr_stop ; error as comparator 2 set as start address. % echo 2 > addr_idx ; select address comparator 3 % echo 0x3000 > addr_stop ; this is OK}hj3sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1j3hhhMuhjkhhubh)}(hcTo remove programming on all the comparators (and all the other hardware) use the reset parameter::h]hbTo remove programming on all the comparators (and all the other hardware) use the reset parameter:}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM~hjkhhubj3)}(h% echo 1 > reseth]h% echo 1 > reset}hj3sbah}(h]h ]h"]h$]h&]j3j3uh1j3hhhMhjkhhubeh}(h]sysfs-files-and-directoriesah ]h"]sysfs files and directoriesah$]h&]uh1hhhhhhhhK ubh)}(hhh](h)}(hThe ‘mode’ sysfs parameter.h]hThe ‘mode’ sysfs parameter.}(hj 4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4hhhhhMubh)}(hX6This is a bitfield selection parameter that sets the overall trace mode for the ETM. The table below describes the bits, using the defines from the driver source file, along with a description of the feature these represent. Many features are optional and therefore dependent on implementation in the hardware.h]hX6This is a bitfield selection parameter that sets the overall trace mode for the ETM. The table below describes the bits, using the defines from the driver source file, along with a description of the feature these represent. Many features are optional and therefore dependent on implementation in the hardware.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubh)}(hBit assignments shown below:-h]hBit assignments shown below:-}(hj%4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4hhubj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhMhj4hhubhdefinition_list)}(hhh](hdefinition_list_item)}(h**bit (0):** ETM_MODE_EXCLUDE h](hterm)}(h **bit (0):**h]hstrong)}(hjL4h]hbit (0):}(hjP4hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjJ4ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhjD4ubh definition)}(hhh]h)}(hETM_MODE_EXCLUDEh]hETM_MODE_EXCLUDE}(hjh4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhje4ubah}(h]h ]h"]h$]h&]uh1jc4hjD4ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj?4ubjC4)}(h**description:** This is the default value for the include / exclude function when setting address ranges. Set 1 for exclude range. When the mode parameter is set this value is applied to the currently indexed address range. h](jI4)}(h**description:**h]jO4)}(hj4h]h description:}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj4ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj4ubjd4)}(hhh]h)}(hThis is the default value for the include / exclude function when setting address ranges. Set 1 for exclude range. When the mode parameter is set this value is applied to the currently indexed address range.h]hThis is the default value for the include / exclude function when setting address ranges. Set 1 for exclude range. When the mode parameter is set this value is applied to the currently indexed address range.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4ubah}(h]h ]h"]h$]h&]uh1jc4hj4ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj?4hhubeh}(h]h ]h"]h$]h&]uh1j=4hj4hhhhhNubhtarget)}(h.. _coresight-branch-broadcast:h]h}(h]h ]h"]h$]h&]refidcoresight-branch-broadcastuh1j4hMhj4hhhhubj>4)}(hhh](jC4)}(h**bit (4):** ETM_MODE_BB h](jI4)}(h **bit (4):**h]jO4)}(hj4h]hbit (4):}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj4ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj4ubjd4)}(hhh]h)}(h ETM_MODE_BBh]h ETM_MODE_BB}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj4ubah}(h]h ]h"]h$]h&]uh1jc4hj4ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj4ubjC4)}(hX1**description:** Set to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature is when code is patched dynamically at run time and the full program flow may not be able to be reconstructed using only conditional branches. There is currently no support in Perf for supplying modified binaries to the decoder, so this feature is only intended to be used for debugging purposes or with a 3rd party tool. Choosing this option will result in a significant increase in the amount of trace generated - possible danger of overflows, or fewer instructions covered. Note, that this option also overrides any setting of :ref:`ETM_MODE_RETURNSTACK `, so where a branch broadcast range overlaps a return stack range, return stacks will not be available for that range. h](jI4)}(h**description:**h]jO4)}(hj5h]h description:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj 5ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj 5ubjd4)}(hhh](h)}(hSet to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature is when code is patched dynamically at run time and the full program flow may not be able to be reconstructed using only conditional branches.h]hSet to enable branch broadcast if supported in hardware [IDR0]. The primary use for this feature is when code is patched dynamically at run time and the full program flow may not be able to be reconstructed using only conditional branches.}(hj'5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$5ubh)}(hThere is currently no support in Perf for supplying modified binaries to the decoder, so this feature is only intended to be used for debugging purposes or with a 3rd party tool.h]hThere is currently no support in Perf for supplying modified binaries to the decoder, so this feature is only intended to be used for debugging purposes or with a 3rd party tool.}(hj55hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj$5ubh)}(hXzChoosing this option will result in a significant increase in the amount of trace generated - possible danger of overflows, or fewer instructions covered. Note, that this option also overrides any setting of :ref:`ETM_MODE_RETURNSTACK `, so where a branch broadcast range overlaps a return stack range, return stacks will not be available for that range.h](hChoosing this option will result in a significant increase in the amount of trace generated - possible danger of overflows, or fewer instructions covered. Note, that this option also overrides any setting of }(hjC5hhhNhNubh)}(h4:ref:`ETM_MODE_RETURNSTACK `h]hinline)}(hjM5h]hETM_MODE_RETURNSTACK}(hjQ5hhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jO5hjK5ubah}(h]h ]h"]h$]h&]refdoc)trace/coresight/coresight-etm4x-reference refdomainj\5reftyperef refexplicitrefwarn reftargetcoresight-return-stackuh1hhhhMhjC5ubhv, so where a branch broadcast range overlaps a return stack range, return stacks will not be available for that range.}(hjC5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj$5ubeh}(h]h ]h"]h$]h&]uh1jc4hj 5ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj4hhubeh}(h]j4ah ]h"]coresight-branch-broadcastah$]h&]uh1j=4hj4hhhhhNexpect_referenced_by_name}j5j4sexpect_referenced_by_id}j4j4subj4)}(h.. _coresight-cycle-accurate:h]h}(h]h ]h"]h$]h&]j4coresight-cycle-accurateuh1j4hMhj4hhhhubj>4)}(hhh](jC4)}(h**bit (5):** ETMv4_MODE_CYCACC h](jI4)}(h **bit (5):**h]jO4)}(hj5h]hbit (5):}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj5ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj5ubjd4)}(hhh]h)}(hETMv4_MODE_CYCACCh]hETMv4_MODE_CYCACC}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jc4hj5ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5ubjC4)}(hJ**description:** Set to enable cycle accurate trace if supported [IDR0]. h](jI4)}(h**description:**h]jO4)}(hj5h]h description:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj5ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj5ubjd4)}(hhh]h)}(h7Set to enable cycle accurate trace if supported [IDR0].h]h7Set to enable cycle accurate trace if supported [IDR0].}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1jc4hj5ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5hhubjC4)}(h**bit (6):** ETMv4_MODE_CTXID h](jI4)}(h **bit (6):**h]jO4)}(hj6h]hbit (6):}(hj6hhhNhNubah}(h]h ^]h"]h$]h&]uh1jN4hj6ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj6ubjd4)}(hhh]h)}(hETMv4_MODE_CTXIDh]hETMv4_MODE_CTXID}(hj-6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj*6ubah}(h]h ]h"]h$]h&]uh1jc4hj6ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5hhubjC4)}(hT**description:** Set to enable context ID tracing if supported in hardware [IDR2]. h](jI4)}(h**description:**h]jO4)}(hjM6h]h description:}(hjO6hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjK6ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhjG6ubjd4)}(hhh]h)}(hASet to enable context ID tracing if supported in hardware [IDR2].h]hASet to enable context ID tracing if supported in hardware [IDR2].}(hje6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjb6ubah}(h]h ]h"]h$]h&]uh1jc4hjG6ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5hhubjC4)}(h**bit (7):** ETM_MODE_VMID h](jI4)}(h **bit (7):**h]jO4)}(hj6h]hbit (7):}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj6ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj6ubjd4)}(hhh]h)}(h ETM_MODE_VMIDh]h ETM_MODE_VMID}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1jc4hj6ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5hhubjC4)}(hO**description:** Set to enable virtual machine ID tracing if supported [IDR2]. h](jI4)}(h**description:**h]jO4)}(hj6h]h description:}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj6ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj6ubjd4)}(hhh]h)}(h=Set to enable virtual machine ID tracing if supported [IDR2].h]h=Set to enable virtual machine ID tracing if supported [IDR2].}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1jc4hj6ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj5hhubeh}(h]j5ah ]h"]coresight-cycle-accurateah$]h&]uh1j=4hj4hhhhhNj5}j6j5sj5}j5j5subj4)}(h.. _coresight-timestamp:h]h}(h]h ]h"]h$]h&]j4coresight-timestampuh1j4hMhj4hhhhubj>4)}(hhh](jC4)}(h#**bit (11):** ETMv4_MODE_TIMESTAMP h](jI4)}(h **bit (11):**h]jO4)}(hj 7h]h bit (11):}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj 7ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj7ubjd4)}(hhh]h)}(hETMv4_MODE_TIMESTAMPh]hETMv4_MODE_TIMESTAMP}(hj$7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj!7ubah}(h]h ]h"]h$]h&]uh1jc4hj7ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7ubjC4)}(hI**description:** Set to enable timestamp generation if supported [IDR0]. h](jI4)}(h**description:**h]jO4)}(hjD7h]h description:}(hjF7hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjB7ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj>7ubjd4)}(hhh]h)}(h7Set to enable timestamp generation if supported [IDR0].h]h7Set to enable timestamp generation if supported [IDR0].}(hj\7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjY7ubah}(h]h ]h"]h$]h&]uh1jc4hj>7ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubeh}(h]j7ah ]h"]coresight-timestampah$]h&]uh1j=4hj4hhhhhNj5}jz7j6sj5}j7j6subj4)}(h.. _coresight-return-stack:h]h}(h]h ]h"]h$]h&]j4coresight-return-stackuh1j4hMhj4hhhhubj>4)}(hhh](jC4)}(h"**bit (12):** ETM_MODE_RETURNSTACKh](jI4)}(h **bit (12):**h]jO4)}(hj7h]h bit (12):}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj7ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj7ubjd4)}(hhh]h)}(hETM_MODE_RETURNSTACKh]hETM_MODE_RETURNSTACK}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7ubah}(h]h ]h"]h$]h&]uh1jc4hj7ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7ubjC4)}(hL**description:** Set to enable trace return stack use if supported [IDR0]. h](jI4)}(h**description:**h]jO4)}(hj7h]h description:}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj7ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj7ubjd4)}(hhh]h)}(h9Set to enable trace return stack use if supported [IDR0].h]h9Set to enable trace return stack use if supported [IDR0].}(hj7hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj7ubah}(h]h ]h"]h$]h&]uh1jc4hj7ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h%**bit (13-14):** ETM_MODE_QELEM(val) h](jI4)}(h**bit (13-14):**h]jO4)}(hj8h]h bit (13-14):}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj8ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj7ubjd4)}(hhh]h)}(hETM_MODE_QELEM(val)h]hETM_MODE_QELEM(val)}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jc4hj7ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hk**description:** ‘val’ determines level of Q element support enabled if implemented by the ETM [IDR0] h](jI4)}(h**description:**h]jO4)}(hj;8h]h description:}(hj=8hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj98ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj58ubjd4)}(hhh]h)}(hX‘val’ determines level of Q element support enabled if implemented by the ETM [IDR0]h]hX‘val’ determines level of Q element support enabled if implemented by the ETM [IDR0]}(hjS8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjP8ubah}(h]h ]h"]h$]h&]uh1jc4hj58ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h#**bit (19):** ETM_MODE_ATB_TRIGGER h](jI4)}(h **bit (19):**h]jO4)}(hjs8h]h bit (19):}(hju8hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjq8ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhjm8ubjd4)}(hhh]h)}(hETM_MODE_ATB_TRIGGERh]hETM_MODE_ATB_TRIGGER}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jc4hjm8ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hs**description:** Set to enable the ATBTRIGGER bit in the event control register [EVENTCTLR1] if supported [IDR5]. h](jI4)}(h**description:**h]jO4)}(hj8h]h description:}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj8ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj8ubjd4)}(hhh]h)}(h`Set to enable the ATBTRIGGER bit in the event control register [EVENTCTLR1] if supported [IDR5].h]h`Set to enable the ATBTRIGGER bit in the event control register [EVENTCTLR1] if supported [IDR5].}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jc4hj8ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h"**bit (20):** ETM_MODE_LPOVERRIDE h](jI4)}(h **bit (20):**h]jO4)}(hj8h]h bit (20):}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj8ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj8ubjd4)}(hhh]h)}(hETM_MODE_LPOVERRIDEh]hETM_MODE_LPOVERRIDE}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1jc4hj8ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(ht**description:** Set to enable the LPOVERRIDE bit in the event control register [EVENTCTLR1], if supported [IDR5]. h](jI4)}(h**description:**h]jO4)}(hj9h]h description:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj9ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj9ubjd4)}(hhh]h)}(haSet to enable the LPOVERRIDE bit in the event control register [EVENTCTLR1], if supported [IDR5].h]haSet to enable the LPOVERRIDE bit in the event control register [EVENTCTLR1], if supported [IDR5].}(hj39hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj09ubah}(h]h ]h"]h$]h&]uh1jc4hj9ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h!**bit (21):** ETM_MODE_ISTALL_EN h](jI4)}(h **bit (21):**h]jO4)}(hjS9h]h bit (21):}(hjU9hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjQ9ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhjM9ubjd4)}(hhh]h)}(hETM_MODE_ISTALL_ENh]hETM_MODE_ISTALL_EN}(hjk9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjh9ubah}(h]h ]h"]h$]h&]uh1jc4hjM9ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hY**description:** Set to enable the ISTALL bit in the stall control register [STALLCTLR] h](jI4)}(h**description:**h]jO4)}(hj9h]h description:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj9ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj9ubjd4)}(hhh]h)}(hFSet to enable the ISTALL bit in the stall control register [STALLCTLR]h]hFSet to enable the ISTALL bit in the stall control register [STALLCTLR]}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jc4hj9ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h **bit (23):** ETM_MODE_INSTPRIO h](jI4)}(h **bit (23):**h]jO4)}(hj9h]h bit (23):}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj9ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj9ubjd4)}(hhh]h)}(hETM_MODE_INSTPRIOh]hETM_MODE_INSTPRIO}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj9ubah}(h]h ]h"]h$]h&]uh1jc4hj9ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hv**description:** Set to enable the INSTPRIORITY bit in the stall control register [STALLCTLR] , if supported [IDR0]. h](jI4)}(h**description:**h]jO4)}(hj9h]h description:}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj9ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj9ubjd4)}(hhh]h)}(hcSet to enable the INSTPRIORITY bit in the stall control register [STALLCTLR] , if supported [IDR0].h]hcSet to enable the INSTPRIORITY bit in the stall control register [STALLCTLR] , if supported [IDR0].}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jc4hj9ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h"**bit (24):** ETM_MODE_NOOVERFLOW h](jI4)}(h **bit (24):**h]jO4)}(hj3:h]h bit (24):}(hj5:hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj1:ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj-:ubjd4)}(hhh]h)}(hETM_MODE_NOOVERFLOWh]hETM_MODE_NOOVERFLOW}(hjK:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjH:ubah}(h]h ]h"]h$]h&]uh1jc4hj-:ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hs**description:** Set to enable the NOOVERFLOW bit in the stall control register [STALLCTLR], if supported [IDR3]. h](jI4)}(h**description:**h]jO4)}(hjk:h]h description:}(hjm:hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hji:ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhje:ubjd4)}(hhh]h)}(h`Set to enable the NOOVERFLOW bit in the stall control register [STALLCTLR], if supported [IDR3].h]h`Set to enable the NOOVERFLOW bit in the stall control register [STALLCTLR], if supported [IDR3].}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jc4hje:ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h#**bit (25):** ETM_MODE_TRACE_RESET h](jI4)}(h **bit (25):**h]jO4)}(hj:h]h bit (25):}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj:ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj:ubjd4)}(hhh]h)}(hETM_MODE_TRACE_RESETh]hETM_MODE_TRACE_RESET}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jc4hj:ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hr**description:** Set to enable the TRCRESET bit in the viewinst control register [VICTLR] , if supported [IDR3]. h](jI4)}(h**description:**h]jO4)}(hj:h]h description:}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj:ubah}(h]h ]h"]h$]h&]uh1jH4hhhM hj:ubjd4)}(hhh]h)}(h_Set to enable the TRCRESET bit in the viewinst control register [VICTLR] , if supported [IDR3].h]h_Set to enable the TRCRESET bit in the viewinst control register [VICTLR] , if supported [IDR3].}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj:ubah}(h]h ]h"]h$]h&]uh1jc4hj:ubeh}(h]h ]h"]h$]h&]uh1jB4hhhM hj7hhubjC4)}(h!**bit (26):** ETM_MODE_TRACE_ERR h](jI4)}(h **bit (26):**h]jO4)}(hj;h]h bit (26):}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj;ubah}(h]h ]h"]h$]h&]uh1jH4hhhM hj ;ubjd4)}(hhh]h)}(hETM_MODE_TRACE_ERRh]hETM_MODE_TRACE_ERR}(hj+;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj(;ubah}(h]h ]h"]h$]h&]uh1jc4hj ;ubeh}(h]h ]h"]h$]h&]uh1jB4hhhM hj7hhubjC4)}(h[**description:** Set to enable the TRCCTRL bit in the viewinst control register [VICTLR]. h](jI4)}(h**description:**h]jO4)}(hjK;h]h description:}(hjM;hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hjI;ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhjE;ubjd4)}(hhh]h)}(hHSet to enable the TRCCTRL bit in the viewinst control register [VICTLR].h]hHSet to enable the TRCCTRL bit in the viewinst control register [VICTLR].}(hjc;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj`;ubah}(h]h ]h"]h$]h&]uh1jc4hjE;ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h***bit (27):** ETM_MODE_VIEWINST_STARTSTOP h](jI4)}(h **bit (27):**h]jO4)}(hj;h]h bit (27):}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj;ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj};ubjd4)}(hhh]h)}(hETM_MODE_VIEWINST_STARTSTOPh]hETM_MODE_VIEWINST_STARTSTOP}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1jc4hj};ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h{**description:** Set the initial state value of the ViewInst start / stop logic in the viewinst control register [VICTLR] h](jI4)}(h**description:**h]jO4)}(hj;h]h description:}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj;ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj;ubjd4)}(hhh]h)}(hhSet the initial state value of the ViewInst start / stop logic in the viewinst control register [VICTLR]h]hhSet the initial state value of the ViewInst start / stop logic in the viewinst control register [VICTLR]}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj;ubah}(h]h ]h"]h$]h&]uh1jc4hj;ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(h!**bit (30):** ETM_MODE_EXCL_KERN h](jI4)}(h **bit (30):**h]jO4)}(hj;h]h bit (30):}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj;ubah}(h]h ]h"]h$]h&]uh1jH4hhhMhj;ubjd4)}(hhh]h)}(hETM_MODE_EXCL_KERNh]hETM_MODE_EXCL_KERN}(hj <hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj<ubah}(h]h ]h"]h$]h&]uh1jc4hj;ubeh}(h]h ]h"]h$]h&]uh1jB4hhhMhj7hhubjC4)}(hT**description:** Set default trace setup to exclude kernel mode trace (see note a) h](jI4)}(h**description:**h]jO4)}(hj+<h]h description:}(hj-<hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj)<ubah}(h]h ]h"]h$]h&]uh1jH4hhhM!hj%<ubjd4)}(hhh]h)}(hASet default trace setup to exclude kernel mode trace (see note a)h]hASet default trace setup to exclude kernel mode trace (see note a)}(hjC<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hj@<ubah}(h]h ]h"]h$]h&]uh1jc4hj%<ubeh}(h]h ]h"]h$]h&]uh1jB4hhhM!hj7hhubjC4)}(h!**bit (31):** ETM_MODE_EXCL_USER h](jI4)}(h **bit (31):**h]jO4)}(hjc<h]h bit (31):}(hje<hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hja<ubah}(h]h ]h"]h$]h&]uh1jH4hhhM$hj]<ubjd4)}(hhh]h)}(hETM_MODE_EXCL_USERh]hETM_MODE_EXCL_USER}(hj{<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hjx<ubah}(h]h ]h"]h$]h&]uh1jc4hj]<ubeh}(h]h ]h"]h$]h&]uh1jB4hhhM$hj7hhubjC4)}(hR**description:** Set default trace setup to exclude user space trace (see note a) h](jI4)}(h**description:**h]jO4)}(hj<h]h description:}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1jN4hj<ubah}(h]h ]h"]h$]h&]uh1jH4hhhM'hj<ubjd4)}(hhh]h)}(h@Set default trace setup to exclude user space trace (see note a)h]h@Set default trace setup to exclude user space trace (see note a)}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM'hj<ubah}(h]h ]h"]h$]h&]uh1jc4hj<ubeh}(h]h ]h"]h$]h&]uh1jB4hhhM'hj7hhubeh}(h]j7ah ]h"]coresight-return-stackah$]h&]uh1j=4hj4hhhhhNj5}j<j7sj5}j7j7subj)}(h----h]h}(h]h ]h"]h$]h&]uh1jhhhM)hj4hhubh)}(hXK*Note a)* On startup the ETM is programmed to trace the complete address space using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to set EL exclude bits for NS state in either user space (EL0) or kernel space (EL1) in the address range comparator. (the default setting excludes all secure EL, and NS EL2)h](j3)}(h *Note a)*h]hNote a)}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1j3hj<ubhXB On startup the ETM is programmed to trace the complete address space using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to set EL exclude bits for NS state in either user space (EL0) or kernel space (EL1) in the address range comparator. (the default setting excludes all secure EL, and NS EL2)}(hj<hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM+hj4hhubh)}(hOnce the reset parameter has been used, and/or custom programming has been implemented - using these bits will result in the EL bits for address comparator 0 being set in the same way.h]hOnce the reset parameter has been used, and/or custom programming has been implemented - using these bits will result in the EL bits for address comparator 0 being set in the same way.}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM1hj4hhubh)}(hX9*Note b)* Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with data trace. As A-profile data trace is architecturally prohibited in ETMv4, these have been omitted here. Possible uses could be where a kernel has support for control of R or M profile infrastructure as part of a heterogeneous system.h](j3)}(h *Note b)*h]hNote b)}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j3hj =ubhX0 Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with data trace. As A-profile data trace is architecturally prohibited in ETMv4, these have been omitted here. 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