€•¬u      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ7/translations/zh_CN/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ7/translations/zh_TW/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ7/translations/it_IT/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ7/translations/ja_JP/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ7/translations/ko_KR/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ7/translations/sp_SP/trace/coresight/coresight-cpu-debug”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒCoresight CPU Debug Module”h]”hŒCoresight CPU Debug Module”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒQ/var/lib/git/docbuild/linux/Documentation/trace/coresight/coresight-cpu-debug.rst”h KubhŒblock_quote”“”)”}”(hŒC:Author:   Leo Yan <leo.yan@linaro.org>
:Date:     April 5th, 2017
”h]”hŒ
field_list”“”)”}”(hhh]”(hŒfield”“”)”}”(hhh]”(hŒ
field_name”“”)”}”(hŒAuthor”h]”hŒAuthor”…””}”(hhÉhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhhÄhŸh¶h K ubhŒ
field_body”“”)”}”(hŒLeo Yan <leo.yan@linaro.org>”h]”hŒ	paragraph”“”)”}”(hhÛh]”(hŒ	Leo Yan <”…””}”(hhßhžhhŸNh NubhŒ	reference”“”)”}”(hŒleo.yan@linaro.org”h]”hŒleo.yan@linaro.org”…””}”(hhèhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:leo.yan@linaro.org”uh1hæhhßubhŒ>”…””}”(hhßhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KhhÙubah}”(h]”h ]”h"]”h$]”h&]”uh1h×hhÄubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÂhŸh¶h Khh¿ubhÃ)”}”(hhh]”(hÈ)”}”(hŒDate”h]”hŒDate”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÇhj  hŸh¶h K ubhØ)”}”(hŒApril 5th, 2017
”h]”hÞ)”}”(hŒApril 5th, 2017”h]”hŒApril 5th, 2017”…””}”(hj#  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Khj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1h×hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÂhŸh¶h Khh¿ubeh}”(h]”h ]”h"]”h$]”h&]”uh1h½hh¹ubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒIntroduction”h]”hŒIntroduction”…””}”(hjL  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjI  hžhhŸh¶h K	ubhÞ)”}”(hXâ  Coresight CPU debug module is defined in ARMv8-a architecture reference manual
(ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
debug module and it is mainly used for two modes: self-hosted debug and
external debug. Usually the external debug mode is well known as the external
debugger connects with SoC from JTAG port; on the other hand the program can
explore debugging method which rely on self-hosted debug mode, this document
is to focus on this part.”h]”hXæ  Coresight CPU debug module is defined in ARMv8-a architecture reference manual
(ARM DDI 0487A.k) Chapter â€˜Part H: External debugâ€™, the CPU can integrate
debug module and it is mainly used for two modes: self-hosted debug and
external debug. Usually the external debug mode is well known as the external
debugger connects with SoC from JTAG port; on the other hand the program can
explore debugging method which rely on self-hosted debug mode, this document
is to focus on this part.”…””}”(hjZ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KhjI  hžhubhÞ)”}”(hXä  The debug module provides sample-based profiling extension, which can be used
to sample CPU program counter, secure state and exception level, etc; usually
every CPU has one dedicated debug module to be connected. Based on self-hosted
debug mechanism, Linux kernel can access these related registers from mmio
region when the kernel panic happens. The callback notifier for kernel panic
will dump related registers for every CPU; finally this is good for assistant
analysis for panic.”h]”hXä  The debug module provides sample-based profiling extension, which can be used
to sample CPU program counter, secure state and exception level, etc; usually
every CPU has one dedicated debug module to be connected. Based on self-hosted
debug mechanism, Linux kernel can access these related registers from mmio
region when the kernel panic happens. The callback notifier for kernel panic
will dump related registers for every CPU; finally this is good for assistant
analysis for panic.”…””}”(hjh  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KhjI  hžhubeh}”(h]”Œintroduction”ah ]”h"]”Œintroduction”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K	ubh¢)”}”(hhh]”(h§)”}”(hŒImplementation”h]”hŒImplementation”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj~  hžhhŸh¶h KubhŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hX  During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
registers to decide if sample-based profiling is implemented or not. On some
platforms this hardware feature is fully or partially implemented; and if
this feature is not supported then registration will fail.
”h]”hÞ)”}”(hX  During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
registers to decide if sample-based profiling is implemented or not. On some
platforms this hardware feature is fully or partially implemented; and if
this feature is not supported then registration will fail.”h]”hX  During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
registers to decide if sample-based profiling is implemented or not. On some
platforms this hardware feature is fully or partially implemented; and if
this feature is not supported then registration will fail.”…””}”(hjš  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Khj–  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j”  hj‘  hžhhŸh¶h Nubj•  )”}”(hXˆ  At the time this documentation was written, the debug driver mainly relies on
information gathered by the kernel panic callback notifier from three
sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
program counter; EDVIDSR has information for secure state, exception level,
bit width, etc; EDCIDSR is context ID value which contains the sampled value
of CONTEXTIDR_EL1.
”h]”hÞ)”}”(hX‡  At the time this documentation was written, the debug driver mainly relies on
information gathered by the kernel panic callback notifier from three
sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
program counter; EDVIDSR has information for secure state, exception level,
bit width, etc; EDCIDSR is context ID value which contains the sampled value
of CONTEXTIDR_EL1.”h]”hX‡  At the time this documentation was written, the debug driver mainly relies on
information gathered by the kernel panic callback notifier from three
sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
program counter; EDVIDSR has information for secure state, exception level,
bit width, etc; EDCIDSR is context ID value which contains the sampled value
of CONTEXTIDR_EL1.”…””}”(hj²  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K$hj®  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j”  hj‘  hžhhŸh¶h Nubj•  )”}”(hXF  The driver supports a CPU running in either AArch64 or AArch32 mode. The
registers naming convention is a bit different between them, AArch64 uses
'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
use AArch64 naming convention.
”h]”hÞ)”}”(hXE  The driver supports a CPU running in either AArch64 or AArch32 mode. The
registers naming convention is a bit different between them, AArch64 uses
'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
use AArch64 naming convention.”h]”hXM  The driver supports a CPU running in either AArch64 or AArch32 mode. The
registers naming convention is a bit different between them, AArch64 uses
â€˜EDâ€™ for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
â€˜DBGâ€™ as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
use AArch64 naming convention.”…””}”(hjÊ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K+hjÆ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j”  hj‘  hžhhŸh¶h Nubj•  )”}”(hX•  ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
register bits definition. So the driver consolidates two difference:

If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
but ARMv7-a defines "PCSR samples are offset by a value that depends on the
instruction set state". For ARMv7-a, the driver checks furthermore if CPU
runs with ARM or thumb instruction set and calibrate PCSR value, the
detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
C11.11.34 "DBGPCSR, Program Counter Sampling Register".

If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
no offset applied and do not sample the instruction set state in AArch32
state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
state EDPCSR is sampled and no offset are applied.

”h]”(hÞ)”}”(hŒ‹ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
register bits definition. So the driver consolidates two difference:”h]”hŒ‹ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
register bits definition. So the driver consolidates two difference:”…””}”(hjâ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K1hjÞ  ubhÞ)”}”(hX©  If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
but ARMv7-a defines "PCSR samples are offset by a value that depends on the
instruction set state". For ARMv7-a, the driver checks furthermore if CPU
runs with ARM or thumb instruction set and calibrate PCSR value, the
detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
C11.11.34 "DBGPCSR, Program Counter Sampling Register".”h]”hX±  If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
but ARMv7-a defines â€œPCSR samples are offset by a value that depends on the
instruction set stateâ€. For ARMv7-a, the driver checks furthermore if CPU
runs with ARM or thumb instruction set and calibrate PCSR value, the
detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
C11.11.34 â€œDBGPCSR, Program Counter Sampling Registerâ€.”…””}”(hjð  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K4hjÞ  ubhÞ)”}”(hX[  If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
no offset applied and do not sample the instruction set state in AArch32
state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
state EDPCSR is sampled and no offset are applied.”h]”hX_  If PCSROffset=0b0010, ARMv8-a defines â€œEDPCSR implemented, and samples have
no offset applied and do not sample the instruction set state in AArch32
stateâ€. So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
state EDPCSR is sampled and no offset are applied.”…””}”(hjþ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K;hjÞ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j”  hj‘  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j  hŸh¶h Khj~  hžhubeh}”(h]”Œimplementation”ah ]”h"]”Œimplementation”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒClock and power domain”h]”hŒClock and power domain”…””}”(hj%  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj"  hžhhŸh¶h KCubhÞ)”}”(hX  Before accessing debug registers, we should ensure the clock and power domain
have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
Debug registers', the debug registers are spread into two domains: the debug
domain and the CPU domain.
::”h]”hX  Before accessing debug registers, we should ensure the clock and power domain
have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter â€˜H9.1
Debug registersâ€™, the debug registers are spread into two domains: the debug
domain and the CPU domain.”…””}”(hj3  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KEhj"  hžhubhŒliteral_block”“”)”}”(hX;                                 +---------------+
                               |               |
                               |               |
                    +----------+--+            |
       dbg_clock -->|          |**|            |<-- cpu_clock
                    |    Debug |**|   CPU      |
dbg_power_domain -->|          |**|            |<-- cpu_power_domain
                    +----------+--+            |
                               |               |
                               |               |
                               +---------------+”h]”hX;                                 +---------------+
                               |               |
                               |               |
                    +----------+--+            |
       dbg_clock -->|          |**|            |<-- cpu_clock
                    |    Debug |**|   CPU      |
dbg_power_domain -->|          |**|            |<-- cpu_power_domain
                    +----------+--+            |
                               |               |
                               |               |
                               +---------------+”…””}”hjC  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jA  hŸh¶h KKhj"  hžhubhÞ)”}”(hŒøFor debug domain, the user uses DT binding "clocks" and "power-domains" to
specify the corresponding clock source and power supply for the debug logic.
The driver calls the pm_runtime_{put|get} operations as needed to handle the
debug power domain.”h]”hX   For debug domain, the user uses DT binding â€œclocksâ€ and â€œpower-domainsâ€ to
specify the corresponding clock source and power supply for the debug logic.
The driver calls the pm_runtime_{put|get} operations as needed to handle the
debug power domain.”…””}”(hjS  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KWhj"  hžhubhÞ)”}”(hŒ¬For CPU domain, the different SoC designs have different power management
schemes and finally this heavily impacts external debug module. So we can
divide into below cases:”h]”hŒ¬For CPU domain, the different SoC designs have different power management
schemes and finally this heavily impacts external debug module. So we can
divide into below cases:”…””}”(hja  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K\hj"  hžhubj  )”}”(hhh]”(j•  )”}”(hX±  On systems with a sane power controller which can behave correctly with
respect to CPU power domain, the CPU power domain can be controlled by
register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
of CPU power down. As result, this can ensure the CPU power domain is
powered on properly during the period when access debug related registers;
”h]”hÞ)”}”(hX°  On systems with a sane power controller which can behave correctly with
respect to CPU power domain, the CPU power domain can be controlled by
register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
of CPU power down. As result, this can ensure the CPU power domain is
powered on properly during the period when access debug related registers;”h]”hX°  On systems with a sane power controller which can behave correctly with
respect to CPU power domain, the CPU power domain can be controlled by
register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
of CPU power down. As result, this can ensure the CPU power domain is
powered on properly during the period when access debug related registers;”…””}”(hjv  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K`hjr  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j”  hjo  hžhhŸh¶h Nubj•  )”}”(hXí  Some designs will power down an entire cluster if all CPUs on the cluster
are powered down - including the parts of the debug registers that should
remain powered in the debug power domain. The bits in EDPRCR are not
respected in these cases, so these designs do not support debug over
power down in the way that the CoreSight / Debug designers anticipated.
This means that even checking EDPRSR has the potential to cause a bus hang
if the target register is unpowered.

In this case, accessing to the debug registers while they are not powered
is a recipe for disaster; so we need preventing CPU low power states at boot
time or when user enable module at the run time. Please see chapter
"How to use the module" for detailed usage info for this.

”h]”(hÞ)”}”(hXÕ  Some designs will power down an entire cluster if all CPUs on the cluster
are powered down - including the parts of the debug registers that should
remain powered in the debug power domain. The bits in EDPRCR are not
respected in these cases, so these designs do not support debug over
power down in the way that the CoreSight / Debug designers anticipated.
This means that even checking EDPRSR has the potential to cause a bus hang
if the target register is unpowered.”h]”hXÕ  Some designs will power down an entire cluster if all CPUs on the cluster
are powered down - including the parts of the debug registers that should
remain powered in the debug power domain. The bits in EDPRCR are not
respected in these cases, so these designs do not support debug over
power down in the way that the CoreSight / Debug designers anticipated.
This means that even checking EDPRSR has the potential to cause a bus hang
if the target register is unpowered.”…””}”(hjŽ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KghjŠ  ubhÞ)”}”(hX  In this case, accessing to the debug registers while they are not powered
is a recipe for disaster; so we need preventing CPU low power states at boot
time or when user enable module at the run time. Please see chapter
"How to use the module" for detailed usage info for this.”h]”hX  In this case, accessing to the debug registers while they are not powered
is a recipe for disaster; so we need preventing CPU low power states at boot
time or when user enable module at the run time. Please see chapter
â€œHow to use the moduleâ€ for detailed usage info for this.”…””}”(hjœ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KohjŠ  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j”  hjo  hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”j  j  uh1j  hŸh¶h K`hj"  hžhubeh}”(h]”Œclock-and-power-domain”ah ]”h"]”Œclock and power domain”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KCubh¢)”}”(hhh]”(h§)”}”(hŒDevice Tree Bindings”h]”hŒDevice Tree Bindings”…””}”(hjÁ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¾  hžhhŸh¶h KvubhÞ)”}”(hŒSSee Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for
details.”h]”hŒSSee Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for
details.”…””}”(hjÏ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Kxhj¾  hžhubeh}”(h]”Œdevice-tree-bindings”ah ]”h"]”Œdevice tree bindings”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kvubh¢)”}”(hhh]”(h§)”}”(hŒHow to use the module”h]”hŒHow to use the module”…””}”(hjè  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjå  hžhhŸh¶h K}ubhÞ)”}”(hŒŒIf you want to enable debugging functionality at boot time, you can add
"coresight_cpu_debug.enable=1" to the kernel command line parameter.”h]”hŒIf you want to enable debugging functionality at boot time, you can add
â€œcoresight_cpu_debug.enable=1â€ to the kernel command line parameter.”…””}”(hjö  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Khjå  hžhubhÞ)”}”(hŒTThe driver also can work as module, so can enable the debugging when insmod
module::”h]”hŒSThe driver also can work as module, so can enable the debugging when insmod
module:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K‚hjå  hžhubjB  )”}”(hŒ'# insmod coresight_cpu_debug.ko debug=1”h]”hŒ'# insmod coresight_cpu_debug.ko debug=1”…””}”hj  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h K…hjå  hžhubhÞ)”}”(hŒ©When boot time or insmod module you have not enabled the debugging, the driver
uses the debugfs file system to provide a knob to dynamically enable or disable
debugging:”h]”hŒ©When boot time or insmod module you have not enabled the debugging, the driver
uses the debugfs file system to provide a knob to dynamically enable or disable
debugging:”…””}”(hj   hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K‡hjå  hžhubhÞ)”}”(hŒMTo enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable::”h]”hŒPTo enable it, write a â€˜1â€™ into /sys/kernel/debug/coresight_cpu_debug/enable:”…””}”(hj.  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K‹hjå  hžhubjB  )”}”(hŒ7# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable”h]”hŒ7# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable”…””}”hj<  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h Khjå  hžhubhÞ)”}”(hŒNTo disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::”h]”hŒQTo disable it, write a â€˜0â€™ into /sys/kernel/debug/coresight_cpu_debug/enable:”…””}”(hjJ  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Khjå  hžhubjB  )”}”(hŒ7# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable”h]”hŒ7# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable”…””}”hjX  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h K‘hjå  hžhubhÞ)”}”(hXN  As explained in chapter "Clock and power domain", if you are working on one
platform which has idle states to power off debug logic and the power
controller cannot work well for the request from EDPRCR, then you should
firstly constraint CPU idle states before enable CPU debugging feature; so can
ensure the accessing to debug logic.”h]”hXR  As explained in chapter â€œClock and power domainâ€, if you are working on one
platform which has idle states to power off debug logic and the power
controller cannot work well for the request from EDPRCR, then you should
firstly constraint CPU idle states before enable CPU debugging feature; so can
ensure the accessing to debug logic.”…””}”(hjf  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K“hjå  hžhubhÞ)”}”(hŒqIf you want to limit idle states at boot time, you can use "nohlt" or
"cpuidle.off=1" in the kernel command line.”h]”hŒyIf you want to limit idle states at boot time, you can use â€œnohltâ€ or
â€œcpuidle.off=1â€ in the kernel command line.”…””}”(hjt  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K™hjå  hžhubhÞ)”}”(hŒ>At the runtime you can disable idle states with below methods:”h]”hŒ>At the runtime you can disable idle states with below methods:”…””}”(hj‚  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Kœhjå  hžhubhÞ)”}”(hXU  It is possible to disable CPU idle states by way of the PM QoS
subsystem, more specifically by using the "/dev/cpu_dma_latency"
interface (see Documentation/power/pm_qos_interface.rst for more
details).  As specified in the PM QoS documentation the requested
parameter will stay in effect until the file descriptor is released.
For example::”h]”hXX  It is possible to disable CPU idle states by way of the PM QoS
subsystem, more specifically by using the â€œ/dev/cpu_dma_latencyâ€
interface (see Documentation/power/pm_qos_interface.rst for more
details).  As specified in the PM QoS documentation the requested
parameter will stay in effect until the file descriptor is released.
For example:”…””}”(hj  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h Kžhjå  hžhubjB  )”}”(hŒO# exec 3<> /dev/cpu_dma_latency; echo 0 >&3
...
Do some work...
...
# exec 3<>-”h]”hŒO# exec 3<> /dev/cpu_dma_latency; echo 0 >&3
...
Do some work...
...
# exec 3<>-”…””}”hjž  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h K¥hjå  hžhubhÞ)”}”(hŒ6The same can also be done from an application program.”h]”hŒ6The same can also be done from an application program.”…””}”(hj¬  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K«hjå  hžhubhÞ)”}”(hŒnDisable specific CPU's specific idle state from cpuidle sysfs (see
Documentation/admin-guide/pm/cpuidle.rst)::”h]”hŒoDisable specific CPUâ€™s specific idle state from cpuidle sysfs (see
Documentation/admin-guide/pm/cpuidle.rst):”…””}”(hjº  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h K­hjå  hžhubjB  )”}”(hŒF# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable”h]”hŒF# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable”…””}”hjÈ  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h K°hjå  hžhubeh}”(h]”Œhow-to-use-the-module”ah ]”h"]”Œhow to use the module”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K}ubh¢)”}”(hhh]”(h§)”}”(hŒOutput format”h]”hŒOutput format”…””}”(hjá  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÞ  hžhhŸh¶h K³ubhÞ)”}”(hŒ3Here is an example of the debugging output format::”h]”hŒ2Here is an example of the debugging output format:”…””}”(hjï  hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝhŸh¶h KµhjÞ  hžhubjB  )”}”(hXË  ARM external debug module:
coresight-cpu-debug 850000.debug: CPU[0]:
coresight-cpu-debug 850000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
coresight-cpu-debug 850000.debug:  EDPCSR:  handle_IPI+0x174/0x1d8
coresight-cpu-debug 850000.debug:  EDCIDSR: 00000000
coresight-cpu-debug 850000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
coresight-cpu-debug 852000.debug: CPU[1]:
coresight-cpu-debug 852000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
coresight-cpu-debug 852000.debug:  EDPCSR:  debug_notifier_call+0x23c/0x358
coresight-cpu-debug 852000.debug:  EDCIDSR: 00000000
coresight-cpu-debug 852000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)”h]”hXË  ARM external debug module:
coresight-cpu-debug 850000.debug: CPU[0]:
coresight-cpu-debug 850000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
coresight-cpu-debug 850000.debug:  EDPCSR:  handle_IPI+0x174/0x1d8
coresight-cpu-debug 850000.debug:  EDCIDSR: 00000000
coresight-cpu-debug 850000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
coresight-cpu-debug 852000.debug: CPU[1]:
coresight-cpu-debug 852000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
coresight-cpu-debug 852000.debug:  EDPCSR:  debug_notifier_call+0x23c/0x358
coresight-cpu-debug 852000.debug:  EDCIDSR: 00000000
coresight-cpu-debug 852000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)”…””}”hjý  sbah}”(h]”h ]”h"]”h$]”h&]”jQ  jR  uh1jA  hŸh¶h K·hjÞ  hžhubeh}”(h]”Œoutput-format”ah ]”h"]”Œoutput format”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K³ubeh}”(h]”Œcoresight-cpu-debug-module”ah ]”h"]”Œcoresight cpu debug module”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
source_url”NŒtoc_backlinks”Œentry”Œfootnote_backlinks”KŒsectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒstrip_classes”NŒreport_level”KŒ
halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ	traceback”ˆŒinput_encoding”Œ	utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”j>  Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œlanguage_code”Œen”Œrecord_dependencies”NŒconfig”NŒ	id_prefix”hŒauto_id_prefix”Œid”Œdump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ_destination”NŒ_config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ	tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œdocinfo_xform”KŒsectsubtitle_xform”‰Œimage_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j  j  j{  jx  j  j  j»  j¸  jâ  jß  jÛ  jØ  j  j  uŒ	nametypes”}”(j  ‰j{  ‰j  ‰j»  ‰jâ  ‰jÛ  ‰j  ‰uh}”(j  h£jx  jI  j  j~  j¸  j"  jß  j¾  jØ  jå  j  jÞ  uŒfootnote_refs”}”Œcitation_refs”}”Œautofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ	footnotes”]”Œ	citations”]”Œautofootnote_start”KŒsymbol_footnote_start”K Œ
id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ
decoration”Nhžhub.