€•      Œsphinx.addnodes”Œdocument”“”)”}”(Œ	rawsource”Œ ”Œchildren”]”(Œtranslations”ŒLanguagesNode”“”)”}”(hhh]”(h Œpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ
attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ	refdomain”Œstd”Œreftype”Œdoc”Œ	reftarget”Œ#/translations/zh_CN/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/zh_TW/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/it_IT/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/ja_JP/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/ko_KR/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/pt_BR/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ	refdomain”h)Œreftype”h+Œ	reftarget”Œ#/translations/sp_SP/spi/spi-summary”Œmodname”NŒ	classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h
hhŒ	_document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ$Overview of Linux kernel SPI support”h]”hŒ$Overview of Linux kernel SPI support”…””}”(hh¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhh·h²hh³Œ=/var/lib/git/docbuild/linux/Documentation/spi/spi-summary.rst”h´KubhŒ	paragraph”“”)”}”(hŒ02-Feb-2012”h]”hŒ02-Feb-2012”…””}”(hhÍh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khh·h²hubh¶)”}”(hhh]”(h»)”}”(hŒWhat is SPI?”h]”hŒWhat is SPI?”…””}”(hhÞh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhhÛh²hh³hÊh´KubhÌ)”}”(hX  The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
link used to connect microcontrollers to sensors, memory, and peripherals.
It's a simple "de facto" standard, not complicated enough to acquire a
standardization body.  SPI uses a host/target configuration.”h]”hX"  The â€œSerial Peripheral Interfaceâ€ (SPI) is a synchronous four wire serial
link used to connect microcontrollers to sensors, memory, and peripherals.
Itâ€™s a simple â€œde factoâ€ standard, not complicated enough to acquire a
standardization body.  SPI uses a host/target configuration.”…””}”(hhìh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K	hhÛh²hubhÌ)”}”(hX  The three signal wires hold a clock (SCK, often on the order of 10 MHz),
and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
Slave Out" (MISO) signals.  (Other names are also used.)  There are four
clocking modes through which data is exchanged; mode-0 and mode-3 are most
commonly used.  Each clock cycle shifts data out and data in; the clock
doesn't cycle except when there is a data bit to shift.  Not all data bits
are used though; not every protocol uses those full duplex capabilities.”h]”hX  The three signal wires hold a clock (SCK, often on the order of 10 MHz),
and parallel data lines with â€œMaster Out, Slave Inâ€ (MOSI) or â€œMaster In,
Slave Outâ€ (MISO) signals.  (Other names are also used.)  There are four
clocking modes through which data is exchanged; mode-0 and mode-3 are most
commonly used.  Each clock cycle shifts data out and data in; the clock
doesnâ€™t cycle except when there is a data bit to shift.  Not all data bits
are used though; not every protocol uses those full duplex capabilities.”…””}”(hhúh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhhÛh²hubhÌ)”}”(hX[  SPI hosts use a fourth "chip select" line to activate a given SPI target
device, so those three signal wires may be connected to several chips
in parallel.  All SPI targets support chipselects; they are usually active
low signals, labeled nCSx for target 'x' (e.g. nCS0).  Some devices have
other signals, often including an interrupt to the host.”h]”hXc  SPI hosts use a fourth â€œchip selectâ€ line to activate a given SPI target
device, so those three signal wires may be connected to several chips
in parallel.  All SPI targets support chipselects; they are usually active
low signals, labeled nCSx for target â€˜xâ€™ (e.g. nCS0).  Some devices have
other signals, often including an interrupt to the host.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhhÛh²hubhÌ)”}”(hŒ·Unlike serial busses like USB or SMBus, even low level protocols for
SPI target functions are usually not interoperable between vendors
(except for commodities like SPI memory chips).”h]”hŒ·Unlike serial busses like USB or SMBus, even low level protocols for
SPI target functions are usually not interoperable between vendors
(except for commodities like SPI memory chips).”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhhÛh²hubhŒblock_quote”“”)”}”(hXD  - SPI may be used for request/response style device protocols, as with
  touchscreen sensors and memory chips.

- It may also be used to stream data in either direction (half duplex),
  or both of them at the same time (full duplex).

- Some devices may use eight bit words.  Others may use different word
  lengths, such as streams of 12-bit or 20-bit digital samples.

- Words are usually sent with their most significant bit (MSB) first,
  but sometimes the least significant bit (LSB) goes first instead.

- Sometimes SPI is used to daisy-chain devices, like shift registers.
”h]”hŒbullet_list”“”)”}”(hhh]”(hŒ	list_item”“”)”}”(hŒkSPI may be used for request/response style device protocols, as with
touchscreen sensors and memory chips.
”h]”hÌ)”}”(hŒjSPI may be used for request/response style device protocols, as with
touchscreen sensors and memory chips.”h]”hŒjSPI may be used for request/response style device protocols, as with
touchscreen sensors and memory chips.”…””}”(hj5  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hj1  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒvIt may also be used to stream data in either direction (half duplex),
or both of them at the same time (full duplex).
”h]”hÌ)”}”(hŒuIt may also be used to stream data in either direction (half duplex),
or both of them at the same time (full duplex).”h]”hŒuIt may also be used to stream data in either direction (half duplex),
or both of them at the same time (full duplex).”…””}”(hjM  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K#hjI  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒƒSome devices may use eight bit words.  Others may use different word
lengths, such as streams of 12-bit or 20-bit digital samples.
”h]”hÌ)”}”(hŒ‚Some devices may use eight bit words.  Others may use different word
lengths, such as streams of 12-bit or 20-bit digital samples.”h]”hŒ‚Some devices may use eight bit words.  Others may use different word
lengths, such as streams of 12-bit or 20-bit digital samples.”…””}”(hje  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K&hja  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒ†Words are usually sent with their most significant bit (MSB) first,
but sometimes the least significant bit (LSB) goes first instead.
”h]”hÌ)”}”(hŒ…Words are usually sent with their most significant bit (MSB) first,
but sometimes the least significant bit (LSB) goes first instead.”h]”hŒ…Words are usually sent with their most significant bit (MSB) first,
but sometimes the least significant bit (LSB) goes first instead.”…””}”(hj}  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K)hjy  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒDSometimes SPI is used to daisy-chain devices, like shift registers.
”h]”hÌ)”}”(hŒCSometimes SPI is used to daisy-chain devices, like shift registers.”h]”hŒCSometimes SPI is used to daisy-chain devices, like shift registers.”…””}”(hj•  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K,hj‘  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j*  h³hÊh´K hj&  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´K hhÛh²hubhÌ)”}”(hŒïIn the same way, SPI targets will only rarely support any kind of automatic
discovery/enumeration protocol. The tree of target devices accessible from
a given SPI host controller will normally be set up manually, with
configuration tables.”h]”hŒïIn the same way, SPI targets will only rarely support any kind of automatic
discovery/enumeration protocol. The tree of target devices accessible from
a given SPI host controller will normally be set up manually, with
configuration tables.”…””}”(hj·  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K.hhÛh²hubhÌ)”}”(hX"  SPI is only one of the names used by such four-wire protocols, and
most controllers have no problem handling "MicroWire" (think of it as
half-duplex SPI, for request/response protocols), SSP ("Synchronous
Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
related protocols.”h]”hX.  SPI is only one of the names used by such four-wire protocols, and
most controllers have no problem handling â€œMicroWireâ€ (think of it as
half-duplex SPI, for request/response protocols), SSP (â€œSynchronous
Serial Protocolâ€), PSP (â€œProgrammable Serial Protocolâ€), and other
related protocols.”…””}”(hjÅ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K3hhÛh²hubhÌ)”}”(hXÄ  Some chips eliminate a signal line by combining MOSI and MISO, and
limiting themselves to half-duplex at the hardware level.  In fact
some SPI chips have this signal mode as a strapping option.  These
can be accessed using the same programming interface as SPI, but of
course they won't handle full duplex transfers.  You may find such
chips described as using "three wire" signaling: SCK, data, nCSx.
(That data line is sometimes called MOMI or SISO.)”h]”hXÊ  Some chips eliminate a signal line by combining MOSI and MISO, and
limiting themselves to half-duplex at the hardware level.  In fact
some SPI chips have this signal mode as a strapping option.  These
can be accessed using the same programming interface as SPI, but of
course they wonâ€™t handle full duplex transfers.  You may find such
chips described as using â€œthree wireâ€ signaling: SCK, data, nCSx.
(That data line is sometimes called MOMI or SISO.)”…””}”(hjÓ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K9hhÛh²hubhÌ)”}”(hŒ¦Microcontrollers often support both host and target sides of the SPI
protocol.  This document (and Linux) supports both the host and target
sides of SPI interactions.”h]”hŒ¦Microcontrollers often support both host and target sides of the SPI
protocol.  This document (and Linux) supports both the host and target
sides of SPI interactions.”…””}”(hjá  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KAhhÛh²hubeh}”(h]”Œwhat-is-spi”ah ]”h"]”Œwhat is spi?”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒ'Who uses it?  On what kinds of systems?”h]”hŒ'Who uses it?  On what kinds of systems?”…””}”(hjú  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj÷  h²hh³hÊh´KGubhÌ)”}”(hXk  Linux developers using SPI are probably writing device drivers for embedded
systems boards.  SPI is used to control external chips, and it is also a
protocol supported by every MMC or SD memory card.  (The older "DataFlash"
cards, predating MMC cards but using the same connectors and card shape,
support only SPI.)  Some PC hardware uses SPI flash for BIOS code.”h]”hXo  Linux developers using SPI are probably writing device drivers for embedded
systems boards.  SPI is used to control external chips, and it is also a
protocol supported by every MMC or SD memory card.  (The older â€œDataFlashâ€
cards, predating MMC cards but using the same connectors and card shape,
support only SPI.)  Some PC hardware uses SPI flash for BIOS code.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KHhj÷  h²hubhÌ)”}”(hŒ¨SPI target chips range from digital/analog converters used for analog
sensors and codecs, to memory, to peripherals like USB controllers
or Ethernet adapters; and more.”h]”hŒ¨SPI target chips range from digital/analog converters used for analog
sensors and codecs, to memory, to peripherals like USB controllers
or Ethernet adapters; and more.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KNhj÷  h²hubhÌ)”}”(hXÊ  Most systems using SPI will integrate a few devices on a mainboard.
Some provide SPI links on expansion connectors; in cases where no
dedicated SPI controller exists, GPIO pins can be used to create a
low speed "bitbanging" adapter.  Very few systems will "hotplug" an SPI
controller; the reasons to use SPI focus on low cost and simple operation,
and if dynamic reconfiguration is important, USB will often be a more
appropriate low-pincount peripheral bus.”h]”hXÒ  Most systems using SPI will integrate a few devices on a mainboard.
Some provide SPI links on expansion connectors; in cases where no
dedicated SPI controller exists, GPIO pins can be used to create a
low speed â€œbitbangingâ€ adapter.  Very few systems will â€œhotplugâ€ an SPI
controller; the reasons to use SPI focus on low cost and simple operation,
and if dynamic reconfiguration is important, USB will often be a more
appropriate low-pincount peripheral bus.”…””}”(hj$  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KRhj÷  h²hubhÌ)”}”(hŒÊMany microcontrollers that can run Linux integrate one or more I/O
interfaces with SPI modes.  Given SPI support, they could use MMC or SD
cards without needing a special purpose MMC/SD/SDIO controller.”h]”hŒÊMany microcontrollers that can run Linux integrate one or more I/O
interfaces with SPI modes.  Given SPI support, they could use MMC or SD
cards without needing a special purpose MMC/SD/SDIO controller.”…””}”(hj2  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KZhj÷  h²hubeh}”(h]”Œ$who-uses-it-on-what-kinds-of-systems”ah ]”h"]”Œ&who uses it? on what kinds of systems?”ah$]”h&]”uh1hµhh·h²hh³hÊh´KGubh¶)”}”(hhh]”(h»)”}”(hŒ5I'm confused.  What are these four SPI "clock modes"?”h]”hŒ;Iâ€™m confused.  What are these four SPI â€œclock modesâ€?”…””}”(hjK  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjH  h²hh³hÊh´K`ubhÌ)”}”(hŒ‰It's easy to be confused here, and the vendor documentation you'll
find isn't necessarily helpful.  The four modes combine two mode bits:”h]”hŒItâ€™s easy to be confused here, and the vendor documentation youâ€™ll
find isnâ€™t necessarily helpful.  The four modes combine two mode bits:”…””}”(hjY  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KahjH  h²hubj%  )”}”(hX<  - CPOL indicates the initial clock polarity.  CPOL=0 means the
  clock starts low, so the first (leading) edge is rising, and
  the second (trailing) edge is falling.  CPOL=1 means the clock
  starts high, so the first (leading) edge is falling.

- CPHA indicates the clock phase used to sample data; CPHA=0 says
  sample on the leading edge, CPHA=1 means the trailing edge.

  Since the signal needs to stabilize before it's sampled, CPHA=0
  implies that its data is written half a clock before the first
  clock edge.  The chipselect may have made it become available.
”h]”j+  )”}”(hhh]”(j0  )”}”(hŒîCPOL indicates the initial clock polarity.  CPOL=0 means the
clock starts low, so the first (leading) edge is rising, and
the second (trailing) edge is falling.  CPOL=1 means the clock
starts high, so the first (leading) edge is falling.
”h]”hÌ)”}”(hŒíCPOL indicates the initial clock polarity.  CPOL=0 means the
clock starts low, so the first (leading) edge is rising, and
the second (trailing) edge is falling.  CPOL=1 means the clock
starts high, so the first (leading) edge is falling.”h]”hŒíCPOL indicates the initial clock polarity.  CPOL=0 means the
clock starts low, so the first (leading) edge is rising, and
the second (trailing) edge is falling.  CPOL=1 means the clock
starts high, so the first (leading) edge is falling.”…””}”(hjr  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kdhjn  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjk  ubj0  )”}”(hX;  CPHA indicates the clock phase used to sample data; CPHA=0 says
sample on the leading edge, CPHA=1 means the trailing edge.

Since the signal needs to stabilize before it's sampled, CPHA=0
implies that its data is written half a clock before the first
clock edge.  The chipselect may have made it become available.
”h]”(hÌ)”}”(hŒ{CPHA indicates the clock phase used to sample data; CPHA=0 says
sample on the leading edge, CPHA=1 means the trailing edge.”h]”hŒ{CPHA indicates the clock phase used to sample data; CPHA=0 says
sample on the leading edge, CPHA=1 means the trailing edge.”…””}”(hjŠ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kihj†  ubhÌ)”}”(hŒ½Since the signal needs to stabilize before it's sampled, CPHA=0
implies that its data is written half a clock before the first
clock edge.  The chipselect may have made it become available.”h]”hŒ¿Since the signal needs to stabilize before itâ€™s sampled, CPHA=0
implies that its data is written half a clock before the first
clock edge.  The chipselect may have made it become available.”…””}”(hj˜  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Klhj†  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjk  ubeh}”(h]”h ]”h"]”h$]”h&]”j¯  j°  uh1j*  h³hÊh´Kdhjg  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´KdhjH  h²hubhÌ)”}”(hŒ‚Chip specs won't always say "uses SPI mode X" in as many words,
but their timing diagrams will make the CPOL and CPHA modes clear.”h]”hŒˆChip specs wonâ€™t always say â€œuses SPI mode Xâ€ in as many words,
but their timing diagrams will make the CPOL and CPHA modes clear.”…””}”(hj¸  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KphjH  h²hubhÌ)”}”(hŒõIn the SPI mode number, CPOL is the high order bit and CPHA is the
low order bit.  So when a chip's timing diagram shows the clock
starting low (CPOL=0) and data stabilized for sampling during the
trailing clock edge (CPHA=1), that's SPI mode 1.”h]”hŒùIn the SPI mode number, CPOL is the high order bit and CPHA is the
low order bit.  So when a chipâ€™s timing diagram shows the clock
starting low (CPOL=0) and data stabilized for sampling during the
trailing clock edge (CPHA=1), thatâ€™s SPI mode 1.”…””}”(hjÆ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KshjH  h²hubhÌ)”}”(hX’  Note that the clock mode is relevant as soon as the chipselect goes
active.  So the host must set the clock to inactive before selecting
a target, and the target can tell the chosen polarity by sampling the
clock level when its select line goes active.  That's why many devices
support for example both modes 0 and 3:  they don't care about polarity,
and always clock data in/out on rising clock edges.”h]”hX–  Note that the clock mode is relevant as soon as the chipselect goes
active.  So the host must set the clock to inactive before selecting
a target, and the target can tell the chosen polarity by sampling the
clock level when its select line goes active.  Thatâ€™s why many devices
support for example both modes 0 and 3:  they donâ€™t care about polarity,
and always clock data in/out on rising clock edges.”…””}”(hjÔ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KxhjH  h²hubeh}”(h]”Œ0i-m-confused-what-are-these-four-spi-clock-modes”ah ]”h"]”Œ4i'm confused. what are these four spi "clock modes"?”ah$]”h&]”uh1hµhh·h²hh³hÊh´K`ubh¶)”}”(hhh]”(h»)”}”(hŒ0How do these driver programming interfaces work?”h]”hŒ0How do these driver programming interfaces work?”…””}”(hjí  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjê  h²hh³hÊh´KubhÌ)”}”(hŒæThe <linux/spi/spi.h> header file includes kerneldoc, as does the
main source code, and you should certainly read that chapter of the
kernel API document.  This is just an overview, so you get the big
picture before those details.”h]”hŒæThe <linux/spi/spi.h> header file includes kerneldoc, as does the
main source code, and you should certainly read that chapter of the
kernel API document.  This is just an overview, so you get the big
picture before those details.”…””}”(hjû  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K‚hjê  h²hubhÌ)”}”(hXI  SPI requests always go into I/O queues.  Requests for a given SPI device
are always executed in FIFO order, and complete asynchronously through
completion callbacks.  There are also some simple synchronous wrappers
for those calls, including ones for common transaction types like writing
a command and then reading its response.”h]”hXI  SPI requests always go into I/O queues.  Requests for a given SPI device
are always executed in FIFO order, and complete asynchronously through
completion callbacks.  There are also some simple synchronous wrappers
for those calls, including ones for common transaction types like writing
a command and then reading its response.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K‡hjê  h²hubhÌ)”}”(hŒ/There are two types of SPI driver, here called:”h]”hŒ/There are two types of SPI driver, here called:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Khjê  h²hubj%  )”}”(hX¹  Controller drivers ...
      controllers may be built into System-On-Chip
      processors, and often support both Controller and target roles.
      These drivers touch hardware registers and may use DMA.
      Or they can be PIO bitbangers, needing just GPIO pins.

Protocol drivers ...
      these pass messages through the controller
      driver to communicate with a target or Controller device on the
      other side of an SPI link.
”h]”hŒdefinition_list”“”)”}”(hhh]”(hŒdefinition_list_item”“”)”}”(hŒóController drivers ...
controllers may be built into System-On-Chip
processors, and often support both Controller and target roles.
These drivers touch hardware registers and may use DMA.
Or they can be PIO bitbangers, needing just GPIO pins.
”h]”(hŒterm”“”)”}”(hŒController drivers ...”h]”hŒController drivers ...”…””}”(hj6  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´K“hj0  ubhŒ
definition”“”)”}”(hhh]”hÌ)”}”(hŒÛcontrollers may be built into System-On-Chip
processors, and often support both Controller and target roles.
These drivers touch hardware registers and may use DMA.
Or they can be PIO bitbangers, needing just GPIO pins.”h]”hŒÛcontrollers may be built into System-On-Chip
processors, and often support both Controller and target roles.
These drivers touch hardware registers and may use DMA.
Or they can be PIO bitbangers, needing just GPIO pins.”…””}”(hjI  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KhjF  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj0  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´K“hj+  ubj/  )”}”(hŒ›Protocol drivers ...
these pass messages through the controller
driver to communicate with a target or Controller device on the
other side of an SPI link.
”h]”(j5  )”}”(hŒProtocol drivers ...”h]”hŒProtocol drivers ...”…””}”(hjg  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´K˜hjc  ubjE  )”}”(hhh]”hÌ)”}”(hŒ…these pass messages through the controller
driver to communicate with a target or Controller device on the
other side of an SPI link.”h]”hŒ…these pass messages through the controller
driver to communicate with a target or Controller device on the
other side of an SPI link.”…””}”(hjx  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K–hju  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hjc  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´K˜hj+  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j)  hj%  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´Khjê  h²hubhÌ)”}”(hX_  So for example one protocol driver might talk to the MTD layer to export
data to filesystems stored on SPI flash like DataFlash; and others might
control audio interfaces, present touchscreen sensors as input interfaces,
or monitor temperature and voltage levels during industrial processing.
And those might all be sharing the same controller driver.”h]”hX_  So for example one protocol driver might talk to the MTD layer to export
data to filesystems stored on SPI flash like DataFlash; and others might
control audio interfaces, present touchscreen sensors as input interfaces,
or monitor temperature and voltage levels during industrial processing.
And those might all be sharing the same controller driver.”…””}”(hjž  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kšhjê  h²hubhÌ)”}”(hŒdA "struct spi_device" encapsulates the controller-side interface between
those two types of drivers.”h]”hŒhA â€œstruct spi_deviceâ€ encapsulates the controller-side interface between
those two types of drivers.”…””}”(hj¬  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K hjê  h²hubhÌ)”}”(hŒ÷There is a minimal core of SPI programming interfaces, focussing on
using the driver model to connect controller and protocol drivers using
device tables provided by board specific initialization code.  SPI
shows up in sysfs in several locations::”h]”hŒöThere is a minimal core of SPI programming interfaces, focussing on
using the driver model to connect controller and protocol drivers using
device tables provided by board specific initialization code.  SPI
shows up in sysfs in several locations:”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´K£hjê  h²hubhŒliteral_block”“”)”}”(hX?  /sys/devices/.../CTLR ... physical node for a given SPI controller

/sys/devices/.../CTLR/spiB.C ... spi_device on bus "B",
     chipselect C, accessed through CTLR.

/sys/bus/spi/devices/spiB.C ... symlink to that physical
     .../CTLR/spiB.C device

/sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
     that should be used with this device (for hotplug/coldplug)

/sys/bus/spi/drivers/D ... driver for one or more spi*.* devices

/sys/class/spi_master/spiB ... symlink to a logical node which could hold
     class related state for the SPI host controller managing bus "B".
     All spiB.* devices share one physical SPI bus segment, with SCLK,
     MOSI, and MISO.

/sys/devices/.../CTLR/slave ... virtual file for (un)registering the
     target device for an SPI target controller.
     Writing the driver name of an SPI target handler to this file
     registers the target device; writing "(null)" unregisters the target
     device.
     Reading from this file shows the name of the target device ("(null)"
     if not registered).

/sys/class/spi_slave/spiB ... symlink to a logical node which could hold
     class related state for the SPI target controller on bus "B".  When
     registered, a single spiB.* device is present here, possible sharing
     the physical SPI bus segment with other SPI target devices.”h]”hX?  /sys/devices/.../CTLR ... physical node for a given SPI controller

/sys/devices/.../CTLR/spiB.C ... spi_device on bus "B",
     chipselect C, accessed through CTLR.

/sys/bus/spi/devices/spiB.C ... symlink to that physical
     .../CTLR/spiB.C device

/sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
     that should be used with this device (for hotplug/coldplug)

/sys/bus/spi/drivers/D ... driver for one or more spi*.* devices

/sys/class/spi_master/spiB ... symlink to a logical node which could hold
     class related state for the SPI host controller managing bus "B".
     All spiB.* devices share one physical SPI bus segment, with SCLK,
     MOSI, and MISO.

/sys/devices/.../CTLR/slave ... virtual file for (un)registering the
     target device for an SPI target controller.
     Writing the driver name of an SPI target handler to this file
     registers the target device; writing "(null)" unregisters the target
     device.
     Reading from this file shows the name of the target device ("(null)"
     if not registered).

/sys/class/spi_slave/spiB ... symlink to a logical node which could hold
     class related state for the SPI target controller on bus "B".  When
     registered, a single spiB.* device is present here, possible sharing
     the physical SPI bus segment with other SPI target devices.”…””}”hjÊ  sbah}”(h]”h ]”h"]”h$]”h&]”Œ	xml:space”Œpreserve”uh1jÈ  h³hÊh´K¨hjê  h²hubhÌ)”}”(hŒ–At this time, the only class-specific state is the bus number ("B" in "spiB"),
so those /sys/class entries are only useful to quickly identify busses.”h]”hŒžAt this time, the only class-specific state is the bus number (â€œBâ€ in â€œspiBâ€),
so those /sys/class entries are only useful to quickly identify busses.”…””}”(hjÚ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÇhjê  h²hubeh}”(h]”Œ/how-do-these-driver-programming-interfaces-work”ah ]”h"]”Œ0how do these driver programming interfaces work?”ah$]”h&]”uh1hµhh·h²hh³hÊh´Kubh¶)”}”(hhh]”(h»)”}”(hŒ6How does board-specific init code declare SPI devices?”h]”hŒ6How does board-specific init code declare SPI devices?”…””}”(hjó  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjð  h²hh³hÊh´KÌubhÌ)”}”(hŒÑLinux needs several kinds of information to properly configure SPI devices.
That information is normally provided by board-specific code, even for
chips that do support some of automated discovery/enumeration.”h]”hŒÑLinux needs several kinds of information to properly configure SPI devices.
That information is normally provided by board-specific code, even for
chips that do support some of automated discovery/enumeration.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÍhjð  h²hubh¶)”}”(hhh]”(h»)”}”(hŒDeclare Controllers”h]”hŒDeclare Controllers”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´KÒubhÌ)”}”(hXa  The first kind of information is a list of what SPI controllers exist.
For System-on-Chip (SOC) based boards, these will usually be platform
devices, and the controller may need some platform_data in order to
operate properly.  The "struct platform_device" will include resources
like the physical address of the controller's first register and its IRQ.”h]”hXg  The first kind of information is a list of what SPI controllers exist.
For System-on-Chip (SOC) based boards, these will usually be platform
devices, and the controller may need some platform_data in order to
operate properly.  The â€œstruct platform_deviceâ€ will include resources
like the physical address of the controllerâ€™s first register and its IRQ.”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÔhj  h²hubhÌ)”}”(hX•  Platforms will often abstract the "register SPI controller" operation,
maybe coupling it with code to initialize pin configurations, so that
the arch/.../mach-*/board-*.c files for several boards can all share the
same basic controller setup code.  This is because most SOCs have several
SPI-capable controllers, and only the ones actually usable on a given
board should normally be set up and registered.”h]”(hŒ£Platforms will often abstract the â€œregister SPI controllerâ€ operation,
maybe coupling it with code to initialize pin configurations, so that
the arch/.../mach-”…””}”(hj.  h²hh³Nh´NubhŒemphasis”“”)”}”(hŒ	*/board-*”h]”hŒ/board-”…””}”(hj8  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j6  hj.  ubhŒí.c files for several boards can all share the
same basic controller setup code.  This is because most SOCs have several
SPI-capable controllers, and only the ones actually usable on a given
board should normally be set up and registered.”…””}”(hj.  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´KÚhj  h²hubhÌ)”}”(hŒESo for example arch/.../mach-*/board-*.c files might have code like::”h]”(hŒSo for example arch/.../mach-”…””}”(hjP  h²hh³Nh´Nubj7  )”}”(hŒ	*/board-*”h]”hŒ/board-”…””}”(hjX  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j6  hjP  ubhŒ.c files might have code like:”…””}”(hjP  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Káhj  h²hubjÉ  )”}”(hX‰  #include <mach/spi.h>   /* for mysoc_spi_data */

/* if your mach-* infrastructure doesn't support kernels that can
 * run on multiple boards, pdata wouldn't benefit from "__init".
 */
static struct mysoc_spi_data pdata __initdata = { ... };

static __init board_init(void)
{
        ...
        /* this board only uses SPI controller #2 */
        mysoc_register_spi(2, &pdata);
        ...
}”h]”hX‰  #include <mach/spi.h>   /* for mysoc_spi_data */

/* if your mach-* infrastructure doesn't support kernels that can
 * run on multiple boards, pdata wouldn't benefit from "__init".
 */
static struct mysoc_spi_data pdata __initdata = { ... };

static __init board_init(void)
{
        ...
        /* this board only uses SPI controller #2 */
        mysoc_register_spi(2, &pdata);
        ...
}”…””}”hjp  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Kãhj  h²hubhÌ)”}”(hŒ9And SOC-specific utility code might look something like::”h]”hŒ8And SOC-specific utility code might look something like:”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Kòhj  h²hubjÉ  )”}”(hX±  #include <mach/spi.h>

static struct platform_device spi2 = { ... };

void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata)
{
        struct mysoc_spi_data *pdata2;

        pdata2 = kmalloc_obj(*pdata2);
        *pdata2 = pdata;
        ...
        if (n == 2) {
                spi2->dev.platform_data = pdata2;
                register_platform_device(&spi2);

                /* also: set up pin modes so the spi2 signals are
                 * visible on the relevant pins ... bootloaders on
                 * production boards may already have done this, but
                 * developer boards will often need Linux to do it.
                 */
        }
        ...
}”h]”hX±  #include <mach/spi.h>

static struct platform_device spi2 = { ... };

void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata)
{
        struct mysoc_spi_data *pdata2;

        pdata2 = kmalloc_obj(*pdata2);
        *pdata2 = pdata;
        ...
        if (n == 2) {
                spi2->dev.platform_data = pdata2;
                register_platform_device(&spi2);

                /* also: set up pin modes so the spi2 signals are
                 * visible on the relevant pins ... bootloaders on
                 * production boards may already have done this, but
                 * developer boards will often need Linux to do it.
                 */
        }
        ...
}”…””}”hjŒ  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Kôhj  h²hubhÌ)”}”(hŒîNotice how the platform_data for boards may be different, even if the
same SOC controller is used.  For example, on one board SPI might use
an external clock, where another derives the SPI clock from current
settings of some master clock.”h]”hŒîNotice how the platform_data for boards may be different, even if the
same SOC controller is used.  For example, on one board SPI might use
an external clock, where another derives the SPI clock from current
settings of some master clock.”…””}”(hjš  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj  h²hubeh}”(h]”Œdeclare-controllers”ah ]”h"]”Œdeclare controllers”ah$]”h&]”uh1hµhjð  h²hh³hÊh´KÒubh¶)”}”(hhh]”(h»)”}”(hŒDeclare target Devices”h]”hŒDeclare target Devices”…””}”(hj³  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj°  h²hh³hÊh´MubhÌ)”}”(hŒ«The second kind of information is a list of what SPI target devices exist
on the target board, often with some board-specific data needed for the
driver to work correctly.”h]”hŒ«The second kind of information is a list of what SPI target devices exist
on the target board, often with some board-specific data needed for the
driver to work correctly.”…””}”(hjÁ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj°  h²hubhÌ)”}”(hŒ¹Normally your arch/.../mach-*/board-*.c files would provide a small table
listing the SPI devices on each board.  (This would typically be only a
small handful.)  That might look like::”h]”(hŒNormally your arch/.../mach-”…””}”(hjÏ  h²hh³Nh´Nubj7  )”}”(hŒ	*/board-*”h]”hŒ/board-”…””}”(hj×  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j6  hjÏ  ubhŒ“.c files would provide a small table
listing the SPI devices on each board.  (This would typically be only a
small handful.)  That might look like:”…””}”(hjÏ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj°  h²hubjÉ  )”}”(hX  static struct ads7846_platform_data ads_info = {
        .vref_delay_usecs       = 100,
        .x_plate_ohms           = 580,
        .y_plate_ohms           = 410,
};

static struct spi_board_info spi_board_info[] __initdata = {
{
        .modalias       = "ads7846",
        .platform_data  = &ads_info,
        .mode           = SPI_MODE_0,
        .irq            = GPIO_IRQ(31),
        .max_speed_hz   = 120000 /* max sample rate at 3V */ * 16,
        .bus_num        = 1,
        .chip_select    = 0,
},
};”h]”hX  static struct ads7846_platform_data ads_info = {
        .vref_delay_usecs       = 100,
        .x_plate_ohms           = 580,
        .y_plate_ohms           = 410,
};

static struct spi_board_info spi_board_info[] __initdata = {
{
        .modalias       = "ads7846",
        .platform_data  = &ads_info,
        .mode           = SPI_MODE_0,
        .irq            = GPIO_IRQ(31),
        .max_speed_hz   = 120000 /* max sample rate at 3V */ * 16,
        .bus_num        = 1,
        .chip_select    = 0,
},
};”…””}”hjï  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Mhj°  h²hubhÌ)”}”(hXS  Again, notice how board-specific information is provided; each chip may need
several types.  This example shows generic constraints like the fastest SPI
clock to allow (a function of board voltage in this case) or how an IRQ pin
is wired, plus chip-specific constraints like an important delay that's
changed by the capacitance at one pin.”h]”hXU  Again, notice how board-specific information is provided; each chip may need
several types.  This example shows generic constraints like the fastest SPI
clock to allow (a function of board voltage in this case) or how an IRQ pin
is wired, plus chip-specific constraints like an important delay thatâ€™s
changed by the capacitance at one pin.”…””}”(hjý  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M.hj°  h²hubhÌ)”}”(hŒÑ(There's also "controller_data", information that may be useful to the
controller driver.  An example would be peripheral-specific DMA tuning
data or chipselect callbacks.  This is stored in spi_device later.)”h]”hŒ×(Thereâ€™s also â€œcontroller_dataâ€, information that may be useful to the
controller driver.  An example would be peripheral-specific DMA tuning
data or chipselect callbacks.  This is stored in spi_device later.)”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M4hj°  h²hubhÌ)”}”(hX\  The board_info should provide enough information to let the system work
without the chip's driver being loaded.  The most troublesome aspect of
that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since
sharing a bus with a device that interprets chipselect "backwards" is
not possible until the infrastructure knows how to deselect it.”h]”hXb  The board_info should provide enough information to let the system work
without the chipâ€™s driver being loaded.  The most troublesome aspect of
that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since
sharing a bus with a device that interprets chipselect â€œbackwardsâ€ is
not possible until the infrastructure knows how to deselect it.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M8hj°  h²hubhÌ)”}”(hŒ«Then your board initialization code would register that table with the SPI
infrastructure, so that it's available later when the SPI host controller
driver is registered::”h]”hŒ¬Then your board initialization code would register that table with the SPI
infrastructure, so that itâ€™s available later when the SPI host controller
driver is registered:”…””}”(hj'  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M>hj°  h²hubjÉ  )”}”(hŒDspi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));”h]”hŒDspi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));”…””}”hj5  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´MBhj°  h²hubhÌ)”}”(hŒHLike with other static board-specific setup, you won't unregister those.”h]”hŒJLike with other static board-specific setup, you wonâ€™t unregister those.”…””}”(hjC  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MDhj°  h²hubhÌ)”}”(hXu  The widely used "card" style computers bundle memory, cpu, and little else
onto a card that's maybe just thirty square centimeters.  On such systems,
your ``arch/.../mach-.../board-*.c`` file would primarily provide information
about the devices on the mainboard into which such a card is plugged.  That
certainly includes SPI devices hooked up through the card connectors!”h]”(hŒ¡The widely used â€œcardâ€ style computers bundle memory, cpu, and little else
onto a card thatâ€™s maybe just thirty square centimeters.  On such systems,
your ”…””}”(hjQ  h²hh³Nh´NubhŒliteral”“”)”}”(hŒ``arch/.../mach-.../board-*.c``”h]”hŒarch/.../mach-.../board-*.c”…””}”(hj[  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjQ  ubhŒ» file would primarily provide information
about the devices on the mainboard into which such a card is plugged.  That
certainly includes SPI devices hooked up through the card connectors!”…””}”(hjQ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MFhj°  h²hubeh}”(h]”Œdeclare-target-devices”ah ]”h"]”Œdeclare target devices”ah$]”h&]”uh1hµhjð  h²hh³hÊh´Mubh¶)”}”(hhh]”(h»)”}”(hŒNon-static Configurations”h]”hŒNon-static Configurations”…””}”(hj~  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj{  h²hh³hÊh´MNubhÌ)”}”(hŒßWhen Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those
configurations will also be dynamic.  Fortunately, such devices all support
basic device identification probes, so they should hotplug normally.”h]”hŒßWhen Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those
configurations will also be dynamic.  Fortunately, such devices all support
basic device identification probes, so they should hotplug normally.”…””}”(hjŒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MPhj{  h²hubeh}”(h]”Œnon-static-configurations”ah ]”h"]”Œnon-static configurations”ah$]”h&]”uh1hµhjð  h²hh³hÊh´MNubeh}”(h]”Œ5how-does-board-specific-init-code-declare-spi-devices”ah ]”h"]”Œ6how does board-specific init code declare spi devices?”ah$]”h&]”uh1hµhh·h²hh³hÊh´KÌubh¶)”}”(hhh]”(h»)”}”(hŒ(How do I write an "SPI Protocol Driver"?”h]”hŒ,How do I write an â€œSPI Protocol Driverâ€?”…””}”(hj­  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjª  h²hh³hÊh´MVubhÌ)”}”(hŒ‡Most SPI drivers are currently kernel drivers, but there's also support
for userspace drivers.  Here we talk only about kernel drivers.”h]”hŒ‰Most SPI drivers are currently kernel drivers, but thereâ€™s also support
for userspace drivers.  Here we talk only about kernel drivers.”…””}”(hj»  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MWhjª  h²hubhÌ)”}”(hŒ@SPI protocol drivers somewhat resemble platform device drivers::”h]”hŒ?SPI protocol drivers somewhat resemble platform device drivers:”…””}”(hjÉ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MZhjª  h²hubjÉ  )”}”(hŒòstatic struct spi_driver CHIP_driver = {
        .driver = {
                .name           = "CHIP",
                .pm             = &CHIP_pm_ops,
        },

        .probe          = CHIP_probe,
        .remove         = CHIP_remove,
};”h]”hŒòstatic struct spi_driver CHIP_driver = {
        .driver = {
                .name           = "CHIP",
                .pm             = &CHIP_pm_ops,
        },

        .probe          = CHIP_probe,
        .remove         = CHIP_remove,
};”…””}”hj×  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´M\hjª  h²hubhÌ)”}”(hX  The driver core will automatically attempt to bind this driver to any SPI
device whose board_info gave a modalias of "CHIP".  Your probe() code
might look like this unless you're creating a device which is managing
a bus (appearing under /sys/class/spi_master).”h]”hX  The driver core will automatically attempt to bind this driver to any SPI
device whose board_info gave a modalias of â€œCHIPâ€.  Your probe() code
might look like this unless youâ€™re creating a device which is managing
a bus (appearing under /sys/class/spi_master).”…””}”(hjå  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mfhjª  h²hubjÉ  )”}”(hXý  static int CHIP_probe(struct spi_device *spi)
{
        struct CHIP                     *chip;
        struct CHIP_platform_data       *pdata;

        /* assuming the driver requires board-specific data: */
        pdata = &spi->dev.platform_data;
        if (!pdata)
                return -ENODEV;

        /* get memory for driver's per-chip state */
        chip = kzalloc(*chip);
        if (!chip)
                return -ENOMEM;
        spi_set_drvdata(spi, chip);

        ... etc
        return 0;
}”h]”hXý  static int CHIP_probe(struct spi_device *spi)
{
        struct CHIP                     *chip;
        struct CHIP_platform_data       *pdata;

        /* assuming the driver requires board-specific data: */
        pdata = &spi->dev.platform_data;
        if (!pdata)
                return -ENODEV;

        /* get memory for driver's per-chip state */
        chip = kzalloc(*chip);
        if (!chip)
                return -ENOMEM;
        spi_set_drvdata(spi, chip);

        ... etc
        return 0;
}”…””}”hjó  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Mmhjª  h²hubhÌ)”}”(hŒàAs soon as it enters probe(), the driver may issue I/O requests to
the SPI device using "struct spi_message".  When remove() returns,
or after probe() fails, the driver guarantees that it won't submit
any more such messages.”h]”hŒæAs soon as it enters probe(), the driver may issue I/O requests to
the SPI device using â€œstruct spi_messageâ€.  When remove() returns,
or after probe() fails, the driver guarantees that it wonâ€™t submit
any more such messages.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhjª  h²hubj%  )”}”(hX]	  - An spi_message is a sequence of protocol operations, executed
  as one atomic sequence.  SPI driver controls include:

    + when bidirectional reads and writes start ... by how its
      sequence of spi_transfer requests is arranged;

    + which I/O buffers are used ... each spi_transfer wraps a
      buffer for each transfer direction, supporting full duplex
      (two pointers, maybe the same one in both cases) and half
      duplex (one pointer is NULL) transfers;

    + optionally defining short delays after transfers ... using
      the spi_transfer.delay.value setting (this delay can be the
      only protocol effect, if the buffer length is zero) ...
      when specifying this delay the default spi_transfer.delay.unit
      is microseconds, however this can be adjusted to clock cycles
      or nanoseconds if needed;

    + whether the chipselect becomes inactive after a transfer and
      any delay ... by using the spi_transfer.cs_change flag;

    + hinting whether the next message is likely to go to this same
      device ... using the spi_transfer.cs_change flag on the last
      transfer in that atomic group, and potentially saving costs
      for chip deselect and select operations.

- Follow standard kernel rules, and provide DMA-safe buffers in
  your messages.  That way controller drivers using DMA aren't forced
  to make extra copies unless the hardware requires it (e.g. working
  around hardware errata that force the use of bounce buffering).

- The basic I/O primitive is spi_async().  Async requests may be
  issued in any context (irq handler, task, etc) and completion
  is reported using a callback provided with the message.
  After any detected error, the chip is deselected and processing
  of that spi_message is aborted.

- There are also synchronous wrappers like spi_sync(), and wrappers
  like spi_read(), spi_write(), and spi_write_then_read().  These
  may be issued only in contexts that may sleep, and they're all
  clean (and small, and "optional") layers over spi_async().

- The spi_write_then_read() call, and convenience wrappers around
  it, should only be used with small amounts of data where the
  cost of an extra copy may be ignored.  It's designed to support
  common RPC-style requests, such as writing an eight bit command
  and reading a sixteen bit response -- spi_w8r16() being one its
  wrappers, doing exactly that.
”h]”j+  )”}”(hhh]”(j0  )”}”(hXš  An spi_message is a sequence of protocol operations, executed
as one atomic sequence.  SPI driver controls include:

  + when bidirectional reads and writes start ... by how its
    sequence of spi_transfer requests is arranged;

  + which I/O buffers are used ... each spi_transfer wraps a
    buffer for each transfer direction, supporting full duplex
    (two pointers, maybe the same one in both cases) and half
    duplex (one pointer is NULL) transfers;

  + optionally defining short delays after transfers ... using
    the spi_transfer.delay.value setting (this delay can be the
    only protocol effect, if the buffer length is zero) ...
    when specifying this delay the default spi_transfer.delay.unit
    is microseconds, however this can be adjusted to clock cycles
    or nanoseconds if needed;

  + whether the chipselect becomes inactive after a transfer and
    any delay ... by using the spi_transfer.cs_change flag;

  + hinting whether the next message is likely to go to this same
    device ... using the spi_transfer.cs_change flag on the last
    transfer in that atomic group, and potentially saving costs
    for chip deselect and select operations.
”h]”(hÌ)”}”(hŒsAn spi_message is a sequence of protocol operations, executed
as one atomic sequence.  SPI driver controls include:”h]”hŒsAn spi_message is a sequence of protocol operations, executed
as one atomic sequence.  SPI driver controls include:”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M†hj  ubj%  )”}”(hX  + when bidirectional reads and writes start ... by how its
  sequence of spi_transfer requests is arranged;

+ which I/O buffers are used ... each spi_transfer wraps a
  buffer for each transfer direction, supporting full duplex
  (two pointers, maybe the same one in both cases) and half
  duplex (one pointer is NULL) transfers;

+ optionally defining short delays after transfers ... using
  the spi_transfer.delay.value setting (this delay can be the
  only protocol effect, if the buffer length is zero) ...
  when specifying this delay the default spi_transfer.delay.unit
  is microseconds, however this can be adjusted to clock cycles
  or nanoseconds if needed;

+ whether the chipselect becomes inactive after a transfer and
  any delay ... by using the spi_transfer.cs_change flag;

+ hinting whether the next message is likely to go to this same
  device ... using the spi_transfer.cs_change flag on the last
  transfer in that atomic group, and potentially saving costs
  for chip deselect and select operations.
”h]”j+  )”}”(hhh]”(j0  )”}”(hŒhwhen bidirectional reads and writes start ... by how its
sequence of spi_transfer requests is arranged;
”h]”hÌ)”}”(hŒgwhen bidirectional reads and writes start ... by how its
sequence of spi_transfer requests is arranged;”h]”hŒgwhen bidirectional reads and writes start ... by how its
sequence of spi_transfer requests is arranged;”…””}”(hj3  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‰hj/  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒÖwhich I/O buffers are used ... each spi_transfer wraps a
buffer for each transfer direction, supporting full duplex
(two pointers, maybe the same one in both cases) and half
duplex (one pointer is NULL) transfers;
”h]”hÌ)”}”(hŒÕwhich I/O buffers are used ... each spi_transfer wraps a
buffer for each transfer direction, supporting full duplex
(two pointers, maybe the same one in both cases) and half
duplex (one pointer is NULL) transfers;”h]”hŒÕwhich I/O buffers are used ... each spi_transfer wraps a
buffer for each transfer direction, supporting full duplex
(two pointers, maybe the same one in both cases) and half
duplex (one pointer is NULL) transfers;”…””}”(hjK  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MŒhjG  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hXF  optionally defining short delays after transfers ... using
the spi_transfer.delay.value setting (this delay can be the
only protocol effect, if the buffer length is zero) ...
when specifying this delay the default spi_transfer.delay.unit
is microseconds, however this can be adjusted to clock cycles
or nanoseconds if needed;
”h]”hÌ)”}”(hXE  optionally defining short delays after transfers ... using
the spi_transfer.delay.value setting (this delay can be the
only protocol effect, if the buffer length is zero) ...
when specifying this delay the default spi_transfer.delay.unit
is microseconds, however this can be adjusted to clock cycles
or nanoseconds if needed;”h]”hXE  optionally defining short delays after transfers ... using
the spi_transfer.delay.value setting (this delay can be the
only protocol effect, if the buffer length is zero) ...
when specifying this delay the default spi_transfer.delay.unit
is microseconds, however this can be adjusted to clock cycles
or nanoseconds if needed;”…””}”(hjc  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‘hj_  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒuwhether the chipselect becomes inactive after a transfer and
any delay ... by using the spi_transfer.cs_change flag;
”h]”hÌ)”}”(hŒtwhether the chipselect becomes inactive after a transfer and
any delay ... by using the spi_transfer.cs_change flag;”h]”hŒtwhether the chipselect becomes inactive after a transfer and
any delay ... by using the spi_transfer.cs_change flag;”…””}”(hj{  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M˜hjw  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubj0  )”}”(hŒàhinting whether the next message is likely to go to this same
device ... using the spi_transfer.cs_change flag on the last
transfer in that atomic group, and potentially saving costs
for chip deselect and select operations.
”h]”hÌ)”}”(hŒßhinting whether the next message is likely to go to this same
device ... using the spi_transfer.cs_change flag on the last
transfer in that atomic group, and potentially saving costs
for chip deselect and select operations.”h]”hŒßhinting whether the next message is likely to go to this same
device ... using the spi_transfer.cs_change flag on the last
transfer in that atomic group, and potentially saving costs
for chip deselect and select operations.”…””}”(hj“  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M›hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj,  ubeh}”(h]”h ]”h"]”h$]”h&]”j¯  Œ+”uh1j*  h³hÊh´M‰hj(  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´M‰hj  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj  ubj0  )”}”(hX  Follow standard kernel rules, and provide DMA-safe buffers in
your messages.  That way controller drivers using DMA aren't forced
to make extra copies unless the hardware requires it (e.g. working
around hardware errata that force the use of bounce buffering).
”h]”hÌ)”}”(hX  Follow standard kernel rules, and provide DMA-safe buffers in
your messages.  That way controller drivers using DMA aren't forced
to make extra copies unless the hardware requires it (e.g. working
around hardware errata that force the use of bounce buffering).”h]”hX  Follow standard kernel rules, and provide DMA-safe buffers in
your messages.  That way controller drivers using DMA arenâ€™t forced
to make extra copies unless the hardware requires it (e.g. working
around hardware errata that force the use of bounce buffering).”…””}”(hj¾  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M hjº  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj  ubj0  )”}”(hX  The basic I/O primitive is spi_async().  Async requests may be
issued in any context (irq handler, task, etc) and completion
is reported using a callback provided with the message.
After any detected error, the chip is deselected and processing
of that spi_message is aborted.
”h]”hÌ)”}”(hX  The basic I/O primitive is spi_async().  Async requests may be
issued in any context (irq handler, task, etc) and completion
is reported using a callback provided with the message.
After any detected error, the chip is deselected and processing
of that spi_message is aborted.”h]”hX  The basic I/O primitive is spi_async().  Async requests may be
issued in any context (irq handler, task, etc) and completion
is reported using a callback provided with the message.
After any detected error, the chip is deselected and processing
of that spi_message is aborted.”…””}”(hjÖ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¥hjÒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj  ubj0  )”}”(hŒüThere are also synchronous wrappers like spi_sync(), and wrappers
like spi_read(), spi_write(), and spi_write_then_read().  These
may be issued only in contexts that may sleep, and they're all
clean (and small, and "optional") layers over spi_async().
”h]”hÌ)”}”(hŒûThere are also synchronous wrappers like spi_sync(), and wrappers
like spi_read(), spi_write(), and spi_write_then_read().  These
may be issued only in contexts that may sleep, and they're all
clean (and small, and "optional") layers over spi_async().”h]”hX  There are also synchronous wrappers like spi_sync(), and wrappers
like spi_read(), spi_write(), and spi_write_then_read().  These
may be issued only in contexts that may sleep, and theyâ€™re all
clean (and small, and â€œoptionalâ€) layers over spi_async().”…””}”(hjî  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M«hjê  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj  ubj0  )”}”(hX[  The spi_write_then_read() call, and convenience wrappers around
it, should only be used with small amounts of data where the
cost of an extra copy may be ignored.  It's designed to support
common RPC-style requests, such as writing an eight bit command
and reading a sixteen bit response -- spi_w8r16() being one its
wrappers, doing exactly that.
”h]”hÌ)”}”(hXZ  The spi_write_then_read() call, and convenience wrappers around
it, should only be used with small amounts of data where the
cost of an extra copy may be ignored.  It's designed to support
common RPC-style requests, such as writing an eight bit command
and reading a sixteen bit response -- spi_w8r16() being one its
wrappers, doing exactly that.”h]”hX\  The spi_write_then_read() call, and convenience wrappers around
it, should only be used with small amounts of data where the
cost of an extra copy may be ignored.  Itâ€™s designed to support
common RPC-style requests, such as writing an eight bit command
and reading a sixteen bit response -- spi_w8r16() being one its
wrappers, doing exactly that.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M°hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj  ubeh}”(h]”h ]”h"]”h$]”h&]”j¯  j°  uh1j*  h³hÊh´M†hj  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´M†hjª  h²hubhÌ)”}”(hX=  Some drivers may need to modify spi_device characteristics like the
transfer mode, wordsize, or clock rate.  This is done with spi_setup(),
which would normally be called from probe() before the first I/O is
done to the device.  However, that can also be called at any time
that no message is pending for that device.”h]”hX=  Some drivers may need to modify spi_device characteristics like the
transfer mode, wordsize, or clock rate.  This is done with spi_setup(),
which would normally be called from probe() before the first I/O is
done to the device.  However, that can also be called at any time
that no message is pending for that device.”…””}”(hj&  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M·hjª  h²hubhÌ)”}”(hŒìWhile "spi_device" would be the bottom boundary of the driver, the
upper boundaries might include sysfs (especially for sensor readings),
the input layer, ALSA, networking, MTD, the character device framework,
or other Linux subsystems.”h]”hŒðWhile â€œspi_deviceâ€ would be the bottom boundary of the driver, the
upper boundaries might include sysfs (especially for sensor readings),
the input layer, ALSA, networking, MTD, the character device framework,
or other Linux subsystems.”…””}”(hj4  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M½hjª  h²hubhÌ)”}”(hŒhNote that there are two types of memory your driver must manage as part
of interacting with SPI devices.”h]”hŒhNote that there are two types of memory your driver must manage as part
of interacting with SPI devices.”…””}”(hjB  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÂhjª  h²hubj%  )”}”(hXº  - I/O buffers use the usual Linux rules, and must be DMA-safe.
  You'd normally allocate them from the heap or free page pool.
  Don't use the stack, or anything that's declared "static".

- The spi_message and spi_transfer metadata used to glue those
  I/O buffers into a group of protocol transactions.  These can
  be allocated anywhere it's convenient, including as part of
  other allocate-once driver data structures.  Zero-init these.
”h]”j+  )”}”(hhh]”(j0  )”}”(hŒ¶I/O buffers use the usual Linux rules, and must be DMA-safe.
You'd normally allocate them from the heap or free page pool.
Don't use the stack, or anything that's declared "static".
”h]”hÌ)”}”(hŒµI/O buffers use the usual Linux rules, and must be DMA-safe.
You'd normally allocate them from the heap or free page pool.
Don't use the stack, or anything that's declared "static".”h]”hŒ¿I/O buffers use the usual Linux rules, and must be DMA-safe.
Youâ€™d normally allocate them from the heap or free page pool.
Donâ€™t use the stack, or anything thatâ€™s declared â€œstaticâ€.”…””}”(hj[  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÅhjW  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjT  ubj0  )”}”(hŒõThe spi_message and spi_transfer metadata used to glue those
I/O buffers into a group of protocol transactions.  These can
be allocated anywhere it's convenient, including as part of
other allocate-once driver data structures.  Zero-init these.
”h]”hÌ)”}”(hŒôThe spi_message and spi_transfer metadata used to glue those
I/O buffers into a group of protocol transactions.  These can
be allocated anywhere it's convenient, including as part of
other allocate-once driver data structures.  Zero-init these.”h]”hŒöThe spi_message and spi_transfer metadata used to glue those
I/O buffers into a group of protocol transactions.  These can
be allocated anywhere itâ€™s convenient, including as part of
other allocate-once driver data structures.  Zero-init these.”…””}”(hjs  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÉhjo  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjT  ubeh}”(h]”h ]”h"]”h$]”h&]”j¯  j°  uh1j*  h³hÊh´MÅhjP  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j$  h³hÊh´MÅhjª  h²hubhÌ)”}”(hŒ¡If you like, spi_message_alloc() and spi_message_free() convenience
routines are available to allocate and zero-initialize an spi_message
with several transfers.”h]”hŒ¡If you like, spi_message_alloc() and spi_message_free() convenience
routines are available to allocate and zero-initialize an spi_message
with several transfers.”…””}”(hj“  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÎhjª  h²hubeh}”(h]”Œ%how-do-i-write-an-spi-protocol-driver”ah ]”h"]”Œ(how do i write an "spi protocol driver"?”ah$]”h&]”uh1hµhh·h²hh³hÊh´MVubh¶)”}”(hhh]”(h»)”}”(hŒ*How do I write an "SPI Controller Driver"?”h]”hŒ.How do I write an â€œSPI Controller Driverâ€?”…””}”(hj¬  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj©  h²hh³hÊh´MÔubhÌ)”}”(hŒƒAn SPI controller will probably be registered on the platform_bus; write
a driver to bind to the device, whichever bus is involved.”h]”hŒƒAn SPI controller will probably be registered on the platform_bus; write
a driver to bind to the device, whichever bus is involved.”…””}”(hjº  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÕhj©  h²hubhÌ)”}”(hŒØThe main task of this type of driver is to provide an "spi_controller".
Use spi_alloc_host() to allocate the host controller, and
spi_controller_get_devdata() to get the driver-private data allocated for that
device.”h]”hŒÜThe main task of this type of driver is to provide an â€œspi_controllerâ€.
Use spi_alloc_host() to allocate the host controller, and
spi_controller_get_devdata() to get the driver-private data allocated for that
device.”…””}”(hjÈ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MØhj©  h²hubjÉ  )”•G’      }”(hŒ¬struct spi_controller   *ctlr;
struct CONTROLLER       *c;

ctlr = spi_alloc_host(dev, sizeof *c);
if (!ctlr)
        return -ENODEV;

c = spi_controller_get_devdata(ctlr);”h]”hŒ¬struct spi_controller   *ctlr;
struct CONTROLLER       *c;

ctlr = spi_alloc_host(dev, sizeof *c);
if (!ctlr)
        return -ENODEV;

c = spi_controller_get_devdata(ctlr);”…””}”hjÖ  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Mßhj©  h²hubhÌ)”}”(hX5  The driver will initialize the fields of that spi_controller, including the bus
number (maybe the same as the platform device ID) and three methods used to
interact with the SPI core and SPI protocol drivers.  It will also initialize
its own internal state.  (See below about bus numbering and those methods.)”h]”hX5  The driver will initialize the fields of that spi_controller, including the bus
number (maybe the same as the platform device ID) and three methods used to
interact with the SPI core and SPI protocol drivers.  It will also initialize
its own internal state.  (See below about bus numbering and those methods.)”…””}”(hjä  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mèhj©  h²hubhÌ)”}”(hX  After you initialize the spi_controller, then use spi_register_controller() to
publish it to the rest of the system. At that time, device nodes for the
controller and any predeclared spi devices will be made available, and
the driver model core will take care of binding them to drivers.”h]”hX  After you initialize the spi_controller, then use spi_register_controller() to
publish it to the rest of the system. At that time, device nodes for the
controller and any predeclared spi devices will be made available, and
the driver model core will take care of binding them to drivers.”…””}”(hjò  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Míhj©  h²hubhÌ)”}”(hŒƒIf you need to remove your SPI controller driver, spi_unregister_controller()
will reverse the effect of spi_register_controller().”h]”hŒƒIf you need to remove your SPI controller driver, spi_unregister_controller()
will reverse the effect of spi_register_controller().”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mòhj©  h²hubh¶)”}”(hhh]”(h»)”}”(hŒBus Numbering”h]”hŒBus Numbering”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj  h²hh³hÊh´M÷ubhÌ)”}”(hXi  Bus numbering is important, since that's how Linux identifies a given
SPI bus (shared SCK, MOSI, MISO).  Valid bus numbers start at zero.  On
SOC systems, the bus numbers should match the numbers defined by the chip
manufacturer.  For example, hardware controller SPI2 would be bus number 2,
and spi_board_info for devices connected to it would use that number.”h]”hXk  Bus numbering is important, since thatâ€™s how Linux identifies a given
SPI bus (shared SCK, MOSI, MISO).  Valid bus numbers start at zero.  On
SOC systems, the bus numbers should match the numbers defined by the chip
manufacturer.  For example, hardware controller SPI2 would be bus number 2,
and spi_board_info for devices connected to it would use that number.”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mùhj  h²hubhÌ)”}”(hX  If you don't have such hardware-assigned bus number, and for some reason
you can't just assign them, then provide a negative bus number.  That will
then be replaced by a dynamically assigned number. You'd then need to treat
this as a non-static configuration (see above).”h]”hX  If you donâ€™t have such hardware-assigned bus number, and for some reason
you canâ€™t just assign them, then provide a negative bus number.  That will
then be replaced by a dynamically assigned number. Youâ€™d then need to treat
this as a non-static configuration (see above).”…””}”(hj-  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mÿhj  h²hubeh}”(h]”Œbus-numbering”ah ]”h"]”Œbus numbering”ah$]”h&]”uh1hµhj©  h²hh³hÊh´M÷ubh¶)”}”(hhh]”(h»)”}”(hŒSPI Host Controller Methods”h]”hŒSPI Host Controller Methods”…””}”(hjF  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjC  h²hh³hÊh´Mubj*  )”}”(hhh]”(j/  )”}”(hX‡  ``ctlr->setup(struct spi_device *spi)``
This sets up the device clock rate, SPI mode, and word sizes.
Drivers may change the defaults provided by board_info, and then
call spi_setup(spi) to invoke this routine.  It may sleep.

Unless each SPI target has its own configuration registers, don't
change them right away ... otherwise drivers could corrupt I/O
that's in progress for other SPI devices.

.. note::

        BUG ALERT:  for some reason the first version of
        many spi_controller drivers seems to get this wrong.
        When you code setup(), ASSUME that the controller
        is actively processing transfers for another device.
”h]”(j5  )”}”(hŒ'``ctlr->setup(struct spi_device *spi)``”h]”jZ  )”}”(hj]  h]”hŒ#ctlr->setup(struct spi_device *spi)”…””}”(hj_  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj[  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´MhjW  ubjE  )”}”(hhh]”(hÌ)”}”(hŒ¹This sets up the device clock rate, SPI mode, and word sizes.
Drivers may change the defaults provided by board_info, and then
call spi_setup(spi) to invoke this routine.  It may sleep.”h]”hŒ¹This sets up the device clock rate, SPI mode, and word sizes.
Drivers may change the defaults provided by board_info, and then
call spi_setup(spi) to invoke this routine.  It may sleep.”…””}”(hju  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M	hjr  ubhÌ)”}”(hŒªUnless each SPI target has its own configuration registers, don't
change them right away ... otherwise drivers could corrupt I/O
that's in progress for other SPI devices.”h]”hŒ®Unless each SPI target has its own configuration registers, donâ€™t
change them right away ... otherwise drivers could corrupt I/O
thatâ€™s in progress for other SPI devices.”…””}”(hjƒ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhjr  ubhŒnote”“”)”}”(hŒÌBUG ALERT:  for some reason the first version of
many spi_controller drivers seems to get this wrong.
When you code setup(), ASSUME that the controller
is actively processing transfers for another device.”h]”hÌ)”}”(hŒÌBUG ALERT:  for some reason the first version of
many spi_controller drivers seems to get this wrong.
When you code setup(), ASSUME that the controller
is actively processing transfers for another device.”h]”hŒÌBUG ALERT:  for some reason the first version of
many spi_controller drivers seems to get this wrong.
When you code setup(), ASSUME that the controller
is actively processing transfers for another device.”…””}”(hj—  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj“  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‘  hjr  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jD  hjW  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´MhjT  ubj/  )”}”(hŒì``ctlr->cleanup(struct spi_device *spi)``
Your controller driver may use spi_device.controller_state to hold
state it dynamically associates with that device.  If you do that,
be sure to provide the cleanup() method to free that state.
”h]”(j5  )”}”(hŒ)``ctlr->cleanup(struct spi_device *spi)``”h]”jZ  )”}”(hj½  h]”hŒ%ctlr->cleanup(struct spi_device *spi)”…””}”(hj¿  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj»  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´Mhj·  ubjE  )”}”(hhh]”hÌ)”}”(hŒÁYour controller driver may use spi_device.controller_state to hold
state it dynamically associates with that device.  If you do that,
be sure to provide the cleanup() method to free that state.”h]”hŒÁYour controller driver may use spi_device.controller_state to hold
state it dynamically associates with that device.  If you do that,
be sure to provide the cleanup() method to free that state.”…””}”(hjÕ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MhjÒ  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj·  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´MhjT  h²hubj/  )”}”(hX  ``ctlr->prepare_transfer_hardware(struct spi_controller *ctlr)``
This will be called by the queue mechanism to signal to the driver
that a message is coming in soon, so the subsystem requests the
driver to prepare the transfer hardware by issuing this call.
This may sleep.
”h]”(j5  )”}”(hŒ@``ctlr->prepare_transfer_hardware(struct spi_controller *ctlr)``”h]”jZ  )”}”(hjõ  h]”hŒ<ctlr->prepare_transfer_hardware(struct spi_controller *ctlr)”…””}”(hj÷  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjó  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´M!hjï  ubjE  )”}”(hhh]”hÌ)”}”(hŒÐThis will be called by the queue mechanism to signal to the driver
that a message is coming in soon, so the subsystem requests the
driver to prepare the transfer hardware by issuing this call.
This may sleep.”h]”hŒÐThis will be called by the queue mechanism to signal to the driver
that a message is coming in soon, so the subsystem requests the
driver to prepare the transfer hardware by issuing this call.
This may sleep.”…””}”(hj	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mhj
	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hjï  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´M!hjT  h²hubj/  )”}”(hX  ``ctlr->unprepare_transfer_hardware(struct spi_controller *ctlr)``
This will be called by the queue mechanism to signal to the driver
that there are no more messages pending in the queue and it may
relax the hardware (e.g. by power management calls). This may sleep.
”h]”(j5  )”}”(hŒB``ctlr->unprepare_transfer_hardware(struct spi_controller *ctlr)``”h]”jZ  )”}”(hj-	  h]”hŒ>ctlr->unprepare_transfer_hardware(struct spi_controller *ctlr)”…””}”(hj/	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj+	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´M&hj'	  ubjE  )”}”(hhh]”hÌ)”}”(hŒÇThis will be called by the queue mechanism to signal to the driver
that there are no more messages pending in the queue and it may
relax the hardware (e.g. by power management calls). This may sleep.”h]”hŒÇThis will be called by the queue mechanism to signal to the driver
that there are no more messages pending in the queue and it may
relax the hardware (e.g. by power management calls). This may sleep.”…””}”(hjE	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M$hjB	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj'	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´M&hjT  h²hubj/  )”}”(hX_  ``ctlr->transfer_one_message(struct spi_controller *ctlr, struct spi_message *mesg)``
The subsystem calls the driver to transfer a single message while
queuing transfers that arrive in the meantime. When the driver is
finished with this message, it must call
spi_finalize_current_message() so the subsystem can issue the next
message. This may sleep.
”h]”(j5  )”}”(hŒU``ctlr->transfer_one_message(struct spi_controller *ctlr, struct spi_message *mesg)``”h]”jZ  )”}”(hje	  h]”hŒQctlr->transfer_one_message(struct spi_controller *ctlr, struct spi_message *mesg)”…””}”(hjg	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjc	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´M-hj_	  ubjE  )”}”(hhh]”hÌ)”}”(hX  The subsystem calls the driver to transfer a single message while
queuing transfers that arrive in the meantime. When the driver is
finished with this message, it must call
spi_finalize_current_message() so the subsystem can issue the next
message. This may sleep.”h]”hX  The subsystem calls the driver to transfer a single message while
queuing transfers that arrive in the meantime. When the driver is
finished with this message, it must call
spi_finalize_current_message() so the subsystem can issue the next
message. This may sleep.”…””}”(hj}	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M)hjz	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj_	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´M-hjT  h²hubj/  )”}”(hXu  ``ctrl->transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *transfer)``
The subsystem calls the driver to transfer a single transfer while
queuing transfers that arrive in the meantime. When the driver is
finished with this transfer, it must call
spi_finalize_current_transfer() so the subsystem can issue the next
transfer. This may sleep. Note: transfer_one and transfer_one_message
are mutually exclusive; when both are set, the generic subsystem does
not call your transfer_one callback.

Return values:

* negative errno: error
* 0: transfer is finished
* 1: transfer is still in progress
”h]”(j5  )”}”(hŒj``ctrl->transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *transfer)``”h]”jZ  )”}”(hj	  h]”hŒfctrl->transfer_one(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *transfer)”…””}”(hjŸ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj›	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´M<hj—	  ubjE  )”}”(hhh]”(hÌ)”}”(hX£  The subsystem calls the driver to transfer a single transfer while
queuing transfers that arrive in the meantime. When the driver is
finished with this transfer, it must call
spi_finalize_current_transfer() so the subsystem can issue the next
transfer. This may sleep. Note: transfer_one and transfer_one_message
are mutually exclusive; when both are set, the generic subsystem does
not call your transfer_one callback.”h]”hX£  The subsystem calls the driver to transfer a single transfer while
queuing transfers that arrive in the meantime. When the driver is
finished with this transfer, it must call
spi_finalize_current_transfer() so the subsystem can issue the next
transfer. This may sleep. Note: transfer_one and transfer_one_message
are mutually exclusive; when both are set, the generic subsystem does
not call your transfer_one callback.”…””}”(hjµ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M0hj²	  ubhÌ)”}”(hŒReturn values:”h]”hŒReturn values:”…””}”(hjÃ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M8hj²	  ubj+  )”}”(hhh]”(j0  )”}”(hŒnegative errno: error”h]”hÌ)”}”(hjÖ	  h]”hŒnegative errno: error”…””}”(hjØ	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M:hjÔ	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjÑ	  ubj0  )”}”(hŒ0: transfer is finished”h]”hÌ)”}”(hjí	  h]”hŒ0: transfer is finished”…””}”(hjï	  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M;hjë	  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjÑ	  ubj0  )”}”(hŒ!1: transfer is still in progress
”h]”hÌ)”}”(hŒ 1: transfer is still in progress”h]”hŒ 1: transfer is still in progress”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M<hj
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hjÑ	  ubeh}”(h]”h ]”h"]”h$]”h&]”j¯  Œ*”uh1j*  h³hÊh´M:hj²	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj—	  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´M<hjT  h²hubj/  )”}”(hX  ``ctrl->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)``
This method allows SPI client drivers to request SPI host controller
for configuring device specific CS setup, hold and inactive timing
requirements.
”h]”(j5  )”}”(hŒp``ctrl->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)``”h]”jZ  )”}”(hj3
  h]”hŒlctrl->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)”…””}”(hj5
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj1
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´MAhj-
  ubjE  )”}”(hhh]”hÌ)”}”(hŒ•This method allows SPI client drivers to request SPI host controller
for configuring device specific CS setup, hold and inactive timing
requirements.”h]”hŒ•This method allows SPI client drivers to request SPI host controller
for configuring device specific CS setup, hold and inactive timing
requirements.”…””}”(hjK
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M?hjH
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj-
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´MAhjT  h²hubeh}”(h]”h ]”h"]”h$]”h&]”uh1j)  hjC  h²hh³Nh´Nubeh}”(h]”Œspi-host-controller-methods”ah ]”h"]”Œspi host controller methods”ah$]”h&]”uh1hµhj©  h²hh³hÊh´Mubh¶)”}”(hhh]”(h»)”}”(hŒDeprecated Methods”h]”hŒDeprecated Methods”…””}”(hjv
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjs
  h²hh³hÊh´MDubj*  )”}”(hhh]”j/  )”}”(hXÐ  ``ctrl->transfer(struct spi_device *spi, struct spi_message *message)``
This must not sleep. Its responsibility is to arrange that the
transfer happens and its complete() callback is issued. The two
will normally happen later, after other transfers complete, and
if the controller is idle it will need to be kickstarted. This
method is not used on queued controllers and must be NULL if
transfer_one_message() and (un)prepare_transfer_hardware() are
implemented.

”h]”(j5  )”}”(hŒG``ctrl->transfer(struct spi_device *spi, struct spi_message *message)``”h]”jZ  )”}”(hj
  h]”hŒCctrl->transfer(struct spi_device *spi, struct spi_message *message)”…””}”(hj
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hj‹
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j4  h³hÊh´MNhj‡
  ubjE  )”}”(hhh]”hÌ)”}”(hX†  This must not sleep. Its responsibility is to arrange that the
transfer happens and its complete() callback is issued. The two
will normally happen later, after other transfers complete, and
if the controller is idle it will need to be kickstarted. This
method is not used on queued controllers and must be NULL if
transfer_one_message() and (un)prepare_transfer_hardware() are
implemented.”h]”hX†  This must not sleep. Its responsibility is to arrange that the
transfer happens and its complete() callback is issued. The two
will normally happen later, after other transfers complete, and
if the controller is idle it will need to be kickstarted. This
method is not used on queued controllers and must be NULL if
transfer_one_message() and (un)prepare_transfer_hardware() are
implemented.”…””}”(hj¥
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MGhj¢
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1jD  hj‡
  ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j.  h³hÊh´MNhj„
  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j)  hjs
  h²hh³hÊh´Nubeh}”(h]”Œdeprecated-methods”ah ]”h"]”Œdeprecated methods”ah$]”h&]”uh1hµhj©  h²hh³hÊh´MDubh¶)”}”(hhh]”(h»)”}”(hŒSPI Message Queue”h]”hŒSPI Message Queue”…””}”(hjÐ
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhjÍ
  h²hh³hÊh´MQubhÌ)”}”(hX_  If you are happy with the standard queueing mechanism provided by the
SPI subsystem, just implement the queued methods specified above. Using
the message queue has the upside of centralizing a lot of code and
providing pure process-context execution of methods. The message queue
can also be elevated to realtime priority on high-priority SPI traffic.”h]”hX_  If you are happy with the standard queueing mechanism provided by the
SPI subsystem, just implement the queued methods specified above. Using
the message queue has the upside of centralizing a lot of code and
providing pure process-context execution of methods. The message queue
can also be elevated to realtime priority on high-priority SPI traffic.”…””}”(hjÞ
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MShjÍ
  h²hubhÌ)”}”(hŒ¤Unless the queueing mechanism in the SPI subsystem is selected, the bulk
of the driver will be managing the I/O queue fed by the now deprecated
function transfer().”h]”hŒ¤Unless the queueing mechanism in the SPI subsystem is selected, the bulk
of the driver will be managing the I/O queue fed by the now deprecated
function transfer().”…””}”(hjì
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MYhjÍ
  h²hubhÌ)”}”(hŒŒThat queue could be purely conceptual.  For example, a driver used only
for low-frequency sensor access might be fine using synchronous PIO.”h]”hŒŒThat queue could be purely conceptual.  For example, a driver used only
for low-frequency sensor access might be fine using synchronous PIO.”…””}”(hjú
  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M]hjÍ
  h²hubhÌ)”}”(hXª  But the queue will probably be very real, using message->queue, PIO,
often DMA (especially if the root filesystem is in SPI flash), and
execution contexts like IRQ handlers, tasklets, or workqueues (such
as keventd).  Your driver can be as fancy, or as simple, as you need.
Such a transfer() method would normally just add the message to a
queue, and then start some asynchronous transfer engine (unless it's
already running).”h]”hX¬  But the queue will probably be very real, using message->queue, PIO,
often DMA (especially if the root filesystem is in SPI flash), and
execution contexts like IRQ handlers, tasklets, or workqueues (such
as keventd).  Your driver can be as fancy, or as simple, as you need.
Such a transfer() method would normally just add the message to a
queue, and then start some asynchronous transfer engine (unless itâ€™s
already running).”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M`hjÍ
  h²hubeh}”(h]”Œspi-message-queue”ah ]”h"]”Œspi message queue”ah$]”h&]”uh1hµhj©  h²hh³hÊh´MQubeh}”(h]”Œ'how-do-i-write-an-spi-controller-driver”ah ]”h"]”Œ*how do i write an "spi controller driver"?”ah$]”h&]”uh1hµhh·h²hh³hÊh´MÔubh¶)”}”(hhh]”(h»)”}”(hŒExtensions to the SPI protocol”h]”hŒExtensions to the SPI protocol”…””}”(hj)  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj&  h²hh³hÊh´MjubhÌ)”}”(hXS  The fact that SPI doesn't have a formal specification or standard permits chip
manufacturers to implement the SPI protocol in slightly different ways. In most
cases, SPI protocol implementations from different vendors are compatible among
each other. For example, in SPI mode 0 (CPOL=0, CPHA=0) the bus lines may behave
like the following:”h]”hXU  The fact that SPI doesnâ€™t have a formal specification or standard permits chip
manufacturers to implement the SPI protocol in slightly different ways. In most
cases, SPI protocol implementations from different vendors are compatible among
each other. For example, in SPI mode 0 (CPOL=0, CPHA=0) the bus lines may behave
like the following:”…””}”(hj7  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´Mkhj&  h²hubjÉ  )”}”(hXN  nCSx ___                                                                   ___
        \_________________________________________________________________/
        â€¢                                                                 â€¢
        â€¢                                                                 â€¢
SCLK         ___     ___     ___     ___     ___     ___     ___     ___
     _______/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \_____
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
MOSI XXX__________         _______                 _______         ________XXX
0xA5 XXX__/ 1     \_0_____/ 1     \_0_______0_____/ 1     \_0_____/ 1    \_XXX
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
MISO XXX__________         _______________________          _______        XXX
0xBA XXX__/     1 \_____0_/     1       1       1 \_____0__/    1  \____0__XXX”h]”hXN  nCSx ___                                                                   ___
        \_________________________________________________________________/
        â€¢                                                                 â€¢
        â€¢                                                                 â€¢
SCLK         ___     ___     ___     ___     ___     ___     ___     ___
     _______/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \_____
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
MOSI XXX__________         _______                 _______         ________XXX
0xA5 XXX__/ 1     \_0_____/ 1     \_0_______0_____/ 1     \_0_____/ 1    \_XXX
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
MISO XXX__________         _______________________          _______        XXX
0xBA XXX__/     1 \_____0_/     1       1       1 \_____0__/    1  \____0__XXX”…””}”hjE  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Mshj&  h²hubhÌ)”}”(hŒLegend::”h]”hŒLegend:”…””}”(hjS  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‚hj&  h²hubjÉ  )”}”(hŒ¸â€¢ marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.”h]”hŒ¸â€¢ marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.”…””}”hja  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´M„hj&  h²hubhÌ)”}”(hX  In some few cases, chips extend the SPI protocol by specifying line behaviors
that other SPI protocols don't (e.g. data line state for when CS is not
asserted). Those distinct SPI protocols, modes, and configurations are supported
by different SPI mode flags.”h]”hX  In some few cases, chips extend the SPI protocol by specifying line behaviors
that other SPI protocols donâ€™t (e.g. data line state for when CS is not
asserted). Those distinct SPI protocols, modes, and configurations are supported
by different SPI mode flags.”…””}”(hjo  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‰hj&  h²hubh¶)”}”(hhh]”(h»)”}”(hŒMOSI idle state configuration”h]”hŒMOSI idle state configuration”…””}”(hj€  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj}  h²hh³hÊh´MubhÌ)”}”(hX¹  Common SPI protocol implementations don't specify any state or behavior for the
MOSI line when the controller is not clocking out data. However, there do exist
peripherals that require specific MOSI line state when data is not being clocked
out. For example, if the peripheral expects the MOSI line to be high when the
controller is not clocking out data (``SPI_MOSI_IDLE_HIGH``), then a transfer in
SPI mode 0 would look like the following:”h]”(hXf  Common SPI protocol implementations donâ€™t specify any state or behavior for the
MOSI line when the controller is not clocking out data. However, there do exist
peripherals that require specific MOSI line state when data is not being clocked
out. For example, if the peripheral expects the MOSI line to be high when the
controller is not clocking out data (”…””}”(hjŽ  h²hh³Nh´NubjZ  )”}”(hŒ``SPI_MOSI_IDLE_HIGH``”h]”hŒSPI_MOSI_IDLE_HIGH”…””}”(hj–  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjŽ  ubhŒ?), then a transfer in
SPI mode 0 would look like the following:”…””}”(hjŽ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M‘hj}  h²hubjÉ  )”}”(hXK  nCSx ___                                                                   ___
        \_________________________________________________________________/
        â€¢                                                                 â€¢
        â€¢                                                                 â€¢
SCLK         ___     ___     ___     ___     ___     ___     ___     ___
     _______/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \_____
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
MOSI _____         _______         _______         _______________         ___
0x56      \_0_____/ 1     \_0_____/ 1     \_0_____/ 1       1     \_0_____/
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
MISO XXX__________         _______________________          _______        XXX
0xBA XXX__/     1 \_____0_/     1       1       1 \_____0__/    1  \____0__XXX”h]”hXK  nCSx ___                                                                   ___
        \_________________________________________________________________/
        â€¢                                                                 â€¢
        â€¢                                                                 â€¢
SCLK         ___     ___     ___     ___     ___     ___     ___     ___
     _______/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \_____
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
        â€¢   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ;   :   ; â€¢
MOSI _____         _______         _______         _______________         ___
0x56      \_0_____/ 1     \_0_____/ 1     \_0_____/ 1       1     \_0_____/
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
        â€¢       ;       ;       ;       ;       ;       ;       ;       ; â€¢
MISO XXX__________         _______________________          _______        XXX
0xBA XXX__/     1 \_____0_/     1       1       1 \_____0__/    1  \____0__XXX”…””}”hj®  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´Mšhj}  h²hubhÌ)”}”(hŒLegend::”h]”hŒLegend:”…””}”(hj¼  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M©hj}  h²hubjÉ  )”}”(hŒ¸â€¢ marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.”h]”hŒ¸â€¢ marks the start/end of transmission;
: marks when data is clocked into the peripheral;
; marks when data is clocked into the controller;
X marks when line states are not specified.”…””}”hjÊ  sbah}”(h]”h ]”h"]”h$]”h&]”jØ  jÙ  uh1jÈ  h³hÊh´M«hj}  h²hubhÌ)”}”(hŒÑIn this extension to the usual SPI protocol, the MOSI line state is specified to
be kept high when CS is asserted but the controller is not clocking out data to
the peripheral and also when CS is not asserted.”h]”hŒÑIn this extension to the usual SPI protocol, the MOSI line state is specified to
be kept high when CS is asserted but the controller is not clocking out data to
the peripheral and also when CS is not asserted.”…””}”(hjØ  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M°hj}  h²hubhÌ)”}”(hX§  Peripherals that require this extension must request it by setting the
``SPI_MOSI_IDLE_HIGH`` bit into the mode attribute of their ``struct
spi_device`` and call spi_setup(). Controllers that support this extension
should indicate it by setting ``SPI_MOSI_IDLE_HIGH`` in the mode_bits attribute
of their ``struct spi_controller``. The configuration to idle MOSI low is
analogous but uses the ``SPI_MOSI_IDLE_LOW`` mode bit.”h]”(hŒGPeripherals that require this extension must request it by setting the
”…””}”(hjæ  h²hh³Nh´NubjZ  )”}”(hŒ``SPI_MOSI_IDLE_HIGH``”h]”hŒSPI_MOSI_IDLE_HIGH”…””}”(hjî  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjæ  ubhŒ& bit into the mode attribute of their ”…””}”(hjæ  h²hh³Nh´NubjZ  )”}”(hŒ``struct
spi_device``”h]”hŒstruct
spi_device”…””}”(hj   h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjæ  ubhŒ] and call spi_setup(). Controllers that support this extension
should indicate it by setting ”…””}”(hjæ  h²hh³Nh´NubjZ  )”}”(hŒ``SPI_MOSI_IDLE_HIGH``”h]”hŒSPI_MOSI_IDLE_HIGH”…””}”(hj  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjæ  ubhŒ% in the mode_bits attribute
of their ”…””}”(hjæ  h²hh³Nh´NubjZ  )”}”(hŒ``struct spi_controller``”h]”hŒstruct spi_controller”…””}”(hj$  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjæ  ubhŒ?. The configuration to idle MOSI low is
analogous but uses the ”…””}”(hjæ  h²hh³Nh´NubjZ  )”}”(hŒ``SPI_MOSI_IDLE_LOW``”h]”hŒSPI_MOSI_IDLE_LOW”…””}”(hj6  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jY  hjæ  ubhŒ
 mode bit.”…””}”(hjæ  h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M´hj}  h²hubeh}”(h]”Œmosi-idle-state-configuration”ah ]”h"]”Œmosi idle state configuration”ah$]”h&]”uh1hµhj&  h²hh³hÊh´Mubeh}”(h]”Œextensions-to-the-spi-protocol”ah ]”h"]”Œextensions to the spi protocol”ah$]”h&]”uh1hµhh·h²hh³hÊh´Mjubh¶)”}”(hhh]”(h»)”}”(hŒ	THANKS TO”h]”hŒ	THANKS TO”…””}”(hja  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hºhj^  h²hh³hÊh´M½ubhÌ)”}”(hŒTContributors to Linux-SPI discussions include (in alphabetical order,
by last name):”h]”hŒTContributors to Linux-SPI discussions include (in alphabetical order,
by last name):”…””}”(hjo  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´M¾hj^  h²hubj+  )”}”(hhh]”(j0  )”}”(hŒ
Mark Brown”h]”hÌ)”}”(hj‚  h]”hŒ
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  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj}  h²hh³hÊh´Nubj0  )”}”(hŒAndrew Victor”h]”hÌ)”}”(hj#  h]”hŒAndrew Victor”…””}”(hj%  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÈhj!  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj}  h²hh³hÊh´Nubj0  )”}”(hŒLinus Walleij”h]”hÌ)”}”(hj:  h]”hŒLinus Walleij”…””}”(hj<  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÉhj8  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj}  h²hh³hÊh´Nubj0  )”}”(hŒVitaly Wool”h]”hÌ)”}”(hjQ  h]”hŒVitaly Wool”…””}”(hjS  h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hËh³hÊh´MÊhjO  ubah}”(h]”h ]”h"]”h$]”h&]”uh1j/  hj}  h²hh³hÊh´Nubeh}”(h]”h ]”h"]”h$]”h&]”j¯  j°  uh1j*  h³hÊh´MÁhj^  h²hubeh}”(h]”Œ	thanks-to”ah ]”h"]”Œ	thanks to”ah$]”h&]”uh1hµhh·h²hh³hÊh´M½ubeh}”(h]”Œ$overview-of-linux-kernel-spi-support”ah ]”h"]”Œ$overview of linux kernel spi support”ah$]”h&]”uh1hµhhh²hh³hÊh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÊuh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hºNŒ	generator”NŒ	datestamp”NŒsource_link”NŒ
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