€•vŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ+/translations/zh_CN/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/zh_TW/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/it_IT/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/ja_JP/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/ko_KR/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ+/translations/sp_SP/spi/multiple-data-lanes”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ$SPI devices with multiple data lanes”h]”hŒ$SPI devices with multiple data lanes”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒE/var/lib/git/docbuild/linux/Documentation/spi/multiple-data-lanes.rst”h KubhŒ paragraph”“”)”}”(hŒùSome specialized SPI controllers and peripherals support multiple data lanes that allow reading more than one word at a time in parallel. This is different from dual/quad/octal SPI where multiple bits of a single word are transferred simultaneously.”h]”hŒùSome specialized SPI controllers and peripherals support multiple data lanes that allow reading more than one word at a time in parallel. This is different from dual/quad/octal SPI where multiple bits of a single word are transferred simultaneously.”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒŸFor example, controllers that support parallel flash memories have this feature as do some simultaneous-sampling ADCs where each channel has its own data lane.”h]”hŒŸFor example, controllers that support parallel flash memories have this feature as do some simultaneous-sampling ADCs where each channel has its own data lane.”…””}”(hhÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒDescribing the wiring”h]”hŒDescribing the wiring”…””}”(hhØhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hhÕhžhhŸh¶h Kubh¸)”}”(hXBThe ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the devicetree are used to describe how many data lanes are connected between the controller and how wide each lane is. The number of items in the array indicates how many lanes there are, and the value of each item indicates how many bits wide that lane is.”h]”(hŒThe ”…””}”(hhæhžhhŸNh NubhŒliteral”“”)”}”(hŒ``spi-tx-bus-width``”h]”hŒspi-tx-bus-width”…””}”(hhðhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhæubhŒ and ”…””}”(hhæhžhhŸNh Nubhï)”}”(hŒ``spi-rx-bus-width``”h]”hŒspi-rx-bus-width”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhhæubhX properties in the devicetree are used to describe how many data lanes are connected between the controller and how wide each lane is. The number of items in the array indicates how many lanes there are, and the value of each item indicates how many bits wide that lane is.”…””}”(hhæhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubh¸)”}”(hŒ`For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be wired up like this::”h]”hŒ_For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be wired up like this:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÕhžhubhŒ literal_block”“”)”}”(hXr+--------------+ +----------+ | SPI | | AD4630 | | Controller | | ADC | | | | | | CS0 |--->| CS | | SCK |--->| SCK | | SDO |--->| SDI | | | | | | SDIA0 |<---| SDOA0 | | SDIA1 |<---| SDOA1 | | SDIA2 |<---| SDOA2 | | SDIA3 |<---| SDOA3 | | | | | | SDIB0 |<---| SDOB0 | | SDIB1 |<---| SDOB1 | | SDIB2 |<---| SDOB2 | | SDIB3 |<---| SDOB3 | | | | | +--------------+ +----------+”h]”hXr+--------------+ +----------+ | SPI | | AD4630 | | Controller | | ADC | | | | | | CS0 |--->| CS | | SCK |--->| SCK | | SDO |--->| SDI | | | | | | SDIA0 |<---| SDOA0 | | SDIA1 |<---| SDOA1 | | SDIA2 |<---| SDOA2 | | SDIA3 |<---| SDOA3 | | | | | | SDIB0 |<---| SDOB0 | | SDIB1 |<---| SDOB1 | | SDIB2 |<---| SDOB2 | | SDIB3 |<---| SDOB3 | | | | | +--------------+ +----------+”…””}”hj*sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1j(hŸh¶h KhhÕhžhubh¸)”}”(hŒ+It is described in a devicetree like this::”h]”hŒ*It is described in a devicetree like this:”…””}”(hj:hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K.hhÕhžhubj))”}”(hŒÛspi { compatible = "my,spi-controller"; ... adc@0 { compatible = "adi,ad4630"; reg = <0>; ... spi-rx-bus-width = <4>, <4>; /* 2 lanes of 4 bits each */ ... }; };”h]”hŒÛspi { compatible = "my,spi-controller"; ... adc@0 { compatible = "adi,ad4630"; reg = <0>; ... spi-rx-bus-width = <4>, <4>; /* 2 lanes of 4 bits each */ ... }; };”…””}”hjHsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h K0hhÕhžhubh¸)”}”(hŒõIn most cases, lanes will be wired up symmetrically (A to A, B to B, etc). If this isn't the case, extra ``spi-rx-lane-map`` and ``spi-tx-lane-map`` properties are needed to provide a mapping between controller lanes and the physical lane wires.”h]”(hŒkIn most cases, lanes will be wired up symmetrically (A to A, B to B, etc). If this isn’t the case, extra ”…””}”(hjVhžhhŸNh Nubhï)”}”(hŒ``spi-rx-lane-map``”h]”hŒspi-rx-lane-map”…””}”(hj^hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjVubhŒ and ”…””}”(hjVhžhhŸNh Nubhï)”}”(hŒ``spi-tx-lane-map``”h]”hŒspi-tx-lane-map”…””}”(hjphžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjVubhŒa properties are needed to provide a mapping between controller lanes and the physical lane wires.”…””}”(hjVhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K>hhÕhžhubh¸)”}”(hŒnHere is an example where a multi-lane SPI controller has each lane wired to separate single-lane peripherals::”h]”hŒmHere is an example where a multi-lane SPI controller has each lane wired to separate single-lane peripherals:”…””}”(hjˆhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KChhÕhžhubj))”}”(hXƒ+--------------+ +----------+ | SPI | | Thing 1 | | Controller | | | | | | | | CS0 |--->| CS | | SDO0 |--->| SDI | | SDI0 |<---| SDO | | SCLK0 |--->| SCLK | | | | | | | +----------+ | | | | +----------+ | | | Thing 2 | | | | | | CS1 |--->| CS | | SDO1 |--->| SDI | | SDI1 |<---| SDO | | SCLK1 |--->| SCLK | | | | | +--------------+ +----------+”h]”hXƒ+--------------+ +----------+ | SPI | | Thing 1 | | Controller | | | | | | | | CS0 |--->| CS | | SDO0 |--->| SDI | | SDI0 |<---| SDO | | SCLK0 |--->| SCLK | | | | | | | +----------+ | | | | +----------+ | | | Thing 2 | | | | | | CS1 |--->| CS | | SDO1 |--->| SDI | | SDI1 |<---| SDO | | SCLK1 |--->| SCLK | | | | | +--------------+ +----------+”…””}”hj–sbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h KFhhÕhžhubh¸)”}”(hŒ-This is described in a devicetree like this::”h]”hŒ,This is described in a devicetree like this:”…””}”(hj¤hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K[hhÕhžhubj))”}”(hX›spi { compatible = "my,spi-controller"; ... thing1@0 { compatible = "my,thing1"; reg = <0>; ... }; thing2@1 { compatible = "my,thing2"; reg = <1>; ... spi-tx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for tx wire */ spi-rx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for rx wire */ ... }; };”h]”hX›spi { compatible = "my,spi-controller"; ... thing1@0 { compatible = "my,thing1"; reg = <0>; ... }; thing2@1 { compatible = "my,thing2"; reg = <1>; ... spi-tx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for tx wire */ spi-rx-lane-map = <1>; /* lane 0 is not used, lane 1 is used for rx wire */ ... }; };”…””}”hj²sbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h K]hhÕhžhubh¸)”}”(hŒ¹The default values of ``spi-rx-bus-width`` and ``spi-tx-bus-width`` are ``<1>``, so these properties can still be omitted even when ``spi-rx-lane-map`` and ``spi-tx-lane-map`` are used.”h]”(hŒThe default values of ”…””}”(hjÀhžhhŸNh Nubhï)”}”(hŒ``spi-rx-bus-width``”h]”hŒspi-rx-bus-width”…””}”(hjÈhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjÀubhŒ and ”…””}”(hjÀhžhhŸNh Nubhï)”}”(hŒ``spi-tx-bus-width``”h]”hŒspi-tx-bus-width”…””}”(hjÚhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjÀubhŒ are ”…””}”(hjÀhžhhŸNh Nubhï)”}”(hŒ``<1>``”h]”hŒ<1>”…””}”(hjìhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjÀubhŒ5, so these properties can still be omitted even when ”…””}”(hjÀhžhhŸNh Nubhï)”}”(hŒ``spi-rx-lane-map``”h]”hŒspi-rx-lane-map”…””}”(hjþhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjÀubhŒ and ”…””}”(hjÀhžhhŸNh Nubhï)”}”(hŒ``spi-tx-lane-map``”h]”hŒspi-tx-lane-map”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hîhjÀubhŒ are used.”…””}”(hjÀhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KshhÕhžhubeh}”(h]”Œdescribing-the-wiring”ah ]”h"]”Œdescribing the wiring”ah$]”h&]”uh1h¡hh£hžhhŸh¶h Kubh¢)”}”(hhh]”(h§)”}”(hŒUsage in a peripheral driver”h]”hŒUsage in a peripheral driver”…””}”(hj3hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj0hžhhŸh¶h Kyubh¸)”}”(hX4These types of SPI controllers generally do not support arbitrary use of the multiple lanes. Instead, they operate in one of a few defined modes. Peripheral drivers should set the :c:type:`struct spi_transfer.multi_lane_mode ` field to indicate which mode they want to use for a given transfer.”h]”(hŒ´These types of SPI controllers generally do not support arbitrary use of the multiple lanes. Instead, they operate in one of a few defined modes. Peripheral drivers should set the ”…””}”(hjAhžhhŸNh Nubh)”}”(hŒ<:c:type:`struct spi_transfer.multi_lane_mode `”h]”hï)”}”(hjKh]”hŒ#struct spi_transfer.multi_lane_mode”…””}”(hjMhžhhŸNh Nubah}”(h]”h ]”(Œxref”Œc”Œc-type”eh"]”h$]”h&]”uh1hîhjIubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”Œspi/multiple-data-lanes”Œ refdomain”jXŒreftype”Œtype”Œ refexplicit”ˆŒrefwarn”‰Œ reftarget”Œ spi_transfer”uh1hhŸh¶h K{hjAubhŒD field to indicate which mode they want to use for a given transfer.”…””}”(hjAhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K{hj0hžhubh¸)”}”(hŒ@The possible values for this field have the following semantics:”h]”hŒ@The possible values for this field have the following semantics:”…””}”(hjvhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K€hj0hžhubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hX«:c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lanes are ignored. This means that it is operating just like a conventional SPI peripheral. This is the default, so it does not need to be explicitly set. Example:: tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, }; spi_sync_transfer(spi, &xfer, 1); Assuming the controller is sending the MSB first, the sequence of bits sent over the tx wire would be (right-most bit is sent first):: controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 ”h]”hŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hX:c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lanes are ignored. This means that it is operating just like a conventional SPI peripheral. This is the default, so it does not need to be explicitly set. Example:: tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, }; spi_sync_transfer(spi, &xfer, 1); Assuming the controller is sending the MSB first, the sequence of bits sent over the tx wire would be (right-most bit is sent first):: controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 ”h]”(hŒterm”“”)”}”(hŒN:c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lanes are”h]”(h)”}”(hŒ$:c:macro:`SPI_MULTI_BUS_MODE_SINGLE`”h]”hï)”}”(hj¢h]”hŒSPI_MULTI_BUS_MODE_SINGLE”…””}”(hj¤hžhhŸNh Nubah}”(h]”h ]”(jWjXŒc-macro”eh"]”h$]”h&]”uh1hîhj ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jdŒ refdomain”jXŒreftype”Œmacro”Œ refexplicit”‰Œrefwarn”‰jjŒSPI_MULTI_BUS_MODE_SINGLE”uh1hhŸh¶h K–hjœubhŒ*: Only use the first lane. Other lanes are”…””}”(hjœhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jšhŸh¶h K–hj–ubhŒ definition”“”)”}”(hhh]”(h¸)”}”(hŒignored. This means that it is operating just like a conventional SPI peripheral. This is the default, so it does not need to be explicitly set.”h]”hŒignored. This means that it is operating just like a conventional SPI peripheral. This is the default, so it does not need to be explicitly set.”…””}”(hjÎhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KƒhjËubh¸)”}”(hŒ Example::”h]”hŒExample:”…””}”(hjÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K†hjËubj))”}”(hŒytx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, }; spi_sync_transfer(spi, &xfer, 1);”h]”hŒytx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, }; spi_sync_transfer(spi, &xfer, 1);”…””}”hjêsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h KˆhjËubh¸)”}”(hŒ†Assuming the controller is sending the MSB first, the sequence of bits sent over the tx wire would be (right-most bit is sent first)::”h]”hŒ…Assuming the controller is sending the MSB first, the sequence of bits sent over the tx wire would be (right-most bit is sent first):”…””}”(hjøhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K‘hjËubj))”}”(hŒ{controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0”h]”hŒ{controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h K”hjËubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÉhj–ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j”hŸh¶h K–hj‘ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj‹ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‰hj†hžhhŸNh NubjŠ)”}”(hXg:c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all of the lanes at the same time. This only makes sense for writes and not for reads. Example:: tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, .multi_lane_mode = SPI_MULTI_BUS_MODE_MIRROR, }; spi_sync_transfer(spi, &xfer, 1); The data is mirrored on each tx wire:: controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 SDO 1 0-0-0-1-0-0-0-1 SDI 1 ”h]”j)”}”(hhh]”j•)”}”(hXI:c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all of the lanes at the same time. This only makes sense for writes and not for reads. Example:: tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, .multi_lane_mode = SPI_MULTI_BUS_MODE_MIRROR, }; spi_sync_transfer(spi, &xfer, 1); The data is mirrored on each tx wire:: controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 SDO 1 0-0-0-1-0-0-0-1 SDI 1 ”h]”(j›)”}”(hŒM:c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all of the”h]”(h)”}”(hŒ$:c:macro:`SPI_MULTI_BUS_MODE_MIRROR`”h]”hï)”}”(hj=h]”hŒSPI_MULTI_BUS_MODE_MIRROR”…””}”(hj?hžhhŸNh Nubah}”(h]”h ]”(jWjXŒc-macro”eh"]”h$]”h&]”uh1hîhj;ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jdŒ refdomain”jXŒreftype”Œmacro”Œ refexplicit”‰Œrefwarn”‰jjŒSPI_MULTI_BUS_MODE_MIRROR”uh1hhŸh¶h K­hj7ubhŒ): Send a single data word over all of the”…””}”(hj7hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jšhŸh¶h K­hj3ubjÊ)”}”(hhh]”(h¸)”}”(hŒKlanes at the same time. This only makes sense for writes and not for reads.”h]”hŒKlanes at the same time. This only makes sense for writes and not for reads.”…””}”(hjghžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K™hjdubh¸)”}”(hŒ Example::”h]”hŒExample:”…””}”(hjuhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kœhjdubj))”}”(hŒ«tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, .multi_lane_mode = SPI_MULTI_BUS_MODE_MIRROR, }; spi_sync_transfer(spi, &xfer, 1);”h]”hŒ«tx_buf[0] = 0x88; struct spi_transfer xfer = { .tx_buf = tx_buf, .len = 1, .multi_lane_mode = SPI_MULTI_BUS_MODE_MIRROR, }; spi_sync_transfer(spi, &xfer, 1);”…””}”hjƒsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h Kžhjdubh¸)”}”(hŒ&The data is mirrored on each tx wire::”h]”hŒ%The data is mirrored on each tx wire:”…””}”(hj‘hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K¨hjdubj))”}”(hŒ¡controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 SDO 1 0-0-0-1-0-0-0-1 SDI 1”h]”hŒ¡controller > data bits > peripheral ---------- ---------------- ---------- SDO 0 0-0-0-1-0-0-0-1 SDI 0 SDO 1 0-0-0-1-0-0-0-1 SDI 1”…””}”hjŸsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h Kªhjdubeh}”(h]”h ]”h"]”h$]”h&]”uh1jÉhj3ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j”hŸh¶h K­hj0ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj,ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‰hj†hžhhŸNh NubjŠ)”}”(hX6:c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data words at the same time, one on each lane. This means that the buffer needs to be sized to hold data for all lanes. Data is interleaved in the buffer, with the first word corresponding to lane 0, the second to lane 1, and so on. Once the last lane is used, the next word in the buffer corresponds to lane 0 again. Accordingly, the buffer size must be a multiple of the number of lanes. This mode works for both reads and writes. Example:: struct spi_transfer xfer = { .rx_buf = rx_buf, .len = 2, .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE, }; spi_sync_transfer(spi, &xfer, 1); Each rx wire has a different data word sent simultaneously:: controller < data bits < peripheral ---------- ---------------- ---------- SDI 0 0-0-0-1-0-0-0-1 SDO 0 SDI 1 1-0-0-0-1-0-0-0 SDO 1 After the transfer, ``rx_buf[0] == 0x11`` (word from SDO 0) and ``rx_buf[1] == 0x88`` (word from SDO 1). ”h]”j)”}”(hhh]”j•)”}”(hX:c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data words at the same time, one on each lane. This means that the buffer needs to be sized to hold data for all lanes. Data is interleaved in the buffer, with the first word corresponding to lane 0, the second to lane 1, and so on. Once the last lane is used, the next word in the buffer corresponds to lane 0 again. Accordingly, the buffer size must be a multiple of the number of lanes. This mode works for both reads and writes. Example:: struct spi_transfer xfer = { .rx_buf = rx_buf, .len = 2, .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE, }; spi_sync_transfer(spi, &xfer, 1); Each rx wire has a different data word sent simultaneously:: controller < data bits < peripheral ---------- ---------------- ---------- SDI 0 0-0-0-1-0-0-0-1 SDO 0 SDI 1 1-0-0-0-1-0-0-0 SDO 1 After the transfer, ``rx_buf[0] == 0x11`` (word from SDO 0) and ``rx_buf[1] == 0x88`` (word from SDO 1). ”h]”(j›)”}”(hŒN:c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data words”h]”(h)”}”(hŒ$:c:macro:`SPI_MULTI_BUS_MODE_STRIPE`”h]”hï)”}”(hjÖh]”hŒSPI_MULTI_BUS_MODE_STRIPE”…””}”(hjØhžhhŸNh Nubah}”(h]”h ]”(jWjXŒc-macro”eh"]”h$]”h&]”uh1hîhjÔubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jdŒ refdomain”jXŒreftype”Œmacro”Œ refexplicit”‰Œrefwarn”‰jjŒSPI_MULTI_BUS_MODE_STRIPE”uh1hhŸh¶h KÊhjÐubhŒ*: Send or receive two different data words”…””}”(hjÐhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jšhŸh¶h KÊhjÌubjÊ)”}”(hhh]”(h¸)”}”(hX¥at the same time, one on each lane. This means that the buffer needs to be sized to hold data for all lanes. Data is interleaved in the buffer, with the first word corresponding to lane 0, the second to lane 1, and so on. Once the last lane is used, the next word in the buffer corresponds to lane 0 again. Accordingly, the buffer size must be a multiple of the number of lanes. This mode works for both reads and writes.”h]”hX¥at the same time, one on each lane. This means that the buffer needs to be sized to hold data for all lanes. Data is interleaved in the buffer, with the first word corresponding to lane 0, the second to lane 1, and so on. Once the last lane is used, the next word in the buffer corresponds to lane 0 again. Accordingly, the buffer size must be a multiple of the number of lanes. This mode works for both reads and writes.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K°hjýubh¸)”}”(hŒ Example::”h]”hŒExample:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K·hjýubj))”}”(hŒ˜struct spi_transfer xfer = { .rx_buf = rx_buf, .len = 2, .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE, }; spi_sync_transfer(spi, &xfer, 1);”h]”hŒ˜struct spi_transfer xfer = { .rx_buf = rx_buf, .len = 2, .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE, }; spi_sync_transfer(spi, &xfer, 1);”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”j8j9uh1j(hŸh¶h K¹hjýubh¸)”}”(hŒ` to a value greater than 1.”h]”(hŒCTo support multiple data lanes, SPI controller drivers need to set ”…””}”(hj±hžhhŸNh Nubh)”}”(hŒ?:c:type:`struct spi_controller.num_data_lanes `”h]”hï)”}”(hj»h]”hŒ$struct spi_controller.num_data_lanes”…””}”(hj½hžhhŸNh Nubah}”(h]”h ]”(jWjXŒc-type”eh"]”h$]”h&]”uh1hîhj¹ubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jdŒ refdomain”jXŒreftype”Œtype”Œ refexplicit”ˆŒrefwarn”‰jjŒspi_controller”uh1hhŸh¶h KÐhj±ubhŒ to a value greater than 1.”…””}”(hj±hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÐhj hžhubh¸)”}”(hŒöThen the part of the driver that handles SPI transfers needs to check the :c:type:`struct spi_transfer.multi_lane_mode ` field and implement the appropriate behavior for each supported mode and return an error for unsupported modes.”h]”(hŒJThen the part of the driver that handles SPI transfers needs to check the ”…””}”(hjâhžhhŸNh Nubh)”}”(hŒ<:c:type:`struct spi_transfer.multi_lane_mode `”h]”hï)”}”(hjìh]”hŒ#struct spi_transfer.multi_lane_mode”…””}”(hjîhžhhŸNh Nubah}”(h]”h ]”(jWjXŒc-type”eh"]”h$]”h&]”uh1hîhjêubah}”(h]”h ]”h"]”h$]”h&]”Œrefdoc”jdŒ refdomain”jXŒreftype”Œtype”Œ refexplicit”ˆŒrefwarn”‰jjŒ spi_transfer”uh1hhŸh¶h KÔhjâubhŒp field and implement the appropriate behavior for each supported mode and return an error for unsupported modes.”…””}”(hjâhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÔhj hžhubh¸)”}”(hŒ)The core SPI code should handle the rest.”h]”hŒ)The core SPI code should handle the rest.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KÙhj hžhubeh}”(h]”Œspi-controller-driver-support”ah ]”h"]”Œspi controller driver support”ah$]”h&]”uh1h¡hh£hžhhŸh¶h KÎubeh}”(h]”Œ$spi-devices-with-multiple-data-lanes”ah ]”h"]”Œ$spi devices with multiple data lanes”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jTŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(j.j+j-j*jjšj&j#uŒ nametypes”}”(j.‰j-‰j‰j&‰uh}”(j+h£j*hÕjšj0j#j uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.