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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h0HDAudio multi-link extensions on Intel platformsh]h0HDAudio multi-link extensions on Intel platforms}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjchhhKubh field_body)}(h|copy| 2023 Intel Corporation h]h paragraph)}(h|copy| 2023 Intel Corporationh](h©}(hj~hhhNhNubh 2023 Intel Corporation}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhKhjxubah}(h]h ]h"]h$]h&]uh1jvhjcubeh}(h]h ]h"]h$]h&]uh1jahhhKhj^hhubah}(h]h ]h"]h$]h&]uh1j\hjIhhhhhKubj})}(hThis file documents the 'multi-link structure' introduced in 2015 with the Skylake processor and recently extended in newer Intel platformsh]hThis file documents the ‘multi-link structure’ introduced in 2015 with the Skylake processor and recently extended in newer Intel platforms}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK hjIhhubjH)}(hhh](jM)}(h8HDaudio existing link mapping (2015 addition in SkyLake)h]h8HDaudio existing link mapping (2015 addition in SkyLake)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj})}(hqExternal HDAudio codecs are handled with link #0, while iDISP codec for HDMI/DisplayPort is handled with link #1.h]hqExternal HDAudio codecs are handled with link #0, while iDISP codec for HDMI/DisplayPort is handled with link #1.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubj})}(hThe only change to the 2015 definitions is the declaration of the LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a backwards-compatible change.h]hThe only change to the 2015 definitions is the declaration of the LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a backwards-compatible change.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubj})}(hLCTL.SPA and LCTL.CPA are automatically set when exiting reset. They are only used in existing drivers when the SCF value needs to be corrected.h]hLCTL.SPA and LCTL.CPA are automatically set when exiting reset. They are only used in existing drivers when the SCF value needs to be corrected.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubjH)}(hhh](jM)}(h"Basic structure for HDaudio codecsh]h"Basic structure for HDaudio codecs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubh literal_block)}(hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=0 | +---------------+ | S192 | +---------------+ | S96 | +---------------+ | S48 | +---------------+ | S24 | +---------------+ | S12 | +---------------+ | S6 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | SCF | +---------------+ 0x8 +---------------+ LOSIDV | L1OSIVD15 | +---------------+ | L1OSIDV.. | +---------------+ | L1OSIDV1 | +---------------+ 0xC +---------------+ LSDIID | SDIID14 | +---------------+ | SDIID... | +---------------+ | SDIID0 | +---------------+h]hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=0 | +---------------+ | S192 | +---------------+ | S96 | +---------------+ | S48 | +---------------+ | S24 | +---------------+ | S12 | +---------------+ | S6 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | SCF | +---------------+ 0x8 +---------------+ LOSIDV | L1OSIVD15 | +---------------+ | L1OSIDV.. | +---------------+ | L1OSIDV1 | +---------------+ 0xC +---------------+ LSDIID | SDIID14 | +---------------+ | SDIID... | +---------------+ | SDIID0 | +---------------+}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK hjhhubeh}(h]"basic-structure-for-hdaudio-codecsah ]h"]"basic structure for hdaudio codecsah$]h&]uh1jGhjhhhhhKubeh}(h]6hdaudio-existing-link-mapping-2015-addition-in-skylakeah ]h"]8hdaudio existing link mapping (2015 addition in skylake)ah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(h'SoundWire HDaudio extended link mappingh]h'SoundWire HDaudio extended link mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKQubj})}(hGA SoundWire extended link is identified when LCAP.ALT=1 and LEPTR.ID=0.h]hGA SoundWire extended link is identified when LCAP.ALT=1 and LEPTR.ID=0.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKShjhhubj})}(h.DMA control uses the existing LOSIDV register.h]h.DMA control uses the existing LOSIDV register.}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKVhjhhubj})}(heChanges include additional descriptions for enumeration that were not present in earlier generations.h]heChanges include additional descriptions for enumeration that were not present in earlier generations.}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKXhjhhubh bullet_list)}(hhh](h list_item)}(hImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNCh]j})}(hj`h]hImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK[hj^ubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubj])}(h/number of sublinks (manager IP) in LCAP.LSCOUNTh]j})}(hjwh]h/number of sublinks (manager IP) in LCAP.LSCOUNT}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK\hjuubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubj])}(h1power management moved from SHIM to LCTL.SPA bitsh]j})}(hjh]h1power management moved from SHIM to LCTL.SPA bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK]hjubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubj])}(hPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLENh]j})}(hjh]hPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK^hjubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubj])}(h*mapping of SoundWire codecs to SDI ID bitsh]j})}(hjh]h*mapping of SoundWire codecs to SDI ID bits}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK_hjubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubj])}(hmove of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000. h]j})}(hmove of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000.h]hmove of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK`hjubah}(h]h ]h"]h$]h&]uh1j\hjYhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jWhhhK[hjhhubjH)}(hhh](jM)}(h8Extended structure for SoundWire (assuming 4 Manager IP)h]h8Extended structure for SoundWire (assuming 4 Manager IP)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKeubj)}(hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | LSS | +---------------+ | SLCOUNT=4 |-----------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ for each sublink x | INTEN | | +---------------+ | | OFLEN | | +---------------+ | | 0x8 +---------------+ LOSIDV | | L1OSIVD15 | | +---------------+ | | L1OSIDV.. | | +---------------+ | | L1OSIDV1 | +---+----------------------------------------------------------+ +---------------+ | | v | 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 | | SDIID14 | | | SoundWire SHIM | | +---------------+ | | generic | | | SDIID... | | +-----------------+ 0x00030100 | +---------------+ | | SoundWire IP | | | SDIID0 | | +-----------------+ 0x00036000 | +---------------+ | | SoundWire SHIM | | | | vendor-specific | | 0x1C +---------------+ LSYNC | +-----------------+ | | CMDSYNC | | v +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x | SYNCGO | | | SoundWire SHIM | +---------------+ | | generic | | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x +---------------+ | | SoundWire IP | | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x +---------------+ | | SoundWire SHIM | | | vendor-specific | 0x20 +---------------+ LEPTR | +-----------------+ | ID = 0 | | +---------------+ | | VER | | +---------------+ | | PTR |------------+ +---------------+h]hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | LSS | +---------------+ | SLCOUNT=4 |-----------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ for each sublink x | INTEN | | +---------------+ | | OFLEN | | +---------------+ | | 0x8 +---------------+ LOSIDV | | L1OSIVD15 | | +---------------+ | | L1OSIDV.. | | +---------------+ | | L1OSIDV1 | +---+----------------------------------------------------------+ +---------------+ | | v | 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 | | SDIID14 | | | SoundWire SHIM | | +---------------+ | | generic | | | SDIID... | | +-----------------+ 0x00030100 | +---------------+ | | SoundWire IP | | | SDIID0 | | +-----------------+ 0x00036000 | +---------------+ | | SoundWire SHIM | | | | vendor-specific | | 0x1C +---------------+ LSYNC | +-----------------+ | | CMDSYNC | | v +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x | SYNCGO | | | SoundWire SHIM | +---------------+ | | generic | | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x +---------------+ | | SoundWire IP | | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x +---------------+ | | SoundWire SHIM | | | vendor-specific | 0x20 +---------------+ LEPTR | +-----------------+ | ID = 0 | | +---------------+ | | VER | | +---------------+ | | PTR |------------+ +---------------+}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKihjhhubeh}(h]6extended-structure-for-soundwire-assuming-4-manager-ipah ]h"]8extended structure for soundwire (assuming 4 manager ip)ah$]h&]uh1jGhjhhhhhKeubeh}(h]'soundwire-hdaudio-extended-link-mappingah ]h"]'soundwire hdaudio extended link mappingah$]h&]uh1jGhjIhhhhhKQubjH)}(hhh](jM)}(h"DMIC HDaudio extended link mappingh]h"DMIC HDaudio extended link mapping}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(hMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC1 are set.h]hMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC1 are set.}(hj1hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(h-DMA control uses the existing LOSIDV registerh]h-DMA control uses the existing LOSIDV register}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(heChanges include additional descriptions for enumeration that were not present in earlier generations.h]heChanges include additional descriptions for enumeration that were not present in earlier generations.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubjX)}(hhh](j])}(hImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNCh]j})}(hj`h]hImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj^ubah}(h]h ]h"]h$]h&]uh1j\hj[hhhhhNubj])}(h#power management with LCTL.SPA bitsh]j})}(hjwh]h#power management with LCTL.SPA bits}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjuubah}(h]h ]h"]h$]h&]uh1j\hj[hhhhhNubj])}(hQhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN h]j})}(hPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLENh]hPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubah}(h]h ]h"]h$]h&]uh1j\hj[hhhhhNubj])}(hmove of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000. h]j})}(hmove of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000.h]hmove of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubah}(h]h ]h"]h$]h&]uh1j\hj[hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jWhhhKhj hhubjH)}(hhh](jM)}(hExtended structure for DMICh]hExtended structure for DMIC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj)}(hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=1 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | INTEN | +---------------+ | OFLEN | +---------------+ +---> 0x10000 +-----------------+ 0x00010000 | | DMIC SHIM | 0x8 +---------------+ LOSIDV | | generic | | L1OSIVD15 | | +-----------------+ 0x00010100 +---------------+ | | DMIC IP | | L1OSIDV.. | | +-----------------+ 0x00016000 +---------------+ | | DMIC SHIM | | L1OSIDV1 | | | vendor-specific | +---------------+ | +-----------------+ | 0x20 +---------------+ LEPTR | | ID = 0xC1 | | +---------------+ | | VER | | +---------------+ | | PTR |-----------+ +---------------+h]hX+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=1 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | INTEN | +---------------+ | OFLEN | +---------------+ +---> 0x10000 +-----------------+ 0x00010000 | | DMIC SHIM | 0x8 +---------------+ LOSIDV | | generic | | L1OSIVD15 | | +-----------------+ 0x00010100 +---------------+ | | DMIC IP | | L1OSIDV.. | | +-----------------+ 0x00016000 +---------------+ | | DMIC SHIM | | L1OSIDV1 | | | vendor-specific | +---------------+ | +-----------------+ | 0x20 +---------------+ LEPTR | | ID = 0xC1 | | +---------------+ | | VER | | +---------------+ | | PTR |-----------+ +---------------+}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubeh}(h]extended-structure-for-dmicah ]h"]extended structure for dmicah$]h&]uh1jGhj hhhhhKubeh}(h]"dmic-hdaudio-extended-link-mappingah ]h"]"dmic hdaudio extended link mappingah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(h!SSP HDaudio extended link mappingh]h!SSP HDaudio extended link mapping}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhKubj})}(hMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC0 are set.h]hMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC0 are set.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubj})}(h-DMA control uses the existing LOSIDV registerh]h-DMA control uses the existing LOSIDV register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubj})}(hXChanges include additional descriptions for enumeration and control that were not present in earlier generations: - number of sublinks (SSP IP instances) in LCAP.LSCOUNT - power management moved from SHIM to LCTL.SPA bits - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN - move of SHIM and SSP IP registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x28000.h]hXChanges include additional descriptions for enumeration and control that were not present in earlier generations: - number of sublinks (SSP IP instances) in LCAP.LSCOUNT - power management moved from SHIM to LCTL.SPA bits - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN - move of SHIM and SSP IP registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x28000.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubjH)}(hhh](jM)}(h;Extended structure for SSP (assuming 3 instances of the IP)h]h;Extended structure for SSP (assuming 3 instances of the IP)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj,hhhhhMubj)}(hX7+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=3 |-------------------------for each sublink x -------------------------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ | | INTEN | | +---------------+ | | OFLEN | | +---------------+ +---> 0x28000 +-----------------+ 0x00028000 | | | SSP SHIM | | 0x8 +---------------+ LOSIDV | | generic | | | L1OSIVD15 | | +-----------------+ 0x00028100 | +---------------+ | | SSP IP | | | L1OSIDV.. | | +-----------------+ 0x00028C00 | +---------------+ | | SSP SHIM | | | L1OSIDV1 | | | vendor-specific | | +---------------+ | +-----------------+ | | v 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x | ID = 0xC0 | | | SSP SHIM | +---------------+ | | generic | | VER | | +-----------------+ 0x00028100 + 0x1000 * x +---------------+ | | SSP IP | | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x +---------------+ | SSP SHIM | | vendor-specific | +-----------------+h]hX7+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=3 |-------------------------for each sublink x -------------------------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ | | INTEN | | +---------------+ | | OFLEN | | +---------------+ +---> 0x28000 +-----------------+ 0x00028000 | | | SSP SHIM | | 0x8 +---------------+ LOSIDV | | generic | | | L1OSIVD15 | | +-----------------+ 0x00028100 | +---------------+ | | SSP IP | | | L1OSIDV.. | | +-----------------+ 0x00028C00 | +---------------+ | | SSP SHIM | | | L1OSIDV1 | | | vendor-specific | | +---------------+ | +-----------------+ | | v 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x | ID = 0xC0 | | | SSP SHIM | +---------------+ | | generic | | VER | | +-----------------+ 0x00028100 + 0x1000 * x +---------------+ | | SSP IP | | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x +---------------+ | SSP SHIM | | vendor-specific | +-----------------+}hj=sbah}(h]h ]h"]h$]h&]hhuh1jhhhM hj,hhubeh}(h]9extended-structure-for-ssp-assuming-3-instances-of-the-ipah ]h"];extended structure for ssp (assuming 3 instances of the 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