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EIGHTH NOTE”h]”hŒ♪”…””}”hjÔsbah}”(h]”h ]”h"]”Œsung”ah$]”h&]”uh1håh³hÖh´KJhhh²hubhæ)”}”(hŒ0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONE”h]”hŒ¹”…””}”hjãsbah}”(h]”h ]”h"]”Œsup1”ah$]”h&]”uh1håh³hÖh´KKhhh²hubhæ)”}”(hŒ0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWO”h]”hŒ²”…””}”hjòsbah}”(h]”h ]”h"]”Œsup2”ah$]”h&]”uh1håh³hÖh´KLhhh²hubhæ)”}”(hŒ2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREE”h]”hŒ³”…””}”hjsbah}”(h]”h ]”h"]”Œsup3”ah$]”h&]”uh1håh³hÖh´KMhhh²hubhæ)”}”(hŒ4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGN”h]”hŒ×”…””}”hjsbah}”(h]”h ]”h"]”Œtimes”ah$]”h&]”uh1håh³hÖh´KNhhh²hubhæ)”}”(hŒ0.. |trade| unicode:: U+02122 .. TRADE MARK SIGN”h]”hŒâ„¢”…””}”hjsbah}”(h]”h ]”h"]”Œtrade”ah$]”h&]”uh1håh³hÖh´KOhhh²hubhæ)”}”(hŒ... |uarr| unicode:: U+02191 .. UPWARDS ARROW”h]”hŒ↑”…””}”hj.sbah}”(h]”h ]”h"]”Œuarr”ah$]”h&]”uh1håh³hÖh´KPhhh²hubhæ)”}”(hŒ... |verbar| unicode:: U+0007C .. VERTICAL LINE”h]”hŒ|”…””}”hj=sbah}”(h]”h ]”h"]”Œverbar”ah$]”h&]”uh1håh³hÖh´KQhhh²hubhæ)”}”(hŒ*.. |yen| unicode:: U+000A5 .. YEN SIGN ”h]”hŒÂ¥”…””}”hjLsbah}”(h]”h ]”h"]”Œyen”ah$]”h&]”uh1håh³hÖh´KRhhh²hubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ0HDAudio multi-link extensions on Intel platforms”h]”hŒ0HDAudio multi-link extensions on Intel platforms”…””}”(hjbh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hj]h²hh³hÇh´KubhŒ field_list”“”)”}”(hhh]”hŒfield”“”)”}”(hhh]”(hŒ field_name”“”)”}”(hŒ Copyright”h]”hŒ Copyright”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jzhjwh³hÇh´KubhŒ field_body”“”)”}”(hŒ|copy| 2023 Intel Corporation ”h]”hŒ paragraph”“”)”}”(hŒ|copy| 2023 Intel Corporation”h]”(hŒ©”…””}”(hj’h²hh³Nh´NubhŒ 2023 Intel Corporation”…””}”(hj’h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjŒubah}”(h]”h ]”h"]”h$]”h&]”uh1jŠhjwubeh}”(h]”h ]”h"]”h$]”h&]”uh1juh³hÇh´Khjrh²hubah}”(h]”h ]”h"]”h$]”h&]”uh1jphj]h²hh³hÇh´Kubj‘)”}”(hŒ‹This file documents the 'multi-link structure' introduced in 2015 with the Skylake processor and recently extended in newer Intel platforms”h]”hŒThis file documents the ‘multi-link structure’ introduced in 2015 with the Skylake processor and recently extended in newer Intel platforms”…””}”(hj¶h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K hj]h²hubj\)”}”(hhh]”(ja)”}”(hŒ8HDaudio existing link mapping (2015 addition in SkyLake)”h]”hŒ8HDaudio existing link mapping (2015 addition in SkyLake)”…””}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hjÄh²hh³hÇh´Kubj‘)”}”(hŒqExternal HDAudio codecs are handled with link #0, while iDISP codec for HDMI/DisplayPort is handled with link #1.”h]”hŒqExternal HDAudio codecs are handled with link #0, while iDISP codec for HDMI/DisplayPort is handled with link #1.”…””}”(hjÕh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÄh²hubj‘)”}”(hŒ¢The only change to the 2015 definitions is the declaration of the LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a backwards-compatible change.”h]”hŒ¢The only change to the 2015 definitions is the declaration of the LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a backwards-compatible change.”…””}”(hjãh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÄh²hubj‘)”}”(hŒLCTL.SPA and LCTL.CPA are automatically set when exiting reset. They are only used in existing drivers when the SCF value needs to be corrected.”h]”hŒLCTL.SPA and LCTL.CPA are automatically set when exiting reset. They are only used in existing drivers when the SCF value needs to be corrected.”…””}”(hjñh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KhjÄh²hubj\)”}”(hhh]”(ja)”}”(hŒ"Basic structure for HDaudio codecs”h]”hŒ"Basic structure for HDaudio codecs”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hjÿh²hh³hÇh´KubhŒ literal_block”“”)”}”(hXÜ+-----------+ | ML cap #0 | +-----------+ | ML cap #1 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=0 | +---------------+ | S192 | +---------------+ | S96 | +---------------+ | S48 | +---------------+ | S24 | +---------------+ | S12 | +---------------+ | S6 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | SCF | +---------------+ 0x8 +---------------+ LOSIDV | L1OSIVD15 | +---------------+ | L1OSIDV.. | +---------------+ | L1OSIDV1 | +---------------+ 0xC +---------------+ LSDIID | SDIID14 | +---------------+ | SDIID... | +---------------+ | SDIID0 | +---------------+”h]”hXÜ+-----------+ | ML cap #0 | +-----------+ | ML cap #1 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=0 | +---------------+ | S192 | +---------------+ | S96 | +---------------+ | S48 | +---------------+ | S24 | +---------------+ | S12 | +---------------+ | S6 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | SCF | +---------------+ 0x8 +---------------+ LOSIDV | L1OSIVD15 | +---------------+ | L1OSIDV.. | +---------------+ | L1OSIDV1 | +---------------+ 0xC +---------------+ LSDIID | SDIID14 | +---------------+ | SDIID... | +---------------+ | SDIID0 | +---------------+”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K hjÿh²hubeh}”(h]”Œ"basic-structure-for-hdaudio-codecs”ah ]”h"]”Œ"basic structure for hdaudio codecs”ah$]”h&]”uh1j[hjÄh²hh³hÇh´Kubeh}”(h]”Œ6hdaudio-existing-link-mapping-2015-addition-in-skylake”ah ]”h"]”Œ8hdaudio existing link mapping (2015 addition in skylake)”ah$]”h&]”uh1j[hj]h²hh³hÇh´Kubj\)”}”(hhh]”(ja)”}”(hŒ'SoundWire HDaudio extended link mapping”h]”hŒ'SoundWire HDaudio extended link mapping”…””}”(hj3h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hj0h²hh³hÇh´KQubj‘)”}”(hŒGA SoundWire extended link is identified when LCAP.ALT=1 and LEPTR.ID=0.”h]”hŒGA SoundWire extended link is identified when LCAP.ALT=1 and LEPTR.ID=0.”…””}”(hjAh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KShj0h²hubj‘)”}”(hŒ.DMA control uses the existing LOSIDV register.”h]”hŒ.DMA control uses the existing LOSIDV register.”…””}”(hjOh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KVhj0h²hubj‘)”}”(hŒeChanges include additional descriptions for enumeration that were not present in earlier generations.”h]”hŒeChanges include additional descriptions for enumeration that were not present in earlier generations.”…””}”(hj]h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´KXhj0h²hubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC”h]”j‘)”}”(hjth]”hŒImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC”…””}”(hjvh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K[hjrubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubjq)”}”(hŒ/number of sublinks (manager IP) in LCAP.LSCOUNT”h]”j‘)”}”(hj‹h]”hŒ/number of sublinks (manager IP) in LCAP.LSCOUNT”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K\hj‰ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubjq)”}”(hŒ1power management moved from SHIM to LCTL.SPA bits”h]”j‘)”}”(hj¢h]”hŒ1power management moved from SHIM to LCTL.SPA bits”…””}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K]hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubjq)”}”(hŒPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN”h]”j‘)”}”(hj¹h]”hŒPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN”…””}”(hj»h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K^hj·ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubjq)”}”(hŒ*mapping of SoundWire codecs to SDI ID bits”h]”j‘)”}”(hjÐh]”hŒ*mapping of SoundWire codecs to SDI ID bits”…””}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K_hjÎubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubjq)”}”(hŒ±move of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000. ”h]”j‘)”}”(hŒ°move of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000.”h]”hŒ°move of SHIM and Cadence registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x30000.”…””}”(hjéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K`hjåubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjmh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jkh³hÇh´K[hj0h²hubj\)”}”(hhh]”(ja)”}”(hŒ8Extended structure for SoundWire (assuming 4 Manager IP)”h]”hŒ8Extended structure for SoundWire (assuming 4 Manager IP)”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hjh²hh³hÇh´Keubj)”}”(hX×+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | LSS | +---------------+ | SLCOUNT=4 |-----------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ for each sublink x | INTEN | | +---------------+ | | OFLEN | | +---------------+ | | 0x8 +---------------+ LOSIDV | | L1OSIVD15 | | +---------------+ | | L1OSIDV.. | | +---------------+ | | L1OSIDV1 | +---+----------------------------------------------------------+ +---------------+ | | v | 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 | | SDIID14 | | | SoundWire SHIM | | +---------------+ | | generic | | | SDIID... | | +-----------------+ 0x00030100 | +---------------+ | | SoundWire IP | | | SDIID0 | | +-----------------+ 0x00036000 | +---------------+ | | SoundWire SHIM | | | | vendor-specific | | 0x1C +---------------+ LSYNC | +-----------------+ | | CMDSYNC | | v +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x | SYNCGO | | | SoundWire SHIM | +---------------+ | | generic | | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x +---------------+ | | SoundWire IP | | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x +---------------+ | | SoundWire SHIM | | | vendor-specific | 0x20 +---------------+ LEPTR | +-----------------+ | ID = 0 | | +---------------+ | | VER | | +---------------+ | | PTR |------------+ +---------------+”h]”hX×+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | LSS | +---------------+ | SLCOUNT=4 |-----------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ for each sublink x | INTEN | | +---------------+ | | OFLEN | | +---------------+ | | 0x8 +---------------+ LOSIDV | | L1OSIVD15 | | +---------------+ | | L1OSIDV.. | | +---------------+ | | L1OSIDV1 | +---+----------------------------------------------------------+ +---------------+ | | v | 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 | | SDIID14 | | | SoundWire SHIM | | +---------------+ | | generic | | | SDIID... | | +-----------------+ 0x00030100 | +---------------+ | | SoundWire IP | | | SDIID0 | | +-----------------+ 0x00036000 | +---------------+ | | SoundWire SHIM | | | | vendor-specific | | 0x1C +---------------+ LSYNC | +-----------------+ | | CMDSYNC | | v +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x | SYNCGO | | | SoundWire SHIM | +---------------+ | | generic | | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x +---------------+ | | SoundWire IP | | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x +---------------+ | | SoundWire SHIM | | | vendor-specific | 0x20 +---------------+ LEPTR | +-----------------+ | ID = 0 | | +---------------+ | | VER | | +---------------+ | | PTR |------------+ +---------------+”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´Kihjh²hubeh}”(h]”Œ6extended-structure-for-soundwire-assuming-4-manager-ip”ah ]”h"]”Œ8extended structure for soundwire (assuming 4 manager ip)”ah$]”h&]”uh1j[hj0h²hh³hÇh´Keubeh}”(h]”Œ'soundwire-hdaudio-extended-link-mapping”ah ]”h"]”Œ'soundwire hdaudio extended link mapping”ah$]”h&]”uh1j[hj]h²hh³hÇh´KQubj\)”}”(hhh]”(ja)”}”(hŒ"DMIC HDaudio extended link mapping”h]”hŒ"DMIC HDaudio extended link mapping”…””}”(hj7h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hj4h²hh³hÇh´K­ubj‘)”}”(hŒMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC1 are set.”h]”hŒMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC1 are set.”…””}”(hjEh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K¯hj4h²hubj‘)”}”(hŒ-DMA control uses the existing LOSIDV register”h]”hŒ-DMA control uses the existing LOSIDV register”…””}”(hjSh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K²hj4h²hubj‘)”}”(hŒeChanges include additional descriptions for enumeration that were not present in earlier generations.”h]”hŒeChanges include additional descriptions for enumeration that were not present in earlier generations.”…””}”(hjah²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K´hj4h²hubjl)”}”(hhh]”(jq)”}”(hŒImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC”h]”j‘)”}”(hjth]”hŒImulti-link synchronization: capabilities in LCAP.LSS and control in LSYNC”…””}”(hjvh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K·hjrubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjoh²hh³hÇh´Nubjq)”}”(hŒ#power management with LCTL.SPA bits”h]”j‘)”}”(hj‹h]”hŒ#power management with LCTL.SPA bits”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K¸hj‰ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjoh²hh³hÇh´Nubjq)”}”(hŒQhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN ”h]”j‘)”}”(hŒPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN”h]”hŒPhand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN”…””}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K¹hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjoh²hh³hÇh´Nubjq)”}”(hŒ¥move of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000. ”h]”j‘)”}”(hŒ¤move of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000.”h]”hŒ¤move of DMIC registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x10000.”…””}”(hj¼h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´K»hj¸ubah}”(h]”h ]”h"]”h$]”h&]”uh1jphjoh²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jjuh1jkh³hÇh´K·hj4h²hubj\)”}”(hhh]”(ja)”}”(hŒExtended structure for DMIC”h]”hŒExtended structure for DMIC”…””}”(hjÙh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hjÖh²hh³hÇh´KÀubj)”}”(hXŸ+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=1 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | INTEN | +---------------+ | OFLEN | +---------------+ +---> 0x10000 +-----------------+ 0x00010000 | | DMIC SHIM | 0x8 +---------------+ LOSIDV | | generic | | L1OSIVD15 | | +-----------------+ 0x00010100 +---------------+ | | DMIC IP | | L1OSIDV.. | | +-----------------+ 0x00016000 +---------------+ | | DMIC SHIM | | L1OSIDV1 | | | vendor-specific | +---------------+ | +-----------------+ | 0x20 +---------------+ LEPTR | | ID = 0xC1 | | +---------------+ | | VER | | +---------------+ | | PTR |-----------+ +---------------+”h]”hXŸ+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=1 | +---------------+ 0x4 +---------------+ LCTL | INTSTS | +---------------+ | CPA | +---------------+ | SPA | +---------------+ | INTEN | +---------------+ | OFLEN | +---------------+ +---> 0x10000 +-----------------+ 0x00010000 | | DMIC SHIM | 0x8 +---------------+ LOSIDV | | generic | | L1OSIVD15 | | +-----------------+ 0x00010100 +---------------+ | | DMIC IP | | L1OSIDV.. | | +-----------------+ 0x00016000 +---------------+ | | DMIC SHIM | | L1OSIDV1 | | | vendor-specific | +---------------+ | +-----------------+ | 0x20 +---------------+ LEPTR | | ID = 0xC1 | | +---------------+ | | VER | | +---------------+ | | PTR |-----------+ +---------------+”…””}”hjçsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´KÄhjÖh²hubeh}”(h]”Œextended-structure-for-dmic”ah ]”h"]”Œextended structure for dmic”ah$]”h&]”uh1j[hj4h²hh³hÇh´KÀubeh}”(h]”Œ"dmic-hdaudio-extended-link-mapping”ah ]”h"]”Œ"dmic hdaudio extended link mapping”ah$]”h&]”uh1j[hj]h²hh³hÇh´K­ubj\)”}”(hhh]”(ja)”}”(hŒ!SSP HDaudio extended link mapping”h]”hŒ!SSP HDaudio extended link mapping”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hjh²hh³hÇh´Kôubj‘)”}”(hŒMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC0 are set.”h]”hŒMA DMIC extended link is identified when LCAP.ALT=1 and LEPTR.ID=0xC0 are set.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Köhjh²hubj‘)”}”(hŒ-DMA control uses the existing LOSIDV register”h]”hŒ-DMA control uses the existing LOSIDV register”…””}”(hj$h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kùhjh²hubj‘)”}”(hXãChanges include additional descriptions for enumeration and control that were not present in earlier generations: - number of sublinks (SSP IP instances) in LCAP.LSCOUNT - power management moved from SHIM to LCTL.SPA bits - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN - move of SHIM and SSP IP registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x28000.”h]”hXãChanges include additional descriptions for enumeration and control that were not present in earlier generations: - number of sublinks (SSP IP instances) in LCAP.LSCOUNT - power management moved from SHIM to LCTL.SPA bits - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN - move of SHIM and SSP IP registers to different offsets, with no change in functionality. The LEPTR.PTR value is an offset from the ML address, with a default value of 0x28000.”…””}”(hj2h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jh³hÇh´Kûhjh²hubj\)”}”(hhh]”(ja)”}”(hŒ;Extended structure for SSP (assuming 3 instances of the IP)”h]”hŒ;Extended structure for SSP (assuming 3 instances of the IP)”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j`hj@h²hh³hÇh´Mubj)”}”(hX7+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=3 |-------------------------for each sublink x -------------------------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ | | INTEN | | +---------------+ | | OFLEN | | +---------------+ +---> 0x28000 +-----------------+ 0x00028000 | | | SSP SHIM | | 0x8 +---------------+ LOSIDV | | generic | | | L1OSIVD15 | | +-----------------+ 0x00028100 | +---------------+ | | SSP IP | | | L1OSIDV.. | | +-----------------+ 0x00028C00 | +---------------+ | | SSP SHIM | | | L1OSIDV1 | | | vendor-specific | | +---------------+ | +-----------------+ | | v 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x | ID = 0xC0 | | | SSP SHIM | +---------------+ | | generic | | VER | | +-----------------+ 0x00028100 + 0x1000 * x +---------------+ | | SSP IP | | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x +---------------+ | SSP SHIM | | vendor-specific | +-----------------+”h]”hX7+-----------+ | ML cap #0 | +-----------+ | ML cap #1 | +-----------+ | ML cap #2 |---+ +-----------+ | | +--> 0x0 +---------------+ LCAP | ALT=1 | +---------------+ | INTC | +---------------+ | OFLS | +---------------+ | SLCOUNT=3 |-------------------------for each sublink x -------------------------+ +---------------+ | | 0x4 +---------------+ LCTL | | INTSTS | | +---------------+ | | CPA (x bits) | | +---------------+ | | SPA (x bits) | | +---------------+ | | INTEN | | +---------------+ | | OFLEN | | +---------------+ +---> 0x28000 +-----------------+ 0x00028000 | | | SSP SHIM | | 0x8 +---------------+ LOSIDV | | generic | | | L1OSIVD15 | | +-----------------+ 0x00028100 | +---------------+ | | SSP IP | | | L1OSIDV.. | | +-----------------+ 0x00028C00 | +---------------+ | | SSP SHIM | | | L1OSIDV1 | | | vendor-specific | | +---------------+ | +-----------------+ | | v 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x | ID = 0xC0 | | | SSP SHIM | +---------------+ | | generic | | VER | | +-----------------+ 0x00028100 + 0x1000 * x +---------------+ | | SSP IP | | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x +---------------+ | SSP SHIM | | vendor-specific | +-----------------+”…””}”hjQsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´M 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