sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget/translations/zh_CN/scsi/hptiopmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/zh_TW/scsi/hptiopmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/it_IT/scsi/hptiopmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ja_JP/scsi/hptiopmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/ko_KR/scsi/hptiopmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget/translations/sp_SP/scsi/hptiopmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhh9/var/lib/git/docbuild/linux/Documentation/scsi/hptiop.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .h]hDerived from the Unicode character mappings available from . Processed by unicode2rstsubs.py, part of Docutils: .}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhhhhKubhsubstitution_definition)}(h*.. |amp| unicode:: U+00026 .. AMPERSANDh]h&}hhsbah}(h]h ]h"]ampah$]h&]uh1hhhhKhhhhubh)}(h+.. |apos| unicode:: U+00027 .. APOSTROPHEh]h'}hhsbah}(h]h ]h"]aposah$]h&]uh1hhhhKhhhhubh)}(h).. |ast| unicode:: U+0002A .. ASTERISKh]h*}hhsbah}(h]h ]h"]astah$]h&]uh1hhhhK hhhhubh)}(h+.. |brvbar| unicode:: U+000A6 .. BROKEN BARh]h¦}hjsbah}(h]h ]h"]brvbarah$]h&]uh1hhhhK hhhhubh)}(h0.. |bsol| unicode:: U+0005C .. REVERSE SOLIDUSh]h\}hjsbah}(h]h ]h"]bsolah$]h&]uh1hhhhK hhhhubh)}(h*.. |cent| unicode:: U+000A2 .. CENT SIGNh]h¢}hjsbah}(h]h ]h"]centah$]h&]uh1hhhhK hhhhubh)}(h&.. |colon| unicode:: U+0003A .. COLONh]h:}hj-sbah}(h]h ]h"]colonah$]h&]uh1hhhhK hhhhubh)}(h&.. |comma| unicode:: U+0002C .. COMMAh]h,}hj<sbah}(h]h ]h"]commaah$]h&]uh1hhhhKhhhhubh)}(h... |commat| unicode:: U+00040 .. COMMERCIAL ATh]h@}hjKsbah}(h]h ]h"]commatah$]h&]uh1hhhhKhhhhubh)}(h/.. |copy| unicode:: U+000A9 .. COPYRIGHT SIGNh]h©}hjZsbah}(h]h ]h"]copyah$]h&]uh1hhhhKhhhhubh)}(h... |curren| unicode:: U+000A4 .. CURRENCY SIGNh]h¤}hjisbah}(h]h ]h"]currenah$]h&]uh1hhhhKhhhhubh)}(h0.. |darr| unicode:: U+02193 .. DOWNWARDS ARROWh]h↓}hjxsbah}(h]h ]h"]darrah$]h&]uh1hhhhKhhhhubh)}(h,.. |deg| unicode:: U+000B0 .. DEGREE SIGNh]h°}hjsbah}(h]h ]h"]degah$]h&]uh1hhhhKhhhhubh)}(h... |divide| unicode:: U+000F7 .. DIVISION SIGNh]h÷}hjsbah}(h]h ]h"]divideah$]h&]uh1hhhhKhhhhubh)}(h,.. |dollar| unicode:: U+00024 .. DOLLAR SIGNh]h$}hjsbah}(h]h ]h"]dollarah$]h&]uh1hhhhKhhhhubh)}(h,.. |equals| unicode:: U+0003D .. EQUALS SIGNh]h=}hjsbah}(h]h ]h"]equalsah$]h&]uh1hhhhKhhhhubh)}(h1.. |excl| unicode:: U+00021 .. EXCLAMATION MARKh]h!}hjsbah}(h]h ]h"]exclah$]h&]uh1hhhhKhhhhubh)}(h9.. |frac12| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjsbah}(h]h ]h"]frac12ah$]h&]uh1hhhhKhhhhubh)}(h<.. |frac14| unicode:: U+000BC .. VULGAR FRACTION ONE QUARTERh]h¼}hjsbah}(h]h ]h"]frac14ah$]h&]uh1hhhhKhhhhubh)}(h;.. |frac18| unicode:: U+0215B .. VULGAR FRACTION ONE EIGHTHh]h⅛}hjsbah}(h]h ]h"]frac18ah$]h&]uh1hhhhKhhhhubh)}(h?.. |frac34| unicode:: U+000BE .. VULGAR FRACTION THREE QUARTERSh]h¾}hjsbah}(h]h ]h"]frac34ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac38| unicode:: U+0215C .. VULGAR FRACTION THREE EIGHTHSh]h⅜}hjsbah}(h]h ]h"]frac38ah$]h&]uh1hhhhKhhhhubh)}(h=.. |frac58| unicode:: U+0215D .. VULGAR FRACTION FIVE EIGHTHSh]h⅝}hjsbah}(h]h ]h"]frac58ah$]h&]uh1hhhhKhhhhubh)}(h>.. |frac78| unicode:: U+0215E .. VULGAR FRACTION SEVEN EIGHTHSh]h⅞}hj,sbah}(h]h ]h"]frac78ah$]h&]uh1hhhhKhhhhubh)}(h2.. |gt| unicode:: U+0003E .. GREATER-THAN SIGNh]h>}hj;sbah}(h]h ]h"]gtah$]h&]uh1hhhhKhhhhubh)}(h9.. |half| unicode:: U+000BD .. VULGAR FRACTION ONE HALFh]h½}hjJsbah}(h]h ]h"]halfah$]h&]uh1hhhhK hhhhubh)}(h/.. |horbar| unicode:: U+02015 .. HORIZONTAL BARh]h―}hjYsbah}(h]h ]h"]horbarah$]h&]uh1hhhhK!hhhhubh)}(h'.. |hyphen| unicode:: U+02010 .. HYPHENh]h‐}hjhsbah}(h]h ]h"]hyphenah$]h&]uh1hhhhK"hhhhubh)}(h:.. |iexcl| unicode:: U+000A1 .. INVERTED EXCLAMATION MARKh]h¡}hjwsbah}(h]h ]h"]iexclah$]h&]uh1hhhhK#hhhhubh)}(h7.. |iquest| unicode:: U+000BF .. INVERTED QUESTION MARKh]h¿}hjsbah}(h]h ]h"]iquestah$]h&]uh1hhhhK$hhhhubh)}(hJ.. |laquo| unicode:: U+000AB .. LEFT-POINTING DOUBLE ANGLE QUOTATION MARKh]h«}hjsbah}(h]h ]h"]laquoah$]h&]uh1hhhhK%hhhhubh)}(h0.. |larr| unicode:: U+02190 .. LEFTWARDS ARROWh]h←}hjsbah}(h]h ]h"]larrah$]h&]uh1hhhhK&hhhhubh)}(h3.. |lcub| unicode:: U+0007B .. LEFT CURLY BRACKETh]h{}hjsbah}(h]h ]h"]lcubah$]h&]uh1hhhhK'hhhhubh)}(h;.. |ldquo| unicode:: U+0201C .. LEFT DOUBLE QUOTATION MARKh]h“}hjsbah}(h]h ]h"]ldquoah$]h&]uh1hhhhK(hhhhubh)}(h).. |lowbar| unicode:: U+0005F .. LOW LINEh]h_}hjsbah}(h]h ]h"]lowbarah$]h&]uh1hhhhK)hhhhubh)}(h1.. |lpar| unicode:: U+00028 .. LEFT PARENTHESISh]h(}hjsbah}(h]h ]h"]lparah$]h&]uh1hhhhK*hhhhubh)}(h4.. |lsqb| unicode:: U+0005B .. LEFT SQUARE BRACKETh]h[}hjsbah}(h]h ]h"]lsqbah$]h&]uh1hhhhK+hhhhubh)}(h;.. |lsquo| unicode:: U+02018 .. LEFT SINGLE QUOTATION MARKh]h‘}hjsbah}(h]h ]h"]lsquoah$]h&]uh1hhhhK,hhhhubh)}(h/.. |lt| unicode:: U+0003C .. LESS-THAN SIGNh]h<}hj sbah}(h]h ]h"]ltah$]h&]uh1hhhhK-hhhhubh)}(h+.. |micro| unicode:: U+000B5 .. MICRO SIGNh]hµ}hjsbah}(h]h ]h"]microah$]h&]uh1hhhhK.hhhhubh)}(h+.. |middot| unicode:: U+000B7 .. MIDDLE DOTh]h·}hj+sbah}(h]h ]h"]middotah$]h&]uh1hhhhK/hhhhubh)}(h/.. |nbsp| unicode:: U+000A0 .. NO-BREAK SPACEh]h }hj:sbah}(h]h ]h"]nbspah$]h&]uh1hhhhK0hhhhubh)}(h).. |not| unicode:: U+000AC .. NOT SIGNh]h¬}hjIsbah}(h]h ]h"]notah$]h&]uh1hhhhK1hhhhubh)}(h,.. |num| unicode:: U+00023 .. NUMBER SIGNh]h#}hjXsbah}(h]h ]h"]numah$]h&]uh1hhhhK2hhhhubh)}(h).. |ohm| unicode:: U+02126 .. OHM SIGNh]hΩ}hjgsbah}(h]h ]h"]ohmah$]h&]uh1hhhhK3hhhhubh)}(h;.. |ordf| unicode:: U+000AA .. FEMININE ORDINAL INDICATORh]hª}hjvsbah}(h]h ]h"]ordfah$]h&]uh1hhhhK4hhhhubh)}(h<.. |ordm| unicode:: U+000BA .. MASCULINE ORDINAL INDICATORh]hº}hjsbah}(h]h ]h"]ordmah$]h&]uh1hhhhK5hhhhubh)}(h-.. |para| unicode:: U+000B6 .. PILCROW SIGNh]h¶}hjsbah}(h]h ]h"]paraah$]h&]uh1hhhhK6hhhhubh)}(h-.. |percnt| unicode:: U+00025 .. PERCENT SIGNh]h%}hjsbah}(h]h ]h"]percntah$]h&]uh1hhhhK7hhhhubh)}(h*.. |period| unicode:: U+0002E .. FULL STOPh]h.}hjsbah}(h]h ]h"]periodah$]h&]uh1hhhhK8hhhhubh)}(h*.. |plus| unicode:: U+0002B .. PLUS SIGNh]h+}hjsbah}(h]h ]h"]plusah$]h&]uh1hhhhK9hhhhubh)}(h0.. |plusmn| unicode:: U+000B1 .. PLUS-MINUS SIGNh]h±}hjsbah}(h]h ]h"]plusmnah$]h&]uh1hhhhK:hhhhubh)}(h+.. |pound| unicode:: U+000A3 .. POUND SIGNh]h£}hjsbah}(h]h ]h"]poundah$]h&]uh1hhhhK;hhhhubh)}(h... |quest| unicode:: U+0003F .. QUESTION MARKh]h?}hjsbah}(h]h ]h"]questah$]h&]uh1hhhhKhhhhubh)}(h1.. |rarr| unicode:: U+02192 .. RIGHTWARDS ARROWh]h→}hjsbah}(h]h ]h"]rarrah$]h&]uh1hhhhK?hhhhubh)}(h4.. |rcub| unicode:: U+0007D .. RIGHT CURLY BRACKETh]h}}hj*sbah}(h]h ]h"]rcubah$]h&]uh1hhhhK@hhhhubh)}(h<.. |rdquo| unicode:: U+0201D .. RIGHT DOUBLE QUOTATION MARKh]h”}hj9sbah}(h]h ]h"]rdquoah$]h&]uh1hhhhKAhhhhubh)}(h0.. |reg| unicode:: U+000AE .. REGISTERED SIGNh]h®}hjHsbah}(h]h ]h"]regah$]h&]uh1hhhhKBhhhhubh)}(h2.. |rpar| unicode:: U+00029 .. RIGHT PARENTHESISh]h)}hjWsbah}(h]h ]h"]rparah$]h&]uh1hhhhKChhhhubh)}(h5.. |rsqb| unicode:: U+0005D .. RIGHT SQUARE BRACKETh]h]}hjfsbah}(h]h ]h"]rsqbah$]h&]uh1hhhhKDhhhhubh)}(h<.. |rsquo| unicode:: U+02019 .. RIGHT SINGLE QUOTATION MARKh]h’}hjusbah}(h]h ]h"]rsquoah$]h&]uh1hhhhKEhhhhubh)}(h-.. |sect| unicode:: U+000A7 .. SECTION SIGNh]h§}hjsbah}(h]h ]h"]sectah$]h&]uh1hhhhKFhhhhubh)}(h*.. |semi| unicode:: U+0003B .. SEMICOLONh]h;}hjsbah}(h]h ]h"]semiah$]h&]uh1hhhhKGhhhhubh)}(h,.. |shy| unicode:: U+000AD .. SOFT HYPHENh]h­}hjsbah}(h]h ]h"]shyah$]h&]uh1hhhhKHhhhhubh)}(h(.. |sol| unicode:: U+0002F .. SOLIDUSh]h/}hjsbah}(h]h ]h"]solah$]h&]uh1hhhhKIhhhhubh)}(h,.. |sung| unicode:: U+0266A .. EIGHTH NOTEh]h♪}hjsbah}(h]h ]h"]sungah$]h&]uh1hhhhKJhhhhubh)}(h0.. |sup1| unicode:: U+000B9 .. SUPERSCRIPT ONEh]h¹}hjsbah}(h]h ]h"]sup1ah$]h&]uh1hhhhKKhhhhubh)}(h0.. |sup2| unicode:: U+000B2 .. SUPERSCRIPT TWOh]h²}hjsbah}(h]h ]h"]sup2ah$]h&]uh1hhhhKLhhhhubh)}(h2.. |sup3| unicode:: U+000B3 .. SUPERSCRIPT THREEh]h³}hjsbah}(h]h ]h"]sup3ah$]h&]uh1hhhhKMhhhhubh)}(h4.. |times| unicode:: U+000D7 .. MULTIPLICATION SIGNh]h×}hjsbah}(h]h ]h"]timesah$]h&]uh1hhhhKNhhhhubh)}(h0.. |trade| unicode:: U+02122 .. TRADE MARK SIGNh]h™}hj sbah}(h]h ]h"]tradeah$]h&]uh1hhhhKOhhhhubh)}(h... |uarr| unicode:: U+02191 .. UPWARDS ARROWh]h↑}hjsbah}(h]h ]h"]uarrah$]h&]uh1hhhhKPhhhhubh)}(h... |verbar| unicode:: U+0007C .. VERTICAL LINEh]h|}hj)sbah}(h]h ]h"]verbarah$]h&]uh1hhhhKQhhhhubh)}(h*.. |yen| unicode:: U+000A5 .. YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h6Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)h]h6Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubjH)}(hhh](jM)}(hController Register Maph]hController Register Map}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj\hhhhhK ubh paragraph)}(hYFor RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2h]hYFor RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK hj\hhubh block_quote)}(hX============== ================================== BAR0 offset Register ============== ================================== 0x11C5C Link Interface IRQ Set 0x11C60 Link Interface IRQ Clear ============== ================================== ============== ================================== BAR2 offset Register ============== ================================== 0x10 Inbound Message Register 0 0x14 Inbound Message Register 1 0x18 Outbound Message Register 0 0x1C Outbound Message Register 1 0x20 Inbound Doorbell Register 0x24 Inbound Interrupt Status Register 0x28 Inbound Interrupt Mask Register 0x30 Outbound Interrupt Status Register 0x34 Outbound Interrupt Mask Register 0x40 Inbound Queue Port 0x44 Outbound Queue Port ============== ================================== h](htable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]jn)}(h BAR0 offseth]h BAR0 offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubhtbody)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x11C5Ch]h0x11C5C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hLink Interface IRQ Seth]hLink Interface IRQ Set}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x11C60h]h0x11C60}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj(ubah}(h]h ]h"]h$]h&]uh1jhj%ubj)}(hhh]jn)}(hLink Interface IRQ Clearh]hLink Interface IRQ Clear}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj?ubah}(h]h ]h"]h$]h&]uh1jhj%ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjrubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhjrubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR2 offseth]h BAR2 offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjrubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x10h]h0x10}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Message Register 0h]hInbound Message Register 0}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x14h]h0x14}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Message Register 1h]hInbound Message Register 1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x18h]h0x18}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj=ubah}(h]h ]h"]h$]h&]uh1jhj:ubj)}(hhh]jn)}(hOutbound Message Register 0h]hOutbound Message Register 0}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjTubah}(h]h ]h"]h$]h&]uh1jhj:ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x1Ch]h0x1C}(hjwhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjtubah}(h]h ]h"]h$]h&]uh1jhjqubj)}(hhh]jn)}(hOutbound Message Register 1h]hOutbound Message Register 1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjqubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x20h]h0x20}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Doorbell Registerh]hInbound Doorbell Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x24h]h0x24}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h!Inbound Interrupt Status Registerh]h!Inbound Interrupt Status Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x28h]h0x28}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Interrupt Mask Registerh]hInbound Interrupt Mask Register}(hj3hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj0ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x30h]h0x30}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjPubah}(h]h ]h"]h$]h&]uh1jhjMubj)}(hhh]jn)}(h"Outbound Interrupt Status Registerh]h"Outbound Interrupt Status Register}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjgubah}(h]h ]h"]h$]h&]uh1jhjMubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x34h]h0x34}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h Outbound Interrupt Mask Registerh]h Outbound Interrupt Mask Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x40h]h0x40}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Queue Porth]hInbound Queue Port}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x44h]h0x44}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK!hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound Queue Porth]hOutbound Queue Port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK!hj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjrubeh}(h]h ]h"]h$]h&]colsKuh1jhjoubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j}hhhK hj\hhubjn)}(hJFor Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:h]hJFor Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK$hj\hhubj~)}(hX============== ================================== BAR0 offset Register ============== ================================== 0x10 Inbound Message Register 0 0x14 Inbound Message Register 1 0x18 Outbound Message Register 0 0x1C Outbound Message Register 1 0x20 Inbound Doorbell Register 0x24 Inbound Interrupt Status Register 0x28 Inbound Interrupt Mask Register 0x30 Outbound Interrupt Status Register 0x34 Outbound Interrupt Mask Register 0x40 Inbound Queue Port 0x44 Outbound Queue Port ============== ================================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjW ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhjW ubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR0 offseth]h BAR0 offset}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK'hjt ubah}(h]h ]h"]h$]h&]uh1jhjq ubj)}(hhh]jn)}(hRegisterh]hRegister}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK'hj ubah}(h]h ]h"]h$]h&]uh1jhjq ubeh}(h]h ]h"]h$]h&]uh1jhjn ubah}(h]h ]h"]h$]h&]uh1jhjW ubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x10h]h0x10}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK)hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Message Register 0h]hInbound Message Register 0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK)hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x14h]h0x14}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK*hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Message Register 1h]hInbound Message Register 1}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK*hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x18h]h0x18}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK+hj" ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hOutbound Message Register 0h]hOutbound Message Register 0}(hj< hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK+hj9 ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x1Ch]h0x1C}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK,hjY ubah}(h]h ]h"]h$]h&]uh1jhjV ubj)}(hhh]jn)}(hOutbound Message Register 1h]hOutbound Message Register 1}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK,hjp ubah}(h]h ]h"]h$]h&]uh1jhjV ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x20h]h0x20}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK-hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Doorbell Registerh]hInbound Doorbell Register}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK-hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x24h]h0x24}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK.hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(h!Inbound Interrupt Status Registerh]h!Inbound Interrupt Status Register}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK.hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x28h]h0x28}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Interrupt Mask Registerh]hInbound Interrupt Mask Register}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK/hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x30h]h0x30}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK0hj5 ubah}(h]h ]h"]h$]h&]uh1jhj2 ubj)}(hhh]jn)}(h"Outbound Interrupt Status Registerh]h"Outbound Interrupt Status Register}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK0hjL ubah}(h]h ]h"]h$]h&]uh1jhj2 ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x34h]h0x34}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK1hjl ubah}(h]h ]h"]h$]h&]uh1jhji ubj)}(hhh]jn)}(h Outbound Interrupt Mask Registerh]h Outbound Interrupt Mask Register}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK1hj ubah}(h]h ]h"]h$]h&]uh1jhji ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x40h]h0x40}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK2hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Queue Porth]hInbound Queue Port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK2hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x44h]h0x44}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK3hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hOutbound Queue Porth]hOutbound Queue Port}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK3hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhjW ubeh}(h]h ]h"]h$]h&]colsKuh1jhjT ubah}(h]h ]h"]h$]h&]uh1jhjP ubah}(h]h ]h"]h$]h&]uh1j}hhhK&hj\hhubjn)}(hSFor Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:h]hSFor Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK6hj\hhubj~)}(hXE============== ================================== BAR0 offset Register ============== ================================== 0x20400 Inbound Doorbell Register 0x20404 Inbound Interrupt Mask Register 0x20408 Outbound Doorbell Register 0x2040C Outbound Interrupt Mask Register ============== ================================== ============== ================================== BAR1 offset Register ============== ================================== 0x0 Inbound Queue Head Pointer 0x4 Inbound Queue Tail Pointer 0x8 Outbound Queue Head Pointer 0xC Outbound Queue Tail Pointer 0x10 Inbound Message Register 0x14 Outbound Message Register 0x40-0x1040 Inbound Queue 0x1040-0x2040 Outbound Queue ============== ================================== h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj< ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhj< ubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR0 offseth]h BAR0 offset}(hj\ hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK9hjY ubah}(h]h ]h"]h$]h&]uh1jhjV ubj)}(hhh]jn)}(hRegisterh]hRegister}(hjs hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK9hjp ubah}(h]h ]h"]h$]h&]uh1jhjV ubeh}(h]h ]h"]h$]h&]uh1jhjS ubah}(h]h ]h"]h$]h&]uh1jhj< ubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x20400h]h0x20400}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK;hj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Doorbell Registerh]hInbound Doorbell Register}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK;hj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x20404h]h0x20404}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj> ubah}(h]h ]h"]h$]h&]uh1jhj; ubj)}(hhh]jn)}(h Outbound Interrupt Mask Registerh]h Outbound Interrupt Mask Register}(hjX hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK>hjU ubah}(h]h ]h"]h$]h&]uh1jhj; ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj< ubeh}(h]h ]h"]h$]h&]colsKuh1jhj9 ubah}(h]h ]h"]h$]h&]uh1jhj5 ubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhj ubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhj ubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR1 offseth]h BAR1 offset}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKBhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hRegisterh]hRegister}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKBhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x0h]h0x0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKDhj ubah}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh]jn)}(hInbound Queue Head Pointerh]hInbound Queue Head Pointer}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKDhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x4h]h0x4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKEhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Queue Tail Pointerh]hInbound Queue Tail Pointer}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKEhj3ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x8h]h0x8}(hjVhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKFhjSubah}(h]h ]h"]h$]h&]uh1jhjPubj)}(hhh]jn)}(hOutbound Queue Head Pointerh]hOutbound Queue Head Pointer}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKFhjjubah}(h]h ]h"]h$]h&]uh1jhjPubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0xCh]h0xC}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound Queue Tail Pointerh]hOutbound Queue Tail Pointer}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKGhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x10h]h0x10}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound Message Registerh]hInbound Message Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKHhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h0x14h]h0x14}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound Message Registerh]hOutbound Message Register}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKIhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h 0x40-0x1040h]h 0x40-0x1040}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKJhj/ubah}(h]h ]h"]h$]h&]uh1jhj,ubj)}(hhh]jn)}(h Inbound Queueh]h Inbound Queue}(hjIhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKJhjFubah}(h]h ]h"]h$]h&]uh1jhj,ubeh}(h]h ]h"]h$]h&]uh1jhj ubj)}(hhh](j)}(hhh]jn)}(h 0x1040-0x2040h]h 0x1040-0x2040}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKKhjfubah}(h]h ]h"]h$]h&]uh1jhjcubj)}(hhh]jn)}(hOutbound Queueh]hOutbound Queue}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKKhj}ubah}(h]h ]h"]h$]h&]uh1jhjcubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj5 ubeh}(h]h ]h"]h$]h&]uh1j}hhhK8hj\hhubjn)}(hOFor Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:h]hOFor Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKNhj\hhubj~)}(hX============== ================================== BAR0 offset Register ============== ================================== 0x0 IOP configuration information. ============== ================================== ============== =================================================== BAR1 offset Register ============== =================================================== 0x4000 Inbound List Base Address Low 0x4004 Inbound List Base Address High 0x4018 Inbound List Write Pointer 0x402C Inbound List Configuration and Control 0x4050 Outbound List Base Address Low 0x4054 Outbound List Base Address High 0x4058 Outbound List Copy Pointer Shadow Base Address Low 0x405C Outbound List Copy Pointer Shadow Base Address High 0x4088 Outbound List Interrupt Cause 0x408C Outbound List Interrupt Enable 0x1020C PCIe Function 0 Interrupt Enable 0x10400 PCIe Function 0 to CPU Message A 0x10420 CPU to PCIe Function 0 Message A 0x10480 CPU to PCIe Function 0 Doorbell 0x10484 CPU to PCIe Function 0 Doorbell Enable ============== =================================================== h](j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK"uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR0 offseth]h BAR0 offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKQhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h0x0h]h0x0}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKShj%ubah}(h]h ]h"]h$]h&]uh1jhj"ubj)}(hhh]jn)}(hIOP configuration information.h]hIOP configuration information.}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKShj<ubah}(h]h ]h"]h$]h&]uh1jhj"ubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjoubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthK3uh1jhjoubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(h BAR1 offseth]h BAR1 offset}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hRegisterh]hRegister}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKWhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjoubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(h0x4000h]h0x4000}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound List Base Address Lowh]hInbound List Base Address Low}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4004h]h0x4004}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hInbound List Base Address Highh]hInbound List Base Address High}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKZhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4018h]h0x4018}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK[hj:ubah}(h]h ]h"]h$]h&]uh1jhj7ubj)}(hhh]jn)}(hInbound List Write Pointerh]hInbound List Write Pointer}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK[hjQubah}(h]h ]h"]h$]h&]uh1jhj7ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x402Ch]h0x402C}(hjthhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK\hjqubah}(h]h ]h"]h$]h&]uh1jhjnubj)}(hhh]jn)}(h&Inbound List Configuration and Controlh]h&Inbound List Configuration and Control}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK\hjubah}(h]h ]h"]h$]h&]uh1jhjnubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4050h]h0x4050}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK]hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound List Base Address Lowh]hOutbound List Base Address Low}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK]hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4054h]h0x4054}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound List Base Address Highh]hOutbound List Base Address High}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK^hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4058h]h0x4058}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK_hjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h2Outbound List Copy Pointer Shadow Base Address Lowh]h2Outbound List Copy Pointer Shadow Base Address Low}(hj0hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK_hj-ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x405Ch]h0x405C}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK`hjMubah}(h]h ]h"]h$]h&]uh1jhjJubj)}(hhh]jn)}(h3Outbound List Copy Pointer Shadow Base Address Highh]h3Outbound List Copy Pointer Shadow Base Address High}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK`hjdubah}(h]h ]h"]h$]h&]uh1jhjJubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x4088h]h0x4088}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKahjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound List Interrupt Causeh]hOutbound List Interrupt Cause}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKahjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x408Ch]h0x408C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKbhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hOutbound List Interrupt Enableh]hOutbound List Interrupt Enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKbhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x1020Ch]h0x1020C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKchjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h PCIe Function 0 Interrupt Enableh]h PCIe Function 0 Interrupt Enable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKchj ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x10400h]h0x10400}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKdhj)ubah}(h]h ]h"]h$]h&]uh1jhj&ubj)}(hhh]jn)}(h PCIe Function 0 to CPU Message Ah]h PCIe Function 0 to CPU Message A}(hjChhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKdhj@ubah}(h]h ]h"]h$]h&]uh1jhj&ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x10420h]h0x10420}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKehj`ubah}(h]h ]h"]h$]h&]uh1jhj]ubj)}(hhh]jn)}(h CPU to PCIe Function 0 Message Ah]h CPU to PCIe Function 0 Message A}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKehjwubah}(h]h ]h"]h$]h&]uh1jhj]ubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x10480h]h0x10480}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKfhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hCPU to PCIe Function 0 Doorbellh]hCPU to PCIe Function 0 Doorbell}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKfhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(h0x10484h]h0x10484}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKghjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h&CPU to PCIe Function 0 Doorbell Enableh]h&CPU to PCIe Function 0 Doorbell Enable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKghjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]colsKuh1jhjlubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1j}hhhKPhj\hhubeh}(h]controller-register-mapah ]h"]controller register mapah$]h&]uh1jGhjIhhhhhK ubjH)}(hhh](jM)}(h(I/O Request Workflow of Not Marvell Freyh]h(I/O Request Workflow of Not Marvell Frey}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj#hhhhhKlubjn)}(hAll queued requests are handled via inbound/outbound queue port. A request packet can be allocated in either IOP or host memory.h]hAll queued requests are handled via inbound/outbound queue port. A request packet can be allocated in either IOP or host memory.}(hj4hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKnhj#hhubjn)}(h$To send a request to the controller:h]h$To send a request to the controller:}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKqhj#hhubj~)}(hX- Get a free request packet by reading the inbound queue port or allocate a free request in host DMA coherent memory. The value returned from the inbound queue port is an offset relative to the IOP BAR0. Requests allocated in host memory must be aligned on 32-bytes boundary. - Fill the packet. - Post the packet to IOP by writing it to inbound queue. For requests allocated in IOP memory, write the offset to inbound queue port. For requests allocated in host memory, write (0x80000000|(bus_addr>>5)) to the inbound queue port. - The IOP process the request. When the request is completed, it will be put into outbound queue. An outbound interrupt will be generated. For requests allocated in IOP memory, the request offset is posted to outbound queue. For requests allocated in host memory, (0x80000000|(bus_addr>>5)) is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT flag is set in the request, the low 32-bit context value will be posted instead. - The host read the outbound queue and complete the request. For requests allocated in IOP memory, the host driver free the request by writing it to the outbound queue. h]h bullet_list)}(hhh](h list_item)}(hXGet a free request packet by reading the inbound queue port or allocate a free request in host DMA coherent memory. The value returned from the inbound queue port is an offset relative to the IOP BAR0. Requests allocated in host memory must be aligned on 32-bytes boundary. h](jn)}(hsGet a free request packet by reading the inbound queue port or allocate a free request in host DMA coherent memory.h]hsGet a free request packet by reading the inbound queue port or allocate a free request in host DMA coherent memory.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKshj[ubjn)}(hUThe value returned from the inbound queue port is an offset relative to the IOP BAR0.h]hUThe value returned from the inbound queue port is an offset relative to the IOP BAR0.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKvhj[ubjn)}(hGRequests allocated in host memory must be aligned on 32-bytes boundary.h]hGRequests allocated in host memory must be aligned on 32-bytes boundary.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKyhj[ubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hFill the packet. h]jn)}(hFill the packet.h]hFill the packet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK{hjubah}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hPost the packet to IOP by writing it to inbound queue. For requests allocated in IOP memory, write the offset to inbound queue port. For requests allocated in host memory, write (0x80000000|(bus_addr>>5)) to the inbound queue port. h]jn)}(hPost the packet to IOP by writing it to inbound queue. For requests allocated in IOP memory, write the offset to inbound queue port. For requests allocated in host memory, write (0x80000000|(bus_addr>>5)) to the inbound queue port.h]hPost the packet to IOP by writing it to inbound queue. For requests allocated in IOP memory, write the offset to inbound queue port. For requests allocated in host memory, write (0x80000000|(bus_addr>>5)) to the inbound queue port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhK}hjubah}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hXThe IOP process the request. When the request is completed, it will be put into outbound queue. An outbound interrupt will be generated. For requests allocated in IOP memory, the request offset is posted to outbound queue. For requests allocated in host memory, (0x80000000|(bus_addr>>5)) is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT flag is set in the request, the low 32-bit context value will be posted instead. h](jn)}(hThe IOP process the request. When the request is completed, it will be put into outbound queue. An outbound interrupt will be generated.h]hThe IOP process the request. When the request is completed, it will be put into outbound queue. An outbound interrupt will be generated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hUFor requests allocated in IOP memory, the request offset is posted to outbound queue.h]hUFor requests allocated in IOP memory, the request offset is posted to outbound queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hFor requests allocated in host memory, (0x80000000|(bus_addr>>5)) is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT flag is set in the request, the low 32-bit context value will be posted instead.h]hFor requests allocated in host memory, (0x80000000|(bus_addr>>5)) is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT flag is set in the request, the low 32-bit context value will be posted instead.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hThe host read the outbound queue and complete the request. For requests allocated in IOP memory, the host driver free the request by writing it to the outbound queue. h](jn)}(h:The host read the outbound queue and complete the request.h]h:The host read the outbound queue and complete the request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hkFor requests allocated in IOP memory, the host driver free the request by writing it to the outbound queue.h]hkFor requests allocated in IOP memory, the host driver free the request by writing it to the outbound queue.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubeh}(h]h ]h"]h$]h&]uh1jYhjVubeh}(h]h ]h"]h$]h&]bullet-uh1jThhhKshjPubah}(h]h ]h"]h$]h&]uh1j}hhhKshj#hhubjn)}(hNon-queued requests (reset/flush etc) can be sent via inbound message register 0. An outbound message with the same value indicates the completion of an inbound message.h]hNon-queued requests (reset/flush etc) can be sent via inbound message register 0. An outbound message with the same value indicates the completion of an inbound message.}(hj'hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj#hhubeh}(h](i-o-request-workflow-of-not-marvell-freyah ]h"](i/o request workflow of not marvell freyah$]h&]uh1jGhjIhhhhhKlubjH)}(hhh](jM)}(h$I/O Request Workflow of Marvell Freyh]h$I/O Request Workflow of Marvell Frey}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj=hhhhhKubjn)}(h:All queued requests are handled via inbound/outbound list.h]h:All queued requests are handled via inbound/outbound list.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj=hhubjn)}(h$To send a request to the controller:h]h$To send a request to the controller:}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj=hhubj~)}(hX/- Allocate a free request in host DMA coherent memory. Requests allocated in host memory must be aligned on 32-bytes boundary. - Fill the request with index of the request in the flag. Fill a free inbound list unit with the physical address and the size of the request. Set up the inbound list write pointer with the index of previous unit, round to 0 if the index reaches the supported count of requests. - Post the inbound list writer pointer to IOP. - The IOP process the request. When the request is completed, the flag of the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a free outbound list unit and the index of the outbound list unit will be put into the copy pointer shadow register. An outbound interrupt will be generated. - The host read the outbound list copy pointer shadow register and compare with previous saved read pointer N. If they are different, the host will read the (N+1)th outbound list unit. The host get the index of the request from the (N+1)th outbound list unit and complete the request. h]jU)}(hhh](jZ)}(h~Allocate a free request in host DMA coherent memory. Requests allocated in host memory must be aligned on 32-bytes boundary. h](jn)}(h4Allocate a free request in host DMA coherent memory.h]h4Allocate a free request in host DMA coherent memory.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjqubjn)}(hGRequests allocated in host memory must be aligned on 32-bytes boundary.h]hGRequests allocated in host memory must be aligned on 32-bytes boundary.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjqubeh}(h]h ]h"]h$]h&]uh1jYhjnubjZ)}(hXFill the request with index of the request in the flag. Fill a free inbound list unit with the physical address and the size of the request. Set up the inbound list write pointer with the index of previous unit, round to 0 if the index reaches the supported count of requests. h](jn)}(h7Fill the request with index of the request in the flag.h]h7Fill the request with index of the request in the flag.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hTFill a free inbound list unit with the physical address and the size of the request.h]hTFill a free inbound list unit with the physical address and the size of the request.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hSet up the inbound list write pointer with the index of previous unit, round to 0 if the index reaches the supported count of requests.h]hSet up the inbound list write pointer with the index of previous unit, round to 0 if the index reaches the supported count of requests.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubeh}(h]h ]h"]h$]h&]uh1jYhjnubjZ)}(h-Post the inbound list writer pointer to IOP. h]jn)}(h,Post the inbound list writer pointer to IOP.h]h,Post the inbound list writer pointer to IOP.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jYhjnubjZ)}(hX)The IOP process the request. When the request is completed, the flag of the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a free outbound list unit and the index of the outbound list unit will be put into the copy pointer shadow register. An outbound interrupt will be generated. h]jn)}(hX(The IOP process the request. When the request is completed, the flag of the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a free outbound list unit and the index of the outbound list unit will be put into the copy pointer shadow register. An outbound interrupt will be generated.h]hX(The IOP process the request. When the request is completed, the flag of the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a free outbound list unit and the index of the outbound list unit will be put into the copy pointer shadow register. An outbound interrupt will be generated.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jYhjnubjZ)}(hXThe host read the outbound list copy pointer shadow register and compare with previous saved read pointer N. If they are different, the host will read the (N+1)th outbound list unit. The host get the index of the request from the (N+1)th outbound list unit and complete the request. h](jn)}(hThe host read the outbound list copy pointer shadow register and compare with previous saved read pointer N. If they are different, the host will read the (N+1)th outbound list unit.h]hThe host read the outbound list copy pointer shadow register and compare with previous saved read pointer N. If they are different, the host will read the (N+1)th outbound list unit.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubjn)}(hcThe host get the index of the request from the (N+1)th outbound list unit and complete the request.h]hcThe host get the index of the request from the (N+1)th outbound list unit and complete the request.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubeh}(h]h ]h"]h$]h&]uh1jYhjnubeh}(h]h ]h"]h$]h&]jj uh1jThhhKhjjubah}(h]h ]h"]h$]h&]uh1j}hhhKhj=hhubjn)}(hNon-queued requests (reset communication/reset/flush etc) can be sent via PCIe Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register with the same value indicates the completion of message.h]hNon-queued requests (reset communication/reset/flush etc) can be sent via PCIe Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register with the same value indicates the completion of message.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj=hhubeh}(h]$i-o-request-workflow-of-marvell-freyah ]h"]$i/o request workflow of marvell freyah$]h&]uh1jGhjIhhhhhKubjH)}(hhh](jM)}(hUser-level Interfaceh]hUser-level Interface}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjChhhhhKubjn)}(h.The driver exposes following sysfs attributes:h]h.The driver exposes following sysfs attributes:}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjChhubj~)}(hX.================== === ======================== NAME R/W Description ================== === ======================== driver-version R driver version string firmware-version R firmware version string ================== === ======================== h]j)}(hhh]j)}(hhh](j)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjiubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjiubj)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1jhjiubj)}(hhh]j)}(hhh](j)}(hhh]jn)}(hNAMEh]hNAME}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hR/Wh]hR/W}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]uh1jhjiubj)}(hhh](j)}(hhh](j)}(hhh]jn)}(hdriver-versionh]hdriver-version}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hRh]hR}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh]jn)}(hdriver version stringh]hdriver version string}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjubj)}(hhh](j)}(hhh]jn)}(hfirmware-versionh]hfirmware-version}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhj5ubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]jn)}(hjh]hR}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjLubah}(h]h ]h"]h$]h&]uh1jhj2ubj)}(hhh]jn)}(hfirmware version stringh]hfirmware version string}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1jmhhhKhjbubah}(h]h ]h"]h$]h&]uh1jhj2ubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhjiubeh}(h]h ]h"]h$]h&]colsKuh1jhjfubah}(h]h ]h"]h$]h&]uh1jhjbubah}(h]h ]h"]h$]h&]uh1j}hhhKhjChhubh transition)}(hM-----------------------------------------------------------------------------h]h}(h]h ]h"]h$]h&]uh1jhhhKhjChhubjn)}(hLCopyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.h](h Copyright }(hjhhhNhNubh©}(hjhhhNhNubh< 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1jmhhhKhjChhubj~)}(hXThis file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. linux@highpoint-tech.com http://www.highpoint-tech.comh](jn)}(hThis file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.h]hThis file is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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