\sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget//translations/zh_CN/networking/oa-tc6-frameworkmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/zh_TW/networking/oa-tc6-frameworkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/it_IT/networking/oa-tc6-frameworkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ja_JP/networking/oa-tc6-frameworkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/ko_KR/networking/oa-tc6-frameworkmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget//translations/sp_SP/networking/oa-tc6-frameworkmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h!SPDX-License-Identifier: GPL-2.0+h]h!SPDX-License-Identifier: GPL-2.0+}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhI/var/lib/git/docbuild/linux/Documentation/networking/oa-tc6-framework.rsthKubhsection)}(hhh](htitle)}(hIOPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Supporth]hIOPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(h Introductionh]h Introduction}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hXThe IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach PHY supporting full duplex point-to-point operation over 1 km of single balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach PHY supporting full / half duplex point-to-point operation over 15 m of single balanced pair of conductors, or half duplex multidrop bus operation over 25 m of single balanced pair of conductors.h]hXThe IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach PHY supporting full duplex point-to-point operation over 1 km of single balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach PHY supporting full / half duplex point-to-point operation over 15 m of single balanced pair of conductors, or half duplex multidrop bus operation over 25 m of single balanced pair of conductors.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hXFurthermore, the IEEE 802.3cg project defines the new Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (Clause 148) meant to provide improved determinism to the CSMA/CD media access method. PLCA works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.h]hXFurthermore, the IEEE 802.3cg project defines the new Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer (Clause 148) meant to provide improved determinism to the CSMA/CD media access method. PLCA works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hXBThe aforementioned PHYs are intended to cover the low-speed / low-cost applications in industrial and automotive environment. The large number of pins (16) required by the MII interface, which is specified by the IEEE 802.3 in Clause 22, is one of the major cost factors that need to be addressed to fulfil this objective.h]hXBThe aforementioned PHYs are intended to cover the low-speed / low-cost applications in industrial and automotive environment. The large number of pins (16) required by the MII interface, which is specified by the IEEE 802.3 in Clause 22, is one of the major cost factors that need to be addressed to fulfil this objective.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hX(The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY exposing a low pin count Serial Peripheral Interface (SPI) to the host microcontroller. This also enables the addition of Ethernet functionality to existing low-end microcontrollers which do not integrate a MAC controller.h]hX(The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY exposing a low pin count Serial Peripheral Interface (SPI) to the host microcontroller. This also enables the addition of Ethernet functionality to existing low-end microcontrollers which do not integrate a MAC controller.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubeh}(h] introductionah ]h"] introductionah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hOverviewh]hOverview}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK$ubh)}(hThe MAC-PHY is specified to carry both data (Ethernet frames) and control (register access) transactions over a single full-duplex serial peripheral interface.h]hThe MAC-PHY is specified to carry both data (Ethernet frames) and control (register access) transactions over a single full-duplex serial peripheral interface.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhK$ubh)}(hhh](h)}(hProtocol Overviewh]hProtocol Overview}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjChhhhhK+ubh)}(hXTwo types of transactions are defined in the protocol: data transactions for Ethernet frame transfers and control transactions for register read/write transfers. A chunk is the basic element of data transactions and is composed of 4 bytes of overhead plus 64 bytes of payload size for each chunk. Ethernet frames are transferred over one or more data chunks. Control transactions consist of one or more register read/write control commands.h]hXTwo types of transactions are defined in the protocol: data transactions for Ethernet frame transfers and control transactions for register read/write transfers. A chunk is the basic element of data transactions and is composed of 4 bytes of overhead plus 64 bytes of payload size for each chunk. Ethernet frames are transferred over one or more data chunks. Control transactions consist of one or more register read/write control commands.}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjChhubh)}(hXSPI transactions are initiated by the SPI host with the assertion of CSn low to the MAC-PHY and ends with the deassertion of CSn high. In between each SPI transaction, the SPI host may need time for additional processing and to setup the next SPI data or control transaction.h]hXSPI transactions are initiated by the SPI host with the assertion of CSn low to the MAC-PHY and ends with the deassertion of CSn high. In between each SPI transaction, the SPI host may need time for additional processing and to setup the next SPI data or control transaction.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjChhubh)}(hX#SPI data transactions consist of an equal number of transmit (TX) and receive (RX) chunks. Chunks in both transmit and receive directions may or may not contain valid frame data independent from each other, allowing for the simultaneous transmission and reception of different length frames.h]hX#SPI data transactions consist of an equal number of transmit (TX) and receive (RX) chunks. Chunks in both transmit and receive directions may or may not contain valid frame data independent from each other, allowing for the simultaneous transmission and reception of different length frames.}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hjChhubh)}(hXEach transmit data chunk begins with a 32-bit data header followed by a data chunk payload on MOSI. The data header indicates whether transmit frame data is present and provides the information to determine which bytes of the payload contain valid frame data.h]hXEach transmit data chunk begins with a 32-bit data header followed by a data chunk payload on MOSI. The data header indicates whether transmit frame data is present and provides the information to determine which bytes of the payload contain valid frame data.}(hj~hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK@hjChhubh)}(hXKIn parallel, receive data chunks are received on MISO. Each receive data chunk consists of a data chunk payload ending with a 32-bit data footer. The data footer indicates if there is receive frame data present within the payload or not and provides the information to determine which bytes of the payload contain valid frame data.h]hXKIn parallel, receive data chunks are received on MISO. Each receive data chunk consists of a data chunk payload ending with a 32-bit data footer. The data footer indicates if there is receive frame data present within the payload or not and provides the information to determine which bytes of the payload contain valid frame data.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKEhjChhubeh}(h]protocol-overviewah ]h"]protocol overviewah$]h&]uh1hhhhhhhhK+ubh)}(hhh](h)}(h Referenceh]h Reference}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKLubh)}(h210BASE-T1x MAC-PHY Serial Interface Specification,h]h210BASE-T1x MAC-PHY Serial Interface Specification,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKNhjhhubh)}(heLink: https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdfh](hLink: }(hjhhhNhNubh reference)}(h_https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdfh]h_https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf}(hjhhhNhNubah}(h]h ]h"]h$]h&]refurijuh1jhjubeh}(h]h ]h"]h$]h&]uh1hhhhKPhjhhubeh}(h] referenceah ]h"] referenceah$]h&]uh1hhhhhhhhKLubh)}(hhh](h)}(hHardware Architectureh]hHardware Architecture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKSubh literal_block)}(hX[+----------+ +-------------------------------------+ | | | MAC-PHY | | |<---->| +-----------+ +-------+ +-------+ | | SPI Host | | | SPI Slave | | MAC | | PHY | | | | | +-----------+ +-------+ +-------+ | +----------+ +-------------------------------------+h]hX[+----------+ +-------------------------------------+ | | | MAC-PHY | | |<---->| +-----------+ +-------+ +-------+ | | SPI Host | | | SPI Slave | | MAC | | PHY | | | | | +-----------+ +-------+ +-------+ | +----------+ +-------------------------------------+}hjsbah}(h]h ]h"]h$]h&]hhforcelanguagenonehighlight_args}uh1jhhhKUhjhhubeh}(h]hardware-architectureah ]h"]hardware architectureah$]h&]uh1hhhhhhhhKSubh)}(hhh](h)}(hSoftware Architectureh]hSoftware Architecture}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK_ubj)}(hX+----------------------------------------------------------+ | Networking Subsystem | +----------------------------------------------------------+ / \ / \ | | | | \ / | +----------------------+ +-----------------------------+ | MAC Driver |<--->| OPEN Alliance TC6 Framework | +----------------------+ +-----------------------------+ / \ / \ | | | | | \ / +----------------------------------------------------------+ | SPI Subsystem | +----------------------------------------------------------+ / \ | | \ / +----------------------------------------------------------+ | 10BASE-T1x MAC-PHY Device | +----------------------------------------------------------+h]hX+----------------------------------------------------------+ | Networking Subsystem | +----------------------------------------------------------+ / \ / \ | | | | \ / | +----------------------+ +-----------------------------+ | MAC Driver |<--->| OPEN Alliance TC6 Framework | +----------------------+ +-----------------------------+ / \ / \ | | | | | \ / +----------------------------------------------------------+ | SPI Subsystem | +----------------------------------------------------------+ / \ | | \ / +----------------------------------------------------------+ | 10BASE-T1x MAC-PHY Device | +----------------------------------------------------------+}hj'sbah}(h]h ]h"]h$]h&]hhj j nonej }uh1jhhhKahjhhubeh}(h]software-architectureah ]h"]software architectureah$]h&]uh1hhhhhhhhK_ubh)}(hhh](h)}(hImplementationh]hImplementation}(hjBhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj?hhhhhK}ubh)}(hhh](h)}(h MAC Driverh]h MAC Driver}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhjPhhhhhKubh bullet_list)}(hhh](h list_item)}(hProbed by SPI subsystem. h]h)}(hProbed by SPI subsystem.h]hProbed by SPI subsystem.}(hjlhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhubah}(h]h ]h"]h$]h&]uh1jfhjchhhhhNubjg)}(h.Initializes OA TC6 framework for the MAC-PHY. h]h)}(h-Initializes OA TC6 framework for the MAC-PHY.h]h-Initializes OA TC6 framework for the MAC-PHY.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjchhhhhNubjg)}(h-Registers and configures the network device. h]h)}(h,Registers and configures the network device.h]h,Registers and configures the network device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjchhhhhNubjg)}(hESends the tx ethernet frames from n/w subsystem to OA TC6 framework. h]h)}(hDSends the tx ethernet frames from n/w subsystem to OA TC6 framework.h]hDSends the tx ethernet frames from n/w subsystem to OA TC6 framework.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjchhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jahhhKhjPhhubeh}(h] mac-driverah ]h"] mac driverah$]h&]uh1hhj?hhhhhKubh)}(hhh](h)}(hOPEN Alliance TC6 Frameworkh]hOPEN Alliance TC6 Framework}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubjb)}(hhh](jg)}(hInitializes PHYLIB interface. h]h)}(hInitializes PHYLIB interface.h]hInitializes PHYLIB interface.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjhhhhhNubjg)}(hRegisters mac-phy interrupt. h]h)}(hRegisters mac-phy interrupt.h]hRegisters mac-phy interrupt.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjhhhhhNubjg)}(hPerforms mac-phy register read/write operation using the control transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification. h]h)}(hPerforms mac-phy register read/write operation using the control transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification.h]hPerforms mac-phy register read/write operation using the control transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jfhjhhhhhNubjg)}(hPerforms Ethernet frames transaction using the data transaction protocol for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification. h]h)}(hPerforms Ethernet frames transaction using the data transaction protocol for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification.h]hPerforms Ethernet frames transaction using the data transaction protocol for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj4ubah}(h]h ]h"]h$]h&]uh1jfhjhhhhhNubjg)}(hOForwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w subsystem. h]h)}(hNForwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w subsystem.h]hNForwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w subsystem.}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubah}(h]h ]h"]h$]h&]uh1jfhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jahhhKhjhhubeh}(h]open-alliance-tc6-frameworkah ]h"]open alliance tc6 frameworkah$]h&]uh1hhj?hhhhhKubh)}(hhh](h)}(hData Transactionh]hData Transaction}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjrhhhhhKubh)}(hXQThe Ethernet frames that are typically transferred from the SPI host to the MAC-PHY will be converted into multiple transmit data chunks. Each transmit data chunk will have a 4 bytes header which contains the information needed to determine the validity and the location of the transmit frame data within the 64 bytes data chunk payload.h]hXQThe Ethernet frames that are typically transferred from the SPI host to the MAC-PHY will be converted into multiple transmit data chunks. Each transmit data chunk will have a 4 bytes header which contains the information needed to determine the validity and the location of the transmit frame data within the 64 bytes data chunk payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hXW+---------------------------------------------------+ | Tx Chunk | | +---------------------------+ +----------------+ | MOSI | | 64 bytes chunk payload | | 4 bytes header | |------------> | +---------------------------+ +----------------+ | +---------------------------------------------------+h]hXW+---------------------------------------------------+ | Tx Chunk | | +---------------------------+ +----------------+ | MOSI | | 64 bytes chunk payload | | 4 bytes header | |------------> | +---------------------------+ +----------------+ | +---------------------------------------------------+}hjsbah}(h]h ]h"]h$]h&]hhj j nonej }uh1jhhhKhjrhhubh)}(h)4 bytes header contains the below fields,h]h)4 bytes header contains the below fields,}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubhdefinition_list)}(hhh](hdefinition_list_item)}(hDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI transaction. For TX data chunks, this bit shall be ’1’. 0 - Control command 1 - Data chunk h](hterm)}(hIDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPIh]hIDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubh definition)}(hhh]h)}(h^transaction. For TX data chunks, this bit shall be ’1’. 0 - Control command 1 - Data chunkh]h^transaction. For TX data chunks, this bit shall be ’1’. 0 - Control command 1 - Data chunk}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hzSEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an even/odd transmit data chunk sequence to the MAC-PHY. h](j)}(hCSEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate anh]hCSEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(h5even/odd transmit data chunk sequence to the MAC-PHY.h]h5even/odd transmit data chunk sequence to the MAC-PHY.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubj)}(hX^NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent the MAC-PHY from conveying RX data on the MISO for the current chunk (DV = 0 in the footer), indicating that the host would not process it. Typically, the SPI host should set NORX = 0 indicating that it will accept and process any receive frame data within the current chunk. h](j)}(hINORX (Bit 29) - No Receive flag. The SPI host may set this bit to preventh]hINORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hXthe MAC-PHY from conveying RX data on the MISO for the current chunk (DV = 0 in the footer), indicating that the host would not process it. Typically, the SPI host should set NORX = 0 indicating that it will accept and process any receive frame data within the current chunk.h]hXthe MAC-PHY from conveying RX data on the MISO for the current chunk (DV = 0 in the footer), indicating that the host would not process it. Typically, the SPI host should set NORX = 0 indicating that it will accept and process any receive frame data within the current chunk.}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj*ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjhhubeh}(h]h ]h"]h$]h&]uh1jhjrhhhhhNubh)}(hARSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.h]hARSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hhh](j)}(hVS (Bit 23..22) - Vendor Specific. These bits are implementation specific. If the MAC-PHY does not implement these bits, the host shall set them to ‘0’. h](j)}(hJVS (Bit 23..22) - Vendor Specific. These bits are implementation specific.h]hJVS (Bit 23..22) - Vendor Specific. These bits are implementation specific.}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj^ubj)}(hhh]h)}(hQIf the MAC-PHY does not implement these bits, the host shall set them to ‘0’.h]hQIf the MAC-PHY does not implement these bits, the host shall set them to ‘0’.}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjpubah}(h]h ]h"]h$]h&]uh1jhj^ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj[ubj)}(hX,DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate whether the current chunk contains valid transmit frame data (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the chunk payload. Note that the receive path is unaffected by the setting of the DV bit in the data header. h](j)}(hEDV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicateh]hEDV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hwhether the current chunk contains valid transmit frame data (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the chunk payload. Note that the receive path is unaffected by the setting of the DV bit in the data header.h]hwhether the current chunk contains valid transmit frame data (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the chunk payload. Note that the receive path is unaffected by the setting of the DV bit in the data header.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhj[hhubj)}(hX+SV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the beginning of an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero. This bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2]. h](j)}(hHSV (Bit 20) - Start Valid flag. The SPI host shall set this bit when theh]hHSV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hbeginning of an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero. This bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2].h]hbeginning of an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero. This bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhj[hhubj)}(hXSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shall contain the 32-bit word offset into the transmit data chunk payload that points to the start of a new Ethernet frame to be transmitted. The host shall write this field as zero when SV = 0. h](j)}(hCSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shallh]hCSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shall}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hcontain the 32-bit word offset into the transmit data chunk payload that points to the start of a new Ethernet frame to be transmitted. The host shall write this field as zero when SV = 0.h]hcontain the 32-bit word offset into the transmit data chunk payload that points to the start of a new Ethernet frame to be transmitted. The host shall write this field as zero when SV = 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhj[hhubeh}(h]h ]h"]h$]h&]uh1jhjrhhhhhNubh)}(h=RSVD (Bit 15) - Reserved: All reserved bits shall be ‘0’.h]h=RSVD (Bit 15) - Reserved: All reserved bits shall be ‘0’.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hhh](j)}(hEV (Bit 14) - End Valid flag. The SPI host shall set this bit when the end of an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero. h](j)}(hJEV (Bit 14) - End Valid flag. The SPI host shall set this bit when the endh]hJEV (Bit 14) - End Valid flag. The SPI host shall set this bit when the end}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj1ubj)}(hhh]h)}(hnof an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero.h]hnof an Ethernet frame is present in the current transmit data chunk payload. Otherwise, this bit shall be zero.}(hjFhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1jhj1ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj.ubj)}(hEBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall contain the byte offset into the transmit data chunk payload that points to the last byte of the Ethernet frame to transmit. This field shall be zero when EV = 0. h](j)}(hHEBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall containh]hHEBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall contain}(hjdhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhj`ubj)}(hhh]h)}(hthe byte offset into the transmit data chunk payload that points to the last byte of the Ethernet frame to transmit. This field shall be zero when EV = 0.h]hthe byte offset into the transmit data chunk payload that points to the last byte of the Ethernet frame to transmit. This field shall be zero when EV = 0.}(hjuhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrubah}(h]h ]h"]h$]h&]uh1jhj`ubeh}(h]h ]h"]h$]h&]uh1jhhhKhj.hhubj)}(hX;TSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when the frame is transmitted onto the network. 00 - Do not capture a timestamp 01 - Capture timestamp into timestamp capture register A 10 - Capture timestamp into timestamp capture register B 11 - Capture timestamp into timestamp capture register C h](j)}(hHTSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when theh]hHTSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hframe is transmitted onto the network. 00 - Do not capture a timestamp 01 - Capture timestamp into timestamp capture register A 10 - Capture timestamp into timestamp capture register B 11 - Capture timestamp into timestamp capture register Ch]hframe is transmitted onto the network. 00 - Do not capture a timestamp 01 - Capture timestamp into timestamp capture register A 10 - Capture timestamp into timestamp capture register B 11 - Capture timestamp into timestamp capture register C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhj.hhubeh}(h]h ]h"]h$]h&]uh1jhjrhhhhhNubh)}(h?RSVD (Bit 5..1) - Reserved: All reserved bits shall be ‘0’.h]h?RSVD (Bit 5..1) - Reserved: All reserved bits shall be ‘0’.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hhh]j)}(hdP (Bit 0) - Parity. Parity bit calculated over the transmit data header. Method used is odd parity. h](j)}(hHP (Bit 0) - Parity. Parity bit calculated over the transmit data header.h]hHP (Bit 0) - Parity. Parity bit calculated over the transmit data header.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhKhjubj)}(hhh]h)}(hMethod used is odd parity.h]hMethod used is odd parity.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhKhjubah}(h]h ]h"]h$]h&]uh1jhjrhhhhhNubh)}(hXThe number of buffers available in the MAC-PHY to store the incoming transmit data chunk payloads is represented as transmit credits. The available transmit credits in the MAC-PHY can be read either from the Buffer Status Register or footer (Refer below for the footer info) received from the MAC-PHY. The SPI host should not write more data chunks than the available transmit credits as this will lead to transmit buffer overflow error.h]hXThe number of buffers available in the MAC-PHY to store the incoming transmit data chunk payloads is represented as transmit credits. The available transmit credits in the MAC-PHY can be read either from the Buffer Status Register or footer (Refer below for the footer info) received from the MAC-PHY. The SPI host should not write more data chunks than the available transmit credits as this will lead to transmit buffer overflow error.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hXvIn case the previous data footer had no transmit credits available and once the transmit credits become available for transmitting transmit data chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the first data header this interrupt will be deasserted and the received footer for the first data chunk will have the transmit credits available information.h]hXvIn case the previous data footer had no transmit credits available and once the transmit credits become available for transmitting transmit data chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the first data header this interrupt will be deasserted and the received footer for the first data chunk will have the transmit credits available information.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubh)}(hXhThe Ethernet frames that are typically transferred from MAC-PHY to SPI host will be sent as multiple receive data chunks. Each receive data chunk will have 64 bytes of data chunk payload followed by 4 bytes footer which contains the information needed to determine the validity and the location of the receive frame data within the 64 bytes data chunk payload.h]hXhThe Ethernet frames that are typically transferred from MAC-PHY to SPI host will be sent as multiple receive data chunks. Each receive data chunk will have 64 bytes of data chunk payload followed by 4 bytes footer which contains the information needed to determine the validity and the location of the receive frame data within the 64 bytes data chunk payload.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjrhhubj)}(hXW+---------------------------------------------------+ | Rx Chunk | | +----------------+ +---------------------------+ | MISO | | 4 bytes footer | | 64 bytes chunk payload | |------------> | +----------------+ +---------------------------+ | +---------------------------------------------------+h]hXW+---------------------------------------------------+ | Rx Chunk | | +----------------+ +---------------------------+ | MISO | | 4 bytes footer | | 64 bytes chunk payload | |------------> | +----------------+ +---------------------------+ | +---------------------------------------------------+}hj4sbah}(h]h ]h"]h$]h&]hhj j nonej }uh1jhhhMhjrhhubh)}(h)4 bytes footer contains the below fields,h]h)4 bytes footer contains the below fields,}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjrhhubj)}(hhh](j)}(hzEXST (Bit 31) - Extended Status. This bit is set when any bit in the STATUS0 or STATUS1 registers are set and not masked. h](j)}(hDEXST (Bit 31) - Extended Status. This bit is set when any bit in theh]hDEXST (Bit 31) - Extended Status. This bit is set when any bit in the}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjUubj)}(hhh]h)}(h4STATUS0 or STATUS1 registers are set and not masked.h]h4STATUS0 or STATUS1 registers are set and not masked.}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjgubah}(h]h ]h"]h$]h&]uh1jhjUubeh}(h]h ]h"]h$]h&]uh1jhhhMhjRubj)}(hHDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY received a control or data header with a parity error. h](j)}(hIHDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHYh]hIHDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(h6received a control or data header with a parity error.h]h6received a control or data header with a parity error.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjRhhubj)}(hXkSYNC (Bit 29) - Configuration Synchronized flag. This bit reflects the state of the SYNC bit in the CONFIG0 configuration register (see Table 12). A zero indicates that the MAC-PHY configuration may not be as expected by the SPI host. Following configuration, the SPI host sets the corresponding bitin the configuration register which is reflected in this field. h](j)}(hFSYNC (Bit 29) - Configuration Synchronized flag. This bit reflects theh]hFSYNC (Bit 29) - Configuration Synchronized flag. This bit reflects the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhjubj)}(hhh]h)}(hX#state of the SYNC bit in the CONFIG0 configuration register (see Table 12). A zero indicates that the MAC-PHY configuration may not be as expected by the SPI host. Following configuration, the SPI host sets the corresponding bitin the configuration register which is reflected in this field.h]hX#state of the SYNC bit in the CONFIG0 configuration register (see Table 12). A zero indicates that the MAC-PHY configuration may not be as expected by the SPI host. Following configuration, the SPI host sets the corresponding bitin the configuration register which is reflected in this field.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMhjRhhubj)}(hXDRCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to the SPI host the minimum number of additional receive data chunks of frame data that are available for reading beyond the current receive data chunk. This field is zero when there is no receive frame data pending in the MAC-PHY’s buffer for reading. h](j)}(hGRCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates toh]hGRCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM!hjubj)}(hhh]h)}(hthe SPI host the minimum number of additional receive data chunks of frame data that are available for reading beyond the current receive data chunk. This field is zero when there is no receive frame data pending in the MAC-PHY’s buffer for reading.h]hthe SPI host the minimum number of additional receive data chunks of frame data that are available for reading beyond the current receive data chunk. This field is zero when there is no receive frame data pending in the MAC-PHY’s buffer for reading.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM!hjRhhubj)}(hVS (Bit 23..22) - Vendor Specific. These bits are implementation specific. If not implemented, the MAC-PHY shall set these bits to ‘0’. h](j)}(hJVS (Bit 23..22) - Vendor Specific. These bits are implementation specific.h]hJVS (Bit 23..22) - Vendor Specific. These bits are implementation specific.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM%hjubj)}(hhh]h)}(h@If not implemented, the MAC-PHY shall set these bits to ‘0’.h]h@If not implemented, the MAC-PHY shall set these bits to ‘0’.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj#ubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM%hjRhhubj)}(hDV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate whether the current receive data chunk contains valid receive frame data (DV = 1) or not (DV = 0). When ‘0’, the SPI host shall ignore the chunk payload. h](j)}(hDDV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicateh]hDDV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM*hj@ubj)}(hhh]h)}(hwhether the current receive data chunk contains valid receive frame data (DV = 1) or not (DV = 0). When ‘0’, the SPI host shall ignore the chunk payload.h]hwhether the current receive data chunk contains valid receive frame data (DV = 1) or not (DV = 0). When ‘0’, the SPI host shall ignore the chunk payload.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM(hjRubah}(h]h ]h"]h$]h&]uh1jhj@ubeh}(h]h ]h"]h$]h&]uh1jhhhM*hjRhhubj)}(hX SV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current chunk payload contains the start of an Ethernet frame. Otherwise, this bit is zero. The SV bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2]. h](j)}(hJSV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the currenth]hJSV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM0hjoubj)}(hhh]h)}(hchunk payload contains the start of an Ethernet frame. Otherwise, this bit is zero. The SV bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2].h]hchunk payload contains the start of an Ethernet frame. Otherwise, this bit is zero. The SV bit is not to be confused with the Start-of-Frame Delimiter (SFD) byte described in IEEE 802.3 [2].}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM-hjubah}(h]h ]h"]h$]h&]uh1jhjoubeh}(h]h ]h"]h$]h&]uh1jhhhM0hjRhhubj)}(hXSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains the 32-bit word offset into the receive data chunk payload containing the first byte of a new received Ethernet frame. When a receive timestamp has been added to the beginning of the received Ethernet frame (RTSA = 1) then SWO points to the most significant byte of the timestamp. This field will be zero when SV = 0. h](j)}(hJSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains theh]hJSWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM8hjubj)}(hhh]h)}(hX932-bit word offset into the receive data chunk payload containing the first byte of a new received Ethernet frame. When a receive timestamp has been added to the beginning of the received Ethernet frame (RTSA = 1) then SWO points to the most significant byte of the timestamp. This field will be zero when SV = 0.h]hX932-bit word offset into the receive data chunk payload containing the first byte of a new received Ethernet frame. When a receive timestamp has been added to the beginning of the received Ethernet frame (RTSA = 1) then SWO points to the most significant byte of the timestamp. This field will be zero when SV = 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM8hjRhhubj)}(hX FD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has detected a condition for which the SPI host should drop the received Ethernet frame. This bit is only valid at the end of a received Ethernet frame (EV = 1) and shall be zero at all other times. h](j)}(hGFD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC hash]hGFD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhM>hjubj)}(hhh]h)}(hdetected a condition for which the SPI host should drop the received Ethernet frame. This bit is only valid at the end of a received Ethernet frame (EV = 1) and shall be zero at all other times.h]hdetected a condition for which the SPI host should drop the received Ethernet frame. This bit is only valid at the end of a received Ethernet frame (EV = 1) and shall be zero at all other times.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhM>hjRhhubj)}(hEV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a received Ethernet frame is present in this receive data chunk payload. h](j)}(hIEV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of ah]hIEV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMBhjubj)}(hhh]h)}(hFreceived Ethernet frame is present in this receive data chunk payload.h]hFreceived Ethernet frame is present in this receive data chunk payload.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMAhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMBhjRhhubj)}(hEBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains the byte offset into the receive data chunk payload that locates the last byte of the received Ethernet frame. This field is zero when EV = 0. h](j)}(hGEBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains theh]hGEBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains the}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMGhj+ubj)}(hhh]h)}(hbyte offset into the receive data chunk payload that locates the last byte of the received Ethernet frame. This field is zero when EV = 0.h]hbyte offset into the receive data chunk payload that locates the last byte of the received Ethernet frame. This field is zero when EV = 0.}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMEhj=ubah}(h]h ]h"]h$]h&]uh1jhj+ubeh}(h]h ]h"]h$]h&]uh1jhhhMGhjRhhubj)}(hRTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit or 64-bit timestamp has been added to the beginning of the received Ethernet frame. The MAC-PHY shall set this bit to zero when SV = 0. h](j)}(hHRTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit orh]hHRTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit or}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMLhjZubj)}(hhh]h)}(h64-bit timestamp has been added to the beginning of the received Ethernet frame. The MAC-PHY shall set this bit to zero when SV = 0.h]h64-bit timestamp has been added to the beginning of the received Ethernet frame. The MAC-PHY shall set this bit to zero when SV = 0.}(hjohhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMJhjlubah}(h]h ]h"]h$]h&]uh1jhjZubeh}(h]h ]h"]h$]h&]uh1jhhhMLhjRhhubj)}(hRTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over the 32-bit/64-bit timestamp added to the beginning of the received Ethernet frame. Method used is odd parity. The MAC-PHY shall set this bit to zero when RTSA = 0. h](j)}(hGRTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over theh]hGRTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over the}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMQhjubj)}(hhh]h)}(h32-bit/64-bit timestamp added to the beginning of the received Ethernet frame. Method used is odd parity. The MAC-PHY shall set this bit to zero when RTSA = 0.h]h32-bit/64-bit timestamp added to the beginning of the received Ethernet frame. Method used is odd parity. The MAC-PHY shall set this bit to zero when RTSA = 0.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMOhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMQhjRhhubj)}(hTXC (Bit 5..1) - Transmit Credits. This field contains the minimum number of transmit data chunks of frame data that the SPI host can write in a single transaction without incurring a transmit buffer overflow error. h](j)}(hITXC (Bit 5..1) - Transmit Credits. This field contains the minimum numberh]hITXC (Bit 5..1) - Transmit Credits. This field contains the minimum number}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMVhjubj)}(hhh]h)}(hof transmit data chunks of frame data that the SPI host can write in a single transaction without incurring a transmit buffer overflow error.h]hof transmit data chunks of frame data that the SPI host can write in a single transaction without incurring a transmit buffer overflow error.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMThjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMVhjRhhubj)}(hcP (Bit 0) - Parity. Parity bit calculated over the receive data footer. Method used is odd parity. h](j)}(hGP (Bit 0) - Parity. Parity bit calculated over the receive data footer.h]hGP (Bit 0) - Parity. Parity bit calculated over the receive data footer.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMYhjubj)}(hhh]h)}(hMethod used is odd parity.h]hMethod used is odd parity.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhjubah}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]uh1jhhhMYhjRhhubeh}(h]h ]h"]h$]h&]uh1jhjrhhhhhNubh)}(hXSPI host will initiate the data receive transaction based on the receive chunks available in the MAC-PHY which is provided in the receive chunk footer (RCA - Receive Chunks Available). SPI host will create data invalid transmit data chunks (empty chunks) or data valid transmit data chunks in case there are valid Ethernet frames to transmit to the MAC-PHY. The receive chunks available in MAC-PHY can be read either from the Buffer Status Register or footer.h]hXSPI host will initiate the data receive transaction based on the receive chunks available in the MAC-PHY which is provided in the receive chunk footer (RCA - Receive Chunks Available). SPI host will create data invalid transmit data chunks (empty chunks) or data valid transmit data chunks in case there are valid Ethernet frames to transmit to the MAC-PHY. The receive chunks available in MAC-PHY can be read either from the Buffer Status Register or footer.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM[hjrhhubh)}(hXfIn case the previous data footer had no receive data chunks available and once the receive data chunks become available again for reading, the MAC-PHY interrupt is asserted to SPI host. On reception of the first data header this interrupt will be deasserted and the received footer for the first data chunk will have the receive chunks available information.h]hXfIn case the previous data footer had no receive data chunks available and once the receive data chunks become available again for reading, the MAC-PHY interrupt is asserted to SPI host. On reception of the first data header this interrupt will be deasserted and the received footer for the first data chunk will have the receive chunks available information.}(hj* hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchjrhhubeh}(h]data-transactionah ]h"]data transactionah$]h&]uh1hhj?hhhhhKubh)}(hhh](h)}(hMAC-PHY Interrupth]hMAC-PHY Interrupt}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj@ hhhhhMjubh)}(hHThe MAC-PHY interrupt is asserted when the following conditions are met.h]hHThe MAC-PHY interrupt is asserted when the following conditions are met.}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMlhj@ hhubh)}(hXReceive chunks available - This interrupt is asserted when the previous data footer had no receive data chunks available and once the receive data chunks become available for reading. On reception of the first data header this interrupt will be deasserted.h]hXReceive chunks available - This interrupt is asserted when the previous data footer had no receive data chunks available and once the receive data chunks become available for reading. On reception of the first data header this interrupt will be deasserted.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMnhj@ hhubh)}(hX"Transmit chunk credits available - This interrupt is asserted when the previous data footer indicated no transmit credits available and once the transmit credits become available for transmitting transmit data chunks. On reception of the first data header this interrupt will be deasserted.h]hX"Transmit chunk credits available - This interrupt is asserted when the previous data footer indicated no transmit credits available and once the transmit credits become available for transmitting transmit data chunks. On reception of the first data header this interrupt will be deasserted.}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj@ hhubh)}(hX@Extended status event - This interrupt is asserted when the previous data footer indicated no extended status and once the extended event become available. In this case the host should read status #0 register to know the corresponding error/event. On reception of the first data header this interrupt will be deasserted.h]hX@Extended status event - This interrupt is asserted when the previous data footer indicated no extended status and once the extended event become available. In this case the host should read status #0 register to know the corresponding error/event. On reception of the first data header this interrupt will be deasserted.}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMxhj@ hhubeh}(h]mac-phy-interruptah ]h"]mac-phy interruptah$]h&]uh1hhj?hhhhhMjubh)}(hhh](h)}(hControl Transactionh]hControl Transaction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h14 bytes control header contains the below fields,h]h14 bytes control header contains the below fields,}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh](j)}(hDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI transaction. For control commands, this bit shall be ‘0’. 0 - Control command 1 - Data chunk h](j)}(hIDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPIh]hIDNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(h`transaction. For control commands, this bit shall be ‘0’. 0 - Control command 1 - Data chunkh]h`transaction. For control commands, this bit shall be ‘0’. 0 - Control command 1 - Data chunk}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hHDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates that a header was received with a parity error. The SPI host should always clear this bit. The MAC-PHY ignores the HDRB value sent by the SPI host on MOSI. h](j)}(hGHDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicatesh]hGHDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(hthat a header was received with a parity error. The SPI host should always clear this bit. The MAC-PHY ignores the HDRB value sent by the SPI host on MOSI.h]hthat a header was received with a parity error. The SPI host should always clear this bit. The MAC-PHY ignores the HDRB value sent by the SPI host on MOSI.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]uh1jhhhMhj hhubj)}(hWNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be written to registers (when set) or read from registers (when clear). h](j)}(hJWNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be writtenh]hJWNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be written}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jhhhMhj ubj)}(hhh]h)}(h j4j? j@ jA uh1j hhhj[ hNhNubh)}(hFree allocated OA TC6 lib.h]hFree allocated OA TC6 lib.}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j "oa_tc6_write_register (C function)c.oa_tc6_write_registerhNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(hEint oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value)h]j )}(hEint oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value)h](jj )}(hinth]hint}(hj_hhhNhNubah}(h]h ]jv ah"]h$]h&]uh1ji hj[hhhhhMubj )}(h h]h }(hjmhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj[hhhhhMubj )}(hoa_tc6_write_registerh]j )}(hoa_tc6_write_registerh]hoa_tc6_write_register}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj{ubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hj[hhhhhMubj) )}(h,(struct oa_tc6 *tc6, u32 address, u32 value)h](j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j )}j jsbc.oa_tc6_write_registerasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 addressh](h)}(hhh]j )}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]jc.oa_tc6_write_registerasbuh1hhj ubj )}(h h]h }(hj.hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubj )}(haddressh]haddress}(hj<hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 valueh](h)}(hhh]j )}(hu32h]hu32}(hjXhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjUubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjZmodnameN classnameNj j )}j ]jc.oa_tc6_write_registerasbuh1hhjQubj )}(h h]h }(hjvhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjQubj )}(hvalueh]hvalue}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjQubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubeh}(h]h ]h"]h$]h&]hhuh1j( hj[hhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hjWhhhhhMubah}(h]jRah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhjThhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hjThhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= jj> jj? j@ jA uh1j hhhj[ hNhNubh)}(h'Write a single register in the MAC-PHY.h]h'Write a single register in the MAC-PHY.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j #oa_tc6_write_registers (C function)c.oa_tc6_write_registershNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(hSint oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h]j )}(hSint oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h](jj )}(hinth]hint}(hjhhhNhNubah}(h]h ]jv ah"]h$]h&]uh1ji hjhhhhhMubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhhhMubj )}(hoa_tc6_write_registersh]j )}(hoa_tc6_write_registersh]hoa_tc6_write_registers}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hjhhhhhMubj) )}(h9(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h](j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hj+hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hj<hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj9ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj>modnameN classnameNj j )}j ]j )}j jsbc.oa_tc6_write_registersasbuh1hhjubj )}(h h]h }(hj\hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hjwhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 addressh](h)}(hhh]j )}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]jXc.oa_tc6_write_registersasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(haddressh]haddress}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 value[]h](h)}(hhh]j )}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]jXc.oa_tc6_write_registersasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hvalueh]hvalue}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h[h]h[}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h]h]h]}(hj#hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u8 lengthh](h)}(hhh]j )}(hu8h]hu8}(hj?hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj<ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjAmodnameN classnameNj j )}j ]jXc.oa_tc6_write_registersasbuh1hhj8ubj )}(h h]h }(hj]hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj8ubj )}(hlengthh]hlength}(hjkhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj8ubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubeh}(h]h ]h"]h$]h&]hhuh1j( hjhhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hjhhhhhMubah}(h]jah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhjhhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hjhhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= jj> jj? j@ jA uh1j hhhj[ hNhNubh)}(hWriting multiple consecutive registers starting from @address in the MAC-PHY. Maximum of 128 consecutive registers can be written starting at @address.h]hWriting multiple consecutive registers starting from @address in the MAC-PHY. Maximum of 128 consecutive registers can be written starting at @address.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j !oa_tc6_read_register (C function)c.oa_tc6_read_registerhNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(hEint oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value)h]j )}(hEint oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value)h](jj )}(hinth]hint}(hjhhhNhNubah}(h]h ]jv ah"]h$]h&]uh1ji hjhhhhhMubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhhhMubj )}(hoa_tc6_read_registerh]j )}(hoa_tc6_read_registerh]hoa_tc6_read_register}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hjhhhhhMubj) )}(h-(struct oa_tc6 *tc6, u32 address, u32 *value)h](j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hj#hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj%modnameN classnameNj j )}j ]j )}j jsbc.oa_tc6_read_registerasbuh1hhjubj )}(h h]h }(hjChhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjQhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hj^hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 addressh](h)}(hhh]j )}(hu32h]hu32}(hjzhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjwubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj|modnameN classnameNj j )}j ]j?c.oa_tc6_read_registerasbuh1hhjsubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjsubj )}(haddressh]haddress}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjsubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 *valueh](h)}(hhh]j )}(hu32h]hu32}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j?c.oa_tc6_read_registerasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hvalueh]hvalue}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubeh}(h]h ]h"]h$]h&]hhuh1j( hjhhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hjhhhhhMubah}(h]jah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhjhhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hjhhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= j.j> j.j? j@ jA uh1j hhhj[ hNhNubh)}(h&Read a single register in the MAC-PHY.h]h&Read a single register in the MAC-PHY.}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j "oa_tc6_read_registers (C function)c.oa_tc6_read_registershNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(hRint oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h]j )}(hRint oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h](jj )}(hinth]hint}(hjYhhhNhNubah}(h]h ]jv ah"]h$]h&]uh1ji hjUhhhhhMubj )}(h h]h }(hjghhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjUhhhhhMubj )}(hoa_tc6_read_registersh]j )}(hoa_tc6_read_registersh]hoa_tc6_read_registers}(hjyhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjuubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hjUhhhhhMubj) )}(h9(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length)h](j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j )}j j{sbc.oa_tc6_read_registersasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 addressh](h)}(hhh]j )}(hu32h]hu32}(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetj modnameN classnameNj j )}j ]jc.oa_tc6_read_registersasbuh1hhjubj )}(h h]h }(hj(hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(haddressh]haddress}(hj6hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u32 value[]h](h)}(hhh]j )}(hu32h]hu32}(hjRhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjOubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjTmodnameN classnameNj j )}j ]jc.oa_tc6_read_registersasbuh1hhjKubj )}(h h]h }(hjphhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjKubj )}(hvalueh]hvalue}(hj~hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjKubj )}(hjh]h[}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjKubj )}(hj%h]h]}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjKubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(h u8 lengthh](h)}(hhh]j )}(hu8h]hu8}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]jc.oa_tc6_read_registersasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hlengthh]hlength}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubeh}(h]h ]h"]h$]h&]hhuh1j( hjUhhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hjQhhhhhMubah}(h]jLah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhjNhhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hjNhhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= jj> jj? j@ jA uh1j hhhj[ hNhNubh)}(hReading multiple consecutive registers starting from @address in the MAC-PHY. Maximum of 128 consecutive registers can be read starting at @address.h]hReading multiple consecutive registers starting from @address in the MAC-PHY. Maximum of 128 consecutive registers can be read starting at @address.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j oa_tc6_start_xmit (C function)c.oa_tc6_start_xmithNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(hGnetdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb);h]j )}(hGnetdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb);h](h)}(hhh]j )}(h netdev_tx_th]h netdev_tx_t}(hjAhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj>ubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjCmodnameN classnameNj j )}j ]j )}j oa_tc6_start_xmitsbc.oa_tc6_start_xmitasbuh1hhj:hhhhhMubj )}(h h]h }(hjbhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj:hhhhhMubj )}(hoa_tc6_start_xmith]j )}(hj_h]hoa_tc6_start_xmit}(hjthhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjpubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hj:hhhhhMubj) )}(h)(struct oa_tc6 *tc6, struct sk_buff *skb)h](j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j]c.oa_tc6_start_xmitasbuh1hhjubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubj/ )}(hstruct sk_buff *skbh](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hsk_buffh]hsk_buff}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j]c.oa_tc6_start_xmitasbuh1hhjubj )}(h h]h }(hj;hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjIhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hskbh]hskb}(hjVhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubeh}(h]h ]h"]h$]h&]hhuh1j( hj:hhhhhMubj )}(h;h]h;}(hjqhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hj:hhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hj6hhhhhMubah}(h]j1ah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhj3hhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hj3hhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= jj> jj? j@ jA uh1j hhhj[ hNhNubh)}(hYThe transmit Ethernet frame in the skb is or going to be transmitted through the MAC-PHY.h]hYThe transmit Ethernet frame in the skb is or going to be transmitted through the MAC-PHY.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubj{ )}(hhh]h}(h]h ]h"]h$]h&]entries](j 3oa_tc6_zero_align_receive_frame_enable (C function)(c.oa_tc6_zero_align_receive_frame_enablehNtauh1jz hj[ hhhNhNubj )}(hhh](j )}(h?int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6);h]j )}(h?int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6);h](jj )}(hinth]hint}(hjhhhNhNubah}(h]h ]jv ah"]h$]h&]uh1ji hjhhhhhMubj )}(h h]h }(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhhhMubj )}(h&oa_tc6_zero_align_receive_frame_enableh]j )}(h&oa_tc6_zero_align_receive_frame_enableh]h&oa_tc6_zero_align_receive_frame_enable}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ](j# j$ eh"]h$]h&]hhuh1j hjhhhhhMubj) )}(h(struct oa_tc6 *tc6)h]j/ )}(hstruct oa_tc6 *tc6h](j )}(hj h]hstruct}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(h h]h }(hj hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubh)}(hhh]j )}(hoa_tc6h]hoa_tc6}(hjhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubah}(h]h ]h"]h$]h&] refdomainj reftypej reftargetjmodnameN classnameNj j )}j ]j )}j jsb(c.oa_tc6_zero_align_receive_frame_enableasbuh1hhjubj )}(h h]h }(hj<hhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(hj h]h*}(hjJhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubj )}(htc6h]htc6}(hjWhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjubeh}(h]h ]h"]h$]h&]noemphhhuh1j. hjubah}(h]h ]h"]h$]h&]hhuh1j( hjhhhhhMubj )}(hjsh]h;}(hjrhhhNhNubah}(h]h ]j ah"]h$]h&]uh1j hjhhhhhMubeh}(h]h ]h"]h$]h&]hhj uh1j j j hjhhhhhMubah}(h]jah ](j" j# eh"]h$]h&]j' j( )j) huh1j hhhMhjhhubj+ )}(hhh]h}(h]h ]h"]h$]h&]uh1j* hjhhhhhMubeh}(h]h ](j functioneh"]h$]h&]j< j j= jj> jj? j@ jA uh1j hhhj[ hNhNubh)}(hZero align receive frame feature can be enabled to align all receive ethernet frames data to start at the beginning of any receive data chunk payload with a start word offset (SWO) of zero.h]hZero align receive frame feature can be enabled to align all receive ethernet frames data to start at the beginning of any receive data chunk payload with a start word offset (SWO) of zero.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj[ hhubeh}(h]device-drivers-apiah ]h"]device drivers apiah$]h&]uh1hhj hhhhhMubeh}(h]control-transactionah ]h"]control transactionah$]h&]uh1hhj?hhhhhMubeh}(h]implementationah ]h"]implementationah$]h&]uh1hhhhhhhhK}ubeh}(h]Gopen-alliance-10base-t1x-mac-phy-serial-interface-tc6-framework-supportah ]h"]Iopen alliance 10base-t1x mac-phy serial interface (tc6) framework supportah$]h&]uh1hhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(hN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerjerror_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}substitution_names}refnames}refids}nameids}(jjjjj@j=jjjjjjj<j9jjjjjojlj= j: j j jjjju nametypes}(jjj@jjjj<jjjoj= j jjuh}(jhjhj=jjjCjjjjj9jjj?jjPjljj: jrj j@ jj jj[ j j j\ ja jRjWjjjjjLjQj1j6jju footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages] transformerN include_log] decorationNhhub.