sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget*/translations/zh_CN/networking/dsa/sja1105modnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/zh_TW/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/it_IT/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ja_JP/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/ko_KR/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/pt_BR/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget*/translations/sp_SP/networking/dsa/sja1105modnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhsection)}(hhh](htitle)}(hNXP SJA1105 switch driverh]hNXP SJA1105 switch driver}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhD/var/lib/git/docbuild/linux/Documentation/networking/dsa/sja1105.rsthKubh)}(hhh](h)}(hOverviewh]hOverview}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(hBThe NXP SJA1105 is a family of 10 SPI-managed automotive switches:h]hBThe NXP SJA1105 is a family of 10 SPI-managed automotive switches:}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh bullet_list)}(hhh](h list_item)}(h)SJA1105E: First generation, no TTEtherneth]h)}(hhh]h)SJA1105E: First generation, no TTEthernet}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hhubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h&SJA1105T: First generation, TTEtherneth]h)}(hj h]h&SJA1105T: First generation, TTEthernet}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h4SJA1105P: Second generation, no TTEthernet, no SGMIIh]h)}(hj#h]h4SJA1105P: Second generation, no TTEthernet, no SGMII}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj!ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h1SJA1105Q: Second generation, TTEthernet, no SGMIIh]h)}(hj:h]h1SJA1105Q: Second generation, TTEthernet, no SGMII}(hj<hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj8ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h1SJA1105R: Second generation, no TTEthernet, SGMIIh]h)}(hjQh]h1SJA1105R: Second generation, no TTEthernet, SGMII}(hjShhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjOubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h.SJA1105S: Second generation, TTEthernet, SGMIIh]h)}(hjhh]h.SJA1105S: Second generation, TTEthernet, SGMII}(hjjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjfubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hXSJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and 100base-TX PHYsh]h)}(hXSJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and 100base-TX PHYsh]hXSJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and 100base-TX PHYs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj}ubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hESJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TXh]h)}(hjh]hESJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(hESJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TXh]h)}(hjh]hESJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubh)}(h:SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1 h]h)}(h9SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1h]h9SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1hhhhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1hhhhK hhhhubh)}(hXBeing automotive parts, their configuration interface is geared towards set-and-forget use, with minimal dynamic interaction at runtime. They require a static configuration to be composed by software and packed with CRC and table headers, and sent over SPI.h]hXBeing automotive parts, their configuration interface is geared towards set-and-forget use, with minimal dynamic interaction at runtime. They require a static configuration to be composed by software and packed with CRC and table headers, and sent over SPI.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(hThe static configuration is composed of several configuration tables. Each table takes a number of entries. Some configuration tables can be (partially) reconfigured at runtime, some not. Some tables are mandatory, some not:h]hThe static configuration is composed of several configuration tables. Each table takes a number of entries. Some configuration tables can be (partially) reconfigured at runtime, some not. Some tables are mandatory, some not:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh]htgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjubhthead)}(hhh]hrow)}(hhh](hentry)}(hhh]h)}(hTableh]hTable}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hj5ubah}(h]h ]h"]h$]h&]uh1j3hj0ubj4)}(hhh]h)}(h Mandatoryh]h Mandatory}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjLubah}(h]h ]h"]h$]h&]uh1j3hj0ubj4)}(hhh]h)}(hReconfigurableh]hReconfigurable}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjcubah}(h]h ]h"]h$]h&]uh1j3hj0ubeh}(h]h ]h"]h$]h&]uh1j.hj+ubah}(h]h ]h"]h$]h&]uh1j)hjubhtbody)}(hhh](j/)}(hhh](j4)}(hhh]h)}(hScheduleh]hSchedule}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hSchedule entry pointsh]hSchedule entry points}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h if Schedulingh]h if Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hj ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h VL Lookuph]h VL Lookup}(hj-hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hj*ubah}(h]h ]h"]h$]h&]uh1j3hj'ubj4)}(hhh]h)}(hnoh]hno}(hjDhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjAubah}(h]h ]h"]h$]h&]uh1j3hj'ubj4)}(hhh]h)}(hnoh]hno}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK$hjXubah}(h]h ]h"]h$]h&]uh1j3hj'ubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h VL Policingh]h VL Policing}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjxubah}(h]h ]h"]h$]h&]uh1j3hjuubj4)}(hhh]h)}(h if VL Lookuph]h if VL Lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1j3hjuubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1j3hjuubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h VL Forwardingh]h VL Forwarding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h if VL Lookuph]h if VL Lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h L2 Lookuph]h L2 Lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hj.hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hj+ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK'hjBubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h L2 Policingh]h L2 Policing}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjbubah}(h]h ]h"]h$]h&]uh1j3hj_ubj4)}(hhh]h)}(hyesh]hyes}(hj|hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjyubah}(h]h ]h"]h$]h&]uh1j3hj_ubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1j3hj_ubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h VLAN Lookuph]h VLAN Lookup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h L2 Forwardingh]h L2 Forwarding}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hpartially (fully on P/Q/R/S)h]hpartially (fully on P/Q/R/S)}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK*hj,ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h MAC Configh]h MAC Config}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjLubah}(h]h ]h"]h$]h&]uh1j3hjIubj4)}(hhh]h)}(hyesh]hyes}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjcubah}(h]h ]h"]h$]h&]uh1j3hjIubj4)}(hhh]h)}(hpartially (fully on P/Q/R/S)h]hpartially (fully on P/Q/R/S)}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hjzubah}(h]h ]h"]h$]h&]uh1j3hjIubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hSchedule Paramsh]hSchedule Params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h if Schedulingh]h if Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK,hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hSchedule Entry Points Paramsh]hSchedule Entry Points Params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h if Schedulingh]h if Scheduling}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hVL Forwarding Paramsh]hVL Forwarding Params}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hj6ubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(hif VL Forwardingh]hif VL Forwarding}(hjPhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjMubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(hnoh]hno}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK.hjdubah}(h]h ]h"]h$]h&]uh1j3hj3ubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hL2 Lookup Paramsh]hL2 Lookup Params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hpartially (fully on P/Q/R/S)h]hpartially (fully on P/Q/R/S)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK/hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hL2 Forwarding Paramsh]hL2 Forwarding Params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hClock Sync Paramsh]hClock Sync Params}(hj#hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hj7ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjNubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h AVB Paramsh]h AVB Params}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjnubah}(h]h ]h"]h$]h&]uh1j3hjkubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1j3hjkubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1j3hjkubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hGeneral Paramsh]hGeneral Params}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h partiallyh]h partially}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h Retaggingh]h Retagging}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hj ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hj!ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK4hj8ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(h xMII Paramsh]h xMII Params}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjXubah}(h]h ]h"]h$]h&]uh1j3hjUubj4)}(hhh]h)}(hyesh]hyes}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjoubah}(h]h ]h"]h$]h&]uh1j3hjUubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1j3hjUubeh}(h]h ]h"]h$]h&]uh1j.hjubj/)}(hhh](j4)}(hhh]h)}(hSGMIIh]hSGMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hnoh]hno}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hyesh]hyes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubeh}(h]h ]h"]h$]h&]uh1jhjubeh}(h]h ]h"]h$]h&]colsKuh1jhjubah}(h]h ]h"]h$]h&]uh1jhhhhhhhNubh)}(hsAlso the configuration is write-only (software cannot read it back from the switch except for very few exceptions).h]hsAlso the configuration is write-only (software cannot read it back from the switch except for very few exceptions).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK:hhhhubh)}(hXThe driver creates a static configuration at probe time, and keeps it at all times in memory, as a shadow for the hardware state. When required to change a hardware setting, the static configuration is also updated. If that changed setting can be transmitted to the switch through the dynamic reconfiguration interface, it is; otherwise the switch is reset and reprogrammed with the updated static configuration.h]hXThe driver creates a static configuration at probe time, and keeps it at all times in memory, as a shadow for the hardware state. When required to change a hardware setting, the static configuration is also updated. If that changed setting can be transmitted to the switch through the dynamic reconfiguration interface, it is; otherwise the switch is reset and reprogrammed with the updated static configuration.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK=hhhhubeh}(h]overviewah ]h"]overviewah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hSwitching featuresh]hSwitching features}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj( hhhhhKEubh)}(hXThe driver supports the configuration of L2 forwarding rules in hardware for port bridging. The forwarding, broadcast and flooding domain between ports can be restricted through two methods: either at the L2 forwarding level (isolate one bridge's ports from another's) or at the VLAN port membership level (isolate ports within the same bridge). The final forwarding decision taken by the hardware is a logical AND of these two sets of rules.h]hXThe driver supports the configuration of L2 forwarding rules in hardware for port bridging. The forwarding, broadcast and flooding domain between ports can be restricted through two methods: either at the L2 forwarding level (isolate one bridge’s ports from another’s) or at the VLAN port membership level (isolate ports within the same bridge). The final forwarding decision taken by the hardware is a logical AND of these two sets of rules.}(hj9 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKGhj( hhubh)}(hXThe hardware tags all traffic internally with a port-based VLAN (pvid), or it decodes the VLAN information from the 802.1Q tag. Advanced VLAN classification is not possible. Once attributed a VLAN tag, frames are checked against the port's membership rules and dropped at ingress if they don't match any VLAN. This behavior is available when switch ports join a bridge with ``vlan_filtering 1``.h](hXzThe hardware tags all traffic internally with a port-based VLAN (pvid), or it decodes the VLAN information from the 802.1Q tag. Advanced VLAN classification is not possible. Once attributed a VLAN tag, frames are checked against the port’s membership rules and dropped at ingress if they don’t match any VLAN. This behavior is available when switch ports join a bridge with }(hjG hhhNhNubhliteral)}(h``vlan_filtering 1``h]hvlan_filtering 1}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hjG ubh.}(hjG hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKNhj( hhubh)}(hXNormally the hardware is not configurable with respect to VLAN awareness, but by changing what TPID the switch searches 802.1Q tags for, the semantics of a bridge with ``vlan_filtering 0`` can be kept (accept all traffic, tagged or untagged), and therefore this mode is also supported.h](hNormally the hardware is not configurable with respect to VLAN awareness, but by changing what TPID the switch searches 802.1Q tags for, the semantics of a bridge with }(hji hhhNhNubjP )}(h``vlan_filtering 0``h]hvlan_filtering 0}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hji ubha can be kept (accept all traffic, tagged or untagged), and therefore this mode is also supported.}(hji hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKUhj( hhubh)}(hSegregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but all bridges should have the same level of VLAN awareness (either both have ``vlan_filtering`` 0, or both 1).h](hSegregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but all bridges should have the same level of VLAN awareness (either both have }(hj hhhNhNubjP )}(h``vlan_filtering``h]hvlan_filtering}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hj ubh 0, or both 1).}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKZhj( hhubh)}(h5Topology and loop detection through STP is supported.h]h5Topology and loop detection through STP is supported.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK^hj( hhubeh}(h]switching-featuresah ]h"]switching featuresah$]h&]uh1hhhhhhhhKEubh)}(hhh](h)}(hOffloadsh]hOffloads}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKaubh)}(hhh](h)}(hTime-aware schedulingh]hTime-aware scheduling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKdubh)}(hXThe switch supports a variation of the enhancements for scheduled traffic specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to ensure deterministic latency for priority traffic that is sent in-band with its gate-open event in the network schedule.h]hXThe switch supports a variation of the enhancements for scheduled traffic specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to ensure deterministic latency for priority traffic that is sent in-band with its gate-open event in the network schedule.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKfhj hhubh)}(hXThis capability can be managed through the tc-taprio offload ('flags 2'). The difference compared to the software implementation of taprio is that the latter would only be able to shape traffic originated from the CPU, but not autonomously forwarded flows.h]hXThis capability can be managed through the tc-taprio offload (‘flags 2’). The difference compared to the software implementation of taprio is that the latter would only be able to shape traffic originated from the CPU, but not autonomously forwarded flows.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKkhj hhubh)}(hXhThe device has 8 traffic classes, and maps incoming frames to one of them based on the VLAN PCP bits (if no VLAN is present, the port-based default is used). As described in the previous sections, depending on the value of ``vlan_filtering``, the EtherType recognized by the switch as being VLAN can either be the typical 0x8100 or a custom value used internally by the driver for tagging. Therefore, the switch ignores the VLAN PCP if used in standalone or bridge mode with ``vlan_filtering=0``, as it will not recognize the 0x8100 EtherType. In these modes, injecting into a particular TX queue can only be done by the DSA net devices, which populate the PCP field of the tagging header on egress. Using ``vlan_filtering=1``, the behavior is the other way around: offloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA net devices are no longer able to do that. To inject frames into a hardware TX queue with VLAN awareness active, it is necessary to create a VLAN sub-interface on the DSA conduit port, and send normal (0x8100) VLAN-tagged towards the switch, with the VLAN PCP bits set appropriately.h](hThe device has 8 traffic classes, and maps incoming frames to one of them based on the VLAN PCP bits (if no VLAN is present, the port-based default is used). As described in the previous sections, depending on the value of }(hj hhhNhNubjP )}(h``vlan_filtering``h]hvlan_filtering}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hj ubh, the EtherType recognized by the switch as being VLAN can either be the typical 0x8100 or a custom value used internally by the driver for tagging. Therefore, the switch ignores the VLAN PCP if used in standalone or bridge mode with }(hj hhhNhNubjP )}(h``vlan_filtering=0``h]hvlan_filtering=0}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hj ubh, as it will not recognize the 0x8100 EtherType. In these modes, injecting into a particular TX queue can only be done by the DSA net devices, which populate the PCP field of the tagging header on egress. Using }(hj hhhNhNubjP )}(h``vlan_filtering=1``h]hvlan_filtering=1}(hj) hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hj ubhX, the behavior is the other way around: offloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA net devices are no longer able to do that. To inject frames into a hardware TX queue with VLAN awareness active, it is necessary to create a VLAN sub-interface on the DSA conduit port, and send normal (0x8100) VLAN-tagged towards the switch, with the VLAN PCP bits set appropriately.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKphj hhubh)}(hXJManagement traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the notable exception: the switch always treats it with a fixed priority and disregards any VLAN PCP bits even if present. The traffic class for management traffic has a value of 7 (highest priority) at the moment, which is not configurable in the driver.h]hXJManagement traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the notable exception: the switch always treats it with a fixed priority and disregards any VLAN PCP bits even if present. The traffic class for management traffic has a value of 7 (highest priority) at the moment, which is not configurable in the driver.}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hBelow is an example of configuring a 500 us cyclic schedule on egress port ``swp5``. The traffic class gate for management traffic (7) is open for 100 us, and the gates for all other traffic classes are open for 400 us::h](hKBelow is an example of configuring a 500 us cyclic schedule on egress port }(hjO hhhNhNubjP )}(h``swp5``h]hswp5}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hjO ubh. The traffic class gate for management traffic (7) is open for 100 us, and the gates for all other traffic classes are open for 400 us:}(hjO hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh literal_block)}(hXz#!/bin/bash set -e -u -o pipefail NSEC_PER_SEC="1000000000" gatemask() { local tc_list="$1" local mask=0 for tc in ${tc_list}; do mask=$((${mask} | (1 << ${tc}))) done printf "%02x" ${mask} } if ! systemctl is-active --quiet ptp4l; then echo "Please start the ptp4l service" exit fi now=$(phc_ctl /dev/ptp1 get | gawk '/clock time is/ { print $5; }') # Phase-align the base time to the start of the next second. sec=$(echo "${now}" | gawk -F. '{ print $1; }') base_time="$(((${sec} + 1) * ${NSEC_PER_SEC}))" tc qdisc add dev swp5 parent root handle 100 taprio \ num_tc 8 \ map 0 1 2 3 5 6 7 \ queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ base-time ${base_time} \ sched-entry S $(gatemask 7) 100000 \ sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \ flags 2h]hXz#!/bin/bash set -e -u -o pipefail NSEC_PER_SEC="1000000000" gatemask() { local tc_list="$1" local mask=0 for tc in ${tc_list}; do mask=$((${mask} | (1 << ${tc}))) done printf "%02x" ${mask} } if ! systemctl is-active --quiet ptp4l; then echo "Please start the ptp4l service" exit fi now=$(phc_ctl /dev/ptp1 get | gawk '/clock time is/ { print $5; }') # Phase-align the base time to the start of the next second. sec=$(echo "${now}" | gawk -F. '{ print $1; }') base_time="$(((${sec} + 1) * ${NSEC_PER_SEC}))" tc qdisc add dev swp5 parent root handle 100 taprio \ num_tc 8 \ map 0 1 2 3 5 6 7 \ queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ base-time ${base_time} \ sched-entry S $(gatemask 7) 100000 \ sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \ flags 2}hjq sbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1jo hhhKhj hhubh)}(hX{It is possible to apply the tc-taprio offload on multiple egress ports. There are hardware restrictions related to the fact that no gate event may trigger simultaneously on two ports. The driver checks the consistency of the schedules against this restriction and errors out when appropriate. Schedule analysis is needed to avoid this, which is outside the scope of the document.h]hX{It is possible to apply the tc-taprio offload on multiple egress ports. There are hardware restrictions related to the fact that no gate event may trigger simultaneously on two ports. The driver checks the consistency of the schedules against this restriction and errors out when appropriate. Schedule analysis is needed to avoid this, which is outside the scope of the document.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubeh}(h]time-aware-schedulingah ]h"]time-aware schedulingah$]h&]uh1hhj hhhhhKdubh)}(hhh](h)}(h&Routing actions (redirect, trap, drop)h]h&Routing actions (redirect, trap, drop)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhKubh)}(hThe switch is able to offload flow-based redirection of packets to a set of destination ports specified by the user. Internally, this is implemented by making use of Virtual Links, a TTEthernet concept.h]hThe switch is able to offload flow-based redirection of packets to a set of destination ports specified by the user. Internally, this is implemented by making use of Virtual Links, a TTEthernet concept.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(h6The driver supports 2 types of keys for Virtual Links:h]h6The driver supports 2 types of keys for Virtual Links:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hhh](h)}(hWVLAN-aware virtual links: these match on destination MAC address, VLAN ID and VLAN PCP.h]h)}(hWVLAN-aware virtual links: these match on destination MAC address, VLAN ID and VLAN PCP.h]hWVLAN-aware virtual links: these match on destination MAC address, VLAN ID and VLAN PCP.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubh)}(hIVLAN-unaware virtual links: these match on destination MAC address only. h]h)}(hHVLAN-unaware virtual links: these match on destination MAC address only.h]hHVLAN-unaware virtual links: these match on destination MAC address only.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubah}(h]h ]h"]h$]h&]uh1hhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhKhj hhubh)}(hwThe VLAN awareness state of the bridge (vlan_filtering) cannot be changed while there are virtual link rules installed.h]hwThe VLAN awareness state of the bridge (vlan_filtering) cannot be changed while there are virtual link rules installed.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hX?Composing multiple actions inside the same rule is supported. When only routing actions are requested, the driver creates a "non-critical" virtual link. When the action list also contains tc-gate (more details below), the virtual link becomes "time-critical" (draws frame buffers from a reserved memory partition, etc).h]hXGComposing multiple actions inside the same rule is supported. When only routing actions are requested, the driver creates a “non-critical” virtual link. When the action list also contains tc-gate (more details below), the virtual link becomes “time-critical” (draws frame buffers from a reserved memory partition, etc).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hKThe 3 routing actions that are supported are "trap", "drop" and "redirect".h]hWThe 3 routing actions that are supported are “trap”, “drop” and “redirect”.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubh)}(hExample 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the CPU and to swp3. This type of key (DA only) when the port's VLAN awareness state is off::h]hExample 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the CPU and to swp3. This type of key (DA only) when the port’s VLAN awareness state is off:}(hj' hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjp )}(htc qdisc add dev swp2 clsact tc filter add dev swp2 ingress flower skip_sw dst_mac 42:be:24:9b:76:20 \ action mirred egress redirect dev swp3 \ action traph]htc qdisc add dev swp2 clsact tc filter add dev swp2 ingress flower skip_sw dst_mac 42:be:24:9b:76:20 \ action mirred egress redirect dev swp3 \ action trap}hj5 sbah}(h]h ]h"]h$]h&]j j uh1jo hhhKhj hhubh)}(heExample 2: drop frames received on swp2 with a DA of 42:be:24:9b:76:20, a VID of 100 and a PCP of 0::h]hdExample 2: drop frames received on swp2 with a DA of 42:be:24:9b:76:20, a VID of 100 and a PCP of 0:}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj hhubjp )}(htc filter add dev swp2 ingress protocol 802.1Q flower skip_sw \ dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action droph]htc filter add dev swp2 ingress protocol 802.1Q flower skip_sw \ dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop}hjQ sbah}(h]h ]h"]h$]h&]j j uh1jo hhhKhj hhubeh}(h]"routing-actions-redirect-trap-dropah ]h"]&routing actions (redirect, trap, drop)ah$]h&]uh1hhj hhhhhKubh)}(hhh](h)}(hTime-based ingress policingh]hTime-based ingress policing}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjg hhhhhKubh)}(hXThe TTEthernet hardware abilities of the switch can be constrained to act similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform tight timing-based admission control for up to 1024 flows (identified by a tuple composed of destination MAC address, VLAN ID and VLAN PCP). Packets which are received outside their expected reception window are dropped.h]hXThe TTEthernet hardware abilities of the switch can be constrained to act similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform tight timing-based admission control for up to 1024 flows (identified by a tuple composed of destination MAC address, VLAN ID and VLAN PCP). Packets which are received outside their expected reception window are dropped.}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjg hhubh)}(hXThis capability can be managed through the offload of the tc-gate action. As routing actions are intrinsic to virtual links in TTEthernet (which performs explicit routing of time-critical traffic and does not leave that in the hands of the FDB, flooding etc), the tc-gate action may never appear alone when asking sja1105 to offload it. One (or more) redirect or trap actions must also follow along.h]hXThis capability can be managed through the offload of the tc-gate action. As routing actions are intrinsic to virtual links in TTEthernet (which performs explicit routing of time-critical traffic and does not leave that in the hands of the FDB, flooding etc), the tc-gate action may never appear alone when asking sja1105 to offload it. One (or more) redirect or trap actions must also follow along.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjg hhubh)}(hXExample: create a tc-taprio schedule that is phase-aligned with a tc-gate schedule (the clocks must be synchronized by a 1588 application stack, which is outside the scope of this document). No packet delivered by the sender will be dropped. Note that the reception window is larger than the transmission window (and much more so, in this example) to compensate for the packet propagation delay of the link (which can be determined by the 1588 application stack).h]hXExample: create a tc-taprio schedule that is phase-aligned with a tc-gate schedule (the clocks must be synchronized by a 1588 application stack, which is outside the scope of this document). No packet delivered by the sender will be dropped. Note that the reception window is larger than the transmission window (and much more so, in this example) to compensate for the packet propagation delay of the link (which can be determined by the 1588 application stack).}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjg hhubh)}(hReceiver (sja1105)::h]hReceiver (sja1105):}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjg hhubjp )}(hXtc qdisc add dev swp2 clsact now=$(phc_ctl /dev/ptp1 get | awk '/clock time is/ {print $5}') && \ sec=$(echo $now | awk -F. '{print $1}') && \ base_time="$(((sec + 2) * 1000000000))" && \ echo "base time ${base_time}" tc filter add dev swp2 ingress flower skip_sw \ dst_mac 42:be:24:9b:76:20 \ action gate base-time ${base_time} \ sched-entry OPEN 60000 -1 -1 \ sched-entry CLOSE 40000 -1 -1 \ action traph]hXtc qdisc add dev swp2 clsact now=$(phc_ctl /dev/ptp1 get | awk '/clock time is/ {print $5}') && \ sec=$(echo $now | awk -F. '{print $1}') && \ base_time="$(((sec + 2) * 1000000000))" && \ echo "base time ${base_time}" tc filter add dev swp2 ingress flower skip_sw \ dst_mac 42:be:24:9b:76:20 \ action gate base-time ${base_time} \ sched-entry OPEN 60000 -1 -1 \ sched-entry CLOSE 40000 -1 -1 \ action trap}hj sbah}(h]h ]h"]h$]h&]j j uh1jo hhhKhjg hhubh)}(hSender::h]hSender:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjg hhubjp )}(hXnow=$(phc_ctl /dev/ptp0 get | awk '/clock time is/ {print $5}') && \ sec=$(echo $now | awk -F. '{print $1}') && \ base_time="$(((sec + 2) * 1000000000))" && \ echo "base time ${base_time}" tc qdisc add dev eno0 parent root taprio \ num_tc 8 \ map 0 1 2 3 4 5 6 7 \ queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ base-time ${base_time} \ sched-entry S 01 50000 \ sched-entry S 00 50000 \ flags 2h]hXnow=$(phc_ctl /dev/ptp0 get | awk '/clock time is/ {print $5}') && \ sec=$(echo $now | awk -F. '{print $1}') && \ base_time="$(((sec + 2) * 1000000000))" && \ echo "base time ${base_time}" tc qdisc add dev eno0 parent root taprio \ num_tc 8 \ map 0 1 2 3 4 5 6 7 \ queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ base-time ${base_time} \ sched-entry S 01 50000 \ sched-entry S 00 50000 \ flags 2}hj sbah}(h]h ]h"]h$]h&]j j uh1jo hhhMhjg hhubh)}(hX!The engine used to schedule the ingress gate operations is the same that the one used for the tc-taprio offload. Therefore, the restrictions regarding the fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at the same time (during the same 200 ns slot) still apply.h]hX!The engine used to schedule the ingress gate operations is the same that the one used for the tc-taprio offload. Therefore, the restrictions regarding the fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at the same time (during the same 200 ns slot) still apply.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjg hhubh)}(hXTo come in handy, it is possible to share time-triggered virtual links across more than 1 ingress port, via flow blocks. In this case, the restriction of firing at the same time does not apply because there is a single schedule in the system, that of the shared virtual link::h]hXTo come in handy, it is possible to share time-triggered virtual links across more than 1 ingress port, via flow blocks. In this case, the restriction of firing at the same time does not apply because there is a single schedule in the system, that of the shared virtual link:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjg hhubjp )}(hX7tc qdisc add dev swp2 ingress_block 1 clsact tc qdisc add dev swp3 ingress_block 1 clsact tc filter add block 1 flower skip_sw dst_mac 42:be:24:9b:76:20 \ action gate index 2 \ base-time 0 \ sched-entry OPEN 50000000 -1 -1 \ sched-entry CLOSE 50000000 -1 -1 \ action traph]hX7tc qdisc add dev swp2 ingress_block 1 clsact tc qdisc add dev swp3 ingress_block 1 clsact tc filter add block 1 flower skip_sw dst_mac 42:be:24:9b:76:20 \ action gate index 2 \ base-time 0 \ sched-entry OPEN 50000000 -1 -1 \ sched-entry CLOSE 50000000 -1 -1 \ action trap}hj sbah}(h]h ]h"]h$]h&]j j uh1jo hhhMhjg hhubh)}(hHardware statistics for each flow are also available ("pkts" counts the number of dropped frames, which is a sum of frames dropped due to timing violations, lack of destination ports and MTU enforcement checks). Byte-level counters are not available.h]hHardware statistics for each flow are also available (“pkts” counts the number of dropped frames, which is a sum of frames dropped due to timing violations, lack of destination ports and MTU enforcement checks). Byte-level counters are not available.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM#hjg hhubeh}(h]time-based-ingress-policingah ]h"]time-based ingress policingah$]h&]uh1hhj hhhhhKubeh}(h]offloadsah ]h"]offloadsah$]h&]uh1hhhhhhhhKaubh)}(hhh](h)}(h Limitationsh]h Limitations}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj" hhhhhM)ubh)}(hThe SJA1105 switch family always performs VLAN processing. When configured as VLAN-unaware, frames carry a different VLAN tag internally, depending on whether the port is standalone or under a VLAN-unaware bridge.h]hThe SJA1105 switch family always performs VLAN processing. When configured as VLAN-unaware, frames carry a different VLAN tag internally, depending on whether the port is standalone or under a VLAN-unaware bridge.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM+hj" hhubh)}(hX[The virtual link keys are always fixed at {MAC DA, VLAN ID, VLAN PCP}, but the driver asks for the VLAN ID and VLAN PCP when the port is under a VLAN-aware bridge. Otherwise, it fills in the VLAN ID and PCP automatically, based on whether the port is standalone or in a VLAN-unaware bridge, and accepts only "VLAN-unaware" tc-flower keys (MAC DA).h]hX_The virtual link keys are always fixed at {MAC DA, VLAN ID, VLAN PCP}, but the driver asks for the VLAN ID and VLAN PCP when the port is under a VLAN-aware bridge. Otherwise, it fills in the VLAN ID and PCP automatically, based on whether the port is standalone or in a VLAN-unaware bridge, and accepts only “VLAN-unaware” tc-flower keys (MAC DA).}(hjA hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hj" hhubh)}(hThe existing tc-flower keys that are offloaded using virtual links are no longer operational after one of the following happens:h]hThe existing tc-flower keys that are offloaded using virtual links are no longer operational after one of the following happens:}(hjO hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM5hj" hhubh)}(hhh](h)}(hCport was standalone and joins a bridge (VLAN-aware or VLAN-unaware)h]h)}(hjb h]hCport was standalone and joins a bridge (VLAN-aware or VLAN-unaware)}(hjd hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM8hj` ubah}(h]h ]h"]h$]h&]uh1hhj] hhhhhNubh)}(h;port is part of a bridge whose VLAN awareness state changesh]h)}(hjy h]h;port is part of a bridge whose VLAN awareness state changes}(hj{ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM9hjw ubah}(h]h ]h"]h$]h&]uh1hhj] hhhhhNubh)}(h0port was part of a bridge and becomes standaloneh]h)}(hj h]h0port was part of a bridge and becomes standalone}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM:hj ubah}(h]h ]h"]h$]h&]uh1hhj] hhhhhNubh)}(hport was standalone, but another port joins a VLAN-aware bridge and this changes the global VLAN awareness state of the bridge h]h)}(h~port was standalone, but another port joins a VLAN-aware bridge and this changes the global VLAN awareness state of the bridgeh]h~port was standalone, but another port joins a VLAN-aware bridge and this changes the global VLAN awareness state of the bridge}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj ubah}(h]h ]h"]h$]h&]uh1hhj] hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1hhhhM8hj" hhubh)}(hX0The driver cannot veto all these operations, and it cannot update/remove the existing tc-flower filters either. So for proper operation, the tc-flower filters should be installed only after the forwarding configuration of the port has been made, and removed by user space before making any changes to it.h]hX0The driver cannot veto all these operations, and it cannot update/remove the existing tc-flower filters either. So for proper operation, the tc-flower filters should be installed only after the forwarding configuration of the port has been made, and removed by user space before making any changes to it.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM>hj" hhubeh}(h] limitationsah ]h"] limitationsah$]h&]uh1hhhhhhhhM)ubh)}(hhh](h)}(h%Device Tree bindings and board designh]h%Device Tree bindings and board design}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMDubh)}(hThis section references ``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml`` and aims to showcase some potential switch caveats.h](hThis section references }(hj hhhNhNubjP )}(h>``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml``h]h:Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jO hj ubh4 and aims to showcase some potential switch caveats.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMFhj hhubh)}(hhh](h)}(h'RMII PHY role and out-of-band signalingh]h'RMII PHY role and out-of-band signaling}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMJubh)}(hXEIn the RMII spec, the 50 MHz clock signals are either driven by the MAC or by an external oscillator (but not by the PHY). But the spec is rather loose and devices go outside it in several ways. Some PHYs go against the spec and may provide an output pin where they source the 50 MHz clock themselves, in an attempt to be helpful. On the other hand, the SJA1105 is only binary configurable - when in the RMII MAC role it will also attempt to drive the clock signal. To prevent this from happening it must be put in RMII PHY role. But doing so has some unintended consequences. In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0]. These are practically some extra code words (/J/ and /K/) sent prior to the preamble of each frame. The MAC does not have this out-of-band signaling mechanism defined by the RMII spec. So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105 emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to frame preambles, which the real PHY is not expected to understand. So the PHY simply encodes the extra symbols received from the SJA1105-as-PHY onto the 100Base-Tx wire. On the other side of the wire, some link partners might discard these extra symbols, while others might choke on them and discard the entire Ethernet frames that follow along. This looks like packet loss with some link partners but not with others. The take-away is that in RMII mode, the SJA1105 must be let to drive the reference clock if connected to a PHY.h]hXEIn the RMII spec, the 50 MHz clock signals are either driven by the MAC or by an external oscillator (but not by the PHY). But the spec is rather loose and devices go outside it in several ways. Some PHYs go against the spec and may provide an output pin where they source the 50 MHz clock themselves, in an attempt to be helpful. On the other hand, the SJA1105 is only binary configurable - when in the RMII MAC role it will also attempt to drive the clock signal. To prevent this from happening it must be put in RMII PHY role. But doing so has some unintended consequences. In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0]. These are practically some extra code words (/J/ and /K/) sent prior to the preamble of each frame. The MAC does not have this out-of-band signaling mechanism defined by the RMII spec. So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105 emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to frame preambles, which the real PHY is not expected to understand. So the PHY simply encodes the extra symbols received from the SJA1105-as-PHY onto the 100Base-Tx wire. On the other side of the wire, some link partners might discard these extra symbols, while others might choke on them and discard the entire Ethernet frames that follow along. This looks like packet loss with some link partners but not with others. The take-away is that in RMII mode, the SJA1105 must be let to drive the reference clock if connected to a PHY.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMLhj hhubeh}(h]'rmii-phy-role-and-out-of-band-signalingah ]h"]'rmii phy role and out-of-band signalingah$]h&]uh1hhj hhhhhMJubh)}(hhh](h)}(h$RGMII fixed-link and internal delaysh]h$RGMII fixed-link and internal delays}(hj4 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj1 hhhhhMgubh)}(hXXAs mentioned in the bindings document, the second generation of devices has tunable delay lines as part of the MAC, which can be used to establish the correct RGMII timing budget. When powered up, these can shift the Rx and Tx clocks with a phase difference between 73.8 and 101.7 degrees. The catch is that the delay lines need to lock onto a clock signal with a stable frequency. This means that there must be at least 2 microseconds of silence between the clock at the old vs at the new frequency. Otherwise the lock is lost and the delay lines must be reset (powered down and back up). In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the AN process. In the situation where the switch port is connected through an RGMII fixed-link to a link partner whose link state life cycle is outside the control of Linux (such as a different SoC), then the delay lines would remain unlocked (and inactive) until there is manual intervention (ifdown/ifup on the switch port). The take-away is that in RGMII mode, the switch's internal delays are only reliable if the link partner never changes link speeds, or if it does, it does so in a way that is coordinated with the switch port (practically, both ends of the fixed-link are under control of the same Linux system). As to why would a fixed-link interface ever change link speeds: there are Ethernet controllers out there which come out of reset in 100 Mbps mode, and their driver inevitably needs to change the speed and clock frequency if it's required to work at gigabit.h]hX\As mentioned in the bindings document, the second generation of devices has tunable delay lines as part of the MAC, which can be used to establish the correct RGMII timing budget. When powered up, these can shift the Rx and Tx clocks with a phase difference between 73.8 and 101.7 degrees. The catch is that the delay lines need to lock onto a clock signal with a stable frequency. This means that there must be at least 2 microseconds of silence between the clock at the old vs at the new frequency. Otherwise the lock is lost and the delay lines must be reset (powered down and back up). In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the AN process. In the situation where the switch port is connected through an RGMII fixed-link to a link partner whose link state life cycle is outside the control of Linux (such as a different SoC), then the delay lines would remain unlocked (and inactive) until there is manual intervention (ifdown/ifup on the switch port). The take-away is that in RGMII mode, the switch’s internal delays are only reliable if the link partner never changes link speeds, or if it does, it does so in a way that is coordinated with the switch port (practically, both ends of the fixed-link are under control of the same Linux system). As to why would a fixed-link interface ever change link speeds: there are Ethernet controllers out there which come out of reset in 100 Mbps mode, and their driver inevitably needs to change the speed and clock frequency if it’s required to work at gigabit.}(hjB hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMihj1 hhubeh}(h]$rgmii-fixed-link-and-internal-delaysah ]h"]$rgmii fixed-link and internal delaysah$]h&]uh1hhj hhhhhMgubh)}(hhh](h)}(hMDIO bus and PHY managementh]hMDIO bus and PHY management}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjX hhhhhMubh)}(hXThe SJA1105 does not have an MDIO bus and does not perform in-band AN either. Therefore there is no link state notification coming from the switch device. A board would need to hook up the PHYs connected to the switch to any other MDIO bus available to Linux within the system (e.g. to the DSA conduit's MDIO bus). Link state management then works by the driver manually keeping in sync (over SPI commands) the MAC link speed with the settings negotiated by the PHY.h]hXThe SJA1105 does not have an MDIO bus and does not perform in-band AN either. Therefore there is no link state notification coming from the switch device. A board would need to hook up the PHYs connected to the switch to any other MDIO bus available to Linux within the system (e.g. to the DSA conduit’s MDIO bus). Link state management then works by the driver manually keeping in sync (over SPI commands) the MAC link speed with the settings negotiated by the PHY.}(hji hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjX hhubh)}(hX.By comparison, the SJA1110 supports an MDIO slave access point over which its internal 100base-T1 PHYs can be accessed from the host. This is, however, not used by the driver, instead the internal 100base-T1 and 100base-TX PHYs are accessed through SPI commands, modeled in Linux as virtual MDIO buses.h]hX.By comparison, the SJA1110 supports an MDIO slave access point over which its internal 100base-T1 PHYs can be accessed from the host. This is, however, not used by the driver, instead the internal 100base-T1 and 100base-TX PHYs are accessed through SPI commands, modeled in Linux as virtual MDIO buses.}(hjw hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjX hhubh)}(hXThe microcontroller attached to the SJA1110 port 0 also has an MDIO controller operating in master mode, however the driver does not support this either, since the microcontroller gets disabled when the Linux driver operates. Discrete PHYs connected to the switch ports should have their MDIO interface attached to an MDIO controller from the host system and not to the switch, similar to SJA1105.h]hXThe microcontroller attached to the SJA1110 port 0 also has an MDIO controller operating in master mode, however the driver does not support this either, since the microcontroller gets disabled when the Linux driver operates. Discrete PHYs connected to the switch ports should have their MDIO interface attached to an MDIO controller from the host system and not to the switch, similar to SJA1105.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjX hhubeh}(h]mdio-bus-and-phy-managementah ]h"]mdio bus and phy managementah$]h&]uh1hhj hhhhhMubh)}(hhh](h)}(hPort compatibility matrixh]hPort compatibility matrix}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(h)The SJA1105 port compatibility matrix is:h]h)The SJA1105 port compatibility matrix is:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh]j)}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hj ubj*)}(hhh]j/)}(hhh](j4)}(hhh]h)}(hPorth]hPort}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j3hj ubj4)}(hhh]h)}(h SJA1105E/Th]h SJA1105E/T}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hj ubj4)}(hhh]h)}(h SJA1105P/Qh]h SJA1105P/Q}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hj ubj4)}(hhh]h)}(h SJA1105R/Sh]h SJA1105R/S}(hj6hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj3ubah}(h]h ]h"]h$]h&]uh1j3hj ubeh}(h]h ]h"]h$]h&]uh1j.hj ubah}(h]h ]h"]h$]h&]uh1j)hj ubj)}(hhh](j/)}(hhh](j4)}(hhh]h)}(h0h]h0}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj\ubah}(h]h ]h"]h$]h&]uh1j3hjYubj4)}(hhh]h)}(hxMIIh]hxMII}(hjvhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjsubah}(h]h ]h"]h$]h&]uh1j3hjYubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjYubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjYubeh}(h]h ]h"]h$]h&]uh1j.hjVubj/)}(hhh](j4)}(hhh]h)}(h1h]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjVubj/)}(hhh](j4)}(hhh]h)}(h2h]h2}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j3hj#ubj4)}(hhh]h)}(hxMIIh]hxMII}(hj@hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj=ubah}(h]h ]h"]h$]h&]uh1j3hj#ubxAj4)}(hhh]h)}(hxMIIh]hxMII}(hjWhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjTubah}(h]h ]h"]h$]h&]uh1j3hj#ubj4)}(hhh]h)}(hxMIIh]hxMII}(hjnhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjkubah}(h]h ]h"]h$]h&]uh1j3hj#ubeh}(h]h ]h"]h$]h&]uh1j.hjVubj/)}(hhh](j4)}(hhh]h)}(h3h]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjVubj/)}(hhh](j4)}(hhh]h)}(h4h]h4}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMIIh]hSGMII}(hj8hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj5ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjVubeh}(h]h ]h"]h$]h&]uh1jhj ubeh}(h]h ]h"]h$]h&]colsKuh1jhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubh)}(h)The SJA1110 port compatibility matrix is:h]h)The SJA1110 port compatibility matrix is:}(hjehhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj)}(hhh]j)}(hhh](j )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjvubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjvubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjvubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjvubj )}(hhh]h}(h]h ]h"]h$]h&]colwidthKuh1j hjvubj*)}(hhh]j/)}(hhh](j4)}(hhh]h)}(hPorth]hPort}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSJA1110Ah]hSJA1110A}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSJA1110Bh]hSJA1110B}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSJA1110Ch]hSJA1110C}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSJA1110Dh]hSJA1110D}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hjubah}(h]h ]h"]h$]h&]uh1j)hjvubj)}(hhh](j/)}(hhh](j4)}(hhh]h)}(hjah]h0}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj6ubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(h RevMII (uC)h]h RevMII (uC)}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjLubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(h RevMII (uC)h]h RevMII (uC)}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjcubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(h RevMII (uC)h]h RevMII (uC)}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjzubah}(h]h ]h"]h$]h&]uh1j3hj3ubj4)}(hhh]h)}(h RevMII (uC)h]h RevMII (uC)}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hj3ubeh}(h]h ]h"]h$]h&]uh1j.hj0ubj/)}(hhh](j4)}(hhh]h)}(hjh]h1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h100base-TX or SGMIIh]h100base-TX or SGMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-TXh]h 100base-TX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-TXh]h 100base-TX}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMIIh]hSGMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hj0ubj/)}(hhh](j4)}(hhh]h)}(hj+h]h2}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj,ubah}(h]h ]h"]h$]h&]uh1j3hj)ubj4)}(hhh]h)}(h xMII or SGMIIh]h xMII or SGMII}(hjEhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjBubah}(h]h ]h"]h$]h&]uh1j3hj)ubj4)}(hhh]h)}(hxMIIh]hxMII}(hj\hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjYubah}(h]h ]h"]h$]h&]uh1j3hj)ubj4)}(hhh]h)}(hxMIIh]hxMII}(hjshhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjpubah}(h]h ]h"]h$]h&]uh1j3hj)ubj4)}(hhh]h)}(h xMII or SGMIIh]h xMII or SGMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hj)ubeh}(h]h ]h"]h$]h&]uh1j.hj0ubj/)}(hhh](j4)}(hhh]h)}(hjh]h3}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMII or SGMII or 2500base-Xh]hxMII or SGMII or 2500base-X}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMII or SGMII or 2500base-Xh]hxMII or SGMII or 2500base-X}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hxMIIh]hxMII}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMII or 2500base-Xh]hSGMII or 2500base-X}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hj0ubj/)}(hhh](j4)}(hhh]h)}(hjh]h4}(hj%hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj"ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMII or 2500base-Xh]hSGMII or 2500base-X}(hj;hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj8ubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMII or 2500base-Xh]hSGMII or 2500base-X}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjOubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMII or 2500base-Xh]hSGMII or 2500base-X}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(hSGMII or 2500base-Xh]hSGMII or 2500base-X}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj}ubah}(h]h ]h"]h$]h&]uh1j3hjubeh}(h]h ]h"]h$]h&]uh1j.hj0ubj/)}(hhh](j4)}(hhh]h)}(h5h]h5}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-T1h]h 100base-T1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-T1h]h 100base-T1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-T1h]h 100base-T1}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j3hjubj4)}(hhh]h)}(h 100base-T1h]h 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