€•VŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”Œ*/translations/zh_CN/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/zh_TW/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/it_IT/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/ja_JP/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/ko_KR/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”Œ*/translations/sp_SP/networking/dsa/bcm_sf2”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ-Broadcom Starfighter 2 Ethernet switch driver”h]”hŒ-Broadcom Starfighter 2 Ethernet switch driver”…””}”(hh¨hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hh£hžhhŸŒD/var/lib/git/docbuild/linux/Documentation/networking/dsa/bcm_sf2.rst”h KubhŒ paragraph”“”)”}”(hŒqBroadcom's Starfighter 2 Ethernet switch hardware block is commonly found and deployed in the following products:”h]”hŒsBroadcom’s Starfighter 2 Ethernet switch hardware block is commonly found and deployed in the following products:”…””}”(hh¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒxDSL gateways such as BCM63138”h]”h¸)”}”(hhÐh]”hŒxDSL gateways such as BCM63138”…””}”(hhÒhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhhÎubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒ0streaming/multimedia Set Top Box such as BCM7445”h]”h¸)”}”(hhçh]”hŒ0streaming/multimedia Set Top Box such as BCM7445”…””}”(hhéhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hhåubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h NubhÍ)”}”(hŒ9Cable Modem/residential gateways such as BCM7145/BCM3390 ”h]”h¸)”}”(hŒ8Cable Modem/residential gateways such as BCM7145/BCM3390”h]”hŒ8Cable Modem/residential gateways such as BCM7145/BCM3390”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hhüubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhhÉhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1hÇhŸh¶h Khh£hžhubh¸)”}”(hŒŽThe switch is typically deployed in a configuration involving between 5 to 13 ports, offering a range of built-in and customizable interfaces:”h]”hŒŽThe switch is typically deployed in a configuration involving between 5 to 13 ports, offering a range of built-in and customizable interfaces:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K hh£hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒsingle integrated Gigabit PHY”h]”h¸)”}”(hj/h]”hŒsingle integrated Gigabit PHY”…””}”(hj1hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj-ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj*hžhhŸh¶h NubhÍ)”}”(hŒquad integrated Gigabit PHY”h]”h¸)”}”(hjFh]”hŒquad integrated Gigabit PHY”…””}”(hjHhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjDubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj*hžhhŸh¶h NubhÍ)”}”(hŒ-quad external Gigabit PHY w/ MDIO multiplexer”h]”h¸)”}”(hj]h]”hŒ-quad external Gigabit PHY w/ MDIO multiplexer”…””}”(hj_hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj[ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj*hžhhŸh¶h NubhÍ)”}”(hŒintegrated MoCA PHY”h]”h¸)”}”(hjth]”hŒintegrated MoCA PHY”…””}”(hjvhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjrubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj*hžhhŸh¶h NubhÍ)”}”(hŒ2several external MII/RevMII/GMII/RGMII interfaces ”h]”h¸)”}”(hŒ1several external MII/RevMII/GMII/RGMII interfaces”h]”hŒ1several external MII/RevMII/GMII/RGMII interfaces”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khj‰ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhj*hžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jjuh1hÇhŸh¶h Khh£hžhubh¸)”}”(hXThe switch also supports specific congestion control features which allow MoCA fail-over not to lose packets during a MoCA role re-election, as well as out of band back-pressure to the host CPU network interface when downstream interfaces are connected at a lower speed.”h]”hXThe switch also supports specific congestion control features which allow MoCA fail-over not to lose packets during a MoCA role re-election, as well as out of band back-pressure to the host CPU network interface when downstream interfaces are connected at a lower speed.”…””}”(hj§hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubh¸)”}”(hŒsThe switch hardware block is typically interfaced using MMIO accesses and contains a bunch of sub-blocks/registers:”h]”hŒsThe switch hardware block is typically interfaced using MMIO accesses and contains a bunch of sub-blocks/registers:”…””}”(hjµhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khh£hžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒ(``SWITCH_CORE``: common switch registers”h]”h¸)”}”(hjÈh]”(hŒliteral”“”)”}”(hŒ``SWITCH_CORE``”h]”hŒ SWITCH_CORE”…””}”(hjÏhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjÊubhŒ: common switch registers”…””}”(hjÊhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KhjÆubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ3``SWITCH_REG``: external interfaces switch register”h]”h¸)”}”(hjïh]”(jÎ)”}”(hŒ``SWITCH_REG``”h]”hŒ SWITCH_REG”…””}”(hjôhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjñubhŒ%: external interfaces switch register”…””}”(hjñhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjíubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ|``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE, which is used for indirect PHY accesses)”h]”h¸)”}”(hŒ|``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE, which is used for indirect PHY accesses)”h]”(jÎ)”}”(hŒ``SWITCH_MDIO``”h]”hŒ SWITCH_MDIO”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjubhŒm: external MDIO bus controller (there is another one in SWITCH_CORE, which is used for indirect PHY accesses)”…””}”(hjhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ7``SWITCH_INDIR_RW``: 64-bits wide register helper block”h]”h¸)”}”(hj:h]”(jÎ)”}”(hŒ``SWITCH_INDIR_RW``”h]”hŒSWITCH_INDIR_RW”…””}”(hj?hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhj<ubhŒ$: 64-bits wide register helper block”…””}”(hj<hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K!hj8ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ4``SWITCH_INTRL2_0/1``: Level-2 interrupt controllers”h]”h¸)”}”(hj_h]”(jÎ)”}”(hŒ``SWITCH_INTRL2_0/1``”h]”hŒSWITCH_INTRL2_0/1”…””}”(hjdhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjaubhŒ: Level-2 interrupt controllers”…””}”(hjahžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K"hj]ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ'``SWITCH_ACB``: Admission control block”h]”h¸)”}”(hj„h]”(jÎ)”}”(hŒ``SWITCH_ACB``”h]”hŒ SWITCH_ACB”…””}”(hj‰hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhj†ubhŒ: Admission control block”…””}”(hj†hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K#hj‚ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h NubhÍ)”}”(hŒ(``SWITCH_FCB``: Fail-over control block ”h]”h¸)”}”(hŒ'``SWITCH_FCB``: Fail-over control block”h]”(jÎ)”}”(hŒ``SWITCH_FCB``”h]”hŒ SWITCH_FCB”…””}”(hj¯hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhj«ubhŒ: Fail-over control block”…””}”(hj«hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K$hj§ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjÃhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jjuh1hÇhŸh¶h Khh£hžhubh¢)”}”(hhh]”(h§)”}”(hŒImplementation details”h]”hŒImplementation details”…””}”(hjÖhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjÓhžhhŸh¶h K'ubh¸)”}”(hŒºThe driver is located in ``drivers/net/dsa/bcm_sf2.c`` and is implemented as a DSA driver; see ``Documentation/networking/dsa/dsa.rst`` for details on the subsystem and what it provides.”h]”(hŒThe driver is located in ”…””}”(hjähžhhŸNh NubjÎ)”}”(hŒ``drivers/net/dsa/bcm_sf2.c``”h]”hŒdrivers/net/dsa/bcm_sf2.c”…””}”(hjìhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjäubhŒ) and is implemented as a DSA driver; see ”…””}”(hjähžhhŸNh NubjÎ)”}”(hŒ(``Documentation/networking/dsa/dsa.rst``”h]”hŒ$Documentation/networking/dsa/dsa.rst”…””}”(hjþhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjäubhŒ3 for details on the subsystem and what it provides.”…””}”(hjähžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K)hjÓhžhubh¸)”}”(hX<The SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag which gets inserted by the switch for every packet forwarded to the CPU interface, conversely, the CPU network interface should insert a similar tag for packets entering the CPU port. The tag format is described in ``net/dsa/tag_brcm.c``.”h]”(hX%The SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag which gets inserted by the switch for every packet forwarded to the CPU interface, conversely, the CPU network interface should insert a similar tag for packets entering the CPU port. The tag format is described in ”…””}”(hjhžhhŸNh NubjÎ)”}”(hŒ``net/dsa/tag_brcm.c``”h]”hŒnet/dsa/tag_brcm.c”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjubhŒ.”…””}”(hjhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K-hjÓhžhubh¸)”}”(hŒ`Overall, the SF2 driver is a fairly regular DSA driver; there are a few specifics covered below.”h]”hŒ`Overall, the SF2 driver is a fairly regular DSA driver; there are a few specifics covered below.”…””}”(hj6hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K3hjÓhžhubh¢)”}”(hhh]”(h§)”}”(hŒDevice Tree probing”h]”hŒDevice Tree probing”…””}”(hjGhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjDhžhhŸh¶h K7ubh¸)”}”(hX7The DSA platform device driver is probed using a specific compatible string provided in ``net/dsa/dsa.c``. The reason for that is because the DSA subsystem gets registered as a platform device driver currently. DSA will provide the needed device_node pointers which are then accessible by the switch driver setup function to setup resources such as register ranges and interrupts. This currently works very well because none of the of_* functions utilized by the driver require a struct device to be bound to a struct device_node, but things may change in the future.”h]”(hŒXThe DSA platform device driver is probed using a specific compatible string provided in ”…””}”(hjUhžhhŸNh NubjÎ)”}”(hŒ``net/dsa/dsa.c``”h]”hŒ net/dsa/dsa.c”…””}”(hj]hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjUubhXÎ. The reason for that is because the DSA subsystem gets registered as a platform device driver currently. DSA will provide the needed device_node pointers which are then accessible by the switch driver setup function to setup resources such as register ranges and interrupts. This currently works very well because none of the of_* functions utilized by the driver require a struct device to be bound to a struct device_node, but things may change in the future.”…””}”(hjUhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h K9hjDhžhubeh}”(h]”Œdevice-tree-probing”ah ]”h"]”Œdevice tree probing”ah$]”h&]”uh1h¡hjÓhžhhŸh¶h K7ubh¢)”}”(hhh]”(h§)”}”(hŒMDIO indirect accesses”h]”hŒMDIO indirect accesses”…””}”(hj€hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj}hžhhŸh¶h KCubh¸)”}”(hX¾Due to a limitation in how Broadcom switches have been designed, external Broadcom switches connected to a SF2 require the use of the DSA user MDIO bus in order to properly configure them. By default, the SF2 pseudo-PHY address, and an external switch pseudo-PHY address will both be snooping for incoming MDIO transactions, since they are at the same address (30), resulting in some kind of "double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we selectively divert reads and writes towards external Broadcom switches pseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a configurable pseudo-PHY address which circumvents the initial design limitation.”h]”(hX¹Due to a limitation in how Broadcom switches have been designed, external Broadcom switches connected to a SF2 require the use of the DSA user MDIO bus in order to properly configure them. By default, the SF2 pseudo-PHY address, and an external switch pseudo-PHY address will both be snooping for incoming MDIO transactions, since they are at the same address (30), resulting in some kind of “double†programming. Using DSA, and setting ”…””}”(hjŽhžhhŸNh NubjÎ)”}”(hŒ``ds->phys_mii_mask``”h]”hŒds->phys_mii_mask”…””}”(hj–hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjŽubhŒô accordingly, we selectively divert reads and writes towards external Broadcom switches pseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a configurable pseudo-PHY address which circumvents the initial design limitation.”…””}”(hjŽhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KEhj}hžhubeh}”(h]”Œmdio-indirect-accesses”ah ]”h"]”Œmdio indirect accesses”ah$]”h&]”uh1h¡hjÓhžhhŸh¶h KCubh¢)”}”(hhh]”(h§)”}”(hŒ)Multimedia over CoAxial (MoCA) interfaces”h]”hŒ)Multimedia over CoAxial (MoCA) interfaces”…””}”(hj¹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¶hžhhŸh¶h KPubh¸)”}”(hXÕMoCA interfaces are fairly specific and require the use of a firmware blob which gets loaded onto the MoCA processor(s) for packet processing. The switch hardware contains logic which will assert/de-assert link states accordingly for the MoCA interface whenever the MoCA coaxial cable gets disconnected or the firmware gets reloaded. The SF2 driver relies on such events to properly set its MoCA interface carrier state and properly report this to the networking stack.”h]”hXÕMoCA interfaces are fairly specific and require the use of a firmware blob which gets loaded onto the MoCA processor(s) for packet processing. The switch hardware contains logic which will assert/de-assert link states accordingly for the MoCA interface whenever the MoCA coaxial cable gets disconnected or the firmware gets reloaded. The SF2 driver relies on such events to properly set its MoCA interface carrier state and properly report this to the networking stack.”…””}”(hjÇhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KRhj¶hžhubh¸)”}”(hŒéThe MoCA interfaces are supported using the PHY library's fixed PHY/emulated PHY device and the switch driver registers a ``fixed_link_update`` callback for such PHYs which reflects the link state obtained from the interrupt handler.”h]”(hŒ|The MoCA interfaces are supported using the PHY library’s fixed PHY/emulated PHY device and the switch driver registers a ”…””}”(hjÕhžhhŸNh NubjÎ)”}”(hŒ``fixed_link_update``”h]”hŒfixed_link_update”…””}”(hjÝhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jÍhjÕubhŒZ callback for such PHYs which reflects the link state obtained from the interrupt handler.”…””}”(hjÕhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KYhj¶hžhubeh}”(h]”Œ'multimedia-over-coaxial-moca-interfaces”ah ]”h"]”Œ)multimedia over coaxial (moca) interfaces”ah$]”h&]”uh1h¡hjÓhžhhŸh¶h KPubh¢)”}”(hhh]”(h§)”}”(hŒPower Management”h]”hŒPower Management”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hjýhžhhŸh¶h K_ubh¸)”}”(hŒvWhenever possible, the SF2 driver tries to minimize the overall switch power consumption by applying a combination of:”h]”hŒvWhenever possible, the SF2 driver tries to minimize the overall switch power consumption by applying a combination of:”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KahjýhžhubhÈ)”}”(hhh]”(hÍ)”}”(hŒ%turning off internal buffers/memories”h]”h¸)”}”(hj!h]”hŒ%turning off internal buffers/memories”…””}”(hj#hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kdhjubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h NubhÍ)”}”(hŒ!disabling packet processing logic”h]”h¸)”}”(hj8h]”hŒ!disabling packet processing logic”…””}”(hj:hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kehj6ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h NubhÍ)”}”(hŒ)putting integrated PHYs in IDDQ/low-power”h]”h¸)”}”(hjOh]”hŒ)putting integrated PHYs in IDDQ/low-power”…””}”(hjQhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h KfhjMubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h NubhÍ)”}”(hŒ=reducing the switch core clock based on the active port count”h]”h¸)”}”(hjfh]”hŒ=reducing the switch core clock based on the active port count”…””}”(hjhhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kghjdubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h NubhÍ)”}”(hŒenabling and advertising EEE”h]”h¸)”}”(hj}h]”hŒenabling and advertising EEE”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Khhj{ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h NubhÍ)”}”(hŒ@turning off RGMII data processing logic when the link goes down ”h]”h¸)”}”(hŒ?turning off RGMII data processing logic when the link goes down”h]”hŒ?turning off RGMII data processing logic when the link goes down”…””}”(hj–hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Kihj’ubah}”(h]”h ]”h"]”h$]”h&]”uh1hÌhjhžhhŸh¶h Nubeh}”(h]”h ]”h"]”h$]”h&]”jjuh1hÇhŸh¶h Kdhjýhžhubeh}”(h]”Œpower-management”ah ]”h"]”Œpower management”ah$]”h&]”uh1h¡hjÓhžhhŸh¶h K_ubh¢)”}”(hhh]”(h§)”}”(hŒ Wake-on-LAN”h]”hŒ Wake-on-LAN”…””}”(hj»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¦hj¸hžhhŸh¶h Klubh¸)”}”(hX„Wake-on-LAN is currently implemented by utilizing the host processor Ethernet MAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection between the user request and the supported host Ethernet interface WoL capabilities is done and the intersection result gets configured. During system-wide suspend/resume, only ports not participating in Wake-on-LAN are disabled.”h]”hX„Wake-on-LAN is currently implemented by utilizing the host processor Ethernet MAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection between the user request and the supported host Ethernet interface WoL capabilities is done and the intersection result gets configured. During system-wide suspend/resume, only ports not participating in Wake-on-LAN are disabled.”…””}”(hjÉhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h·hŸh¶h Knhj¸hžhubeh}”(h]”Œ wake-on-lan”ah ]”h"]”Œ wake-on-lan”ah$]”h&]”uh1h¡hjÓhžhhŸh¶h Klubeh}”(h]”Œimplementation-details”ah ]”h"]”Œimplementation details”ah$]”h&]”uh1h¡hh£hžhhŸh¶h K'ubeh}”(h]”Œ-broadcom-starfighter-2-ethernet-switch-driver”ah ]”h"]”Œ-broadcom starfighter 2 ethernet switch driver”ah$]”h&]”uh1h¡hhhžhhŸh¶h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h¶uh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¦NŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h¶Œ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”Œrefids”}”Œnameids”}”(jìjéjäjájzjwj³j°júj÷jµj²jÜjÙuŒ nametypes”}”(jì‰jä‰jz‰j³‰jú‰jµ‰j܉uh}”(jéh£jájÓjwjDj°j}j÷j¶j²jýjÙj¸uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nhžhub.