sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget3/translations/zh_CN/networking/devlink/devlink-portmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/zh_TW/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/it_IT/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ja_JP/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ko_KR/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hPortuguese (Brazilian)}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/pt_BR/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/sp_SP/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhM/var/lib/git/docbuild/linux/Documentation/networking/devlink/devlink-port.rsthKubhtarget)}(h.. _devlink_port:h]h}(h]h ]h"]h$]h&]refid devlink-portuh1hhKhhhhhhubhsection)}(hhh](htitle)}(h Devlink Porth]h Devlink Port}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h``devlink-port`` is a port that exists on the device. It has a logically separate ingress/egress point of the device. A devlink port can be any one of many flavours. A devlink port flavour along with port attributes describe what a port represents.h](hliteral)}(h``devlink-port``h]h devlink-port}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh is a port that exists on the device. It has a logically separate ingress/egress point of the device. A devlink port can be any one of many flavours. A devlink port flavour along with port attributes describe what a port represents.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hwA device driver that intends to publish a devlink port sets the devlink port attributes and registers the devlink port.h]hwA device driver that intends to publish a devlink port sets the devlink port attributes and registers the devlink port.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h*Devlink port flavours are described below.h]h*Devlink port flavours are described below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh](h)}(hList of devlink port flavoursh]hList of devlink port flavours}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj)ubhtgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1j?hj<ubj@)}(hhh]h}(h]h ]h"]h$]h&]jJKZuh1j?hj<ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hFlavourh]hFlavour}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj`ubah}(h]h ]h"]h$]h&]uh1j^hj[ubj_)}(hhh]h)}(h Descriptionh]h Description}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjwubah}(h]h ]h"]h$]h&]uh1j^hj[ubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h!``DEVLINK_PORT_FLAVOUR_PHYSICAL``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PHYSICAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hiAny kind of physical port. This can be an eswitch physical port or any other physical port on the device.h]hiAny kind of physical port. This can be an eswitch physical port or any other physical port on the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_DSA``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_DSA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(h'This indicates a DSA interconnect port.h]h'This indicates a DSA interconnect port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_CPU``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_CPU}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(h1This indicates a CPU port applicable only to DSA.h]h1This indicates a CPU port applicable only to DSA.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj7ubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_PF``h]h)}(hj\h]hDEVLINK_PORT_FLAVOUR_PCI_PF}(hj^hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZubah}(h]h ]h"]h$]h&]uh1hhhhKhjWubah}(h]h ]h"]h$]h&]uh1j^hjTubj_)}(hhh]h)}(hQThis indicates an eswitch port representing a port of PCI physical function (PF).h]hQThis indicates an eswitch port representing a port of PCI physical function (PF).}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjwubah}(h]h ]h"]h$]h&]uh1j^hjTubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_VF``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PCI_VF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hPThis indicates an eswitch port representing a port of PCI virtual function (VF).h]hPThis indicates an eswitch port representing a port of PCI virtual function (VF).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_SF``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PCI_SF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hKThis indicates an eswitch port representing a port of PCI subfunction (SF).h]hKThis indicates an eswitch port representing a port of PCI subfunction (SF).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubjZ)}(hhh](j_)}(hhh]h)}(h ``DEVLINK_PORT_FLAVOUR_VIRTUAL``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_VIRTUAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(h!Any virtual port facing the user.h]h!Any virtual port facing the user.}(hj:hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hj7ubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjVubeh}(h]h ]h"]h$]h&]uh1jThj<ubeh}(h]h ]h"]h$]h&]colsKuh1j:hj)ubeh}(h]id2ah ]colwidths-givenah"]h$]h&]uh1j'hhhhhNhNubh)}(hODevlink port can have a different type based on the link layer described below.h]hODevlink port can have a different type based on the link layer described below.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hhhhubj()}(hhh](h)}(hList of devlink port typesh]hList of devlink port types}(hjzhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjwubj;)}(hhh](j@)}(hhh]h}(h]h ]h"]h$]h&]jJKuh1j?hjubj@)}(hhh]h}(h]h ]h"]h$]h&]jJKZuh1j?hjubjU)}(hhh](jZ)}(hhh](j_)}(hhh]h)}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_TYPE_ETH``h]h)}(hjh]hDEVLINK_PORT_TYPE_ETH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hKDriver should set this port type when a link layer of the port is Ethernet.h]hKDriver should set this port type when a link layer of the port is Ethernet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_TYPE_IB``h]h)}(hjh]hDEVLINK_PORT_TYPE_IB}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hMDriver should set this port type when a link layer of the port is InfiniBand.h]hMDriver should set this port type when a link layer of the port is InfiniBand.}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hj:ubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhjubjZ)}(hhh](j_)}(hhh]h)}(h``DEVLINK_PORT_TYPE_AUTO``h]h)}(hj_h]hDEVLINK_PORT_TYPE_AUTO}(hjahhhNhNubah}(h]h ]h"]h$]h&]uh1hhj]ubah}(h]h ]h"]h$]h&]uh1hhhhK8hjZubah}(h]h ]h"]h$]h&]uh1j^hjWubj_)}(hhh]h)}(hYThis type is indicated by the user when driver should detect the port type automatically.h]hYThis type is indicated by the user when driver should detect the port type automatically.}(hj}hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjzubah}(h]h ]h"]h$]h&]uh1j^hjWubeh}(h]h ]h"]h$]h&]uh1jYhjubeh}(h]h ]h"]h$]h&]uh1jThjubeh}(h]h ]h"]h$]h&]colsKuh1j:hjwubeh}(h]id3ah ]jeah"]h$]h&]uh1j'hhhhhNhNubh)}(hhh](h)}(hPCI controllersh]hPCI controllers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK=ubh)}(hIn most cases a PCI device has only one controller. A controller consists of potentially multiple physical, virtual functions and subfunctions. A function consists of one or more ports. This port is represented by the devlink eswitch port.h]hIn most cases a PCI device has only one controller. A controller consists of potentially multiple physical, virtual functions and subfunctions. A function consists of one or more ports. This port is represented by the devlink eswitch port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjhhubh)}(hX3A PCI device connected to multiple CPUs or multiple PCI root complexes or a SmartNIC, however, may have multiple controllers. For a device with multiple controllers, each controller is distinguished by a unique controller number. An eswitch is on the PCI device which supports ports of multiple controllers.h]hX3A PCI device connected to multiple CPUs or multiple PCI root complexes or a SmartNIC, however, may have multiple controllers. For a device with multiple controllers, each controller is distinguished by a unique controller number. An eswitch is on the PCI device which supports ports of multiple controllers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjhhubh)}(h2An example view of a system with two controllers::h]h1An example view of a system with two controllers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubh literal_block)}(hX --------------------------------------------------------- | | | --------- --------- ------- ------- | ----------- | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | server | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ | | connect | | ------- ------- | ----------- | | controller_num=1 (no eswitch) | ------|-------------------------------------------------- (internal wire) | --------------------------------------------------------- | devlink eswitch ports and reps | | ----------------------------------------------------- | | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | | | | ----------- | --------- --------- ------- ------- | | smartNIC| | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | pci rc |==| ------- ----/---- ---/----- ------- ---/--- ---/--- | | connect | | | pf0 |______/________/ | pf1 |___/_______/ | ----------- | ------- ------- | | | | local controller_num=0 (eswitch) | ---------------------------------------------------------h]hX --------------------------------------------------------- | | | --------- --------- ------- ------- | ----------- | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | server | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ | | connect | | ------- ------- | ----------- | | controller_num=1 (no eswitch) | ------|-------------------------------------------------- (internal wire) | --------------------------------------------------------- | devlink eswitch ports and reps | | ----------------------------------------------------- | | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | | | | ----------- | --------- --------- ------- ------- | | smartNIC| | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | pci rc |==| ------- ----/---- ---/----- ------- ---/--- ---/--- | | connect | | | pf0 |______/________/ | pf1 |___/_______/ | ----------- | ------- ------- | | | | local controller_num=0 (eswitch) | ---------------------------------------------------------}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKJhjhhubh)}(hXIn the above example, the external controller (identified by controller number = 1) doesn't have the eswitch. Local controller (identified by controller number = 0) has the eswitch. The Devlink instance on the local controller has eswitch devlink ports for both the controllers.h]hXIn the above example, the external controller (identified by controller number = 1) doesn’t have the eswitch. Local controller (identified by controller number = 0) has the eswitch. The Devlink instance on the local controller has eswitch devlink ports for both the controllers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjhhubh)}(hXjA non-zero controller number may also be used for ports that are not external. For example, a SmartNIC may have additional local PCI physical functions that are managed by the eswitch but are not on an external host. These ports use a non-zero controller number to distinguish them from the eswitch manager's own functions, while the external flag remains unset.h]hXlA non-zero controller number may also be used for ports that are not external. For example, a SmartNIC may have additional local PCI physical functions that are managed by the eswitch but are not on an external host. These ports use a non-zero controller number to distinguish them from the eswitch manager’s own functions, while the external flag remains unset.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKnhjhhubh)}(hThe ``phys_port_name`` includes the controller prefix (``c``) whenever the controller number is non-zero, regardless of the external flag.h](hThe }(hjhhhNhNubh)}(h``phys_port_name``h]hphys_port_name}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh! includes the controller prefix (}(hjhhhNhNubh)}(h``c``h]hc}(hj,hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubhN) whenever the controller number is non-zero, regardless of the external flag.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKthjhhubh)}(hhh](h)}(hFunction configurationh]hFunction configuration}(hjGhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjDhhhhhKxubh)}(hXUsers can configure one or more function attributes before enumerating the PCI function. Usually it means, user should configure function attribute before a bus specific device for the function is created. However, when SRIOV is enabled, virtual function devices are created on the PCI bus. Hence, function attribute should be configured before binding virtual function device to the driver. For subfunctions, this means user should configure port function attribute before activating the port function.h]hXUsers can configure one or more function attributes before enumerating the PCI function. Usually it means, user should configure function attribute before a bus specific device for the function is created. However, when SRIOV is enabled, virtual function devices are created on the PCI bus. Hence, function attribute should be configured before binding virtual function device to the driver. For subfunctions, this means user should configure port function attribute before activating the port function.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKzhjDhhubh)}(hA user may set the hardware address of the function using `devlink port function set hw_addr` command. For Ethernet port function this means a MAC address.h](h:A user may set the hardware address of the function using }(hjchhhNhNubhtitle_reference)}(h#`devlink port function set hw_addr`h]h!devlink port function set hw_addr}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1jkhjcubh> command. For Ethernet port function this means a MAC address.}(hjchhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(hfUsers may also set the RoCE capability of the function using `devlink port function set roce` command.h](h=Users may also set the RoCE capability of the function using }(hjhhhNhNubjl)}(h `devlink port function set roce`h]hdevlink port function set roce}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jkhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(hcUsers may also set the function as migratable using `devlink port function set migratable` command.h](h4Users may also set the function as migratable using }(hjhhhNhNubjl)}(h&`devlink port function set migratable`h]h$devlink port function set migratable}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jkhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(hvUsers may also set the IPsec crypto capability of the function using `devlink port function set ipsec_crypto` command.h](hEUsers may also set the IPsec crypto capability of the function using }(hjhhhNhNubjl)}(h(`devlink port function set ipsec_crypto`h]h&devlink port function set ipsec_crypto}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jkhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(hvUsers may also set the IPsec packet capability of the function using `devlink port function set ipsec_packet` command.h](hEUsers may also set the IPsec packet capability of the function using }(hjhhhNhNubjl)}(h(`devlink port function set ipsec_packet`h]h&devlink port function set ipsec_packet}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jkhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(h[The ``migratable`` attribute may be set only on ports with ``DEVLINK_PORT_FLAVOUR_PCI_VF``.h](hThe }(hjhhhNhNubh)}(h``migratable``h]h migratable}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh) attribute may be set only on ports with }(hjhhhNhNubh)}(h``DEVLINK_PORT_FLAVOUR_PCI_VF``h]hDEVLINK_PORT_FLAVOUR_PCI_VF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubh.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubh)}(htUsers may also set the maximum IO event queues of the function using `devlink port function set max_io_eqs` command.h](hEUsers may also set the maximum IO event queues of the function using }(hj7hhhNhNubjl)}(h&`devlink port function set max_io_eqs`h]h$devlink port function set max_io_eqs}(hj?hhhNhNubah}(h]h ]h"]h$]h&]uh1jkhj7ubh command.}(hj7hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjDhhubeh}(h]function-configurationah ]h"]function configurationah$]h&]uh1hhjhhhhhKxubh)}(hhh]h)}(hFunction attributesh]hFunction attributes}(hjbhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_hhhhhKubah}(h]function-attributesah ]h"]function attributesah$]h&]uh1hhjhhhhhKubeh}(h]pci-controllersah ]h"]pci controllersah$]h&]uh1hhhhhhhhK=ubh)}(hhh](h)}(hMAC address setuph]hMAC address setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hpThe configured MAC address of the PCI VF/SF will be used by netdevice and rdma device created for the PCI VF/SF.h]hpThe configured MAC address of the PCI VF/SF will be used by netdevice and rdma device created for the PCI VF/SF.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(hGet the MAC address of the VF identified by its unique devlink port index:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 h](h)}(hKGet the MAC address of the VF identified by its unique devlink port index::h]hJGet the MAC address of the VF identified by its unique devlink port index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00h]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXASet the MAC address of the VF identified by its unique devlink port index:: $ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55 h](h)}(hKSet the MAC address of the VF identified by its unique devlink port index::h]hJSet the MAC address of the VF identified by its unique devlink port index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55h]h$ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hGet the MAC address of the SF identified by its unique devlink port index:: $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00 h](h)}(hKGet the MAC address of the SF identified by its unique devlink port index::h]hJGet the MAC address of the SF identified by its unique devlink port index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00h]h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXOSet the MAC address of the SF identified by its unique devlink port index:: $ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88 h](h)}(hKSet the MAC address of the SF identified by its unique devlink port index::h]hJSet the MAC address of the SF identified by its unique devlink port index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88h]h$ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88}hj*sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhjhhubeh}(h]mac-address-setupah ]h"]mac address setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hRoCE capability setuph]hRoCE capability setup}(hjQhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjNhhhhhKubh)}(h,Not all PCI VFs/SFs require RoCE capability.h]h,Not all PCI VFs/SFs require RoCE capability.}(hj_hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNhhubh)}(hGWhen RoCE capability is disabled, it saves system memory per PCI VF/SF.h]hGWhen RoCE capability is disabled, it saves system memory per PCI VF/SF.}(hjmhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNhhubh)}(hWhen user disables RoCE capability for a VF/SF, user application cannot send or receive any RoCE packets through this VF/SF and RoCE GID table for this PCI will be empty.h]hWhen user disables RoCE capability for a VF/SF, user application cannot send or receive any RoCE packets through this VF/SF and RoCE GID table for this PCI will be empty.}(hj{hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNhhubh)}(hnWhen RoCE capability is disabled in the device using port function attribute, VF/SF driver cannot override it.h]hnWhen RoCE capability is disabled in the device using port function attribute, VF/SF driver cannot override it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjNhhubj)}(hhh](j)}(hGet RoCE capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enable h](h)}(h&Get RoCE capability of the VF device::h]h%Get RoCE capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enableh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enable}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX"Set RoCE capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disable h](h)}(h&Set RoCE capability of the VF device::h]h%Set RoCE capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disableh]h$ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disable}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jDjEuh1jhhhKhjNhhubeh}(h]roce-capability-setupah ]h"]roce capability setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hmigratable capability setuph]hmigratable capability setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hLive migration is the process of transferring a live virtual machine from one physical host to another without disrupting its normal operation.h]hLive migration is the process of transferring a live virtual machine from one physical host to another without disrupting its normal operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hrUser who want PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.h]hrUser who want PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWhen user enables migratable capability for a VF, and the HV binds the VF to VFIO driver with migration support, the user can migrate the VM with this VF from one HV to a different one.h]hWhen user enables migratable capability for a VF, and the HV binds the VF to VFIO driver with migration support, the user can migrate the VM with this VF from one HV to a different one.}(hj!hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hHowever, when migratable capability is enable, device will disable features which cannot be migrated. Thus migratable cap can impose limitations on a VF so let the user decide.h]hHowever, when migratable capability is enable, device will disable features which cannot be migrated. Thus migratable cap can impose limitations on a VF so let the user decide.}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hdExample of LM with migratable function configuration: - Get migratable capability of the VF device::h]hcExample of LM with migratable function configuration: - Get migratable capability of the VF device:}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable disableh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable disable}hjKsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjhhubj)}(hhh](j)}(hX2Set migratable capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enable h](h)}(h,Set migratable capability of the VF device::h]h+Set migratable capability of the VF device:}(hj`hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj\ubj)}(h$ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enableh]h$ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enable}hjnsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj\ubeh}(h]h ]h"]h$]h&]uh1jhjYhhhhhNubj)}(hXBind VF to VFIO driver with migration support:: $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bind h](h)}(h/Bind VF to VFIO driver with migration support::h]h.Bind VF to VFIO driver with migration support:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bindh]h$ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bind}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjYhhhhhNubeh}(h]h ]h"]h$]h&]jDjEuh1jhhhKhjhhubh)}(h:Attach VF to the VM. Start the VM. Perform live migration.h]h:Attach VF to the VM. Start the VM. Perform live migration.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubeh}(h]migratable-capability-setupah ]h"]migratable capability setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hIPsec crypto capability setuph]hIPsec crypto capability setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhM ubh)}(hWhen user enables IPsec crypto capability for a VF, user application can offload XFRM state crypto operation (Encrypt/Decrypt) to this VF.h]hWhen user enables IPsec crypto capability for a VF, user application can offload XFRM state crypto operation (Encrypt/Decrypt) to this VF.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubh)}(hsWhen IPsec crypto capability is disabled (default) for a VF, the XFRM state is processed in software by the kernel.h]hsWhen IPsec crypto capability is disabled (default) for a VF, the XFRM state is processed in software by the kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjhhubj)}(hhh](j)}(hGet IPsec crypto capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabled h](h)}(h.Get IPsec crypto capability of the VF device::h]h-Get IPsec crypto capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabledh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabled}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX9Set IPsec crypto capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabled h](h)}(h.Set IPsec crypto capability of the VF device::h]h-Set IPsec crypto capability of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubj)}(h$ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabledh]h$ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabled}hj, sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jDjEuh1jhhhMhjhhubeh}(h]ipsec-crypto-capability-setupah ]h"]ipsec crypto capability setupah$]h&]uh1hhhhhhhhM ubh)}(hhh](h)}(hIPsec packet capability setuph]hIPsec packet capability setup}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjN hhhhhM!ubh)}(hWhen user enables IPsec packet capability for a VF, user application can offload XFRM state and policy crypto operation (Encrypt/Decrypt) to this VF, as well as IPsec encapsulation.h]hWhen user enables IPsec packet capability for a VF, user application can offload XFRM state and policy crypto operation (Encrypt/Decrypt) to this VF, as well as IPsec encapsulation.}(hj_ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM"hjN hhubh)}(h~When IPsec packet capability is disabled (default) for a VF, the XFRM state and policy is processed in software by the kernel.h]h~When IPsec packet capability is disabled (default) for a VF, the XFRM state and policy is processed in software by the kernel.}(hjm hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM&hjN hhubj)}(hhh](j)}(hGet IPsec packet capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled h](h)}(h.Get IPsec packet capability of the VF device::h]h-Get IPsec packet capability of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM)hj~ ubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabledh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhM+hj~ ubeh}(h]h ]h"]h$]h&]uh1jhj{ hhhhhNubj)}(hX9Set IPsec packet capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabled h](h)}(h.Set IPsec packet capability of the VF device::h]h-Set IPsec packet capability of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM0hj ubj)}(h$ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabledh]h$ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabled}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhM2hj ubeh}(h]h ]h"]h$]h&]uh1jhj{ hhhhhNubeh}(h]h ]h"]h$]h&]jDjEuh1jhhhM)hjN hhubeh}(h]ipsec-packet-capability-setupah ]h"]ipsec packet capability setupah$]h&]uh1hhhhhhhhM!ubh)}(hhh](h)}(hMaximum IO events queues setuph]hMaximum IO events queues setup}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhM:ubh)}(hWhen user sets maximum number of IO event queues for a SF or a VF, such function driver is limited to consume only enforced number of IO event queues.h]hWhen user sets maximum number of IO event queues for a SF or a VF, such function driver is limited to consume only enforced number of IO event queues.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj hhubh)}(hXIO event queues deliver events related to IO queues, including network device transmit and receive queues (txq and rxq) and RDMA Queue Pairs (QPs). For example, the number of netdevice channels and RDMA device completion vectors are derived from the function's IO event queues. Usually, the number of interrupt vectors consumed by the driver is limited by the number of IO event queues per device, as each of the IO event queues is connected to an interrupt vector.h]hXIO event queues deliver events related to IO queues, including network device transmit and receive queues (txq and rxq) and RDMA Queue Pairs (QPs). For example, the number of netdevice channels and RDMA device completion vectors are derived from the function’s IO event queues. Usually, the number of interrupt vectors consumed by the driver is limited by the number of IO event queues per device, as each of the IO event queues is connected to an interrupt vector.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM?hj hhubj)}(hhh](j)}(hXGet maximum IO event queues of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10 h](h)}(h.Get maximum IO event queues of the VF device::h]h-Get maximum IO event queues of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMGhj ubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10h]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMIhj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hXBSet maximum IO event queues of the VF device:: $ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32 h](h)}(h.Set maximum IO event queues of the VF device::h]h-Set maximum IO event queues of the VF device:}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj. ubj)}(hX$ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32h]hX$ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32}hj@ sbah}(h]h ]h"]h$]h&]hhuh1jhhhMPhj. ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jDjEuh1jhhhMGhj hhubh)}(hhh](h)}(h Subfunctionh]h Subfunction}(hj] hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjZ hhhhhMXubh)}(hX+Subfunction is a lightweight function that has a parent PCI function on which it is deployed. Subfunction is created and deployed in unit of 1. Unlike SRIOV VFs, a subfunction doesn't require its own PCI virtual function. A subfunction communicates with the hardware through the parent PCI function.h]hX-Subfunction is a lightweight function that has a parent PCI function on which it is deployed. Subfunction is created and deployed in unit of 1. Unlike SRIOV VFs, a subfunction doesn’t require its own PCI virtual function. A subfunction communicates with the hardware through the parent PCI function.}(hjk hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMZhjZ hhubh)}(h9To use a subfunction, 3 steps setup sequence is followed:h]h9To use a subfunction, 3 steps setup sequence is followed:}(hjy hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM_hjZ hhubhenumerated_list)}(hhh](j)}(hcreate - create a subfunction;h]h)}(hj h]hcreate - create a subfunction;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMahj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h-configure - configure subfunction attributes;h]h)}(hj h]h-configure - configure subfunction attributes;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMbhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h!deploy - deploy the subfunction; h]h)}(h deploy - deploy the subfunction;h]h deploy - deploy the subfunction;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMchj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1j hjZ hhhhhMaubh)}(h{Subfunction management is done using devlink port user interface. User performs setup on the subfunction management device.h]h{Subfunction management is done using devlink port user interface. User performs setup on the subfunction management device.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMehjZ hhubeh}(h] subfunctionah ]h"] subfunctionah$]h&]uh1hhj hhhhhMXubeh}(h]maximum-io-events-queues-setupah ]h"]maximum io events queues setupah$]h&]uh1hhhhhhhhM:ubh)}(hhh](h)}(h (1) Createh]h (1) Create}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMiubh)}(hXA subfunction is created using a devlink port interface. A user adds the subfunction by adding a devlink port of subfunction flavour. The devlink kernel code calls down to subfunction management driver (devlink ops) and asks it to create a subfunction devlink port. Driver then instantiates the subfunction port and any associated objects such as health reporters and representor netdevice.h]hXA subfunction is created using a devlink port interface. A user adds the subfunction by adding a devlink port of subfunction flavour. The devlink kernel code calls down to subfunction management driver (devlink ops) and asks it to create a subfunction devlink port. Driver then instantiates the subfunction port and any associated objects such as health reporters and representor netdevice.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMjhj hhubeh}(h]createah ]h"] (1) createah$]h&]uh1hhhhhhhhMiubh)}(hhh](h)}(h (2) Configureh]h (2) Configure}(hj% hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj" hhhhhMrubh)}(hXA subfunction devlink port is created but it is not active yet. That means the entities are created on devlink side, the e-switch port representor is created, but the subfunction device itself is not created. A user might use e-switch port representor to do settings, putting it into bridge, adding TC rules, etc. A user might as well configure the hardware address (such as MAC address) of the subfunction while subfunction is inactive.h]hXA subfunction devlink port is created but it is not active yet. That means the entities are created on devlink side, the e-switch port representor is created, but the subfunction device itself is not created. A user might use e-switch port representor to do settings, putting it into bridge, adding TC rules, etc. A user might as well configure the hardware address (such as MAC address) of the subfunction while subfunction is inactive.}(hj3 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMshj" hhubeh}(h] configureah ]h"] (2) configureah$]h&]uh1hhhhhhhhMrubh)}(hhh](h)}(h (3) Deployh]h (3) Deploy}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjI hhhhhM{ubh)}(hXOnce a subfunction is configured, user must activate it to use it. Upon activation, subfunction management driver asks the subfunction management device to instantiate the subfunction device on particular PCI function. A subfunction device is created on the :ref:`Documentation/driver-api/auxiliary_bus.rst `. At this point a matching subfunction driver binds to the subfunction's auxiliary device.h](hXOnce a subfunction is configured, user must activate it to use it. Upon activation, subfunction management driver asks the subfunction management device to instantiate the subfunction device on particular PCI function. A subfunction device is created on the }(hjZ hhhNhNubh)}(hA:ref:`Documentation/driver-api/auxiliary_bus.rst `h]hinline)}(hjd h]h*Documentation/driver-api/auxiliary_bus.rst}(hjh hhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jf hjb ubah}(h]h ]h"]h$]h&]refdocnetworking/devlink/devlink-port refdomainjs reftyperef refexplicitrefwarn reftarget auxiliary_busuh1hhhhM|hjZ ubh\. At this point a matching subfunction driver binds to the subfunction’s auxiliary device.}(hjZ hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM|hjI hhubh)}(hhh](h)}(hRate object managementh]hRate object management}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMubh)}(hDevlink provides API to manage tx rates of single devlink port or a group. This is done through rate objects, which can be one of the two types:h]hDevlink provides API to manage tx rates of single devlink port or a group. This is done through rate objects, which can be one of the two types:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubhdefinition_list)}(hhh](hdefinition_list_item)}(h``leaf`` Represents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as ``pci//``; h](hterm)}(h``leaf``h]h)}(hj h]hleaf}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubh definition)}(hhh]h)}(hRepresents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as ``pci//``;h](hRepresents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as }(hj hhhNhNubh)}(h``pci//``h]hpci//}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh;}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hX;``node`` Represents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as ``pci//``, where ``node_name`` can be any identifier, except decimal number, to avoid collisions with leafs. h](j )}(h``node``h]h)}(hj h]hnode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hhh]h)}(hX1Represents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as ``pci//``, where ``node_name`` can be any identifier, except decimal number, to avoid collisions with leafs.h](hRepresents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as }(hj# hhhNhNubh)}(h``pci//``h]hpci//}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj# ubh, where }(hj# hhhNhNubh)}(h ``node_name``h]h node_name}(hj= hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj# ubhN can be any identifier, except decimal number, to avoid collisions with leafs.}(hj# hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhj hhubeh}(h]h ]h"]h$]h&]uh1j hj hhhhhNubh)}(h;API allows to configure following rate object's parameters:h]h=API allows to configure following rate object’s parameters:}(hjg hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj )}(hhh](j )}(h``tx_share`` Minimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group. h](j )}(h ``tx_share``h]h)}(hj~ h]htx_share}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj| ubah}(h]h ]h"]h$]h&]uh1j hhhMhjx ubj )}(hhh]h)}(hMinimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group.h]hMinimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hjx ubeh}(h]h ]h"]h$]h&]uh1j hhhMhju ubj )}(h"``tx_max`` Maximum TX rate value. h](j )}(h ``tx_max``h]h)}(hj h]htx_max}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hhh]h)}(hMaximum TX rate value.h]hMaximum TX rate value.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhju hhubj )}(hX4``tx_priority`` Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling. h](j )}(h``tx_priority``h]h)}(hj h]h tx_priority}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hhh]h)}(hX#Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling.h]hX#Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhju hhubj )}(hXv``tx_weight`` Allows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings. h](j )}(h ``tx_weight``h]h)}(hj& h]h tx_weight}(hj( hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj$ ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hhh]h)}(hXgAllows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings.h]hXgAllows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings.}(hj> hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj; ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhju hhubj )}(hX\``parent`` Parent node name. Parent node rate limits are considered as additional limits to all node children limits. ``tx_max`` is an upper limit for children. ``tx_share`` is a total bandwidth distributed among children. If the device supports cross-function scheduling, the parent can be from a different function of the same underlying device. h](j )}(h ``parent``h]h)}(hj^ h]hparent}(hj` hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj\ ubah}(h]h ]h"]h$]h&]uh1j hhhMhjX ubj )}(hhh]h)}(hXPParent node name. Parent node rate limits are considered as additional limits to all node children limits. ``tx_max`` is an upper limit for children. ``tx_share`` is a total bandwidth distributed among children. If the device supports cross-function scheduling, the parent can be from a different function of the same underlying device.h](hkParent node name. Parent node rate limits are considered as additional limits to all node children limits. }(hjv hhhNhNubh)}(h ``tx_max``h]htx_max}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv ubh! is an upper limit for children. }(hjv hhhNhNubh)}(h ``tx_share``h]htx_share}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjv ubh is a total bandwidth distributed among children. If the device supports cross-function scheduling, the parent can be from a different function of the same underlying device.}(hjv hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjs ubah}(h]h ]h"]h$]h&]uh1j hjX ubeh}(h]h ]h"]h$]h&]uh1j hhhMh>ju hhubj )}(hX``tc_bw`` Allow users to set the bandwidth allocation per traffic class on rate objects. This enables fine-grained QoS configurations by assigning a relative share value to each traffic class. The bandwidth is distributed in proportion to the share value for each class, relative to the sum of all shares. When applied to a non-leaf node, tc_bw determines how bandwidth is shared among its child elements. h](j )}(h ``tc_bw``h]h)}(hj h]htc_bw}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j hhhMhj ubj )}(hhh]h)}(hXAllow users to set the bandwidth allocation per traffic class on rate objects. This enables fine-grained QoS configurations by assigning a relative share value to each traffic class. The bandwidth is distributed in proportion to the share value for each class, relative to the sum of all shares. When applied to a non-leaf node, tc_bw determines how bandwidth is shared among its child elements.h]hXAllow users to set the bandwidth allocation per traffic class on rate objects. This enables fine-grained QoS configurations by assigning a relative share value to each traffic class. The bandwidth is distributed in proportion to the share value for each class, relative to the sum of all shares. When applied to a non-leaf node, tc_bw determines how bandwidth is shared among its child elements.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1j hj ubeh}(h]h ]h"]h$]h&]uh1j hhhMhju hhubeh}(h]h ]h"]h$]h&]uh1j hj hhhhhNubh)}(h``tx_priority`` and ``tx_weight`` can be used simultaneously. In that case nodes with the same priority form a WFQ subgroup in the sibling group and arbitration among them is based on assigned weights.h](h)}(h``tx_priority``h]h tx_priority}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh and }(hj hhhNhNubh)}(h ``tx_weight``h]h tx_weight}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh can be used simultaneously. In that case nodes with the same priority form a WFQ subgroup in the sibling group and arbitration among them is based on assigned weights.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(h%Arbitration flow from the high level:h]h%Arbitration flow from the high level:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj )}(hhh](j)}(hChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use ``tx_priority`` as a parameter for this arbitration. h]h)}(hChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use ``tx_priority`` as a parameter for this arbitration.h](hsChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use }(hj5hhhNhNubh)}(h``tx_priority``h]h tx_priority}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj5ubh% as a parameter for this arbitration.}(hj5hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj1ubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubj)}(hIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use ``tx_weight`` as a parameter for this arbitration. h]h)}(hIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use ``tx_weight`` as a parameter for this arbitration.h](hWIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use }(hj_hhhNhNubh)}(h ``tx_weight``h]h tx_weight}(hjghhhNhNubah}(h]h ]h"]h$]h&]uh1hhj_ubh% as a parameter for this arbitration.}(hj_hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj[ubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubj)}(hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established. h]h)}(hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established.h]hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubj)}(hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes. h]h)}(hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes.h]hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jhj.hhhhhNubeh}(h]h ]h"]h$]h&]j j j hj .uh1j hj hhhhhMubh)}(hDriver implementations are allowed to support both or either rate object types and setting methods of their parameters. Additionally driver implementation may export nodes/leafs and their child-parent relationships.h]hDriver implementations are allowed to support both or either rate object types and setting methods of their parameters. Additionally driver implementation may export nodes/leafs and their child-parent relationships.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]rate-object-managementah ]h"]rate object managementah$]h&]uh1hhjI hhhhhMubh)}(hhh](h)}(hTerms and Definitionsh]hTerms and Definitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj()}(hhh](h)}(hTerms and Definitionsh]hTerms and Definitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj;)}(hhh](j@)}(hhh]h}(h]h ]h"]h$]h&]jJKuh1j?hjubj@)}(hhh]h}(h]h ]h"]h$]h&]jJKZuh1j?hjubjU)}(hhh](jZ)}(hhh](j_)}(hhh]h)}(hTermh]hTerm}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hj ubj_)}(hhh]h)}(h Definitionsh]h Definitions}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j^hj ubeh}(h]h ]h"]h$]h&]uh1jYhj ubjZ)}(hhh](j_)}(hhh]h)}(h``PCI device``h]h)}(hjKh]h PCI device}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1j^hjCubj_)}(hhh]h)}(h[A physical PCI device having one or more PCI buses consists of one or more PCI controllers.h]h[A physical PCI device having one or more PCI buses consists of one or more PCI controllers.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjfubah}(h]h ]h"]h$]h&]uh1j^hjCubeh}(h]h ]h"]h$]h&]uh1jYhj ubjZ)}(hhh](j_)}(hhh]h)}(h``PCI controller``h]h)}(hjh]hPCI controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(heA controller consists of potentially multiple physical functions, virtual functions and subfunctions.h]heA controller consists of potentially multiple physical functions, virtual functions and subfunctions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhj ubjZ)}(hhh](j_)}(hhh]h)}(h``Port function``h]h)}(hjh]h Port function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(h+An object to manage the function of a port.h]h+An object to manage the function of a port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhj ubjZ)}(hhh](j_)}(hhh]h)}(h``Subfunction``h]h)}(hj h]h Subfunction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1j^hjubj_)}(hhh]h)}(hLA lightweight function that has parent PCI function on which it is deployed.h]hLA lightweight function that has parent PCI function on which it is deployed.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj&ubah}(h]h ]h"]h$]h&]uh1j^hjubeh}(h]h ]h"]h$]h&]uh1jYhj ubjZ)}(hhh](j_)}(hhh]h)}(h``Subfunction device``h]h)}(hjKh]hSubfunction device}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hhhhMhjFubah}(h]h ]h"]h$]h&]uh1j^hjCubj_)}(hhh]h)}(h