sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftarget3/translations/zh_CN/networking/devlink/devlink-portmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/zh_TW/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/it_IT/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ja_JP/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/ko_KR/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftarget3/translations/sp_SP/networking/devlink/devlink-portmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h SPDX-License-Identifier: GPL-2.0h]h SPDX-License-Identifier: GPL-2.0}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhM/var/lib/git/docbuild/linux/Documentation/networking/devlink/devlink-port.rsthKubhtarget)}(h.. _devlink_port:h]h}(h]h ]h"]h$]h&]refid devlink-portuh1hhKhhhhhhubhsection)}(hhh](htitle)}(h Devlink Porth]h Devlink Port}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhhhhhKubh paragraph)}(h``devlink-port`` is a port that exists on the device. It has a logically separate ingress/egress point of the device. A devlink port can be any one of many flavours. A devlink port flavour along with port attributes describe what a port represents.h](hliteral)}(h``devlink-port``h]h devlink-port}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhubh is a port that exists on the device. It has a logically separate ingress/egress point of the device. A devlink port can be any one of many flavours. A devlink port flavour along with port attributes describe what a port represents.}(hhhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK hhhhubh)}(hwA device driver that intends to publish a devlink port sets the devlink port attributes and registers the devlink port.h]hwA device driver that intends to publish a devlink port sets the devlink port attributes and registers the devlink port.}(hhhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubh)}(h*Devlink port flavours are described below.h]h*Devlink port flavours are described below.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhhhhubhtable)}(hhh](h)}(hList of devlink port flavoursh]hList of devlink port flavours}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubhtgroup)}(hhh](hcolspec)}(hhh]h}(h]h ]h"]h$]h&]colwidthK!uh1j+hj(ubj,)}(hhh]h}(h]h ]h"]h$]h&]j6KZuh1j+hj(ubhtbody)}(hhh](hrow)}(hhh](hentry)}(hhh]h)}(hFlavourh]hFlavour}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjLubah}(h]h ]h"]h$]h&]uh1jJhjGubjK)}(hhh]h)}(h Descriptionh]h Description}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjcubah}(h]h ]h"]h$]h&]uh1jJhjGubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h!``DEVLINK_PORT_FLAVOUR_PHYSICAL``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PHYSICAL}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hiAny kind of physical port. This can be an eswitch physical port or any other physical port on the device.h]hiAny kind of physical port. This can be an eswitch physical port or any other physical port on the device.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_DSA``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_DSA}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h'This indicates a DSA interconnect port.h]h'This indicates a DSA interconnect port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_CPU``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_CPU}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhKhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h1This indicates a CPU port applicable only to DSA.h]h1This indicates a CPU port applicable only to DSA.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj#ubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_PF``h]h)}(hjHh]hDEVLINK_PORT_FLAVOUR_PCI_PF}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjFubah}(h]h ]h"]h$]h&]uh1hhhhKhjCubah}(h]h ]h"]h$]h&]uh1jJhj@ubjK)}(hhh]h)}(hQThis indicates an eswitch port representing a port of PCI physical function (PF).h]hQThis indicates an eswitch port representing a port of PCI physical function (PF).}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK hjcubah}(h]h ]h"]h$]h&]uh1jJhj@ubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_VF``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PCI_VF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK"hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hPThis indicates an eswitch port representing a port of PCI virtual function (VF).h]hPThis indicates an eswitch port representing a port of PCI virtual function (VF).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK#hjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_FLAVOUR_PCI_SF``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_PCI_SF}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK%hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hKThis indicates an eswitch port representing a port of PCI subfunction (SF).h]hKThis indicates an eswitch port representing a port of PCI subfunction (SF).}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK&hjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubjF)}(hhh](jK)}(hhh]h)}(h ``DEVLINK_PORT_FLAVOUR_VIRTUAL``h]h)}(hjh]hDEVLINK_PORT_FLAVOUR_VIRTUAL}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK(hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h;This indicates a virtual port for the PCI virtual function.h]h;This indicates a virtual port for the PCI virtual function.}(hj&hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK)hj#ubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjBubeh}(h]h ]h"]h$]h&]uh1j@hj(ubeh}(h]h ]h"]h$]h&]colsKuh1j&hjubeh}(h]id2ah ]colwidths-givenah"]h$]h&]uh1jhhhhhNhNubh)}(hODevlink port can have a different type based on the link layer described below.h]hODevlink port can have a different type based on the link layer described below.}(hjUhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK+hhhhubj)}(hhh](h)}(hList of devlink port typesh]hList of devlink port types}(hjfhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK-hjcubj')}(hhh](j,)}(hhh]h}(h]h ]h"]h$]h&]j6Kuh1j+hjtubj,)}(hhh]h}(h]h ]h"]h$]h&]j6KZuh1j+hjtubjA)}(hhh](jF)}(hhh](jK)}(hhh]h)}(hTypeh]hType}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK0hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h Descriptionh]h Description}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK1hjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_TYPE_ETH``h]h)}(hjh]hDEVLINK_PORT_TYPE_ETH}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhK2hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hKDriver should set this port type when a link layer of the port is Ethernet.h]hKDriver should set this port type when a link layer of the port is Ethernet.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK3hjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_TYPE_IB``h]h)}(hj h]hDEVLINK_PORT_TYPE_IB}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhhhK5hjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hMDriver should set this port type when a link layer of the port is InfiniBand.h]hMDriver should set this port type when a link layer of the port is InfiniBand.}(hj)hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK6hj&ubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjubjF)}(hhh](jK)}(hhh]h)}(h``DEVLINK_PORT_TYPE_AUTO``h]h)}(hjKh]hDEVLINK_PORT_TYPE_AUTO}(hjMhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjIubah}(h]h ]h"]h$]h&]uh1hhhhK8hjFubah}(h]h ]h"]h$]h&]uh1jJhjCubjK)}(hhh]h)}(hYThis type is indicated by the user when driver should detect the port type automatically.h]hYThis type is indicated by the user when driver should detect the port type automatically.}(hjihhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK9hjfubah}(h]h ]h"]h$]h&]uh1jJhjCubeh}(h]h ]h"]h$]h&]uh1jEhjubeh}(h]h ]h"]h$]h&]uh1j@hjtubeh}(h]h ]h"]h$]h&]colsKuh1j&hjcubeh}(h]id3ah ]jQah"]h$]h&]uh1jhhhhhNhNubh)}(hhh](h)}(hPCI controllersh]hPCI controllers}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhK=ubh)}(hIn most cases a PCI device has only one controller. A controller consists of potentially multiple physical, virtual functions and subfunctions. A function consists of one or more ports. This port is represented by the devlink eswitch port.h]hIn most cases a PCI device has only one controller. A controller consists of potentially multiple physical, virtual functions and subfunctions. A function consists of one or more ports. This port is represented by the devlink eswitch port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhK>hjhhubh)}(hX3A PCI device connected to multiple CPUs or multiple PCI root complexes or a SmartNIC, however, may have multiple controllers. For a device with multiple controllers, each controller is distinguished by a unique controller number. An eswitch is on the PCI device which supports ports of multiple controllers.h]hX3A PCI device connected to multiple CPUs or multiple PCI root complexes or a SmartNIC, however, may have multiple controllers. For a device with multiple controllers, each controller is distinguished by a unique controller number. An eswitch is on the PCI device which supports ports of multiple controllers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKChjhhubh)}(h2An example view of a system with two controllers::h]h1An example view of a system with two controllers:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKHhjhhubh literal_block)}(hX --------------------------------------------------------- | | | --------- --------- ------- ------- | ----------- | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | server | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ | | connect | | ------- ------- | ----------- | | controller_num=1 (no eswitch) | ------|-------------------------------------------------- (internal wire) | --------------------------------------------------------- | devlink eswitch ports and reps | | ----------------------------------------------------- | | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | | | | ----------- | --------- --------- ------- ------- | | smartNIC| | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | pci rc |==| ------- ----/---- ---/----- ------- ---/--- ---/--- | | connect | | | pf0 |______/________/ | pf1 |___/_______/ | ----------- | ------- ------- | | | | local controller_num=0 (eswitch) | ---------------------------------------------------------h]hX --------------------------------------------------------- | | | --------- --------- ------- ------- | ----------- | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | server | | ------- ----/---- ---/----- ------- ---/--- ---/--- | | pci rc |=== | pf0 |______/________/ | pf1 |___/_______/ | | connect | | ------- ------- | ----------- | | controller_num=1 (no eswitch) | ------|-------------------------------------------------- (internal wire) | --------------------------------------------------------- | devlink eswitch ports and reps | | ----------------------------------------------------- | | |ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 | ctrl-0 |ctrl-0 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | |ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 | ctrl-1 |ctrl-1 | | | |pf0 | pf0vfN | pf0sfN | pf1 | pf1vfN |pf1sfN | | | ----------------------------------------------------- | | | | | ----------- | --------- --------- ------- ------- | | smartNIC| | | vf(s) | | sf(s) | |vf(s)| |sf(s)| | | pci rc |==| ------- ----/---- ---/----- ------- ---/--- ---/--- | | connect | | | pf0 |______/________/ | pf1 |___/_______/ | ----------- | ------- ------- | | | | local controller_num=0 (eswitch) | ---------------------------------------------------------}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKJhjhhubh)}(hXIn the above example, the external controller (identified by controller number = 1) doesn't have the eswitch. Local controller (identified by controller number = 0) has the eswitch. The Devlink instance on the local controller has eswitch devlink ports for both the controllers.h]hXIn the above example, the external controller (identified by controller number = 1) doesn’t have the eswitch. Local controller (identified by controller number = 0) has the eswitch. The Devlink instance on the local controller has eswitch devlink ports for both the controllers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKihjhhubh)}(hhh](h)}(hFunction configurationh]hFunction configuration}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKoubh)}(hXUsers can configure one or more function attributes before enumerating the PCI function. Usually it means, user should configure function attribute before a bus specific device for the function is created. However, when SRIOV is enabled, virtual function devices are created on the PCI bus. Hence, function attribute should be configured before binding virtual function device to the driver. For subfunctions, this means user should configure port function attribute before activating the port function.h]hXUsers can configure one or more function attributes before enumerating the PCI function. Usually it means, user should configure function attribute before a bus specific device for the function is created. However, when SRIOV is enabled, virtual function devices are created on the PCI bus. Hence, function attribute should be configured before binding virtual function device to the driver. For subfunctions, this means user should configure port function attribute before activating the port function.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKqhjhhubh)}(hA user may set the hardware address of the function using `devlink port function set hw_addr` command. For Ethernet port function this means a MAC address.h](h:A user may set the hardware address of the function using }(hjhhhNhNubhtitle_reference)}(h#`devlink port function set hw_addr`h]h!devlink port function set hw_addr}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh> command. For Ethernet port function this means a MAC address.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKyhjhhubh)}(hfUsers may also set the RoCE capability of the function using `devlink port function set roce` command.h](h=Users may also set the RoCE capability of the function using }(hj1hhhNhNubj)}(h `devlink port function set roce`h]hdevlink port function set roce}(hj9hhhNhNubah}(h]h ]h"]h$]h&]uh1jhj1ubh command.}(hj1hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhK}hjhhubh)}(hcUsers may also set the function as migratable using `devlink port function set migratable` command.h](h4Users may also set the function as migratable using }(hjQhhhNhNubj)}(h&`devlink port function set migratable`h]h$devlink port function set migratable}(hjYhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjQubh command.}(hjQhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hvUsers may also set the IPsec crypto capability of the function using `devlink port function set ipsec_crypto` command.h](hEUsers may also set the IPsec crypto capability of the function using }(hjqhhhNhNubj)}(h(`devlink port function set ipsec_crypto`h]h&devlink port function set ipsec_crypto}(hjyhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjqubh command.}(hjqhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hvUsers may also set the IPsec packet capability of the function using `devlink port function set ipsec_packet` command.h](hEUsers may also set the IPsec packet capability of the function using }(hjhhhNhNubj)}(h(`devlink port function set ipsec_packet`h]h&devlink port function set ipsec_packet}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(htUsers may also set the maximum IO event queues of the function using `devlink port function set max_io_eqs` command.h](hEUsers may also set the maximum IO event queues of the function using }(hjhhhNhNubj)}(h&`devlink port function set max_io_eqs`h]h$devlink port function set max_io_eqs}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jhjubh command.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhKhjhhubeh}(h]function-configurationah ]h"]function configurationah$]h&]uh1hhjhhhhhKoubh)}(hhh]h)}(hFunction attributesh]hFunction attributes}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubah}(h]function-attributesah ]h"]function attributesah$]h&]uh1hhjhhhhhKubeh}(h]pci-controllersah ]h"]pci controllersah$]h&]uh1hhhhhhhhK=ubh)}(hhh](h)}(hMAC address setuph]hMAC address setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(hpThe configured MAC address of the PCI VF/SF will be used by netdevice and rdma device created for the PCI VF/SF.h]hpThe configured MAC address of the PCI VF/SF will be used by netdevice and rdma device created for the PCI VF/SF.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh bullet_list)}(hhh](h list_item)}(hGet the MAC address of the VF identified by its unique devlink port index:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 h](h)}(hKGet the MAC address of the VF identified by its unique devlink port index::h]hJGet the MAC address of the VF identified by its unique devlink port index:}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj ubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00h]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00}hj2sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXASet the MAC address of the VF identified by its unique devlink port index:: $ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55 h](h)}(hKSet the MAC address of the VF identified by its unique devlink port index::h]hJSet the MAC address of the VF identified by its unique devlink port index:}(hjJhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjFubj)}(h$ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55h]h$ devlink port function set pci/0000:06:00.0/2 hw_addr 00:11:22:33:44:55 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:11:22:33:44:55}hjXsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjFubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hGet the MAC address of the SF identified by its unique devlink port index:: $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00 h](h)}(hKGet the MAC address of the SF identified by its unique devlink port index::h]hJGet the MAC address of the SF identified by its unique devlink port index:}(hjphhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjlubj)}(h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00h]h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00}hj~sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjlubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXOSet the MAC address of the SF identified by its unique devlink port index:: $ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88 h](h)}(hKSet the MAC address of the SF identified by its unique devlink port index::h]hJSet the MAC address of the SF identified by its unique devlink port index:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88h]h$ devlink port function set pci/0000:06:00.0/32768 hw_addr 00:00:00:00:88:88 $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:88:88}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhjhhubeh}(h]mac-address-setupah ]h"]mac address setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hRoCE capability setuph]hRoCE capability setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhKubh)}(h,Not all PCI VFs/SFs require RoCE capability.h]h,Not all PCI VFs/SFs require RoCE capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hGWhen RoCE capability is disabled, it saves system memory per PCI VF/SF.h]hGWhen RoCE capability is disabled, it saves system memory per PCI VF/SF.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hWhen user disables RoCE capability for a VF/SF, user application cannot send or receive any RoCE packets through this VF/SF and RoCE GID table for this PCI will be empty.h]hWhen user disables RoCE capability for a VF/SF, user application cannot send or receive any RoCE packets through this VF/SF and RoCE GID table for this PCI will be empty.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubh)}(hnWhen RoCE capability is disabled in the device using port function attribute, VF/SF driver cannot override it.h]hnWhen RoCE capability is disabled in the device using port function attribute, VF/SF driver cannot override it.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjhhubj)}(hhh](j)}(hGet RoCE capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enable h](h)}(h&Get RoCE capability of the VF device::h]h%Get RoCE capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enableh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce enable}hj&sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX"Set RoCE capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disable h](h)}(h&Set RoCE capability of the VF device::h]h%Set RoCE capability of the VF device:}(hj>hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj:ubj)}(h$ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disableh]h$ devlink port function set pci/0000:06:00.0/2 roce disable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 roce disable}hjLsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj:ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjhhubeh}(h]roce-capability-setupah ]h"]roce capability setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hmigratable capability setuph]hmigratable capability setup}(hjqhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjnhhhhhKubh)}(hLive migration is the process of transferring a live virtual machine from one physical host to another without disrupting its normal operation.h]hLive migration is the process of transferring a live virtual machine from one physical host to another without disrupting its normal operation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubh)}(hrUser who want PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.h]hrUser who want PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubh)}(hWhen user enables migratable capability for a VF, and the HV binds the VF to VFIO driver with migration support, the user can migrate the VM with this VF from one HV to a different one.h]hWhen user enables migratable capability for a VF, and the HV binds the VF to VFIO driver with migration support, the user can migrate the VM with this VF from one HV to a different one.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubh)}(hHowever, when migratable capability is enable, device will disable features which cannot be migrated. Thus migratable cap can impose limitations on a VF so let the user decide.h]hHowever, when migratable capability is enable, device will disable features which cannot be migrated. Thus migratable cap can impose limitations on a VF so let the user decide.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubh)}(hdExample of LM with migratable function configuration: - Get migratable capability of the VF device::h]hcExample of LM with migratable function configuration: - Get migratable capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable disableh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable disable}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjnhhubj)}(hhh](j)}(hX2Set migratable capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enable h](h)}(h,Set migratable capability of the VF device::h]h+Set migratable capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enableh]h$ devlink port function set pci/0000:06:00.0/2 migratable enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 migratable enable}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hXBind VF to VFIO driver with migration support:: $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bind h](h)}(h/Bind VF to VFIO driver with migration support::h]h.Bind VF to VFIO driver with migration support:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjubj)}(h$ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bindh]h$ echo > /sys/bus/pci/devices/0000:08:00.0/driver/unbind $ echo mlx5_vfio_pci > /sys/bus/pci/devices/0000:08:00.0/driver_override $ echo > /sys/bus/pci/devices/0000:08:00.0/driver/bind}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhKhjnhhubh)}(h:Attach VF to the VM. Start the VM. Perform live migration.h]h:Attach VF to the VM. Start the VM. Perform live migration.}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhjnhhubeh}(h]migratable-capability-setupah ]h"]migratable capability setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hIPsec crypto capability setuph]hIPsec crypto capability setup}(hjAhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj>hhhhhKubh)}(hWhen user enables IPsec crypto capability for a VF, user application can offload XFRM state crypto operation (Encrypt/Decrypt) to this VF.h]hWhen user enables IPsec crypto capability for a VF, user application can offload XFRM state crypto operation (Encrypt/Decrypt) to this VF.}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhKhj>hhubh)}(hsWhen IPsec crypto capability is disabled (default) for a VF, the XFRM state is processed in software by the kernel.h]hsWhen IPsec crypto capability is disabled (default) for a VF, the XFRM state is processed in software by the kernel.}(hj]hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj>hhubj)}(hhh](j)}(hGet IPsec crypto capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabled h](h)}(h.Get IPsec crypto capability of the VF device::h]h-Get IPsec crypto capability of the VF device:}(hjrhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjnubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabledh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto disabled}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjnubeh}(h]h ]h"]h$]h&]uh1jhjkhhhhhNubj)}(hX9Set IPsec crypto capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabled h](h)}(h.Set IPsec crypto capability of the VF device::h]h-Set IPsec crypto capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM hjubj)}(h$ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabledh]h$ devlink port function set pci/0000:06:00.0/2 ipsec_crypto enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_crypto enabled}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhM hjubeh}(h]h ]h"]h$]h&]uh1jhjkhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhj>hhubeh}(h]ipsec-crypto-capability-setupah ]h"]ipsec crypto capability setupah$]h&]uh1hhhhhhhhKubh)}(hhh](h)}(hIPsec packet capability setuph]hIPsec packet capability setup}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubh)}(hWhen user enables IPsec packet capability for a VF, user application can offload XFRM state and policy crypto operation (Encrypt/Decrypt) to this VF, as well as IPsec encapsulation.h]hWhen user enables IPsec packet capability for a VF, user application can offload XFRM state and policy crypto operation (Encrypt/Decrypt) to this VF, as well as IPsec encapsulation.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubh)}(h~When IPsec packet capability is disabled (default) for a VF, the XFRM state and policy is processed in software by the kernel.h]h~When IPsec packet capability is disabled (default) for a VF, the XFRM state and policy is processed in software by the kernel.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhhubj)}(hhh](j)}(hGet IPsec packet capability of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled h](h)}(h.Get IPsec packet capability of the VF device::h]h-Get IPsec packet capability of the VF device:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabledh]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hX9Set IPsec packet capability of the VF device:: $ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabled h](h)}(h.Set IPsec packet capability of the VF device::h]h-Set IPsec packet capability of the VF device:}(hj" hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM$hj ubj)}(h$ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabledh]h$ devlink port function set pci/0000:06:00.0/2 ipsec_packet enable $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet enabled}hj0 sbah}(h]h ]h"]h$]h&]hhuh1jhhhM&hj ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhMhjhhubeh}(h]ipsec-packet-capability-setupah ]h"]ipsec packet capability setupah$]h&]uh1hhhhhhhhMubh)}(hhh](h)}(hMaximum IO events queues setuph]hMaximum IO events queues setup}(hjU hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjR hhhhhM.ubh)}(hWhen user sets maximum number of IO event queues for a SF or a VF, such function driver is limited to consume only enforced number of IO event queues.h]hWhen user sets maximum number of IO event queues for a SF or a VF, such function driver is limited to consume only enforced number of IO event queues.}(hjc hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM/hjR hhubh)}(hXIO event queues deliver events related to IO queues, including network device transmit and receive queues (txq and rxq) and RDMA Queue Pairs (QPs). For example, the number of netdevice channels and RDMA device completion vectors are derived from the function's IO event queues. Usually, the number of interrupt vectors consumed by the driver is limited by the number of IO event queues per device, as each of the IO event queues is connected to an interrupt vector.h]hXIO event queues deliver events related to IO queues, including network device transmit and receive queues (txq and rxq) and RDMA Queue Pairs (QPs). For example, the number of netdevice channels and RDMA device completion vectors are derived from the function’s IO event queues. Usually, the number of interrupt vectors consumed by the driver is limited by the number of IO event queues per device, as each of the IO event queues is connected to an interrupt vector.}(hjq hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM3hjR hhubj)}(hhh](j)}(hXGet maximum IO event queues of the VF device:: $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10 h](h)}(h.Get maximum IO event queues of the VF device::h]h-Get maximum IO event queues of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM;hj ubj)}(h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10h]h$ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 10}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhM=hj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hXBSet maximum IO event queues of the VF device:: $ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32 h](h)}(h.Set maximum IO event queues of the VF device::h]h-Set maximum IO event queues of the VF device:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMBhj ubj)}(hX$ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32h]hX$ devlink port function set pci/0000:06:00.0/2 max_io_eqs 32 $ devlink port show pci/0000:06:00.0/2 pci/0000:06:00.0/2: type eth netdev enp6s0pf0vf1 flavour pcivf pfnum 0 vfnum 1 function: hw_addr 00:00:00:00:00:00 ipsec_packet disabled max_io_eqs 32}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMDhj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]jjuh1jhhhM;hjR hhubh)}(hhh](h)}(h Subfunctionh]h Subfunction}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMLubh)}(hX+Subfunction is a lightweight function that has a parent PCI function on which it is deployed. Subfunction is created and deployed in unit of 1. Unlike SRIOV VFs, a subfunction doesn't require its own PCI virtual function. A subfunction communicates with the hardware through the parent PCI function.h]hX-Subfunction is a lightweight function that has a parent PCI function on which it is deployed. Subfunction is created and deployed in unit of 1. Unlike SRIOV VFs, a subfunction doesn’t require its own PCI virtual function. A subfunction communicates with the hardware through the parent PCI function.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMNhj hhubh)}(h9To use a subfunction, 3 steps setup sequence is followed:h]h9To use a subfunction, 3 steps setup sequence is followed:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMShj hhubhenumerated_list)}(hhh](j)}(hcreate - create a subfunction;h]h)}(hj h]hcreate - create a subfunction;}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMUhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h-configure - configure subfunction attributes;h]h)}(hj h]h-configure - configure subfunction attributes;}(hj! hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMVhj ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(h!deploy - deploy the subfunction; h]h)}(h deploy - deploy the subfunction;h]h deploy - deploy the subfunction;}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMWhj4 ubah}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]enumtypearabicprefixhsuffix)uh1j hj hhhhhMUubh)}(h{Subfunction management is done using devlink port user interface. User performs setup on the subfunction management device.h]h{Subfunction management is done using devlink port user interface. User performs setup on the subfunction management device.}(hjW hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMYhj hhubeh}(h] subfunctionah ]h"] subfunctionah$]h&]uh1hhjR hhhhhMLubeh}(h]maximum-io-events-queues-setupah ]h"]maximum io events queues setupah$]h&]uh1hhhhhhhhM.ubh)}(hhh](h)}(h (1) Createh]h (1) Create}(hjx hhhNhNubah}(h]h ]h"]h$]h&]uh1hhju hhhhhM]ubh)}(hXA subfunction is created using a devlink port interface. A user adds the subfunction by adding a devlink port of subfunction flavour. The devlink kernel code calls down to subfunction management driver (devlink ops) and asks it to create a subfunction devlink port. Driver then instantiates the subfunction port and any associated objects such as health reporters and representor netdevice.h]hXA subfunction is created using a devlink port interface. A user adds the subfunction by adding a devlink port of subfunction flavour. The devlink kernel code calls down to subfunction management driver (devlink ops) and asks it to create a subfunction devlink port. Driver then instantiates the subfunction port and any associated objects such as health reporters and representor netdevice.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhM^hju hhubeh}(h]createah ]h"] (1) createah$]h&]uh1hhhhhhhhM]ubh)}(hhh](h)}(h (2) Configureh]h (2) Configure}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMfubh)}(hXA subfunction devlink port is created but it is not active yet. That means the entities are created on devlink side, the e-switch port representor is created, but the subfunction device itself is not created. A user might use e-switch port representor to do settings, putting it into bridge, adding TC rules, etc. A user might as well configure the hardware address (such as MAC address) of the subfunction while subfunction is inactive.h]hXA subfunction devlink port is created but it is not active yet. That means the entities are created on devlink side, the e-switch port representor is created, but the subfunction device itself is not created. A user might use e-switch port representor to do settings, putting it into bridge, adding TC rules, etc. A user might as well configure the hardware address (such as MAC address) of the subfunction while subfunction is inactive.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMghj hhubeh}(h] configureah ]h"] (2) configureah$]h&]uh1hhhhhhhhMfubh)}(hhh](h)}(h (3) Deployh]h (3) Deploy}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMoubh)}(hXOnce a subfunction is configured, user must activate it to use it. Upon activation, subfunction management driver asks the subfunction management device to instantiate the subfunction device on particular PCI function. A subfunction device is created on the :ref:`Documentation/driver-api/auxiliary_bus.rst `. At this point a matching subfunction driver binds to the subfunction's auxiliary device.h](hXOnce a subfunction is configured, user must activate it to use it. Upon activation, subfunction management driver asks the subfunction management device to instantiate the subfunction device on particular PCI function. A subfunction device is created on the }(hj hhhNhNubh)}(hA:ref:`Documentation/driver-api/auxiliary_bus.rst `h]hinline)}(hj h]h*Documentation/driver-api/auxiliary_bus.rst}(hj hhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1j hj ubah}(h]h ]h"]h$]h&]refdocnetworking/devlink/devlink-port refdomainj reftyperef refexplicitrefwarn reftarget auxiliary_busuh1hhhhMphj ubh\. At this point a matching subfunction driver binds to the subfunction’s auxiliary device.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMphj hhubh)}(hhh](h)}(hRate object managementh]hRate object management}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj hhhhhMwubh)}(hDevlink provides API to manage tx rates of single devlink port or a group. This is done through rate objects, which can be one of the two types:h]hDevlink provides API to manage tx rates of single devlink port or a group. This is done through rate objects, which can be one of the two types:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMyhj hhubhdefinition_list)}(hhh](hdefinition_list_item)}(h``leaf`` Represents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as ``pci//``; h](hterm)}(h``leaf``h]h)}(hj9 h]hleaf}(hj; hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj7 ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj1 ubh definition)}(hhh]h)}(hRepresents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as ``pci//``;h](hRepresents a single devlink port; created/destroyed by the driver. Since leaf have 1to1 mapping to its devlink port, in user space it is referred as }(hjS hhhNhNubh)}(h``pci//``h]hpci//}(hj[ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjS ubh;}(hjS hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhM}hjP ubah}(h]h ]h"]h$]h&]uh1jN hj1 ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj, ubj0 )}(hX;``node`` Represents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as ``pci//``, where ``node_name`` can be any identifier, except decimal number, to avoid collisions with leafs. h](j6 )}(h``node``h]h)}(hj h]hnode}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj ubjO )}(hhh]h)}(hX1Represents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as ``pci//``, where ``node_name`` can be any identifier, except decimal number, to avoid collisions with leafs.h](hRepresents a group of rate objects (leafs and/or nodes); created/deleted by request from the userspace; initially empty (no rate objects added). In userspace it is referred as }(hj hhhNhNubh)}(h``pci//``h]hpci//}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh, where }(hj hhhNhNubh)}(h ``node_name``h]h node_name}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubhN can be any identifier, except decimal number, to avoid collisions with leafs.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jN hj ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj, hhubeh}(h]h ]h"]h$]h&]uh1j* hj hhhhhNubh)}(h;API allows to configure following rate object's parameters:h]h=API allows to configure following rate object’s parameters:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj+ )}(hhh](j0 )}(h``tx_share`` Minimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group. h](j6 )}(h ``tx_share``h]h)}(hj h]htx_share}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj ubjO )}(hhh]h)}(hMinimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group.h]hMinimum TX rate value shared among all other rate objects, or rate objects that parts of the parent group, if it is a part of the same group.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jN hj ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj ubj0 )}(h"``tx_max`` Maximum TX rate value. h](j6 )}(h ``tx_max``h]h)}(hj0 h]htx_max}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj. ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj* ubjO )}(hhh]h)}(hMaximum TX rate value.h]hMaximum TX rate value.}(hjH hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjE ubah}(h]h ]h"]h$]h&]uh1jN hj* ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj hhubj0 )}(hX4``tx_priority`` Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling. h](j6 )}(h``tx_priority``h]h)}(hjh h]h tx_priority}(hjj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjf ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhjb ubjO )}(hhh]h)}(hX#Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling.h]hX#Allows for usage of strict priority arbiter among siblings. This arbitration scheme attempts to schedule nodes based on their priority as long as the nodes remain within their bandwidth limit. The higher the priority the higher the probability that the node will get selected for scheduling.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj} ubah}(h]h ]h"]h$]h&]uh1jN hjb ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj hhubj0 )}(hXv``tx_weight`` Allows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings. h](j6 )}(h ``tx_weight``h]h)}(hj h]h tx_weight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj ubjO )}(hhh]h)}(hXgAllows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings.h]hXgAllows for usage of Weighted Fair Queuing arbitration scheme among siblings. This arbitration scheme can be used simultaneously with the strict priority. As a node is configured with a higher rate it gets more BW relative to its siblings. Values are relative like a percentage points, they basically tell how much BW should node take relative to its siblings.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jN hj ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj hhubj0 )}(h``parent`` Parent node name. Parent node rate limits are considered as additional limits to all node children limits. ``tx_max`` is an upper limit for children. ``tx_share`` is a total bandwidth distributed among children. h](j6 )}(h ``parent``h]h)}(hj h]hparent}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1j5 hhhMhj ubjO )}(hhh]h)}(hParent node name. Parent node rate limits are considered as additional limits to all node children limits. ``tx_max`` is an upper limit for children. ``tx_share`` is a total bandwidth distributed among children.h](hkParent node name. Parent node rate limits are considered as additional limits to all node children limits. }(hj hhhNhNubh)}(h ``tx_max``h]htx_max}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh! is an upper limit for children. }(hj hhhNhNubh)}(h ``tx_share``h]htx_share}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh1 is a total bandwidth distributed among children.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jN hj ubeh}(h]h ]h"]h$]h&]uh1j/ hhhMhj hhubeh}(h]h ]h"]h$]h&]uh1j* hj hhhhhNubh)}(h``tx_priority`` and ``tx_weight`` can be used simultaneously. In that case nodes with the same priority form a WFQ subgroup in the sibling group and arbitration among them is based on assigned weights.h](h)}(h``tx_priority``h]h tx_priority}(hj8 hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4 ubh and }(hj4 hhhNhNubh)}(h ``tx_weight``h]h tx_weight}(hjJ hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj4 ubh can be used simultaneously. In that case nodes with the same priority form a WFQ subgroup in the sibling group and arbitration among them is based on assigned weights.}(hj4 hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj hhubh)}(h%Arbitration flow from the high level:h]h%Arbitration flow from the high level:}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubj )}(hhh](j)}(hChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use ``tx_priority`` as a parameter for this arbitration. h]h)}(hChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use ``tx_priority`` as a parameter for this arbitration.h](hsChoose a node, or group of nodes with the highest priority that stays within the BW limit and are not blocked. Use }(hjw hhhNhNubh)}(h``tx_priority``h]h tx_priority}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhjw ubh% as a parameter for this arbitration.}(hjw hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhjs ubah}(h]h ]h"]h$]h&]uh1jhjp hhhhhNubj)}(hIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use ``tx_weight`` as a parameter for this arbitration. h]h)}(hIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use ``tx_weight`` as a parameter for this arbitration.h](hWIf group of nodes have the same priority perform WFQ arbitration on that subgroup. Use }(hj hhhNhNubh)}(h ``tx_weight``h]h tx_weight}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubh% as a parameter for this arbitration.}(hj hhhNhNubeh}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjp hhhhhNubj)}(hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established. -h]h)}(hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established.h]hSelect the winner node, and continue arbitration flow among its children, until leaf node is reached, and the winner is established.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjp hhhhhNubj)}(hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes. h]h)}(hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes.h]hIf all the nodes from the highest priority sub-group are satisfied, or overused their assigned BW, move to the lower priority nodes.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj ubah}(h]h ]h"]h$]h&]uh1jhjp hhhhhNubeh}(h]h ]h"]h$]h&]jR jS jT hjU .uh1j hj hhhhhMubh)}(hDriver implementations are allowed to support both or either rate object types and setting methods of their parameters. Additionally driver implementation may export nodes/leafs and their child-parent relationships.h]hDriver implementations are allowed to support both or either rate object types and setting methods of their parameters. Additionally driver implementation may export nodes/leafs and their child-parent relationships.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj hhubeh}(h]rate-object-managementah ]h"]rate object managementah$]h&]uh1hhj hhhhhMwubh)}(hhh](h)}(hTerms and Definitionsh]hTerms and Definitions}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjhhhhhMubj)}(hhh](h)}(hTerms and Definitionsh]hTerms and Definitions}(hj(hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj%ubj')}(hhh](j,)}(hhh]h}(h]h ]h"]h$]h&]j6Kuh1j+hj6ubj,)}(hhh]h}(h]h ]h"]h$]h&]j6KZuh1j+hj6ubjA)}(hhh](jF)}(hhh](jK)}(hhh]h)}(hTermh]hTerm}(hjThhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjQubah}(h]h ]h"]h$]h&]uh1jJhjNubjK)}(hhh]h)}(h Definitionsh]h Definitions}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhubah}(h]h ]h"]h$]h&]uh1jJhjNubeh}(h]h ]h"]h$]h&]uh1jEhjKubjF)}(hhh](jK)}(hhh]h)}(h``PCI device``h]h)}(hjh]h PCI device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h[A physical PCI device having one or more PCI buses consists of one or more PCI controllers.h]h[A physical PCI device having one or more PCI buses consists of one or more PCI controllers.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjKubjF)}(hhh](jK)}(hhh]h)}(h``PCI controller``h]h)}(hjh]hPCI controller}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(heA controller consists of potentially multiple physical functions, virtual functions and subfunctions.h]heA controller consists of potentially multiple physical functions, virtual functions and subfunctions.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjKubjF)}(hhh](jK)}(hhh]h)}(h``Port function``h]h)}(hj h]h Port function}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhj ubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(h+An object to manage the function of a port.h]h+An object to manage the function of a port.}(hj+hhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhj(ubah}(h]h ]h"]h$]h&]uh1jJhjubeh}(h]h ]h"]h$]h&]uh1jEhjKubjF)}(hhh](jK)}(hhh]h)}(h``Subfunction``h]h)}(hjMh]h Subfunction}(hjOhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjKubah}(h]h ]h"]h$]h&]uh1hhhhMhjHubah}(h]h ]h"]h$]h&]uh1jJhjEubjK)}(hhh]h)}(hLA lightweight function that has parent PCI function on which it is deployed.h]hLA lightweight function that has parent PCI function on which it is deployed.}(hjkhhhNhNubah}(h]h ]h"]h$]h&]uh1hhhhMhjhubah}(h]h ]h"]h$]h&]uh1jJhjEubeh}(h]h ]h"]h$]h&]uh1jEhjKubjF)}(hhh](jK)}(hhh]h)}(h``Subfunction device``h]h)}(hjh]hSubfunction device}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]uh1hhhhMhjubah}(h]h ]h"]h$]h&]uh1jJhjubjK)}(hhh]h)}(hjL jjo jR jg j j ju j j jj jj jjjOjjjcjj%u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}j&KsRparse_messages]transform_messages]hsystem_message)}(hhh]h)}(hhh]h2Hyperlink target "devlink-port" is not referenced.}hjsbah}(h]h ]h"]h$]h&]uh1hhjubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineKuh1j}uba transformerN include_log] decorationNhhub.