€•‡Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œtranslations”Œ LanguagesNode”“”)”}”(hhh]”(hŒpending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”ŒG/translations/zh_CN/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuŒtagname”hhhubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/zh_TW/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/it_IT/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/ja_JP/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/ko_KR/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuh1hhhubh)”}”(hhh]”hŒSpanish”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/sp_SP/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒrefexplicit”ˆuh1hhhubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh£sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1h¡hhhžhhŸŒa/var/lib/git/docbuild/linux/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst”h KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ/PPE Ethernet Driver for Qualcomm IPQ SoC Family”h]”hŒ/PPE Ethernet Driver for Qualcomm IPQ SoC Family”…””}”(hh»hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hh¶hžhhŸh³h KubhŒ paragraph”“”)”}”(hŒBCopyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.”h]”hŒBCopyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.”…””}”(hhËhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khh¶hžhubhÊ)”}”(hŒ)Author: Lei Wei ”h]”(hŒAuthor: Lei Wei <”…””}”(hhÙhžhhŸNh NubhŒ reference”“”)”}”(hŒquic_leiwei@quicinc.com”h]”hŒquic_leiwei@quicinc.com”…””}”(hhãhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:quic_leiwei@quicinc.com”uh1háhhÙubhŒ>”…””}”(hhÙhžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hh¶hžhubhµ)”}”(hhh]”(hº)”}”(hŒContents”h]”hŒContents”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hhýhžhhŸh³h K ubhŒbullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ`PPE Overview`_”h]”hÊ)”}”(hjh]”hâ)”}”(hjh]”hŒPPE Overview”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒPPE Overview”Œrefid”Œppe-overview”uh1háhjŒresolved”Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh³h Nubj)”}”(hŒ`PPE Driver Overview`_”h]”hÊ)”}”(hj<h]”hâ)”}”(hj<h]”hŒPPE Driver Overview”…””}”(hjAhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒPPE Driver Overview”j+Œppe-driver-overview”uh1háhj>j-Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj:ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh³h Nubj)”}”(hŒ`PPE Driver Supported SoCs`_”h]”hÊ)”}”(hj_h]”hâ)”}”(hj_h]”hŒPPE Driver Supported SoCs”…””}”(hjdhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒPPE Driver Supported SoCs”j+Œppe-driver-supported-socs”uh1háhjaj-Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj]ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh³h Nubj)”}”(hŒ`Enabling the Driver`_”h]”hÊ)”}”(hj‚h]”hâ)”}”(hj‚h]”hŒEnabling the Driver”…””}”(hj‡hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒEnabling the Driver”j+Œenabling-the-driver”uh1háhj„j-Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj€ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh³h Nubj)”}”(hŒ`Debugging`_ ”h]”hÊ)”}”(hŒ`Debugging`_”h]”hâ)”}”(hj©h]”hŒ Debugging”…””}”(hj«hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ Debugging”j+Œ debugging”uh1háhj§j-Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj£ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1jhŸh³h Khhýhžhubeh}”(h]”Œcontents”ah ]”h"]”Œcontents”ah$]”h&]”uh1h´hh¶hžhhŸh³h K ubhµ)”}”(hhh]”(hº)”}”(hŒPPE Overview”h]”hŒPPE Overview”…””}”(hjÚhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj×hžhhŸh³h KubhÊ)”}”(hŒÓIPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet packet process engine in the IPQ SoC.”h]”hŒÕIPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcommâ€™s series of networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet packet process engine in the IPQ SoC.”…””}”(hjèhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj×hžhubhÊ)”}”(hŒÙBelow is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and other blocks which are in the SoC but outside the PPE engine. These blocks work together to enable the Ethernet for the IPQ SoC::”h]”hŒØBelow is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and other blocks which are in the SoC but outside the PPE engine. These blocks work together to enable the Ethernet for the IPQ SoC:”…””}”(hjöhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Khj×hžhubhŒ literal_block”“”)”}”(hX/ +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ | | | ^ +-------+ +-------------------------+--------+----------------------+ | | | | GCC | | | EDMA | | | | | +---+---+ | PPE +---+----+ | | | | | clk | | | | | | +-------->| +-----------------------+------+-----+---------------+ | | | | | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | | | +---+--+ +------+--------+ | | | | | | | | | | | | | +-------+ | | +------+---------------+----+ | | | | | |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | | | | | +---+ +---+ +----+ | +--------+ | | | | | | | | | | +------+--------------------+ | | | | | | | | | | | | | | | | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | | | | +------>| +----|------|-------|-------|---------|--------|-----+ | | | | | | +---------------------------------------------------------+ | | | | | | | | | | | | | | | | MII clk | QSGMII USXGMII USXGMII | | | | +--------------->| | | | | | | | | | +-------------------------+ +---------+ +---------+ | | | |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | | +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | +----------------->| | | | | | | | 31.25MHz ref clk +-------------------------+ +---------+ +---------+ | | | | | | | | | | +-----------------------------------------------------+ | |25/50MHz ref clk| +-------------------------+ +------+ +------+ | link | +--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ | +-------------------------+ +------+ +------+ | change | | | MDIO bus | +-----------------------------------------------------+”h]”hX/ +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ | | | ^ +-------+ +-------------------------+--------+----------------------+ | | | | GCC | | | EDMA | | | | | +---+---+ | PPE +---+----+ | | | | | clk | | | | | | +-------->| +-----------------------+------+-----+---------------+ | | | | | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | | | +---+--+ +------+--------+ | | | | | | | | | | | | | +-------+ | | +------+---------------+----+ | | | | | |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | | | | | +---+ +---+ +----+ | +--------+ | | | | | | | | | | +------+--------------------+ | | | | | | | | | | | | | | | | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | | | | +------>| +----|------|-------|-------|---------|--------|-----+ | | | | | | +---------------------------------------------------------+ | | | | | | | | | | | | | | | | MII clk | QSGMII USXGMII USXGMII | | | | +--------------->| | | | | | | | | | +-------------------------+ +---------+ +---------+ | | | |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | | +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | +----------------->| | | | | | | | 31.25MHz ref clk +-------------------------+ +---------+ +---------+ | | | | | | | | | | +-----------------------------------------------------+ | |25/50MHz ref clk| +-------------------------+ +------+ +------+ | link | +--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ | +-------------------------+ +------+ +------+ | change | | | MDIO bus | +-----------------------------------------------------+”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jhŸh³h K!hj×hžhubhÊ)”}”(hŒ˜The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global Clock Controller) blocks are in the SoC and act as clock providers.”h]”hŒ˜The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global Clock Controller) blocks are in the SoC and act as clock providers.”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KKhj×hžhubhÊ)”}”(hŒÖThe UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface modes between the PPE MAC and the external PHY.”h]”hŒÖThe UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface modes between the PPE MAC and the external PHY.”…””}”(hj"hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KNhj×hžhubhÊ)”}”(hŒPThis documentation focuses on the descriptions of PPE engine and the PPE driver.”h]”hŒPThis documentation focuses on the descriptions of PPE engine and the PPE driver.”…””}”(hj0hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KRhj×hžhubhÊ)”}”(hŒThe Ethernet functionality in the PPE (Packet Process Engine) is comprised of three components: the switch core, port wrapper and Ethernet DMA.”h]”hŒThe Ethernet functionality in the PPE (Packet Process Engine) is comprised of three components: the switch core, port wrapper and Ethernet DMA.”…””}”(hj>hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KThj×hžhubhÊ)”}”(hXThe Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU communication using Ethernet DMA. The other one is used to communicate to the EIP engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the packet processing.”h]”hXThe Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU communication using Ethernet DMA. The other one is used to communicate to the EIP engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the packet processing.”…””}”(hjLhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KWhj×hžhubhÊ)”}”(hŒÑThe port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) instances supported on the IPQ9574.”h]”hŒÑThe port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) instances supported on the IPQ9574.”…””}”(hjZhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K_hj×hžhubhÊ)”}”(hŒeEthernet DMA is used to transmit and receive packets between the Ethernet subsystem and ARM host CPU.”h]”hŒeEthernet DMA is used to transmit and receive packets between the Ethernet subsystem and ARM host CPU.”…””}”(hjhhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kchj×hžhubhÊ)”}”(hŒ^The following lists the main blocks in the PPE engine which will be driven by this PPE driver:”h]”hŒ^The following lists the main blocks in the PPE engine which will be driven by this PPE driver:”…””}”(hjvhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kfhj×hžhubj)”}”(hhh]”(j)”}”(hŒ@BM BM is the hardware buffer manager for the PPE switch ports.”h]”hŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒ>BM BM is the hardware buffer manager for the PPE switch ports.”h]”(hŒterm”“”)”}”(hŒBM”h]”hŒBM”…””}”(hj˜hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h Kihj’ubhŒ definition”“”)”}”(hhh]”hÊ)”}”(hŒ;BM is the hardware buffer manager for the PPE switch ports.”h]”hŒ;BM is the hardware buffer manager for the PPE switch ports.”…””}”(hj«hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kjhj¨ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hj’ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h Kihjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hj‡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubj)”}”(hŒSQM Queue Manager for managing the egress hardware queues of the PPE switch ports.”h]”jŒ)”}”(hhh]”j‘)”}”(hŒQQM Queue Manager for managing the egress hardware queues of the PPE switch ports.”h]”(j—)”}”(hŒQM”h]”hŒQM”…””}”(hjÜhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h KkhjØubj§)”}”(hhh]”hÊ)”}”(hŒNQueue Manager for managing the egress hardware queues of the PPE switch ports.”h]”hŒNQueue Manager for managing the egress hardware queues of the PPE switch ports.”…””}”(hjíhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Klhjêubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hjØubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h KkhjÕubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hjÑubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubj)”}”(hŒ[SCH The scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”jŒ)”}”(hhh]”j‘)”}”(hŒYSCH The scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”(j—)”}”(hŒSCH”h]”hŒSCH”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h Kmhjubj§)”}”(hhh]”hÊ)”}”(hŒUThe scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”hŒUThe scheduler which manages the hardware traffic scheduling for the PPE switch ports.”…””}”(hj/hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Knhj,ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hjubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h Kmhjubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubj)”}”(hXL2 The L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”jŒ)”}”(hhh]”j‘)”}”(hŒýL2 The L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”(j—)”}”(hŒL2”h]”hŒL2”…””}”(hj`hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h Kqhj\ubj§)”}”(hhh]”hÊ)”}”(hŒúThe L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”hŒúThe L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”…””}”(hjqhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kphjnubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hj\ubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h KqhjYubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hjUubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubj)”}”(hX}MAC The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”jŒ)”}”(hhh]”j‘)”}”(hXsMAC The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”(j—)”}”(hŒMAC”h]”hŒMAC”…””}”(hj¢hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h Kwhjžubj§)”}”(hhh]”hÊ)”}”(hXoThe PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”hXqThe PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHYâ€™s capability.”…””}”(hj³hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kthj°ubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hjžubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h Kwhj›ubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hj—ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubj)”}”(hŒƒEDMA (Ethernet DMA) The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores. ”h]”jŒ)”}”(hhh]”j‘)”}”(hŒEDMA (Ethernet DMA) The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores. ”h]”(j—)”}”(hŒEDMA (Ethernet DMA)”h]”hŒEDMA (Ethernet DMA)”…””}”(hjähžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j–hŸh³h K{hjàubj§)”}”(hhh]”hÊ)”}”(hŒjThe Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores.”h]”hŒjThe Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores.”…””}”(hjõhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h Kzhjòubah}”(h]”h ]”h"]”h$]”h&]”uh1j¦hjàubeh}”(h]”h ]”h"]”h$]”h&]”uh1jhŸh³h K{hjÝubah}”(h]”h ]”h"]”h$]”h&]”uh1j‹hjÙubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”jÍjÎuh1jhŸh³h Kihj×hžhubhÊ)”}”(hX8The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can be also forwarded to internal switch port0 so that the packet can be delivered to the ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the packet to the corresponding 'netdevice' interface.”h]”hX<The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can be also forwarded to internal switch port0 so that the packet can be delivered to the ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the packet to the corresponding â€˜netdeviceâ€™ interface.”…””}”(hj!hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K}hj×hžhubhÊ)”}”(hXThe software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact with the Linux PHYLINK framework to manage the connectivity between the PPE ports and the connected PHYs, and the port link states. This is also illustrated in above diagram.”h]”hXThe software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact with the Linux PHYLINK framework to manage the connectivity between the PPE ports and the connected PHYs, and the port link states. This is also illustrated in above diagram.”…””}”(hj/hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‚hj×hžhubeh}”(h]”j,ah ]”h"]”Œppe overview”ah$]”h&]”uh1h´hh¶hžhhŸh³h KŒ referenced”Kubhµ)”}”(hhh]”(hº)”}”(hŒPPE Driver Overview”h]”hŒPPE Driver Overview”…””}”(hjHhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjEhžhhŸh³h KˆubhÊ)”}”(hXŒPPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables the netdevice driver for the PPE ports.”h]”hXŒPPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables the netdevice driver for the PPE ports.”…””}”(hjVhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‰hjEhžhubhÊ)”}”(hŒOThe PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:”h]”hŒOThe PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:”…””}”(hjdhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KhjEhžhubj)”}”(hhh]”(j)”}”(hŒMakefile”h]”hÊ)”}”(hjwh]”hŒMakefile”…””}”(hjyhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K‘hjuubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒppe.c”h]”hÊ)”}”(hjŽh]”hŒppe.c”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K’hjŒubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒppe.h”h]”hÊ)”}”(hj¥h]”hŒppe.h”…””}”(hj§hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K“hj£ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒppe_config.c”h]”hÊ)”}”(hj¼h]”hŒppe_config.c”…””}”(hj¾hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K”hjºubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒppe_config.h”h]”hÊ)”}”(hjÓh]”hŒppe_config.h”…””}”(hjÕhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K•hjÑubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒ ppe_debugfs.c”h]”hÊ)”}”(hjêh]”hŒ ppe_debugfs.c”…””}”(hjìhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K–hjèubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒ ppe_debugfs.h”h]”hÊ)”}”(hjh]”hŒ ppe_debugfs.h”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K—hjÿubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubj)”}”(hŒppe_regs.h ”h]”hÊ)”}”(hŒ ppe_regs.h”h]”hŒ ppe_regs.h”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K˜hjubah}”(h]”h ]”h"]”h$]”h&]”uh1jhjrhžhhŸh³h Nubeh}”(h]”h ]”h"]”h$]”h&]”jÍjÎuh1jhŸh³h K‘hjEhžhubhÊ)”}”(hŒßThe ppe.c file contains the main PPE platform driver and undertakes the initialization of PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware blocks are provided in the ppe_config.c file.”h]”hŒßThe ppe.c file contains the main PPE platform driver and undertakes the initialization of PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware blocks are provided in the ppe_config.c file.”…””}”(hj4hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KšhjEhžhubhÊ)”}”(hŒ[The ppe.h defines the PPE device data structure which will be used by PPE driver functions.”h]”hŒ[The ppe.h defines the PPE device data structure which will be used by PPE driver functions.”…””}”(hjBhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KžhjEhžhubhÊ)”}”(hŒ€The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, CPU code counters and queue counters.”h]”hŒ€The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, CPU code counters and queue counters.”…””}”(hjPhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K hjEhžhubeh}”(h]”jPah ]”h"]”Œppe driver overview”ah$]”h&]”uh1h´hh¶hžhhŸh³h KˆjDKubhµ)”}”(hhh]”(hº)”}”(hŒPPE Driver Supported SoCs”h]”hŒPPE Driver Supported SoCs”…””}”(hjhhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjehžhhŸh³h K¥ubhÊ)”}”(hŒ.The PPE driver supports the following IPQ SoC:”h]”hŒ.The PPE driver supports the following IPQ SoC:”…””}”(hjvhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K§hjehžhubj)”}”(hhh]”j)”}”(hŒ IPQ9574 ”h]”hÊ)”}”(hŒIPQ9574”h]”hŒIPQ9574”…””}”(hj‹hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K©hj‡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj„hžhhŸh³h Nubah}”(h]”h ]”h"]”h$]”h&]”jÍjÎuh1jhŸh³h K©hjehžhubeh}”(h]”jsah ]”h"]”Œppe driver supported socs”ah$]”h&]”uh1h´hh¶hžhhŸh³h K¥jDKubhµ)”}”(hhh]”(hº)”}”(hŒEnabling the Driver”h]”hŒEnabling the Driver”…””}”(hj¯hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hj¬hžhhŸh³h KubhÊ)”}”(hŒ0The driver is located in the menu structure at::”h]”hŒ/The driver is located in the menu structure at:”…””}”(hj½hžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K¯hj¬hžhubj)”}”(hŒ´-> Device Drivers -> Network device support (NETDEVICES [=y]) -> Ethernet driver support -> Qualcomm devices -> Qualcomm Technologies, Inc. PPE Ethernet support”h]”hŒ´-> Device Drivers -> Network device support (NETDEVICES [=y]) -> Ethernet driver support -> Qualcomm devices -> Qualcomm Technologies, Inc. PPE Ethernet support”…””}”hjËsbah}”(h]”h ]”h"]”h$]”h&]”h±h²uh1jhŸh³h K±hj¬hžhubhÊ)”}”(hŒGIf the driver is built as a module, the module will be called qcom-ppe.”h]”hŒGIf the driver is built as a module, the module will be called qcom-ppe.”…””}”(hjÙhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K·hj¬hžhubhÊ)”}”(hŒ´The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. Please make sure the dependent modules are installed before installing the PPE driver module.”h]”hŒ´The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. Please make sure the dependent modules are installed before installing the PPE driver module.”…””}”(hjçhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h K¹hj¬hžhubeh}”(h]”j–ah ]”h"]”Œenabling the driver”ah$]”h&]”uh1h´hh¶hžhhŸh³h KjDKubhµ)”}”(hhh]”(hº)”}”(hŒ Debugging”h]”hŒ Debugging”…””}”(hjÿhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1h¹hjühžhhŸh³h K¿ubhÊ)”}”(hŒpThe PPE hardware counters can be accessed using debugfs interface from the ``/sys/kernel/debug/ppe/`` directory.”h]”(hŒKThe PPE hardware counters can be accessed using debugfs interface from the ”…””}”(hj hžhhŸNh NubhŒliteral”“”)”}”(hŒ``/sys/kernel/debug/ppe/``”h]”hŒ/sys/kernel/debug/ppe/”…””}”(hjhžhhŸNh Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jhj ubhŒ directory.”…””}”(hj hžhhŸNh Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÉhŸh³h KÁhjühžhubeh}”(h]”jºah ]”h"]”Œ debugging”ah$]”h&]”uh1h´hh¶hžhhŸh³h K¿jDKubeh}”(h]”Œ/ppe-ethernet-driver-for-qualcomm-ipq-soc-family”ah ]”h"]”Œ/ppe ethernet driver for qualcomm ipq soc family”ah$]”h&]”uh1h´hhhžhhŸh³h Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”h³uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(h¹NŒ generator”NŒ datestamp”NŒsource_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒreport_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jaŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”h³Œ_destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒraw_enabled”KŒline_length_limit”M'Œpep_references”NŒpep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”(Œppe overview”]”jaŒppe driver overview”]”jAaŒppe driver supported socs”]”jdaŒenabling the driver”]”j‡aŒ debugging”]”j«auŒrefids”}”Œnameids”}”(j;j8jÔjÑjAj,jbjPj©jsjùj–j3jºuŒ nametypes”}”(j;‰jÔ‰jA‰jb‰j©‰jù‰j3‰uh}”(j8h¶jÑhýj,j×jPjEjsjej–j¬jºjüuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œtransformer”NŒinclude_log”]”Œ decoration”Nhžhub.