€•{ˆŒsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œ translations”Œ LanguagesNode”“”)”}”(hhh]”(hŒ pending_xref”“”)”}”(hhh]”Œdocutils.nodes”ŒText”“”ŒChinese (Simplified)”…””}”Œparent”hsbaŒ attributes”}”(Œids”]”Œclasses”]”Œnames”]”Œdupnames”]”Œbackrefs”]”Œ refdomain”Œstd”Œreftype”Œdoc”Œ reftarget”ŒG/translations/zh_CN/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuŒtagname”hhh ubh)”}”(hhh]”hŒChinese (Traditional)”…””}”hh2sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/zh_TW/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒItalian”…””}”hhFsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/it_IT/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒJapanese”…””}”hhZsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/ja_JP/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒKorean”…””}”hhnsbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/ko_KR/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒPortuguese (Brazilian)”…””}”hh‚sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/pt_BR/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubh)”}”(hhh]”hŒSpanish”…””}”hh–sbah}”(h]”h ]”h"]”h$]”h&]”Œ refdomain”h)Œreftype”h+Œ reftarget”ŒG/translations/sp_SP/networking/device_drivers/ethernet/qualcomm/ppe/ppe”Œmodname”NŒ classname”NŒ refexplicit”ˆuh1hhh ubeh}”(h]”h ]”h"]”h$]”h&]”Œcurrent_language”ŒEnglish”uh1h hhŒ _document”hŒsource”NŒline”NubhŒcomment”“”)”}”(hŒ SPDX-License-Identifier: GPL-2.0”h]”hŒ SPDX-License-Identifier: GPL-2.0”…””}”hh·sbah}”(h]”h ]”h"]”h$]”h&]”Œ xml:space”Œpreserve”uh1hµhhh²hh³Œa/var/lib/git/docbuild/linux/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst”h´KubhŒsection”“”)”}”(hhh]”(hŒtitle”“”)”}”(hŒ/PPE Ethernet Driver for Qualcomm IPQ SoC Family”h]”hŒ/PPE Ethernet Driver for Qualcomm IPQ SoC Family”…””}”(hhÏh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhhÊh²hh³hÇh´KubhŒ paragraph”“”)”}”(hŒBCopyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.”h]”hŒBCopyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.”…””}”(hhßh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhhÊh²hubhÞ)”}”(hŒ)Author: Lei Wei ”h]”(hŒAuthor: Lei Wei <”…””}”(hhíh²hh³Nh´NubhŒ reference”“”)”}”(hŒquic_leiwei@quicinc.com”h]”hŒquic_leiwei@quicinc.com”…””}”(hh÷h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œrefuri”Œmailto:quic_leiwei@quicinc.com”uh1hõhhíubhŒ>”…””}”(hhíh²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hhÊh²hubhÉ)”}”(hhh]”(hÎ)”}”(hŒContents”h]”hŒContents”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K ubhŒ bullet_list”“”)”}”(hhh]”(hŒ list_item”“”)”}”(hŒ`PPE Overview`_”h]”hÞ)”}”(hj+h]”hö)”}”(hj+h]”hŒ PPE Overview”…””}”(hj0h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ PPE Overview”Œrefid”Œ ppe-overview”uh1hõhj-Œresolved”Kubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj)ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$h²hh³hÇh´Nubj()”}”(hŒ`PPE Driver Overview`_”h]”hÞ)”}”(hjPh]”hö)”}”(hjPh]”hŒPPE Driver Overview”…””}”(hjUh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒPPE Driver Overview”j?Œppe-driver-overview”uh1hõhjRjAKubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhjNubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$h²hh³hÇh´Nubj()”}”(hŒ`PPE Driver Supported SoCs`_”h]”hÞ)”}”(hjsh]”hö)”}”(hjsh]”hŒPPE Driver Supported SoCs”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒPPE Driver Supported SoCs”j?Œppe-driver-supported-socs”uh1hõhjujAKubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjqubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$h²hh³hÇh´Nubj()”}”(hŒ`Enabling the Driver`_”h]”hÞ)”}”(hj–h]”hö)”}”(hj–h]”hŒEnabling the Driver”…””}”(hj›h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”ŒEnabling the Driver”j?Œenabling-the-driver”uh1hõhj˜jAKubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj”ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$h²hh³hÇh´Nubj()”}”(hŒ`Debugging`_ ”h]”hÞ)”}”(hŒ `Debugging`_”h]”hö)”}”(hj½h]”hŒ Debugging”…””}”(hj¿h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”Œname”Œ Debugging”j?Œ debugging”uh1hõhj»jAKubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khj·ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj$h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”Œbullet”Œ-”uh1j"h³hÇh´Khjh²hubeh}”(h]”Œcontents”ah ]”h"]”Œcontents”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K ubhÉ)”}”(hhh]”(hÎ)”}”(hŒ PPE Overview”h]”hŒ PPE Overview”…””}”(hjîh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjëh²hh³hÇh´KubhÞ)”}”(hŒÓIPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet packet process engine in the IPQ SoC.”h]”hŒÕIPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm’s series of networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet packet process engine in the IPQ SoC.”…””}”(hjüh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjëh²hubhÞ)”}”(hŒÙBelow is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and other blocks which are in the SoC but outside the PPE engine. These blocks work together to enable the Ethernet for the IPQ SoC::”h]”hŒØBelow is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and other blocks which are in the SoC but outside the PPE engine. These blocks work together to enable the Ethernet for the IPQ SoC:”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Khjëh²hubhŒ literal_block”“”)”}”(hX/ +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ | | | ^ +-------+ +-------------------------+--------+----------------------+ | | | | GCC | | | EDMA | | | | | +---+---+ | PPE +---+----+ | | | | | clk | | | | | | +-------->| +-----------------------+------+-----+---------------+ | | | | | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | | | +---+--+ +------+--------+ | | | | | | | | | | | | | +-------+ | | +------+---------------+----+ | | | | | |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | | | | | +---+ +---+ +----+ | +--------+ | | | | | | | | | | +------+--------------------+ | | | | | | | | | | | | | | | | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | | | | +------>| +----|------|-------|-------|---------|--------|-----+ | | | | | | +---------------------------------------------------------+ | | | | | | | | | | | | | | | | MII clk | QSGMII USXGMII USXGMII | | | | +--------------->| | | | | | | | | | +-------------------------+ +---------+ +---------+ | | | |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | | +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | +----------------->| | | | | | | | 31.25MHz ref clk +-------------------------+ +---------+ +---------+ | | | | | | | | | | +-----------------------------------------------------+ | |25/50MHz ref clk| +-------------------------+ +------+ +------+ | link | +--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ | +-------------------------+ +------+ +------+ | change | | | MDIO bus | +-----------------------------------------------------+”h]”hX/ +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ | | | ^ +-------+ +-------------------------+--------+----------------------+ | | | | GCC | | | EDMA | | | | | +---+---+ | PPE +---+----+ | | | | | clk | | | | | | +-------->| +-----------------------+------+-----+---------------+ | | | | | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | | | +---+--+ +------+--------+ | | | | | | | | | | | | | +-------+ | | +------+---------------+----+ | | | | | |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | | | | | +---+ +---+ +----+ | +--------+ | | | | | | | | | | +------+--------------------+ | | | | | | | | | | | | | | | | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | | | | +------>| +----|------|-------|-------|---------|--------|-----+ | | | | | | +---------------------------------------------------------+ | | | | | | | | | | | | | | | | MII clk | QSGMII USXGMII USXGMII | | | | +--------------->| | | | | | | | | | +-------------------------+ +---------+ +---------+ | | | |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | | +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | +----------------->| | | | | | | | 31.25MHz ref clk +-------------------------+ +---------+ +---------+ | | | | | | | | | | +-----------------------------------------------------+ | |25/50MHz ref clk| +-------------------------+ +------+ +------+ | link | +--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ | +-------------------------+ +------+ +------+ | change | | | MDIO bus | +-----------------------------------------------------+”…””}”hjsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K!hjëh²hubhÞ)”}”(hŒ˜The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global Clock Controller) blocks are in the SoC and act as clock providers.”h]”hŒ˜The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global Clock Controller) blocks are in the SoC and act as clock providers.”…””}”(hj(h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KKhjëh²hubhÞ)”}”(hŒÖThe UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface modes between the PPE MAC and the external PHY.”h]”hŒÖThe UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface modes between the PPE MAC and the external PHY.”…””}”(hj6h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KNhjëh²hubhÞ)”}”(hŒPThis documentation focuses on the descriptions of PPE engine and the PPE driver.”h]”hŒPThis documentation focuses on the descriptions of PPE engine and the PPE driver.”…””}”(hjDh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KRhjëh²hubhÞ)”}”(hŒThe Ethernet functionality in the PPE (Packet Process Engine) is comprised of three components: the switch core, port wrapper and Ethernet DMA.”h]”hŒThe Ethernet functionality in the PPE (Packet Process Engine) is comprised of three components: the switch core, port wrapper and Ethernet DMA.”…””}”(hjRh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KThjëh²hubhÞ)”}”(hXThe Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU communication using Ethernet DMA. The other one is used to communicate to the EIP engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the packet processing.”h]”hXThe Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU communication using Ethernet DMA. The other one is used to communicate to the EIP engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the packet processing.”…””}”(hj`h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KWhjëh²hubhÞ)”}”(hŒÑThe port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) instances supported on the IPQ9574.”h]”hŒÑThe port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) instances supported on the IPQ9574.”…””}”(hjnh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K_hjëh²hubhÞ)”}”(hŒeEthernet DMA is used to transmit and receive packets between the Ethernet subsystem and ARM host CPU.”h]”hŒeEthernet DMA is used to transmit and receive packets between the Ethernet subsystem and ARM host CPU.”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kchjëh²hubhÞ)”}”(hŒ^The following lists the main blocks in the PPE engine which will be driven by this PPE driver:”h]”hŒ^The following lists the main blocks in the PPE engine which will be driven by this PPE driver:”…””}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kfhjëh²hubj#)”}”(hhh]”(j()”}”(hŒ@BM BM is the hardware buffer manager for the PPE switch ports.”h]”hŒdefinition_list”“”)”}”(hhh]”hŒdefinition_list_item”“”)”}”(hŒ>BM BM is the hardware buffer manager for the PPE switch ports.”h]”(hŒterm”“”)”}”(hŒBM”h]”hŒBM”…””}”(hj¬h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´Kihj¦ubhŒ definition”“”)”}”(hhh]”hÞ)”}”(hŒ;BM is the hardware buffer manager for the PPE switch ports.”h]”hŒ;BM is the hardware buffer manager for the PPE switch ports.”…””}”(hj¿h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kjhj¼ubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhj¦ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´Kihj¡ubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhj›ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubj()”}”(hŒSQM Queue Manager for managing the egress hardware queues of the PPE switch ports.”h]”j )”}”(hhh]”j¥)”}”(hŒQQM Queue Manager for managing the egress hardware queues of the PPE switch ports.”h]”(j«)”}”(hŒQM”h]”hŒQM”…””}”(hjðh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´Kkhjìubj»)”}”(hhh]”hÞ)”}”(hŒNQueue Manager for managing the egress hardware queues of the PPE switch ports.”h]”hŒNQueue Manager for managing the egress hardware queues of the PPE switch ports.”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Klhjþubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhjìubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´Kkhjéubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjåubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubj()”}”(hŒ[SCH The scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”j )”}”(hhh]”j¥)”}”(hŒYSCH The scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”(j«)”}”(hŒSCH”h]”hŒSCH”…””}”(hj2h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´Kmhj.ubj»)”}”(hhh]”hÞ)”}”(hŒUThe scheduler which manages the hardware traffic scheduling for the PPE switch ports.”h]”hŒUThe scheduler which manages the hardware traffic scheduling for the PPE switch ports.”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Knhj@ubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhj.ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´Kmhj+ubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhj'ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubj()”}”(hXL2 The L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”j )”}”(hhh]”j¥)”}”(hŒýL2 The L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”(j«)”}”(hŒL2”h]”hŒL2”…””}”(hjth²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´Kqhjpubj»)”}”(hhh]”hÞ)”}”(hŒúThe L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”h]”hŒúThe L2 block performs the packet bridging in the switch core. The bridge domain is represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.”…””}”(hj…h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kphj‚ubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhjpubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´Kqhjmubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjiubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubj()”}”(hX}MAC The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”j )”}”(hhh]”j¥)”}”(hXsMAC The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”(j«)”}”(hŒMAC”h]”hŒMAC”…””}”(hj¶h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´Kwhj²ubj»)”}”(hhh]”hÞ)”}”(hXoThe PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY's capability.”h]”hXqThe PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding to six switch ports (port1 to port6). The MAC block is connected with external PHY through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and the switch port can select to use GMAC or XMAC through a MUX selection according to the external PHY’s capability.”…””}”(hjÇh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KthjÄubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhj²ubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´Kwhj¯ubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhj«ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubj()”}”(hŒƒEDMA (Ethernet DMA) The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores. ”h]”j )”}”(hhh]”j¥)”}”(hŒEDMA (Ethernet DMA) The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores. ”h]”(j«)”}”(hŒEDMA (Ethernet DMA)”h]”hŒEDMA (Ethernet DMA)”…””}”(hjøh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1jªh³hÇh´K{hjôubj»)”}”(hhh]”hÞ)”}”(hŒjThe Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores.”h]”hŒjThe Ethernet DMA is used to transmit and receive Ethernet packets between the PPE ports and the ARM cores.”…””}”(hj h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´Kzhjubah}”(h]”h ]”h"]”h$]”h&]”uh1jºhjôubeh}”(h]”h ]”h"]”h$]”h&]”uh1j¤h³hÇh´K{hjñubah}”(h]”h ]”h"]”h$]”h&]”uh1jŸhjíubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jájâuh1j"h³hÇh´Kihjëh²hubhÞ)”}”(hX8The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can be also forwarded to internal switch port0 so that the packet can be delivered to the ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the packet to the corresponding 'netdevice' interface.”h]”hX<The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can be also forwarded to internal switch port0 so that the packet can be delivered to the ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the packet to the corresponding ‘netdevice’ interface.”…””}”(hj5h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K}hjëh²hubhÞ)”}”(hXThe software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact with the Linux PHYLINK framework to manage the connectivity between the PPE ports and the connected PHYs, and the port link states. This is also illustrated in above diagram.”h]”hXThe software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact with the Linux PHYLINK framework to manage the connectivity between the PPE ports and the connected PHYs, and the port link states. This is also illustrated in above diagram.”…””}”(hjCh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‚hjëh²hubeh}”(h]”j@ah ]”h"]”Œ ppe overview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KŒ referenced”KubhÉ)”}”(hhh]”(hÎ)”}”(hŒPPE Driver Overview”h]”hŒPPE Driver Overview”…””}”(hj\h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjYh²hh³hÇh´KˆubhÞ)”}”(hXŒPPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables the netdevice driver for the PPE ports.”h]”hXŒPPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables the netdevice driver for the PPE ports.”…””}”(hjjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‰hjYh²hubhÞ)”}”(hŒOThe PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:”h]”hŒOThe PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:”…””}”(hjxh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KhjYh²hubj#)”}”(hhh]”(j()”}”(hŒMakefile”h]”hÞ)”}”(hj‹h]”hŒMakefile”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K‘hj‰ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒppe.c”h]”hÞ)”}”(hj¢h]”hŒppe.c”…””}”(hj¤h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K’hj ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒppe.h”h]”hÞ)”}”(hj¹h]”hŒppe.h”…””}”(hj»h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K“hj·ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒ ppe_config.c”h]”hÞ)”}”(hjÐh]”hŒ ppe_config.c”…””}”(hjÒh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K”hjÎubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒ ppe_config.h”h]”hÞ)”}”(hjçh]”hŒ ppe_config.h”…””}”(hjéh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K•hjåubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒ ppe_debugfs.c”h]”hÞ)”}”(hjþh]”hŒ ppe_debugfs.c”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K–hjüubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒ ppe_debugfs.h”h]”hÞ)”}”(hjh]”hŒ ppe_debugfs.h”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K—hjubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubj()”}”(hŒ ppe_regs.h ”h]”hÞ)”}”(hŒ ppe_regs.h”h]”hŒ ppe_regs.h”…””}”(hj.h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K˜hj*ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj†h²hh³hÇh´Nubeh}”(h]”h ]”h"]”h$]”h&]”jájâuh1j"h³hÇh´K‘hjYh²hubhÞ)”}”(hŒßThe ppe.c file contains the main PPE platform driver and undertakes the initialization of PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware blocks are provided in the ppe_config.c file.”h]”hŒßThe ppe.c file contains the main PPE platform driver and undertakes the initialization of PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware blocks are provided in the ppe_config.c file.”…””}”(hjHh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KšhjYh²hubhÞ)”}”(hŒ[The ppe.h defines the PPE device data structure which will be used by PPE driver functions.”h]”hŒ[The ppe.h defines the PPE device data structure which will be used by PPE driver functions.”…””}”(hjVh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KžhjYh²hubhÞ)”}”(hŒ€The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, CPU code counters and queue counters.”h]”hŒ€The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, CPU code counters and queue counters.”…””}”(hjdh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K hjYh²hubeh}”(h]”jdah ]”h"]”Œppe driver overview”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´KˆjXKubhÉ)”}”(hhh]”(hÎ)”}”(hŒPPE Driver Supported SoCs”h]”hŒPPE Driver Supported SoCs”…””}”(hj|h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjyh²hh³hÇh´K¥ubhÞ)”}”(hŒ.The PPE driver supports the following IPQ SoC:”h]”hŒ.The PPE driver supports the following IPQ SoC:”…””}”(hjŠh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K§hjyh²hubj#)”}”(hhh]”j()”}”(hŒ IPQ9574 ”h]”hÞ)”}”(hŒIPQ9574”h]”hŒIPQ9574”…””}”(hjŸh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K©hj›ubah}”(h]”h ]”h"]”h$]”h&]”uh1j'hj˜h²hh³hÇh´Nubah}”(h]”h ]”h"]”h$]”h&]”jájâuh1j"h³hÇh´K©hjyh²hubeh}”(h]”j‡ah ]”h"]”Œppe driver supported socs”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K¥jXKubhÉ)”}”(hhh]”(hÎ)”}”(hŒEnabling the Driver”h]”hŒEnabling the Driver”…””}”(hjÃh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjÀh²hh³hÇh´K­ubhÞ)”}”(hŒ0The driver is located in the menu structure at::”h]”hŒ/The driver is located in the menu structure at:”…””}”(hjÑh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K¯hjÀh²hubj)”}”(hŒ´-> Device Drivers -> Network device support (NETDEVICES [=y]) -> Ethernet driver support -> Qualcomm devices -> Qualcomm Technologies, Inc. PPE Ethernet support”h]”hŒ´-> Device Drivers -> Network device support (NETDEVICES [=y]) -> Ethernet driver support -> Qualcomm devices -> Qualcomm Technologies, Inc. PPE Ethernet support”…””}”hjßsbah}”(h]”h ]”h"]”h$]”h&]”hÅhÆuh1jh³hÇh´K±hjÀh²hubhÞ)”}”(hŒGIf the driver is built as a module, the module will be called qcom-ppe.”h]”hŒGIf the driver is built as a module, the module will be called qcom-ppe.”…””}”(hjíh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K·hjÀh²hubhÞ)”}”(hŒ´The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. Please make sure the dependent modules are installed before installing the PPE driver module.”h]”hŒ´The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. Please make sure the dependent modules are installed before installing the PPE driver module.”…””}”(hjûh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´K¹hjÀh²hubeh}”(h]”jªah ]”h"]”Œenabling the driver”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K­jXKubhÉ)”}”(hhh]”(hÎ)”}”(hŒ Debugging”h]”hŒ Debugging”…””}”(hjh²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1hÍhjh²hh³hÇh´K¿ubhÞ)”}”(hŒpThe PPE hardware counters can be accessed using debugfs interface from the ``/sys/kernel/debug/ppe/`` directory.”h]”(hŒKThe PPE hardware counters can be accessed using debugfs interface from the ”…””}”(hj!h²hh³Nh´NubhŒliteral”“”)”}”(hŒ``/sys/kernel/debug/ppe/``”h]”hŒ/sys/kernel/debug/ppe/”…””}”(hj+h²hh³Nh´Nubah}”(h]”h ]”h"]”h$]”h&]”uh1j)hj!ubhŒ directory.”…””}”(hj!h²hh³Nh´Nubeh}”(h]”h ]”h"]”h$]”h&]”uh1hÝh³hÇh´KÁhjh²hubeh}”(h]”jÎah ]”h"]”Œ debugging”ah$]”h&]”uh1hÈhhÊh²hh³hÇh´K¿jXKubeh}”(h]”Œ/ppe-ethernet-driver-for-qualcomm-ipq-soc-family”ah ]”h"]”Œ/ppe ethernet driver for qualcomm ipq soc family”ah$]”h&]”uh1hÈhhh²hh³hÇh´Kubeh}”(h]”h ]”h"]”h$]”h&]”Œsource”hÇuh1hŒcurrent_source”NŒ current_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(hÍNŒ generator”NŒ datestamp”NŒ source_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒ report_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”juŒerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”hÇŒ _destination”NŒ _config_files”]”Œ7/var/lib/git/docbuild/linux/Documentation/docutils.conf”aŒfile_insertion_enabled”ˆŒ raw_enabled”KŒline_length_limit”M'Œpep_references”NŒ pep_base_url”Œhttps://peps.python.org/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒ rfc_base_url”Œ&https://datatracker.ietf.org/doc/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œsyntax_highlight”Œlong”Œ smart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œ image_loading”Œlink”Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒsection_self_link”‰Œenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”Œsubstitution_names”}”Œrefnames”}”(Œ ppe overview”]”j0aŒppe driver overview”]”jUaŒppe driver supported socs”]”jxaŒenabling the driver”]”j›aŒ debugging”]”j¿auŒrefids”}”Œnameids”}”(jOjLjèjåjUj@jvjdj½j‡j jªjGjÎuŒ nametypes”}”(jO‰jè‰jU‰jv‰j½‰j ‰jG‰uh}”(jLhÊjåjj@jëjdjYj‡jyjªjÀjÎjuŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œ collections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”Œ transformer”NŒ include_log”]”Œ decoration”Nh²hub.