sphinx.addnodesdocument)}( rawsourcechildren]( translations LanguagesNode)}(hhh](h pending_xref)}(hhh]docutils.nodesTextChinese (Simplified)}parenthsba attributes}(ids]classes]names]dupnames]backrefs] refdomainstdreftypedoc reftargetN/translations/zh_CN/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicitutagnamehhh ubh)}(hhh]hChinese (Traditional)}hh2sbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetN/translations/zh_TW/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hItalian}hhFsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetN/translations/it_IT/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hJapanese}hhZsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetN/translations/ja_JP/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hKorean}hhnsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetN/translations/ko_KR/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicituh1hhh ubh)}(hhh]hSpanish}hhsbah}(h]h ]h"]h$]h&] refdomainh)reftypeh+ reftargetN/translations/sp_SP/networking/device_drivers/ethernet/mellanox/mlx5/switchdevmodnameN classnameN refexplicituh1hhh ubeh}(h]h ]h"]h$]h&]current_languageEnglishuh1h hh _documenthsourceNlineNubhcomment)}(h0SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIBh]h0SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB}hhsbah}(h]h ]h"]h$]h&] xml:spacepreserveuh1hhhhhhh/var/lib/git/docbuild/linux/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/switchdev.rsthKubh)}(h4This data file has been placed in the public domain.h]h4This data file has been placed in the public domain.}hhsbah}(h]h ]h"]h$]h&]hhuh1hhhhhho/srv/docbuild/lib/venvs/build-kernel-docs/lib64/python3.9/site-packages/docutils/parsers/rst/include/isonum.txthKubh)}(hDerived from the Unicode character mappings available from . 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YEN SIGN h]h¥}hj8sbah}(h]h ]h"]yenah$]h&]uh1hhhhKRhhhhubhsection)}(hhh](htitle)}(h Switchdevh]h Switchdev}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjIhhhhhKubh field_list)}(hhh]hfield)}(hhh](h field_name)}(h Copyrighth]h Copyright}(hjhhhhNhNubah}(h]h ]h"]h$]h&]uh1jfhjchhhKubh field_body)}(hC|copy| 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. h]h paragraph)}(hB|copy| 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.h](h©}(hj~hhhNhNubh< 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.}(hj~hhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhKhjxubah}(h]h ]h"]h$]h&]uh1jvhjcubeh}(h]h ]h"]h$]h&]uh1jahhhKhj^hhubah}(h]h ]h"]h$]h&]uh1j\hjIhhhhhKubhtarget)}(h.. _mlx5_bridge_offload:h]h}(h]h ]h"]h$]h&]refidmlx5-bridge-offloaduh1jhK`hjIhhhhubjH)}(hhh](jM)}(hBridge offloadh]hBridge offload}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhK ubj})}(hThe mlx5 driver implements support for offloading bridge rules when in switchdev mode. Linux bridge FDBs are automatically offloaded when mlx5 switchdev representor is attached to bridge.h]hThe mlx5 driver implements support for offloading bridge rules when in switchdev mode. Linux bridge FDBs are automatically offloaded when mlx5 switchdev representor is attached to bridge.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubh bullet_list)}(hhh](h list_item)}(h_Change device to switchdev mode:: $ devlink dev eswitch set pci/0000:06:00.0 mode switchdev h](j})}(h!Change device to switchdev mode::h]h Change device to switchdev mode:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubh literal_block)}(h9$ devlink dev eswitch set pci/0000:06:00.0 mode switchdevh]h9$ devlink dev eswitch set pci/0000:06:00.0 mode switchdev}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hsAttach mlx5 switchdev representor 'enp8s0f0' to bridge netdev 'bridge1':: $ ip link set enp8s0f0 master bridge1 h](j})}(hIAttach mlx5 switchdev representor 'enp8s0f0' to bridge netdev 'bridge1'::h]hPAttach mlx5 switchdev representor ‘enp8s0f0’ to bridge netdev ‘bridge1’:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubj)}(h%$ ip link set enp8s0f0 master bridge1h]h%$ ip link set enp8s0f0 master bridge1}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]bullet-uh1jhhhKhjhhubjH)}(hhh](jM)}(hVLANsh]hVLANs}(hj/hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj,hhhhhKubj})}(h6Following bridge VLAN functions are supported by mlx5:h]h6Following bridge VLAN functions are supported by mlx5:}(hj=hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj,hhubj)}(hhh](j)}(hVLAN filtering (including multiple VLANs per port):: $ ip link set bridge1 type bridge vlan_filtering 1 $ bridge vlan add dev enp8s0f0 vid 2-3 h](j})}(h4VLAN filtering (including multiple VLANs per port)::h]h3VLAN filtering (including multiple VLANs per port):}(hjRhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK hjNubj)}(hY$ ip link set bridge1 type bridge vlan_filtering 1 $ bridge vlan add dev enp8s0f0 vid 2-3h]hY$ ip link set bridge1 type bridge vlan_filtering 1 $ bridge vlan add dev enp8s0f0 vid 2-3}hj`sbah}(h]h ]h"]h$]h&]hhuh1jhhhK"hjNubeh}(h]h ]h"]h$]h&]uh1jhjKhhhhhNubj)}(hKVLAN push on bridge ingress:: $ bridge vlan add dev enp8s0f0 vid 3 pvid h](j})}(hVLAN push on bridge ingress::h]hVLAN push on bridge ingress:}(hjxhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK%hjtubj)}(h)$ bridge vlan add dev enp8s0f0 vid 3 pvidh]h)$ bridge vlan add dev enp8s0f0 vid 3 pvid}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK'hjtubeh}(h]h ]h"]h$]h&]uh1jhjKhhhhhNubj)}(hMVLAN pop on bridge egress:: $ bridge vlan add dev enp8s0f0 vid 3 untagged h](j})}(hVLAN pop on bridge egress::h]hVLAN pop on bridge egress:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK)hjubj)}(h-$ bridge vlan add dev enp8s0f0 vid 3 untaggedh]h-$ bridge vlan add dev enp8s0f0 vid 3 untagged}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK+hjubeh}(h]h ]h"]h$]h&]uh1jhjKhhhhhNubeh}(h]h ]h"]h$]h&]j*j+uh1jhhhK hj,hhubeh}(h]vlansah ]h"]vlansah$]h&]uh1jGhjhhhhhKubeh}(h](bridge-offloadjeh ]h"](bridge offloadmlx5_bridge_offloadeh$]h&]uh1jGhjIhhhhhK expect_referenced_by_name}jjsexpect_referenced_by_id}jjsubjH)}(hhh](jM)}(h Subfunctionh]h Subfunction}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjhhhhhK.ubj})}(hSubfunction which are spawned over the E-switch are created only with devlink device, and by default all the SF auxiliary devices are disabled. This will allow user to configure the SF before the SF have been fully probed, which will save time.h]hSubfunction which are spawned over the E-switch are created only with devlink device, and by default all the SF auxiliary devices are disabled. This will allow user to configure the SF before the SF have been fully probed, which will save time.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK0hjhhubj})}(hUsage example:h]hUsage example:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK5hjhhubj)}(hhh](j)}(hCreate SF:: $ devlink port add pci/0000:08:00.0 flavour pcisf pfnum 0 sfnum 11 $ devlink port function set pci/0000:08:00.0/32768 hw_addr 00:00:00:00:00:11 state active h](j})}(h Create SF::h]h Create SF:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK7hj ubj)}(h$ devlink port add pci/0000:08:00.0 flavour pcisf pfnum 0 sfnum 11 $ devlink port function set pci/0000:08:00.0/32768 hw_addr 00:00:00:00:00:11 state activeh]h$ devlink port add pci/0000:08:00.0 flavour pcisf pfnum 0 sfnum 11 $ devlink port function set pci/0000:08:00.0/32768 hw_addr 00:00:00:00:00:11 state active}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhK9hj ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(h~Enable ETH auxiliary device:: $ devlink dev param set auxiliary/mlx5_core.sf.1 name enable_eth value true cmode driverinit h](j})}(hEnable ETH auxiliary device::h]hEnable ETH auxiliary device:}(hj5hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj1ubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubj)}(hkNow, in order to fully probe the SF, use devlink reload:: $ devlink dev reload auxiliary/mlx5_core.sf.1 h](j})}(h9Now, in order to fully probe the SF, use devlink reload::h]h8Now, in order to fully probe the SF, use devlink reload:}(hj[hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK@hjWubj)}(h-$ devlink dev reload auxiliary/mlx5_core.sf.1h]h-$ devlink dev reload auxiliary/mlx5_core.sf.1}hjisbah}(h]h ]h"]h$]h&]hhuh1jhhhKBhjWubeh}(h]h ]h"]h$]h&]uh1jhjhhhhhNubeh}(h]h ]h"]h$]h&]j*j+uh1jhhhK7hjhhubj})}(hmlx5 supports ETH,rdma and vdpa (vnet) auxiliary devices devlink params (see :ref:`Documentation/networking/devlink/devlink-params.rst `).h](hMmlx5 supports ETH,rdma and vdpa (vnet) auxiliary devices devlink params (see }(hjhhhNhNubh)}(hS:ref:`Documentation/networking/devlink/devlink-params.rst `h]hinline)}(hjh]h3Documentation/networking/devlink/devlink-params.rst}(hjhhhNhNubah}(h]h ](xrefstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdoc:networking/device_drivers/ethernet/mellanox/mlx5/switchdev refdomainjreftyperef refexplicitrefwarn reftargetdevlink_params_genericuh1hhhhKDhjubh).}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhKDhjhhubj})}(hmlx5 supports subfunction management using devlink port (see :ref:`Documentation/networking/devlink/devlink-port.rst `) interface.h](h=mlx5 supports subfunction management using devlink port (see }(hjhhhNhNubh)}(hG:ref:`Documentation/networking/devlink/devlink-port.rst `h]j)}(hjh]h1Documentation/networking/devlink/devlink-port.rst}(hjhhhNhNubah}(h]h ](jstdstd-refeh"]h$]h&]uh1jhjubah}(h]h ]h"]h$]h&]refdocj refdomainjreftyperef refexplicitrefwarnj devlink_portuh1hhhhKFhjubh ) interface.}(hjhhhNhNubeh}(h]h ]h"]h$]h&]uh1j|hhhKFhjhhubj})}(hA subfunction has its own function capabilities and its own resources. This means a subfunction has its own dedicated queues (txq, rxq, cq, eq). These queues are neither shared nor stolen from the parent PCI function.h]hA subfunction has its own function capabilities and its own resources. This means a subfunction has its own dedicated queues (txq, rxq, cq, eq). These queues are neither shared nor stolen from the parent PCI function.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKHhjhhubj})}(hWhen a subfunction is RDMA capable, it has its own QP1, GID table, and RDMA resources neither shared nor stolen from the parent PCI function.h]hWhen a subfunction is RDMA capable, it has its own QP1, GID table, and RDMA resources neither shared nor stolen from the parent PCI function.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKLhjhhubj})}(hA subfunction has a dedicated window in PCI BAR space that is not shared with the other subfunctions or the parent PCI function. This ensures that all devices (netdev, rdma, vdpa, etc.) of the subfunction accesses only assigned PCI BAR space.h]hA subfunction has a dedicated window in PCI BAR space that is not shared with the other subfunctions or the parent PCI function. This ensures that all devices (netdev, rdma, vdpa, etc.) of the subfunction accesses only assigned PCI BAR space.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKOhjhhubj})}(hA subfunction supports eswitch representation through which it supports tc offloads. The user configures eswitch to send/receive packets from/to the subfunction port.h]hA subfunction supports eswitch representation through which it supports tc offloads. The user configures eswitch to send/receive packets from/to the subfunction port.}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKThjhhubj})}(hzSubfunctions share PCI level resources such as PCI MSI-X IRQs with other subfunctions and/or with its parent PCI function.h]hzSubfunctions share PCI level resources such as PCI MSI-X IRQs with other subfunctions and/or with its parent PCI function.}(hj$hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKXhjhhubj})}(h0Example mlx5 software, system, and device view::h]h/Example mlx5 software, system, and device view:}(hj2hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhK[hjhhubj)}(hX _______ | admin | | user |---------- |_______| | | | ____|____ __|______ _________________ | | | | | | | devlink | | tc tool | | user | | tool | |_________| | applications | |_________| | |_________________| | | | | | | | | Userspace +---------|-------------|-------------------|----------|--------------------+ | | +----------+ +----------+ Kernel | | | netdev | | rdma dev | | | +----------+ +----------+ (devlink port add/del | ^ ^ port function set) | | | | | +---------------| _____|___ | | _______|_______ | | | | | mlx5 class | | devlink | +------------+ | | drivers | | kernel | | rep netdev | | |(mlx5_core,ib) | |_________| +------------+ | |_______________| | | | ^ (devlink ops) | | (probe/remove) _________|________ | | ____|________ | subfunction | | +---------------+ | subfunction | | management driver|----- | subfunction |---| driver | | (mlx5_core) | | auxiliary dev | | (mlx5_core) | |__________________| +---------------+ |_____________| | ^ (sf add/del, vhca events) | | (device add/del) _____|____ ____|________ | | | subfunction | | PCI NIC |--- activate/deactivate events--->| host driver | |__________| | (mlx5_core) | |_____________|h]hX _______ | admin | | user |---------- |_______| | | | ____|____ __|______ _________________ | | | | | | | devlink | | tc tool | | user | | tool | |_________| | applications | |_________| | |_________________| | | | | | | | | Userspace +---------|-------------|-------------------|----------|--------------------+ | | +----------+ +----------+ Kernel | | | netdev | | rdma dev | | | +----------+ +----------+ (devlink port add/del | ^ ^ port function set) | | | | | +---------------| _____|___ | | _______|_______ | | | | | mlx5 class | | devlink | +------------+ | | drivers | | kernel | | rep netdev | | |(mlx5_core,ib) | |_________| +------------+ | |_______________| | | | ^ (devlink ops) | | (probe/remove) _________|________ | | ____|________ | subfunction | | +---------------+ | subfunction | | management driver|----- | subfunction |---| driver | | (mlx5_core) | | auxiliary dev | | (mlx5_core) | |__________________| +---------------+ |_____________| | ^ (sf add/del, vhca events) | | (device add/del) _____|____ ____|________ | | | subfunction | | PCI NIC |--- activate/deactivate events--->| host driver | |__________| | (mlx5_core) | |_____________|}hj@sbah}(h]h ]h"]h$]h&]hhuh1jhhhK]hjhhubj})}(h4Subfunction is created using devlink port interface.h]h4Subfunction is created using devlink port interface.}(hjNhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjhhubj)}(hhh](j)}(h_Change device to switchdev mode:: $ devlink dev eswitch set pci/0000:06:00.0 mode switchdev h](j})}(h!Change device to switchdev mode::h]h Change device to switchdev mode:}(hjchhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj_ubj)}(h9$ devlink dev eswitch set pci/0000:06:00.0 mode switchdevh]h9$ devlink dev eswitch set pci/0000:06:00.0 mode switchdev}hjqsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj_ubeh}(h]h ]h"]h$]h&]uh1jhj\hhhhhNubj)}(hX;Add a devlink port of subfunction flavour:: $ devlink port add pci/0000:06:00.0 flavour pcisf pfnum 0 sfnum 88 pci/0000:06:00.0/32768: type eth netdev eth6 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:00:00 state inactive opstate detached h](j})}(h+Add a devlink port of subfunction flavour::h]h*Add a devlink port of subfunction flavour:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubj)}(hX$ devlink port add pci/0000:06:00.0 flavour pcisf pfnum 0 sfnum 88 pci/0000:06:00.0/32768: type eth netdev eth6 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:00:00 state inactive opstate detachedh]hX$ devlink port add pci/0000:06:00.0 flavour pcisf pfnum 0 sfnum 88 pci/0000:06:00.0/32768: type eth netdev eth6 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:00:00 state inactive opstate detached}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhj\hhhhhNubj)}(hShow a devlink port of the subfunction:: $ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00 state inactive opstate detached h](j})}(h(Show a devlink port of the subfunction::h]h'Show a devlink port of the subfunction:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubj)}(h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00 state inactive opstate detachedh]h$ devlink port show pci/0000:06:00.0/32768 pci/0000:06:00.0/32768: type eth netdev enp6s0pf0sf88 flavour pcisf pfnum 0 sfnum 88 function: hw_addr 00:00:00:00:00:00 state inactive opstate detached}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhj\hhhhhNubj)}(h^Delete a devlink port of subfunction after use:: $ devlink port del pci/0000:06:00.0/32768 h](j})}(h0Delete a devlink port of subfunction after use::h]h/Delete a devlink port of subfunction after use:}(hjhhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjubj)}(h)$ devlink port del pci/0000:06:00.0/32768h]h)$ devlink port del pci/0000:06:00.0/32768}hjsbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjubeh}(h]h ]h"]h$]h&]uh1jhj\hhhhhNubeh}(h]h ]h"]h$]h&]j*j+uh1jhhhKhjhhubeh}(h] subfunctionah ]h"] subfunctionah$]h&]uh1jGhjIhhhhhK.ubjH)}(hhh](jM)}(hFunction attributesh]hFunction attributes}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(h{The mlx5 driver provides a mechanism to setup PCI VF/SF function attributes in a unified way for SmartNIC and non-SmartNIC.h]h{The mlx5 driver provides a mechanism to setup PCI VF/SF function attributes in a unified way for SmartNIC and non-SmartNIC.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hThis is supported only when the eswitch mode is set to switchdev. Port function configuration of the PCI VF/SF is supported through devlink eswitch port.h]hThis is supported only when the eswitch mode is set to switchdev. Port function configuration of the PCI VF/SF is supported through devlink eswitch port.}(hj$ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hTPort function attributes should be set before PCI VF/SF is enumerated by the driver.h]hTPort function attributes should be set before PCI VF/SF is enumerated by the driver.}(hj2 hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubjH)}(hhh](jM)}(hMAC address setuph]hMAC address setup}(hjC hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj@ hhhhhKubj})}(hmlx5 driver support devlink port function attr mechanism to setup MAC address. (refer to Documentation/networking/devlink/devlink-port.rst)h]hmlx5 driver support devlink port function attr mechanism to setup MAC address. (refer to Documentation/networking/devlink/devlink-port.rst)}(hjQ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj@ hhubjH)}(hhh](jM)}(hRoCE capability setuph]hRoCE capability setup}(hjb hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj_ hhhhhKubj})}(h5Not all mlx5 PCI devices/SFs require RoCE capability.h]h5Not all mlx5 PCI devices/SFs require RoCE capability.}(hjp hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj_ hhubj})}(h^When RoCE capability is disabled, it saves 1 Mbytes worth of system memory per PCI devices/SF.h]h^When RoCE capability is disabled, it saves 1 Mbytes worth of system memory per PCI devices/SF.}(hj~ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj_ hhubj})}(hmlx5 driver support devlink port function attr mechanism to setup RoCE capability. (refer to Documentation/networking/devlink/devlink-port.rst)h]hmlx5 driver support devlink port function attr mechanism to setup RoCE capability. (refer to Documentation/networking/devlink/devlink-port.rst)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj_ hhubeh}(h]roce-capability-setupah ]h"]roce capability setupah$]h&]uh1jGhj@ hhhhhKubjH)}(hhh](jM)}(hmigratable capability setuph]hmigratable capability setup}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(hxUser who wants mlx5 PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.h]hxUser who wants mlx5 PCI VFs to be able to perform live migration need to explicitly enable the VF migratable capability.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hmlx5 driver support devlink port function attr mechanism to setup migratable capability. (refer to Documentation/networking/devlink/devlink-port.rst)h]hmlx5 driver support devlink port function attr mechanism to setup migratable capability. (refer to Documentation/networking/devlink/devlink-port.rst)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubeh}(h]migratable-capability-setupah ]h"]migratable capability setupah$]h&]uh1jGhj@ hhhhhKubjH)}(hhh](jM)}(hIPsec crypto capability setuph]hIPsec crypto capability setup}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(hX2User who wants mlx5 PCI VFs to be able to perform IPsec crypto offloading need to explicitly enable the VF ipsec_crypto capability. Enabling IPsec capability for VFs is supported starting with ConnectX6dx devices and above. When a VF has IPsec capability enabled, any IPsec offloading is blocked on the PF.h]hX2User who wants mlx5 PCI VFs to be able to perform IPsec crypto offloading need to explicitly enable the VF ipsec_crypto capability. Enabling IPsec capability for VFs is supported starting with ConnectX6dx devices and above. When a VF has IPsec capability enabled, any IPsec offloading is blocked on the PF.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hmlx5 driver support devlink port function attr mechanism to setup ipsec_crypto capability. (refer to Documentation/networking/devlink/devlink-port.rst)h]hmlx5 driver support devlink port function attr mechanism to setup ipsec_crypto capability. (refer to Documentation/networking/devlink/devlink-port.rst)}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubeh}(h]ipsec-crypto-capability-setupah ]h"]ipsec crypto capability setupah$]h&]uh1jGhj@ hhhhhKubjH)}(hhh](jM)}(hIPsec packet capability setuph]hIPsec packet capability setup}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhj hhhhhKubj})}(hX2User who wants mlx5 PCI VFs to be able to perform IPsec packet offloading need to explicitly enable the VF ipsec_packet capability. Enabling IPsec capability for VFs is supported starting with ConnectX6dx devices and above. When a VF has IPsec capability enabled, any IPsec offloading is blocked on the PF.h]hX2User who wants mlx5 PCI VFs to be able to perform IPsec packet offloading need to explicitly enable the VF ipsec_packet capability. Enabling IPsec capability for VFs is supported starting with ConnectX6dx devices and above. When a VF has IPsec capability enabled, any IPsec offloading is blocked on the PF.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubj})}(hmlx5 driver support devlink port function attr mechanism to setup ipsec_packet capability. (refer to Documentation/networking/devlink/devlink-port.rst)h]hmlx5 driver support devlink port function attr mechanism to setup ipsec_packet capability. (refer to Documentation/networking/devlink/devlink-port.rst)}(hj+ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj hhubeh}(h]ipsec-packet-capability-setupah ]h"]ipsec packet capability setupah$]h&]uh1jGhj@ hhhhhKubeh}(h]mac-address-setupah ]h"]mac address setupah$]h&]uh1jGhj hhhhhKubjH)}(hhh](jM)}(hSF state setuph]hSF state setup}(hjL hhhNhNubah}(h]h ]h"]h$]h&]uh1jLhjI hhhhhKubj})}(hSTo use the SF, the user must activate the SF using the SF function state attribute.h]hSTo use the SF, the user must activate the SF using the SF function state attribute.}(hjZ hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjI hhubj)}(hhh](j)}(hX;Get the state of the SF identified by its unique devlink port index:: $ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state inactive opstate detached h](j})}(hEGet the state of the SF identified by its unique devlink port index::h]hDGet the state of the SF identified by its unique devlink port index:}(hjo hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjk ubj)}(h$ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state inactive opstate detachedh]h$ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state inactive opstate detached}hj} sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhjk ubeh}(h]h ]h"]h$]h&]uh1jhjh hhhhhNubj)}(hXdActivate the function and verify its state is active:: $ devlink port function set ens2f0npf0sf88 state active $ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate detached h](j})}(h6Activate the function and verify its state is active::h]h5Activate the function and verify its state is active:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj ubj)}(hX&$ devlink port function set ens2f0npf0sf88 state active $ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate detachedh]hX&$ devlink port function set ens2f0npf0sf88 state active $ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate detached}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhjh hhhhhNubeh}(h]h ]h"]h$]h&]j*j+uh1jhhhKhjI hhubj})}(hUpon function activation, the PF driver instance gets the event from the device that a particular SF was activated. It's the cue to put the device on bus, probe it and instantiate the devlink instance and class specific auxiliary devices for it.h]hUpon function activation, the PF driver instance gets the event from the device that a particular SF was activated. It’s the cue to put the device on bus, probe it and instantiate the devlink instance and class specific auxiliary devices for it.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhjI hhubj)}(hhh](j)}(hXRShow the auxiliary device and port of the subfunction:: $ devlink dev show devlink dev show auxiliary/mlx5_core.sf.4 $ devlink port show auxiliary/mlx5_core.sf.4/1 auxiliary/mlx5_core.sf.4/1: type eth netdev p0sf88 flavour virtual port 0 splittable false $ rdma link show mlx5_0/1 link mlx5_0/1 state ACTIVE physical_state LINK_UP netdev p0sf88 $ rdma dev show 8: rocep6s0f1: node_type ca fw 16.29.0550 node_guid 248a:0703:00b3:d113 sys_image_guid 248a:0703:00b3:d112 13: mlx5_0: node_type ca fw 16.29.0550 node_guid 0000:00ff:fe00:8888 sys_image_guid 248a:0703:00b3:d112 h](j})}(h7Show the auxiliary device and port of the subfunction::h]h6Show the auxiliary device and port of the subfunction:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj ubj)}(hX$ devlink dev show devlink dev show auxiliary/mlx5_core.sf.4 $ devlink port show auxiliary/mlx5_core.sf.4/1 auxiliary/mlx5_core.sf.4/1: type eth netdev p0sf88 flavour virtual port 0 splittable false $ rdma link show mlx5_0/1 link mlx5_0/1 state ACTIVE physical_state LINK_UP netdev p0sf88 $ rdma dev show 8: rocep6s0f1: node_type ca fw 16.29.0550 node_guid 248a:0703:00b3:d113 sys_image_guid 248a:0703:00b3:d112 13: mlx5_0: node_type ca fw 16.29.0550 node_guid 0000:00ff:fe00:8888 sys_image_guid 248a:0703:00b3:d112h]hX$ devlink dev show devlink dev show auxiliary/mlx5_core.sf.4 $ devlink port show auxiliary/mlx5_core.sf.4/1 auxiliary/mlx5_core.sf.4/1: type eth netdev p0sf88 flavour virtual port 0 splittable false $ rdma link show mlx5_0/1 link mlx5_0/1 state ACTIVE physical_state LINK_UP netdev p0sf88 $ rdma dev show 8: rocep6s0f1: node_type ca fw 16.29.0550 node_guid 248a:0703:00b3:d113 sys_image_guid 248a:0703:00b3:d112 13: mlx5_0: node_type ca fw 16.29.0550 node_guid 0000:00ff:fe00:8888 sys_image_guid 248a:0703:00b3:d112}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhKhj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubj)}(hXSubfunction auxiliary device and class device hierarchy:: mlx5_core.sf.4 (subfunction auxiliary device) /\ / \ / \ / \ / \ mlx5_core.eth.4 mlx5_core.rdma.4 (sf eth aux dev) (sf rdma aux dev) | | | | p0sf88 mlx5_0 (sf netdev) (sf rdma device) h](j})}(h9Subfunction auxiliary device and class device hierarchy::h]h8Subfunction auxiliary device and class device hierarchy:}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhKhj ubj)}(hX~ mlx5_core.sf.4 (subfunction auxiliary device) /\ / \ / \ / \ / \ mlx5_core.eth.4 mlx5_core.rdma.4 (sf eth aux dev) (sf rdma aux dev) | | | | p0sf88 mlx5_0 (sf netdev) (sf rdma device)h]hX~ mlx5_core.sf.4 (subfunction auxiliary device) /\ / \ / \ / \ / \ mlx5_core.eth.4 mlx5_core.rdma.4 (sf eth aux dev) (sf rdma aux dev) | | | | p0sf88 mlx5_0 (sf netdev) (sf rdma device)}hj sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj ubeh}(h]h ]h"]h$]h&]uh1jhj hhhhhNubeh}(h]h ]h"]h$]h&]j*j+uh1jhhhKhjI hhubj})}(hX4Additionally, the SF port also gets the event when the driver attaches to the auxiliary device of the subfunction. This results in changing the operational state of the function. This provides visibility to the user to decide when is it safe to delete the SF port for graceful termination of the subfunction.h]hX4Additionally, the SF port also gets the event when the driver attaches to the auxiliary device of the subfunction. This results in changing the operational state of the function. This provides visibility to the user to decide when is it safe to delete the SF port for graceful termination of the subfunction.}(hj hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhMhjI hhubj)}(hhh]j)}(hXShow the SF port operational state:: $ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate attachedh](j})}(h$Show the SF port operational state::h]h#Show the SF port operational state:}(hj5 hhhNhNubah}(h]h ]h"]h$]h&]uh1j|hhhMhj1 ubj)}(h$ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate attachedh]h$ devlink port show ens2f0npf0sf88 pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false function: hw_addr 00:00:00:00:88:88 state active opstate attached}hjC sbah}(h]h ]h"]h$]h&]hhuh1jhhhMhj1 ubeh}(h]h ]h"]h$]h&]uh1jhj. hhhhhNubah}(h]h ]h"]h$]h&]j*j+uh1jhhhMhjI hhubeh}(h]sf-state-setupah ]h"]sf state setupah$]h&]uh1jGhj hhhhhKubeh}(h]function-attributesah ]h"]function attributesah$]h&]uh1jGhjIhhhhhKubeh}(h] switchdevah ]h"] switchdevah$]h&]uh1jGhhhhhhhKubeh}(h]h ]h"]h$]h&]sourcehuh1hcurrent_sourceN current_lineNsettingsdocutils.frontendValues)}(jLN generatorN datestampN source_linkN source_urlN toc_backlinksentryfootnote_backlinksK sectnum_xformKstrip_commentsNstrip_elements_with_classesN strip_classesN report_levelK halt_levelKexit_status_levelKdebugNwarning_streamN tracebackinput_encoding utf-8-siginput_encoding_error_handlerstrictoutput_encodingutf-8output_encoding_error_handlerj error_encodingutf-8error_encoding_error_handlerbackslashreplace language_codeenrecord_dependenciesNconfigN id_prefixhauto_id_prefixid dump_settingsNdump_internalsNdump_transformsNdump_pseudo_xmlNexpose_internalsNstrict_visitorN_disable_configN_sourceh _destinationN _config_files]7/var/lib/git/docbuild/linux/Documentation/docutils.confafile_insertion_enabled raw_enabledKline_length_limitM'pep_referencesN pep_base_urlhttps://peps.python.org/pep_file_url_templatepep-%04drfc_referencesN rfc_base_url&https://datatracker.ietf.org/doc/html/ tab_widthKtrim_footnote_reference_spacesyntax_highlightlong smart_quotessmartquotes_locales]character_level_inline_markupdoctitle_xform docinfo_xformKsectsubtitle_xform image_loadinglinkembed_stylesheetcloak_email_addressessection_self_linkenvNubreporterNindirect_targets]substitution_defs}(hhhhhhj jjjj*jj9j-jHj<jWjKjfjZjujijjxjjjjjjjjjjjjjjjjj jjjj)jj8j,jGj;jVjJjejYjtjhjjwjjjjjjjjjjjjjjjjj jjj j(jj7j+jFj:jUjIjdjXjsjgjjvjjjjjjjjjjjjjjjjj jjj j'jj6j*jEj9jTjHjcjWjrjfjjujjjjjjjjjjjjjjjjjjjj j&jj5j)jDj8usubstitution_names}(amphߌaposhasthbrvbarj bsoljcentj*colonj9commajHcommatjWcopyjfcurrenjudarrjdegjdividejdollarjequalsjexcljfrac12jfrac14jfrac18jfrac34j frac38jfrac58j)frac78j8gtjGhalfjVhorbarjehyphenjtiexcljiquestjlaquojlarrjlcubjldquojlowbarjlparjlsqbjlsquoj ltjmicroj(middotj7nbspjFnotjUnumjdohmjsordfjordmjparajpercntjperiodjplusjplusmnjpoundjquestjquotj raquojrarrj'rcubj6rdquojEregjTrparjcrsqbjrrsquojsectjsemijshyjsoljsungjsup1jsup2jsup3jtimesjtradejuarrj&verbarj5yenjDurefnames}refids}j]jasnameids}(jr jo jjjjjjj jjj jg jF jC j j j j j j j> j; jb j_ u nametypes}(jr jjjj jj jF j j j j> jb uh}(jo jIjjjjjj,jjjg j jC j@ j j_ j j j j j; j j_ jI u footnote_refs} citation_refs} autofootnotes]autofootnote_refs]symbol_footnotes]symbol_footnote_refs] footnotes] citations]autofootnote_startKsymbol_footnote_startK id_counter collectionsCounter}Rparse_messages]transform_messages]hsystem_message)}(hhh]j})}(hhh]h9Hyperlink target "mlx5-bridge-offload" is not referenced.}hjN sbah}(h]h ]h"]h$]h&]uh1j|hjK ubah}(h]h ]h"]h$]h&]levelKtypeINFOsourcehlineK`uh1jI uba transformerN include_log]LDocumentation/networking/device_drivers/ethernet/mellanox/mlx5/switchdev.rst(NNNNta decorationNhhub.